JP4141262B2

JP4141262B2 - Differential amplifier

Info

Publication number: JP4141262B2
Application number: JP2003009112A
Authority: JP
Inventors: 宰大岡
Original assignee: NEC Electronics Corp
Current assignee: NEC Electronics Corp
Priority date: 2003-01-17
Filing date: 2003-01-17
Publication date: 2008-08-27
Anticipated expiration: 2023-01-17
Also published as: JP2004222104A

Description

【０００１】
【発明の属する技術分野】
本発明は差動増幅器に関し、特に駆動能力を高めた差動増幅器に関する。
【０００２】
【従来の技術】
増幅器は電源から供給される電力により増幅素子を駆動して入力信号を増幅し出力するもので、抵抗負荷の場合、出力信号の最大振幅は電源電圧と増幅素子の内部抵抗などによって制限され、図３実線で示すように出力信号Ｓは電源電圧Ｖｄｄと接地電圧Ｖｓｓの中間の電圧範囲Ｖｍａｘ〜Ｖｍｉｎで波形を描く。一方、電池駆動される可搬型電子回路機器、例えば携帯電話などでは低い電源電圧で大電力動作させ電源の利用効率を高めるため出力信号の最大振幅を可及的に電源電圧に近づけるようにしている。増幅器の電力利用効率は（（Ｖｍａｘ−Ｖｍｉｎ）／（Ｖｄｄ−Ｖｓｓ））^２で表され、仮にＶｄｄを５Ｖ、Ｖｓｓを０Ｖとし、出力信号ＳのＶｍａｘが４．６Ｖ、Ｖｍｉｎが０．３Ｖであるとき電力利用効率は約７４％であるが、図示点線で示すように最大振幅を拡大し、Ｖｍａｘを４．８Ｖ、Ｖｍｉｎを０．１Ｖとし振幅を０．４Ｖ拡大するだけで電力利用効率は約８８％となり約１４％改善でき、電池駆動機器を長時間動作させることができる。
【０００３】
そのような増幅器の一例を図４に示す。図において、１Ａ、１Ｂは一対の一導電型（ｎチャンネル）ＭＯＳＦＥＴで、各制御電極（ゲート電極）は一対の入力端子２Ａ、２Ｂに接続され、接地側主電極（ソース電極）は共通接続されて、ｎチャンネルＭＯＳＦＥＴ３を介して接地ライン４に接続されて、第１の差動入力段５を構成している。６Ａ、６Ｂは一対の他導電型（ｐチャンネル）ＭＯＳＦＥＴで、各制御電極（ゲート電極）は一対の入力端子２Ａ、２Ｂに接続され、電源側主電極（ソース電極）は共通接続されて、ｐチャンネルＭＯＳＦＥＴ７を介して電源ライン８に接続され、第２の差動入力段９を構成している。１０は電源ライン８と接地ライン４の間に接続された第１の定電流回路で、２つの定電流源１１、１２間にバイアス素子、図示例では抵抗１３を直列接続している。１４は第１の定電流回路１０と同様に電源ライン８と接地ライン４の間に接続された第２の定電流回路で、２つの定電流源１５、１６間にバイアス素子としての抵抗１７を直列接続している。第１の差動入力段５の一方のＭＯＳＦＥＴ１Ａの他の主電極（ドレイン電極）は第１の定電流回路１０の定電流源１１と抵抗１３の接続点に、第１の差動入力段５の他のＭＯＳＦＥＴ１Ｂの他の主電極（ドレイン電極）は第２の定電流回路１４の定電流源１５と抵抗１７の接続点にそれぞれ接続され、第２の差動入力段９の一方のＭＯＳＦＥＴ６Ａの他の主電極（ドレイン電極）は第１の定電流回路１０の定電流源１２と抵抗１３の接続点に、第２の差動入力段９の他のＭＯＳＦＥＴ６Ｂの他の主電極（ドレイン電極）は第２の定電流回路１４の定電流源１６と抵抗１７の接続点にそれぞれ接続されている。１８はｐチャンネルＭＯＳＦＥＴ１９とｎチャンネルＭＯＳＦＥＴ２０を相補接続した出力段で、ｐチャンネルＭＯＳＦＥＴのソース電極は電源ライン８に接続され、そのドレイン電極はｎチャンネルＭＯＳＦＥＴ２０のドレイン電極に共通接続されて、さらに出力端子２１に接続され、ｎチャンネルＭＯＳＦＥＴ２０のソース電極は接地ライン４に接続されている。また各ＭＯＳＦＥＴ１９、２０の制御電極（ゲート電極）は第２の定電流回路１４の抵抗１７の両端に接続されている。これに類似した差動増幅器は例えば特許文献１や特許文献２に開示されている。
【０００４】
この増幅器は共通の一対の入力端子２Ａ、２Ｂに相補的に動作するｎチャンネルとｐチャンネルの各一対のＭＯＳＦＥＴ１Ａ、１Ｂと６Ａ、６Ｂによって出力段１８のバイアスを制御する。例えば入力端子２Ａの入力信号レベルが低下すると、第１の差動入力段５の一方のｎチャンネルＭＯＳＦＥＴ１Ａのドレイン電圧は上昇し、他のＭＯＳＦＥＴ１Ｂのドレイン電圧は低下する。同時に第２の差動入力段９の一方のｐチャンネルＭＯＳＦＥＴ６Ａのドレイン電圧は上昇し、他のＭＯＳＦＥＴ６Ｂのドレイン電圧は低下する。
【０００５】
第１差動入力段５の他のＭＯＳＦＥＴ１Ｂのドレイン電極と第２の差動入力段９の他のＭＯＳＦＥＴ６Ｂのドレイン電極はそれぞれ定電流回路１４の抵抗１７の両端に接続されており、抵抗１７の端子間電圧を保った状態で抵抗１７の両端の電圧を同時に変化させて出力段１８の電源ライン８に接続されたｐチャンネルＭＯＳＦＥＴ１９及び接地ライン４に接続されたｎチャンネルＭＯＳＦＥＴ２０を制御することができる。
【０００６】
入力端子２Ａの入力信号レベルが増大する場合は、上記とは逆に、抵抗１７の端子間電圧を保った状態で抵抗１７の両端の電圧を同時に引き上げ、出力段１８の電源ライン８に接続されたｐチャンネルＭＯＳＦＥＴ１９の遮断性を高め、接地ライン４に接続されたｎチャンネルＭＯＳＦＥＴ２０の導通性を高めることができる。このようにして図４に示す増幅器は図３にて出力信号Ｓの最大振幅を図示実線状態から図示点線状態に拡大でき電源の利用効率を高めることができる。
【０００７】
【特許文献１】
特開平６−３２６５２９号公報（第４〜６頁、図１）
【特許文献２】
特開平７−１５２４９号公報（第３〜４頁、図３）
【０００８】
【発明が解決しようとする課題】
ところで、図４に示す差動増幅器は、入力信号レベルが電源電圧の高電圧側の電圧Ｖｄｄに近づくと第２の差動入力段９のｐチャンネルＭＯＳＦＥＴ６Ａ、６Ｂがカットオフし、入力信号レベルが低電圧側のゼロ又は負の電圧Ｖｓｓに近づくと第１の差動入力段５のｎチャンネルＭＯＳＦＥＴ１Ａ、１Ｂがカットオフする。そのため入力端子２Ａからみた相互コンダクタンスｇｍは、図５に示すように横軸を入力信号レベル（電圧）、縦軸を相互コンダクタンス（電流／電圧）とすると、ｎチャンネルＭＯＳＦＥＴ１Ａを用いた第１の差動入力段５は、入力信号レベルを低電圧（０Ｖ）から高電圧（例えば９Ｖ）に向かって電圧変化させると、その相互コンダクタンスｇｍ（ｎ）は低電圧側ではゼロで、１Ｖ前後で急上昇し、１Ｖをわずかに超えた部分から高電圧側にむかって単調減少する。
【０００９】
またｐチャンネルＭＯＳＦＥＴ１Ａを用いた第２の差動入力段９は、入力信号レベルを高電圧（９Ｖ）から低電圧（０Ｖ）に向かって変化させると、その相互コンダクタンスｇｍ（ｐ）は高電圧（９Ｖ）側ではゼロで、８Ｖ前後で急上昇し、８Ｖをわずかに下回った電圧から低電圧側にむかって単調減少する。
【００１０】
そのため入力端子２Ｂからみた相互コンダクタンスｇｍ（ｎ＋ｐ）はｇｍ（ｎ）とｇｍ（ｐ）を合成した略凸字状の曲線となり、入力信号レベルの中間領域では高ｇｍであるのに対して、高低両端部では低ｇｍとなり負荷駆動能力が低下し、入力信号レベルに対して相互コンダクタンスの変動が大きいという問題があった。各差動入力段５、９の相互コンダクタンスｇｍ（ｎ）、ｇｍ（ｐ）の大きさは各差動入力段５、９の電流を制御するトランジスタ３、７のバイアス設定により変更可能であるが、入力信号レベルの高低両端部で生じる低ｇｍを解消することはできなかった。
【００１１】
【課題を解決するための手段】
本発明は上記課題の解決を目的として提案されたもので、一対の一導電型トランジスタの一主電極を共通接続し各トランジスタの制御電極を一対の入力端子に接続した第１の差動入力段と、一対の他導電型トランジスタの一主電極を共通接続し各トランジスタの制御電極を前記入力端子に共通接続した第２の差動入力段と、中間にバイアス素子を含む第１、第２の定電流回路と、一対の相補型トランジスタよりなる出力段とを含み、第１の差動入力段の各トランジスタの他の主電極を第１、第２の定電流回路のバイアス素子の一端側にそれぞれ接続し、第２の差動入力段の各トランジスタの他の主電極を第１、第２の定電流回路のバイアス素子の他端側にそれぞれ接続し、出力段の相補型トランジスタの各制御電極を第２の定電流回路のバイアス素子の両端に接続した差動増幅器において、電源ライン側と接地ライン側に第１、第２のカレントミラー回路を配置し、各カレントミラー回路の２つの電流経路に第１、第２の駆動トランジスタを挿入し、第１の駆動トランジスタの電源ライン側電極を第２の差動入力段の共通接続された主電極に、第２の駆動トランジスタの接地ライン側電極を第１の差動入力段の共通接続された主電極に、第１の駆動トランジスタの制御電極を第２の定電流回路のバイアス素子の電源ライン側端部に、第２の駆動トランジスタの制御電極を第２の定電流回路のバイアス素子の接地ライン側端部に、それぞれ接続したことを特徴とする差動増幅器を提供する。
【００１２】
【発明の実施の形態】
本発明による差動増幅器は、第１、第２のカレントミラー回路と第１、第２の駆動トランジスタで構成される差動入力段駆動回路を付加することにより、第１、第２の差動入力段の入力信号レベル領域で不動状態をなくし、入力信号レベルの全領域で相互コンダクタンスｇｍを高く維持できる。第１の差動入力段のトランジスタをｎチャンネルＭＯＳＦＥＴにて、第２の差動入力段のトランジスタをｐチャンネルＭＯＳＦＥＴにて構成した場合、電源ライン側の第１のカレントミラー回路と第１の駆動トランジスタをｐチャンネルＭＯＳＦＥＴにて、接地ライン側の第２のカレントミラー回路と第２の駆動トランジスタをｎチャンネルＭＯＳＦＥＴにて構成することができる。また第１、第２のカレントミラー回路の２つの電流経路を流れる電流を異ならせることにより相互コンダクタンスｇｍの大きさを調整できる。
【００１３】
【実施例】
以下に本発明の実施例を図１から説明する。図において、図４と同一部分には同一符号を付し重複する説明を省略する。即ち、ｎチャンネルＭＯＳＦＥＴ１Ａ、１Ｂからなる第１の差動入力段５は一主電極（ソース電極）が共通接続され、ｎチャンネルＭＯＳＦＥＴ３を介して接地ライン４に接続されている。またｐチャンネルＭＯＳＦＥＴ６Ａ、６Ｂからなる第２の差動入力段９は一主電極（ソース電極）が共通接続され、ｐチャンネルＭＯＳＦＥＴ７を介して電源ライン８に接続されている。各差動入力段５、９の各ＭＯＳＦＥＴ１Ａ、６Ａと１Ｂ、６Ｂのそれぞれの制御電極（ゲート電極）は一対の入力端子２Ａと２Ｂに接続されている。電源ライン８と接地ライン４の間には、第１、第２の定電流回路１０、１４が接続されている。第１の定電流回路１０は定電流源１１、バイアス素子（抵抗）１３、定電流源１２を、第２の定電流回路１４は定電流源１５、バイアス素子（抵抗）１７、定電流源１６を、それぞれ直列的に接続したもので、定電流源１１と抵抗１３の接続部には第１の差動入力段５のｎチャンネルＭＯＳＦＥＴ１Ａの他の主電極（ドレイン電極）が、抵抗１３と定電流源１２の接続部には第２の差動入力段９のｐチャンネルＭＯＳＦＥＴ６Ａの他の主電極（ドレイン電極）が接続されている。また第２の定電流回路１４の定電流源１５と抵抗１７の接続部には第１の差動入力段５のｎチャンネルＭＯＳＦＥＴ１Ｂの他の主電極（ドレイン電極）が、抵抗１７と定電流源１６の接続部には第２の差動入力段９のｐチャンネルＭＯＳＦＥＴ６Ｂの他の主電極（ドレイン電極）が接続されている。そして第２の定電流回路１４の抵抗１７の両端は出力段１８の相補トランジスタ１９、２０の各制御電極（ゲート電極）が接続されている。
【００１４】
本発明による差動増幅器は図４と同一の上記回路に、符号２２を付し図示点線で囲まれる差動入力段駆動回路を付加したことを特徴とする。この差動入力段駆動回路２２は、２つのカレントミラー回路２３、２４を電源ライン８側と接地ライン４側に配置し、各カレントミラー回路２３、２４の２つの電流経路にそれぞれ第１、第２の駆動トランジスタ２５、２６を挿入したもので、第１の駆動トランジスタ２５は制御電極（ゲート電極）が第１の差動入力段５のｎＭＯＳＦＥＴ１Ｂのドレイン電極（抵抗１７の電源ライン側端部、出力段１８のｐＭＯＳＦＥＴ１９のゲート電極）に接続され、第１の駆動トランジスタ２５の電源ライン側の主電極（ソース電極）は第２の差動入力段９の共通接続されたソース電極に接続されている。また第２の駆動トランジスタ２６は制御電極（ゲート電極）が第２の差動入力段９のｐＭＯＳＦＥＴ６Ｂのドレイン電極（抵抗１７の接地ライン側端部、出力段１８のｎＭＯＳＦＥＴ２０のゲート電極）に接続され、第２の駆動トランジスタ２６の接地ライン側主電極（ソース電極）は第１の差動入力段５の共通接続されたソース電極に接続されている。
【００１５】
以下にこの差動増幅器の動作を説明する。この増幅器の差動入力段駆動回路２２を除く部分の動作は図４回路と同じであるため省略する。この増幅器は差動入力段駆動回路２２を構成するカレントミラー回路２３、２４の２つの電流経路には第１、第２の駆動トランジスタ２５、２６が挿入され、第１の駆動トランジスタ２５は第１の差動入力段５のｎＭＯＳＦＥＴ１Ｂのドレイン電圧を検出して開閉され、第２の駆動トランジスタ２６は第２の差動入力段９のｐＭＯＳＦＥＴ６Ｂのドレイン電圧を検出して開閉される。
【００１６】
先ず入力端子２Ｂに接地ライン電圧近傍領域の低電圧レベル（Ｌレベル）の信号を供給した場合、第１の差動入力段５のｎＭＯＳＦＥＴ１Ｂは遮断し、第２の差動入力段９のｐＭＯＳＦＥＴ６Ｂは導通する。ｎＭＯＳＦＥＴ１Ｂが遮断することによりそのドレイン電圧は電源ライン電圧近傍の高電圧レベル（Ｈレベル）となるため、第１の駆動トランジスタ２５は遮断する。そのため第１のカレントミラー回路２３から供給される電流は第２の差動入力段９のソース電極に送り込まれ、ソース電極に送り込まれた電流はドレイン電極へ出力される。一方、第２の駆動トランジスタ２６のゲート電極には第２の差動入力段９のＨレベルのドレイン電圧が供給されるため導通し第１のカレントミラー回路２３から第２の差動入力段９に供給される電流値を決定する。このように入力端子２ＢにＬレベルの信号が供給された場合には第１の差動入力段５のｎＭＯＳＦＥＴ１Ｂは遮断状態となり、このとき第２の差動入力段９のｐＭＯＳＦＥＴ６Ｂの相互コンダクタンスｇｍは差動入力段駆動回路２２がない場合に比して増大する。
【００１７】
次に入力端子２Ｂに電源ライン電圧近傍領域のＨレベルの信号を供給した場合、第２の差動入力段９のｐＭＯＳＦＥＴ６Ｂは遮断し、第１の差動入力段５のｎＭＯＳＦＥＴ１Ｂは導通する。ｐＭＯＳＦＥＴ６Ｂが遮断することによりそのドレイン電圧は接地ライン電圧近傍のＬレベルとなるため、第１の駆動トランジスタ２６は遮断する。そのため第１の差動入力段５のソース電極から吐出される電流は、ソース電極に接続されたトランジスタ３と第２のカレントミラー回路２４に分岐し、ｎＭＯＳＦＥＴ１Ｂから吐出されるドレイン電流を増大させる。一方、第１の駆動トランジスタ２５のゲート電極には第１の差動入力段５のＬレベルのドレイン電圧が供給されるため導通し第２のカレントミラー回路２４に流れる電流値を決定する。このようにして入力端子２ＢにＨレベルの信号が供給されると第２の差動入力段９のｐＭＯＳＦＥＴ６Ｂが遮断状態となり、このとき第１の差動入力段５のｎＭＯＳＦＥＴ１Ｂの相互コンダクタンスｇｍは差動入力段駆動回路２２がない場合に比して増大する。
【００１８】
前記ＬレベルとＨレベルの中間レベルの信号が入力端子２Ｂに供給された場合、第１、第２の駆動トランジスタ２５、２６は遮断状態と飽和導通状態の中間の導通状態となってカレントミラー回路２３、２４間に電流を流すが、駆動トランジスタ２５、２６の導通状態によって流れる電流値が制限されるため、第２の差動入力段９に流入し、第１の差動入力段５から吐出される電流値が制限され、相互コンダクタンスｇｍには大きな影響を与えない。
【００１９】
入力端子２Ｂに供給する入力信号レベルに対する第１、第２の差動入力段５、９の各ＭＯＳＦＥＴ１Ｂ、６Ｂの相互コンダクタンスｇｍを図２に示す。図中、一点鎖線で示すｇｍ(ｎ）は第１差動入力段５のｎＭＯＳＦＥＴ１Ｂの相互コンダクタンス、ニ点鎖線で示すｇｍ（ｐ）は第２差動入力段９のｐＭＯＳＦＥＴ６Ｂの相互コンダクタンス、実線で示すｇｍ（ｎ＋ｐ）は各ＭＯＳＦＥＴ１Ｂ、６Ｂの合成相互コンダクタンスを示す。
【００２０】
第１差動入力段５の相互コンダクタンスｇｍ（ｎ）は入力信号レベルが０から約１．０Ｖまではゼロで、１．０Ｖを超えると急激に増大し、約１．５Ｖで極大（ｎ１・μＡ／Ｖ）となり、入力信号レベルが１．５Ｖ〜７．５Ｖの間では漸減し、ｎ２・μＡ／Ｖまで低下し、入力信号レベルが約７．５Ｖから約８．０Ｖの間で急増し、入力信号レベル８Ｖで再度極大（ｎ３・μＡ／Ｖ）となり、８Ｖ〜９Ｖではほぼ一定（ｎ３・μＡ／Ｖ）となる。このように相互コンダクタンスｇｍ（ｎ）は入力信号レベルが０から９Ｖの間で、３つの概略平坦部を持った上り階段状の軌跡を描く。
【００２１】
次に第２差動入力段９の相互コンダクタンスｇｍ（ｐ）は入力信号レベルが０では極大状態のｐ１・μＡ／Ｖで、入力信号レベルが約１Ｖまではあまり変化せずｐ２・μＡ／Ｖとなる。入力信号レベルが１〜１．５Ｖの間は急減してｐ３・μＡ／Ｖとなるが、入力信号レベルが１．５〜約７．５Ｖの間は漸増して再度極大（ｐ４・μＡ／Ｖ）となり、その後入力信号レベルが８Ｖまでの間に急減して、入力信号レベル８〜９Ｖでは相互コンダクタンスは０となる。このように相互コンダクタンスｇｍ（ｐ）は入力信号レベルが０から９Ｖの間で３つの概略平坦部を有する下り昇階段状の軌跡を描く。
【００２２】
上記各差動入力段５、９に供給される入力信号レベルによって、差動入力段を構成する各ＭＯＳＦＥＴ１、６の一方のＦＥＴが遮断状態となり、相互コンダクタンスが０の領域となっても、他のＦＥＴの相互コンダクタンスは中間入力信号レベル領域の相互コンダクタンス値より大きい再極大領域にあるため、各相互コンダクタンスｇｍ（ｎ）、ｇｍ（ｐ）を合成した合成相互コンダクタンスｇｍ（ｎ＋ｐ）は、入力信号レベルの全領域で高ｇｍにでき、しかも平坦なｇｍ特性を実現でき、これにより入力信号レベルの高レベル領域や低レベル領域での負荷駆動能力が向上し、高速スイッチング、高スルーレートの差動増幅器を実現できる。
【００２３】
尚、本発明は上記実施例にのみ限定されることなく、例えば、第１、第２の定電流回路１０、１４のバイアス素子１３、１７として抵抗だけでなく半導体素子に置換することもできる。また、第１、第２のカレントミラー回路２３、２４のをそれぞれ構成する一対のトランジスタは電流容量を等しくするだけでなく、異なる電流容量とすることもできる。
【００２４】
【発明の効果】
以上のように本発明によれば、差動入力段の相互コンダクタンスを入力信号の入力信号レベル全域にわたって高く平坦にできるため、負荷駆動能力が向上し、これによりスイッチング速度を高速化でき高スルーレートの差動増幅器を実現できる。
【図面の簡単な説明】
【図１】本発明の実施例を示す差動増幅器の回路図
【図２】本発明による差動入力段の入力信号レベルに対する相互コンダクタンスを示す図面
【図３】増幅器の出力信号波形図
【図４】本発明の前提となる差動増幅器の回路図
【図５】図５回路の差動入力段の入力信号レベルに対する相互コンダクタンスを示す図面
【符号の説明】
１Ａ、１ＢｎＭＯＳＦＥＴ
２Ａ、２Ｂ入力端子
４接地ライン
５、９差動入力段
６Ａ、６ＢｐＭＯＳＦＥＴ
８電源ライン
１０、１４定電流回路
１３、１７バイアス素子（抵抗）
１８出力段
１９、２０相補トランジスタ
２２差動入力段駆動回路
２３、２４カレントミラー回路
２５、２６駆動トランジスタ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a differential amplifier, and more particularly to a differential amplifier with improved driving capability.
[0002]
[Prior art]
The amplifier amplifies the input signal by driving the amplifying element with the power supplied from the power source and outputs it. In the case of a resistive load, the maximum amplitude of the output signal is limited by the power supply voltage and the internal resistance of the amplifying element. As shown by the three solid lines, the output signal S draws a waveform in a voltage range Vmax to Vmin intermediate between the power supply voltage Vdd and the ground voltage Vss. On the other hand, in portable electronic circuit devices driven by batteries, such as mobile phones, the maximum amplitude of the output signal is made as close as possible to the power supply voltage in order to increase the power use efficiency by operating at a high power with a low power supply voltage. . The power use efficiency of the amplifier is represented by ((Vmax−Vmin) / (Vdd−Vss)) ² , suppose Vdd is 5V, Vss is 0V, Vmax of the output signal S is 4.6V, and Vmin is 0.3V. In some cases, the power usage efficiency is about 74%. However, as shown by the dotted line in the figure, the maximum amplitude is increased, and the power usage efficiency is increased by increasing Vmax to 4.8 V, Vmin to 0.1 V, and the amplitude to 0.4 V. This is about 88% and can be improved by about 14%, and the battery-driven device can be operated for a long time.
[0003]
An example of such an amplifier is shown in FIG. In the figure, 1A and 1B are a pair of one conductivity type (n-channel) MOSFETs, each control electrode (gate electrode) is connected to a pair of input terminals 2A and 2B, and the ground side main electrode (source electrode) is commonly connected. The first differential input stage 5 is configured by being connected to the ground line 4 through the n-channel MOSFET 3. 6A and 6B are a pair of other conductivity type (p-channel) MOSFETs, each control electrode (gate electrode) is connected to a pair of input terminals 2A and 2B, and the power source side main electrode (source electrode) is connected in common. The second differential input stage 9 is configured by being connected to the power supply line 8 via the channel MOSFET 7. Reference numeral 10 denotes a first constant current circuit connected between the power supply line 8 and the ground line 4, and a bias element, in the illustrated example, a resistor 13 is connected in series between the two constant current sources 11 and 12. 14 is a second constant current circuit connected between the power supply line 8 and the ground line 4 in the same manner as the first constant current circuit 10, and a resistor 17 as a bias element is provided between the two constant current sources 15 and 16. Connected in series. The other main electrode (drain electrode) of one MOSFET 1A of the first differential input stage 5 is connected to the constant current source 11 of the first constant current circuit 10 and the resistor 13 at the first differential input stage 5. The other main electrode (drain electrode) of the other MOSFET 1B is connected to the connection point between the constant current source 15 of the second constant current circuit 14 and the resistor 17, respectively, and the one MOSFET 6A of the second differential input stage 9 is connected. The other main electrode (drain electrode) is connected to the constant current source 12 of the first constant current circuit 10 and the resistor 13, and the other main electrode (drain electrode) of the other MOSFET 6 </ b> B of the second differential input stage 9. Are connected to the connection point of the constant current source 16 and the resistor 17 of the second constant current circuit 14, respectively. Reference numeral 18 denotes an output stage in which a p-channel MOSFET 19 and an n-channel MOSFET 20 are complementarily connected. The source electrode of the p-channel MOSFET is connected to the power supply line 8, the drain electrode is commonly connected to the drain electrode of the n-channel MOSFET 20, and an output terminal. The source electrode of the n-channel MOSFET 20 is connected to the ground line 4. The control electrodes (gate electrodes) of the MOSFETs 19 and 20 are connected to both ends of the resistor 17 of the second constant current circuit 14. Similar differential amplifiers are disclosed in Patent Document 1 and Patent Document 2, for example.
[0004]
This amplifier controls the bias of the output stage 18 by a pair of n-channel and p-channel MOSFETs 1A, 1B and 6A, 6B that operate complementarily to a common pair of input terminals 2A, 2B. For example, when the input signal level at the input terminal 2A decreases, the drain voltage of one n-channel MOSFET 1A of the first differential input stage 5 increases and the drain voltage of the other MOSFET 1B decreases. At the same time, the drain voltage of one p-channel MOSFET 6A of the second differential input stage 9 rises and the drain voltage of the other MOSFET 6B falls.
[0005]
The drain electrode of the other MOSFET 1B of the first differential input stage 5 and the drain electrode of the other MOSFET 6B of the second differential input stage 9 are connected to both ends of the resistor 17 of the constant current circuit 14, respectively. The p-channel MOSFET 19 connected to the power supply line 8 of the output stage 18 and the n-channel MOSFET 20 connected to the ground line 4 can be controlled by simultaneously changing the voltage across the resistor 17 while maintaining the voltage between the terminals. .
[0006]
When the input signal level at the input terminal 2A increases, contrary to the above, the voltage across the resistor 17 is simultaneously raised while the voltage across the resistor 17 is maintained, and is connected to the power supply line 8 of the output stage 18. In addition, the blocking property of the p-channel MOSFET 19 can be improved, and the conductivity of the n-channel MOSFET 20 connected to the ground line 4 can be improved. In this way, the amplifier shown in FIG. 4 can increase the maximum amplitude of the output signal S from the solid line state shown in FIG. 3 to the dotted line state shown in FIG.
[0007]
[Patent Document 1]
JP-A-6-326529 (pages 4-6, FIG. 1)
[Patent Document 2]
Japanese Patent Laid-Open No. 7-15249 (pages 3 to 4, FIG. 3)
[0008]
[Problems to be solved by the invention]
In the differential amplifier shown in FIG. 4, when the input signal level approaches the voltage Vdd on the high voltage side of the power supply voltage, the p-channel MOSFETs 6A and 6B of the second differential input stage 9 are cut off, and the input signal level is When approaching zero or negative voltage Vss on the low voltage side, the n-channel MOSFETs 1A and 1B of the first differential input stage 5 are cut off. Therefore, the mutual conductance gm viewed from the input terminal 2A is the first difference using the n-channel MOSFET 1A, where the horizontal axis is the input signal level (voltage) and the vertical axis is the mutual conductance (current / voltage) as shown in FIG. When the input signal level is changed from a low voltage (0V) to a high voltage (for example, 9V), the dynamic input stage 5 has a mutual conductance gm (n) of zero on the low voltage side and rapidly increasing around 1V. It monotonously decreases from the portion slightly exceeding 1 V toward the high voltage side.
[0009]
In addition, when the second differential input stage 9 using the p-channel MOSFET 1A changes the input signal level from the high voltage (9V) to the low voltage (0V), the mutual conductance gm (p) becomes a high voltage ( 9V) is zero, suddenly rises around 8V, and monotonically decreases from a voltage slightly below 8V toward the low voltage side.
[0010]
Therefore, the mutual conductance gm (n + p) viewed from the input terminal 2B is a substantially convex curve obtained by combining gm (n) and gm (p), and is high and low in the middle region of the input signal level. At both ends, there is a problem that the gm is low, the load driving capability is lowered, and the variation in mutual conductance is large with respect to the input signal level. The magnitudes of the mutual conductances gm (n) and gm (p) of the differential input stages 5 and 9 can be changed by setting the bias of the transistors 3 and 7 that control the currents of the differential input stages 5 and 9. The low gm generated at both the high and low ends of the input signal level could not be eliminated.
[0011]
[Means for Solving the Problems]
The present invention has been proposed for the purpose of solving the above-mentioned problems. A first differential input stage in which one main electrode of a pair of one-conductivity type transistors is commonly connected and a control electrode of each transistor is connected to a pair of input terminals. A second differential input stage in which one main electrode of a pair of other conductivity type transistors is commonly connected and a control electrode of each transistor is commonly connected to the input terminal, and a first and a second Including a constant current circuit and an output stage composed of a pair of complementary transistors, the other main electrode of each transistor of the first differential input stage is connected to one end of the bias element of the first and second constant current circuits The other main electrodes of the transistors of the second differential input stage are connected to the other ends of the bias elements of the first and second constant current circuits, respectively, and the complementary transistors of the output stage are controlled. The electrode is connected to the second constant current circuit. In the differential amplifier connected to both ends of the current element, the first and second current mirror circuits are arranged on the power supply line side and the ground line side, and the first and second drives are provided in the two current paths of each current mirror circuit. A transistor is inserted, the power supply line side electrode of the first drive transistor is connected to the main electrode connected in common to the second differential input stage, and the ground line side electrode of the second drive transistor is connected to the first differential input stage. The control electrode of the first drive transistor at the power line side end of the bias element of the second constant current circuit, and the control electrode of the second drive transistor at the second constant current circuit. There is provided a differential amplifier characterized by being connected to each end of the bias element on the ground line side.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
The differential amplifier according to the present invention includes the first and second differential circuits by adding a differential input stage driving circuit including first and second current mirror circuits and first and second driving transistors. The immobile state is eliminated in the input signal level region of the input stage, and the mutual conductance gm can be maintained high in the entire region of the input signal level. When the transistor of the first differential input stage is configured by an n-channel MOSFET and the transistor of the second differential input stage is configured by a p-channel MOSFET, the first current mirror circuit on the power supply line side and the first drive The transistor can be constituted by a p-channel MOSFET, and the second current mirror circuit on the ground line side and the second drive transistor can be constituted by an n-channel MOSFET. The magnitude of the mutual conductance gm can be adjusted by making the currents flowing through the two current paths of the first and second current mirror circuits different.
[0013]
【Example】
An embodiment of the present invention will be described below with reference to FIG. In the figure, the same parts as those in FIG. That is, the first differential input stage 5 including the n-channel MOSFETs 1A and 1B has one main electrode (source electrode) connected in common, and is connected to the ground line 4 via the n-channel MOSFET 3. The second differential input stage 9 composed of p-channel MOSFETs 6A and 6B has one main electrode (source electrode) connected in common and is connected to the power supply line 8 via the p-channel MOSFET 7. The control electrodes (gate electrodes) of the MOSFETs 1A, 6A and 1B and 6B of the differential input stages 5 and 9 are connected to a pair of input terminals 2A and 2B. The first and second constant current circuits 10 and 14 are connected between the power supply line 8 and the ground line 4. The first constant current circuit 10 includes a constant current source 11, a bias element (resistance) 13, and a constant current source 12. The second constant current circuit 14 includes a constant current source 15, a bias element (resistance) 17, and a constant current source 16. Are connected in series, and the other main electrode (drain electrode) of the n-channel MOSFET 1A of the first differential input stage 5 is connected to the resistor 13 and the constant current source 11 and the resistor 13. The other main electrode (drain electrode) of the p-channel MOSFET 6A of the second differential input stage 9 is connected to the connection portion of the current source 12. Further, the other main electrode (drain electrode) of the n-channel MOSFET 1B of the first differential input stage 5 is connected to the constant current source 15 of the second constant current circuit 14 and the resistor 17, and the resistor 17 and the constant current source. The other main electrode (drain electrode) of the p-channel MOSFET 6B of the second differential input stage 9 is connected to the connection portion 16. The control electrodes (gate electrodes) of the complementary transistors 19 and 20 of the output stage 18 are connected to both ends of the resistor 17 of the second constant current circuit 14.
[0014]
The differential amplifier according to the present invention is characterized in that a differential input stage drive circuit denoted by reference numeral 22 and surrounded by a dotted line in the figure is added to the same circuit as that shown in FIG. The differential input stage drive circuit 22 includes two current mirror circuits 23 and 24 arranged on the power supply line 8 side and the ground line 4 side, and the first and second current paths of the current mirror circuits 23 and 24 are respectively connected to the first and second current paths. 2 drive transistors 25 and 26 are inserted, and the first drive transistor 25 has a control electrode (gate electrode) whose drain electrode of the nMOSFET 1B of the first differential input stage 5 (the end portion of the resistor 17 on the power supply line side, The main electrode (source electrode) on the power supply line side of the first drive transistor 25 is connected to the commonly connected source electrode of the second differential input stage 9. Yes. The control electrode (gate electrode) of the second drive transistor 26 is connected to the drain electrode of the pMOSFET 6B of the second differential input stage 9 (the end on the ground line side of the resistor 17 and the gate electrode of the nMOSFET 20 of the output stage 18). The main electrode (source electrode) on the ground line side of the second drive transistor 26 is connected to the commonly connected source electrode of the first differential input stage 5.
[0015]
The operation of this differential amplifier will be described below. Since the operation of the amplifier other than the differential input stage drive circuit 22 is the same as that of the circuit of FIG. In this amplifier, first and second drive transistors 25 and 26 are inserted into two current paths of current mirror circuits 23 and 24 constituting the differential input stage drive circuit 22, and the first drive transistor 25 is the first drive transistor 25. The second drive transistor 26 is opened and closed by detecting the drain voltage of the pMOSFET 6B in the second differential input stage 9 by detecting the drain voltage of the nMOSFET 1B in the differential input stage 5.
[0016]
First, when a low voltage level (L level) signal in the vicinity of the ground line voltage is supplied to the input terminal 2B, the nMOSFET 1B of the first differential input stage 5 is cut off and the pMOSFET 6B of the second differential input stage 9 is turned off. Conduct. When the nMOSFET 1B is cut off, the drain voltage becomes a high voltage level (H level) in the vicinity of the power supply line voltage, so that the first drive transistor 25 is cut off. Therefore, the current supplied from the first current mirror circuit 23 is sent to the source electrode of the second differential input stage 9, and the current sent to the source electrode is output to the drain electrode. On the other hand, since the H-level drain voltage of the second differential input stage 9 is supplied to the gate electrode of the second drive transistor 26, the second differential input stage 9 is turned on from the first current mirror circuit 23. The current value to be supplied to is determined. In this way, when an L level signal is supplied to the input terminal 2B, the nMOSFET 1B of the first differential input stage 5 is cut off. At this time, the mutual conductance gm of the pMOSFET 6B of the second differential input stage 9 is It increases compared with the case where there is no differential input stage drive circuit 22.
[0017]
Next, when an H level signal in the vicinity of the power supply line voltage is supplied to the input terminal 2B, the pMOSFET 6B of the second differential input stage 9 is cut off and the nMOSFET 1B of the first differential input stage 5 is turned on. When the pMOSFET 6B is cut off, the drain voltage becomes L level in the vicinity of the ground line voltage, so that the first drive transistor 26 is cut off. Therefore, the current discharged from the source electrode of the first differential input stage 5 branches to the transistor 3 and the second current mirror circuit 24 connected to the source electrode, and the drain current discharged from the nMOSFET 1B is increased. On the other hand, since the drain voltage of the L level of the first differential input stage 5 is supplied to the gate electrode of the first driving transistor 25, the current value flowing through the second current mirror circuit 24 is determined. When the H level signal is supplied to the input terminal 2B in this way, the pMOSFET 6B of the second differential input stage 9 is cut off. At this time, the mutual conductance gm of the nMOSFET 1B of the first differential input stage 5 is different. It increases compared with the case where there is no dynamic input stage drive circuit 22.
[0018]
When the signal of the intermediate level between the L level and the H level is supplied to the input terminal 2B, the first and second drive transistors 25 and 26 are in a conductive state intermediate between the cutoff state and the saturation conductive state, and thereby become a current mirror circuit. Although the current flows between 23 and 24, the value of the current that flows is limited by the conduction state of the drive transistors 25 and 26. Therefore, the current flows into the second differential input stage 9 and is discharged from the first differential input stage 5. Current value is limited, and the mutual conductance gm is not greatly affected.
[0019]
FIG. 2 shows the mutual conductance gm of the MOSFETs 1B and 6B of the first and second differential input stages 5 and 9 with respect to the input signal level supplied to the input terminal 2B. In the figure, gm (n) indicated by a one-dot chain line is a mutual conductance of the nMOSFET 1B of the first differential input stage 5, gm (p) indicated by a two-dot chain line is a mutual conductance of the pMOSFET 6B of the second differential input stage 9, and a solid line. “Gm (n + p)” indicates the combined mutual conductance of the MOSFETs 1B and 6B.
[0020]
The transconductance gm (n) of the first differential input stage 5 is zero when the input signal level is from 0 to about 1.0 V, increases rapidly when it exceeds 1.0 V, and reaches a maximum at about 1.5 V (n1 · μA / V), the input signal level gradually decreases between 1.5V and 7.5V, decreases to n2 · μA / V, and the input signal level rapidly increases between about 7.5V and about 8.0V. When the input signal level is 8V, the maximum value is again reached (n3 · μA / V), and from 8V to 9V, it becomes almost constant (n3 · μA / V). As described above, the mutual conductance gm (n) draws an up-step-like trajectory having three substantially flat portions when the input signal level is between 0 and 9V.
[0021]
Next, the mutual conductance gm (p) of the second differential input stage 9 is p1 · μA / V which is a maximum state when the input signal level is 0, and does not change much until the input signal level is about 1V, and p2 · μA / V. It becomes. When the input signal level is 1 to 1.5V, it suddenly decreases to p3 · μA / V, but when the input signal level is 1.5 to about 7.5V, it gradually increases and becomes maximum again (p4 · μA / V). After that, the input signal level rapidly decreases to 8V, and the transconductance becomes 0 at the input signal level of 8-9V. Thus, the mutual conductance gm (p) draws a descending step-like trajectory having three substantially flat portions when the input signal level is between 0 and 9V.
[0022]
Depending on the input signal level supplied to each of the differential input stages 5 and 9, one FET of the MOSFETs 1 and 6 constituting the differential input stage is cut off and the mutual conductance is in the zero region. The mutual conductance gm (n + p) obtained by synthesizing the mutual conductances gm (n) and gm (p) is the input signal of High gm can be achieved in all levels, and flat gm characteristics can be realized. This improves load drive capability in high and low levels of the input signal level. High-speed switching and high slew rate differential An amplifier can be realized.
[0023]
Note that the present invention is not limited to the above-described embodiment. For example, the bias elements 13 and 17 of the first and second constant current circuits 10 and 14 can be replaced with semiconductor elements as well as resistors. In addition, the pair of transistors constituting the first and second current mirror circuits 23 and 24 can have not only the same current capacity but also different current capacities.
[0024]
【The invention's effect】
As described above, according to the present invention, the transconductance of the differential input stage can be made high and flat over the entire input signal level of the input signal, so that the load driving capability is improved, thereby increasing the switching speed and the high slew rate. The differential amplifier can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a differential amplifier showing an embodiment of the present invention. FIG. 2 is a diagram showing transconductance with respect to an input signal level of a differential input stage according to the present invention. 4] A circuit diagram of a differential amplifier as a premise of the present invention. [FIG. 5] FIG. 5 is a diagram showing a transconductance with respect to an input signal level of a differential input stage of the circuit.
1A, 1B nMOSFET
2A, 2B Input terminal 4 Ground line 5, 9 Differential input stage 6A, 6B pMOSFET
8 Power supply line 10, 14 Constant current circuit 13, 17 Bias element (resistance)
18 Output stage 19, 20 Complementary transistor 22 Differential input stage drive circuit 23, 24 Current mirror circuit 25, 26 Drive transistor

Claims

A first differential input stage in which a main electrode of a pair of one conductivity type transistors is connected in common and a control electrode of each transistor is connected to a pair of input terminals, and a main electrode of a pair of other conductivity type transistors are connected in common. A second differential input stage having a control electrode of each transistor commonly connected to the input terminal; first and second constant current circuits including a bias element in the middle; and an output stage comprising a pair of complementary transistors In addition, other main electrodes of the transistors of the first differential input stage are respectively connected to one ends of the bias elements of the first and second constant current circuits, and other transistors of the second differential input stage are connected. Are connected to the other ends of the bias elements of the first and second constant current circuits, and the control electrodes of the complementary transistors in the output stage are connected to both ends of the bias elements of the second constant current circuit. In the differential amplifier,
The first and second current mirror circuits are arranged on the power supply line side and the ground line side, and the first and second drive transistors are inserted into the two current paths of each current mirror circuit. The line side electrode is connected to the commonly connected main electrode of the second differential input stage, the ground line side electrode of the second drive transistor is connected to the commonly connected main electrode of the first differential input stage, and the first The control electrode of the driving transistor is on the power line end of the bias element of the second constant current circuit, and the control electrode of the second driving transistor is on the ground line side end of the bias element of the second constant current circuit, respectively. A differential amplifier characterized by being connected.

2. The differential amplifier according to claim 1, wherein the first differential input stage transistor is an n-channel MOSFET, and the second differential input stage transistor is a p-channel MOSFET.

The first current mirror circuit and the first drive transistor on the power supply line side are each composed of a p-channel MOSFET, and the second current mirror circuit and the second drive transistor on the ground line side are each composed of an n-channel MOSFET. The differential amplifier according to claim 2.

2. The differential amplifier according to claim 1, wherein currents flowing through the two current paths of the first and second current mirror circuits are made different.