JP4856201B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device having a floating gate electrode.

  FIG. 9A is a diagram showing the structure of a nonvolatile memory cell according to a conventional example, and is a cross-sectional view in the word line direction (channel width direction: direction perpendicular to the direction in which channel current flows). A plurality of floating gate electrodes 3 are adjacent to each other at a predetermined distance on the silicon substrate 1 with the tunnel insulating film 2 interposed therebetween. An element isolation insulating film 4 is buried between the lower portions of the floating gate electrodes 3. Further, part of the side surface and the upper surface of each floating gate electrode 3 and the upper surface of the element isolation insulating film 4 are covered with the control gate electrode 6 with the interelectrode insulating film 5 interposed therebetween.

  FIG. 9B is a diagram showing the structure of the nonvolatile memory cell, and is a cross-sectional view in the bit line direction (channel length direction: direction in which channel current flows). A plurality of cell diffusion layers 7 are formed on the surface of the silicon substrate 1. The floating gate electrode 3, the interelectrode insulating film 5, and the control gate are sandwiched between the diffusion layers 7 with the tunnel insulating film 2 interposed therebetween. A plurality of stacked cells CE composed of electrodes 6 are adjacent to each other at a predetermined distance. An interlayer insulating film 8 is buried between the stacked cells CE.

  As shown in FIG. 9B, the floating gate electrodes 3 and 3 adjacent in the bit line direction (channel length direction) are opposed to each other with the interlayer insulating film 8 interposed therebetween. As the memory cell is miniaturized, the facing distance is shortened, and the stray capacitance C between the facing surfaces of the adjacent floating gate electrodes 3 and 3 is increased. For this reason, the write / erase state of the adjacent cell affects the operation characteristics of the cell of interest, and so-called interference between adjacent cells occurs, causing a memory malfunction.

  Further, as shown in FIG. 9A, the width of the control gate electrode embedded between the floating gate electrodes 3 and 3 adjacent in the word line direction (channel width direction) It becomes narrower with the development. Normally, since the buried portion of the control gate electrode is made of a semiconductor containing a dopant impurity, depletion occurs in the buried portion when a high electric field is applied such as during a write / erase operation. For this reason, a decrease in the electric capacity between the control gate electrode 6 and the floating gate electrode 3 cannot be ignored, causing a malfunction of the memory cell. In addition, when depletion occurs in the buried portion, the electrical shielding effect between the floating gate electrodes 3 and 3 on both sides of the buried portion is lowered, so that the probability of memory malfunction due to interference between adjacent cells is increased.

  In Patent Document 1, a convex element formation region is provided on the substrate surface which is separated from each other by a separation groove and whose upper end is rounded, and a tunnel film, an FG electrode, a capacitor insulating film, and a GC electrode are provided thereon. A formed EEPROM is disclosed.

  In Patent Document 2, a separation groove is provided in the FG electrode in a self-aligned manner, and after the entire surface is oxidized, the separation groove is filled with an insulating film, and the surface is retreated to expose the side surface of the FG electrode. An EEPROM manufacturing method is disclosed in which a second interelectrode insulating film is formed on the entire surface, and further a CG electrode is formed.

JP-A-8-88285 JP-A-11-177066

  An object of the present invention is to provide a method of manufacturing a semiconductor device that avoids a malfunction of a memory cell due to interference between adjacent memory cells.

According to one embodiment of the present invention, there is provided a method for manufacturing a semiconductor device including a plurality of impurity-doped polycrystalline silicon having an upper region and side portions in a channel width direction on a semiconductor substrate with a tunnel insulating film interposed therebetween. Forming a floating gate electrode, forming an element isolation insulating film between the floating gate electrodes facing each other, and covering a part of the side portion of the floating gate electrode with the element isolation insulating film; The exposed insulating layer portion of the floating gate electrode and the exposed insulating layer portion of the element isolation insulating film are subjected to radical oxidation reaction in an oxidizing atmosphere containing oxygen radicals, so that the first insulating film serving as the lowermost layer of the interelectrode insulating film simultaneously with forming a radical oxidation film on the floating gate electrode as, the channel width direction of the width of the upper region of the floating gate electrode, Ji lower region of said floating gate electrode Narrower than the width of the channel width direction, and, at the bottom of a portion of the radical oxide film formed to straddle over the extension of the interface of the lower region and the device isolation insulation film of the floating gate electrode, the floating a step of interposing between the upper region of the side and the side of the device isolation insulation film of the gate electrode, on the insulating film, partially embedded between the floating gate electrode facing each other And a step of forming a control gate electrode having a semiconductor in which the buried portion contains a dopant impurity .

  According to the present invention, it is possible to provide a method of manufacturing a semiconductor device that avoids a malfunction of a memory cell due to interference between adjacent memory cells.

The figure which shows the structure of the non-volatile memory which concerns on 1st Embodiment. 1 is a diagram showing a structure of a nonvolatile memory cell according to a first embodiment. Sectional drawing which shows the modification of the non-volatile memory cell of 1st Embodiment. Sectional drawing which shows the modification of the non-volatile memory cell of 1st Embodiment. The figure which shows the manufacture procedure of the non-volatile memory cell which concerns on 1st Embodiment. The figure which shows the manufacture procedure of the non-volatile memory cell which concerns on 1st Embodiment. The figure which shows the manufacturing procedure of the non-volatile memory cell which concerns on 2nd Embodiment. The figure which shows the manufacturing procedure of the non-volatile memory cell which concerns on 3rd Embodiment. The figure which shows the structure of the non-volatile memory cell which concerns on a prior art example.

(First embodiment)
FIGS. 1A and 1B are diagrams showing a configuration of a nonvolatile memory (NAND flash memory) which is a semiconductor device according to the first embodiment of the present invention. FIG. 1A is a plan view of a memory cell of a NAND flash memory, and FIG. 1B is an equivalent circuit diagram of the memory cell.

  1A and 1B, M1 to M8 are nonvolatile memory cell portions, S1 and S2 are selection transistor portions, CG1 to CG8 (word lines) are control gates, SG1 and SG2 are selection gates, BL1 and BL2 indicates a bit line, and Vss indicates a source voltage.

  FIG. 2 is a diagram showing the structure of the nonvolatile memory cell according to the first embodiment of the present invention, and is a cross-sectional view in the word line direction (channel width direction).

  A plurality of floating gate electrodes 3 are adjacent to each other at a predetermined distance on the silicon substrate 1 with the tunnel insulating film 2 interposed therebetween. Each floating gate electrode 3 has an upper width narrower than a lower width. The element isolation insulating film 4 is buried between the adjacent floating gate electrodes 3 and 3 up to the position in the height direction of the wide region below the floating gate electrode 3. Further, the control gate electrode 6 is covered on the floating gate electrode 3 and the element isolation insulating film 4 with the interelectrode insulating film 5 interposed therebetween. A part of the control gate electrode 6 is buried between adjacent floating gate electrodes 3 and 3.

  In this memory cell structure, as compared with the conventional structure shown in FIG. 9A, the facing area (the area of the interelectrode insulating film 5) between the floating gate electrode 3 and the control gate electrode 6 is ensured. The area of the side surface of the floating gate electrode 3 orthogonal to the line direction (channel length direction) can be reduced. Therefore, the parasitic capacitance between the floating gate electrodes 3 and 3 adjacent to each other in the bit line direction (channel length direction) is reduced while securing the coupling ratio of the memory cell and suppressing the increase in the cell operating voltage. The occurrence rate of malfunctions can be reduced.

  In this memory cell structure, the width W1 of the upper portion of the buried portion of the control gate electrode 6 is subtracted twice the film thickness W3 of the interelectrode insulating film 5 from the minimum interval W2 of the floating gate electrodes 3 and 3 facing each other. It is wider than the width. Therefore, when the buried portion of the control gate electrode 6 is made of a semiconductor containing a dopant impurity, the dopant can be sufficiently diffused to the bottom surface portion of the control gate electrode 6. As a result, depletion is unlikely to occur in the buried portion when a high electric field is applied as in the write / erase operation. For this reason, it is possible to avoid a malfunction of the memory cell due to a decrease in electric capacity between the control gate electrode 6 and the floating gate electrode 3. Further, it is possible to avoid a memory malfunction due to a decrease in the electrical shield effect between the adjacent floating gate electrodes 3 and 3.

  FIG. 3 is a sectional view showing a modification of the nonvolatile memory cell according to the first embodiment. In this modification, the element isolation insulating film 4 is buried between adjacent floating gate electrodes 3 and 3 up to a position in the height direction where the width of the floating gate electrode 3 becomes narrow. In this memory cell structure, depletion of the buried portion of the control gate electrode 6 described above is less likely to occur, so that the memory malfunction rate due to depletion can be further reduced.

  2 and 3, the position in the height direction where the width of the floating gate electrode 3 becomes narrow may be anywhere, but a position as close to the tunnel insulating film 2 as possible is preferable because the effect is greater. Further, the width of the floating gate electrode 3 is not limited to one step as shown in FIGS. 2 and 3, but may be changed in two steps in the height direction as shown in FIG. You may change in three steps or more.

  FIGS. 5A to 5D and FIG. 6A and FIG. 6B are diagrams showing a manufacturing procedure of the nonvolatile memory cell according to the first embodiment. 2 will be described with reference to FIGS. 5A to 5D and FIGS. 6A to 6B. 5A to 5D are cross-sectional views of the nonvolatile memory cell in the word line direction (channel width direction). 6A and 6B, a cross-sectional view in the bit line direction (channel length direction) of the nonvolatile memory cell is shown on the left side, and a cross-sectional view in the word line direction (channel width direction) of the nonvolatile memory cell is shown on the right side. ing.

  First, as shown in FIG. 5A, a tunnel insulating film 102 having a thickness of 10 nm is formed on the surface of a silicon substrate 101 doped with a desired impurity by a thermal oxidation method, and then a thickness of 150 nm serving as a floating gate electrode. The phosphorus-doped polycrystalline silicon layer 103 is deposited by a low pressure CVD (Chemical Vapor Deposition) method. Thereafter, a stopper film 104 of CMP (Chemical Mechanical Polish) and a mask film 105 of RIE (Reactive Ion Etching) are sequentially deposited by a low pressure CVD method.

  Thereafter, the mask film 105, the stopper film 104, and the upper layer portion of the phosphorus-doped polycrystalline silicon layer 103 are sequentially etched by RIE using a resist mask (not shown). Thereby, the side wall part 201 is formed.

  Next, as shown in FIG. 5B, a silicon oxide film is deposited on the entire surface by a low pressure CVD method, and then the entire surface RIE is performed. At this time, the conditions for the entire surface RIE are set so that the sidewall mask film 105a remains on the sidewall 201. Next, as shown in FIG. 5C, the exposed region of the polycrystalline silicon layer 103 and the tunnel insulating film 102 are sequentially etched using the mask film 105 and the sidewall mask film 105a as a mask. The exposed region is etched to form an element isolation trench 106 having a depth of 150 nm. As a result, the shape of the floating gate electrode having a lower width and a narrow upper width was formed.

  Next, as shown in FIG. 5D, a device isolation silicon oxide film 107a having a thickness of 400 nm is deposited on the entire surface by plasma CVD to completely fill the device isolation trench 106. Next, as shown in FIG. Thereafter, the silicon oxide film 107a and the mask film 105 on the surface portion are removed by CMP to planarize the surface. Thereafter, the exposed stopper film 104 is removed by etching with a phosphoric acid solution, and then the exposed surface of the silicon oxide film 107a is removed by etching with a dilute hydrofluoric acid solution. Retract to the position.

  Next, as shown in FIG. 6A, a 15-nm-thick interelectrode insulating film 109 having a three-layer structure composed of a silicon oxide film / silicon nitride film / silicon oxide film is sequentially deposited on the entire surface by a low pressure CVD method. Then, a 100 nm thick conductive layer 110 having a two-layer structure composed of a polycrystalline silicon layer / tungsten silicide layer serving as a control gate electrode is sequentially deposited by a low pressure CVD method, and an RIE mask film 111 is further deposited by a low pressure CVD method. . Thereafter, the mask film 111, the conductive layer 110, the interelectrode insulating film 109, the polycrystalline silicon layer 103, and the tunnel insulating film 102 are sequentially etched by the RIE method using a resist mask (not shown) to form a stacked cell. A slit portion 112 is formed therebetween. Thereby, the shapes of the floating gate electrode 113 and the control gate electrode 114 are determined.

  Next, as shown in FIG. 6B, a silicon oxide film 115 called an electrode sidewall oxide film having a thickness of 10 nm is formed on the exposed surface by a combination of a thermal oxidation method and a low pressure CVD method, and then an ion implantation method is used. Then, a cell diffusion layer 116 is formed, and a BPSG (Boro Phosphosilicate Glass) film 117 serving as an interlayer insulating film is formed by a low pressure CVD method so as to cover the entire surface. Thereafter, a wiring layer or the like is formed by a well-known method to complete the nonvolatile memory cell.

(Second Embodiment)
FIGS. 7A to 7C are diagrams showing a manufacturing procedure of a nonvolatile memory cell which is a semiconductor device according to the second embodiment. Hereinafter, the manufacturing procedure of the memory cell as shown in FIG. 2 will be described with reference to FIGS. 7A to 7C are cross-sectional views in the word line direction (channel width direction).

  First, as shown in FIG. 7A, a tunnel insulating film 102 having a thickness of 10 nm is formed on the surface of a silicon substrate 101 doped with a desired impurity by a thermal oxidation method, and then a thickness of 150 nm serving as a floating gate electrode. The phosphorus-doped polycrystalline silicon layer 103 is deposited by a low pressure CVD method. Thereafter, the phosphorus-doped polycrystalline silicon layer 103 and the tunnel insulating film 102 are sequentially etched by RIE using a resist mask (not shown), and the exposed region of the silicon substrate 101 is further etched to a depth of 150 nm. An element isolation trench is formed.

  Next, an element isolation silicon oxide film 107a having a thickness of 400 nm is deposited on the entire surface by plasma CVD to completely fill the element isolation trench. Thereafter, the surface is planarized by CMP, and the exposed surface of the silicon oxide film 107a is etched away with a diluted hydrofluoric acid solution to expose the side wall surface of the floating gate electrode 103 by 70 nm.

  Next, as shown in FIG. 7B, the exposed surface of the floating gate electrode 103a is retreated by 30 nm by isotropic etching with an alkaline solution. As a result, the floating gate electrode 103a has a wide lower portion and a narrow upper portion. Next, as shown in FIG. 7C, the exposed surface of the silicon oxide film 107a is removed by etching with a diluted hydrofluoric acid solution, and the silicon oxide film 107a is retracted to a height position where the width of the floating gate electrode is wide. .

  Thereafter, by using the method as shown in FIGS. 6A and 6B, the memory cell structure as shown in FIG. 2 is completed.

(Third embodiment)
(A) and (b) of FIG. 8 are diagrams showing a manufacturing procedure of a nonvolatile memory cell which is a semiconductor device according to the third embodiment. Hereinafter, the manufacturing procedure of the memory cell as shown in FIG. 3 will be described with reference to FIGS. 8A and 8B are cross-sectional views in the word line direction (channel width direction).

  First, as shown in FIG. 8A, a tunnel insulating film 102 having a thickness of 7 nm is formed on the surface of a silicon substrate 101 doped with a desired impurity by a thermal oxidation method, and then a thickness of 150 nm serving as a floating gate electrode. The phosphorus-doped polycrystalline silicon layer 103 is deposited by a low pressure CVD method. Thereafter, the phosphorus-doped polycrystalline silicon layer 103 and the tunnel insulating film 102 are sequentially etched by RIE using a resist mask (not shown), and the exposed region of the silicon substrate 101 is further etched to a depth of 150 nm. An element isolation trench is formed.

  Next, an element isolation silicon oxide film 107a having a thickness of 400 nm is deposited on the entire surface by plasma CVD to completely fill the element isolation trench. Thereafter, the surface is planarized by CMP, and the exposed surface of the silicon oxide film 107a is etched away with a diluted hydrofluoric acid solution to expose the side wall surface of the floating gate electrode 103 by 70 nm.

  Next, as shown in FIG. 8B, oxidation is performed at 800 ° C. for 1 hour in an oxygen atmosphere (oxidizing atmosphere) containing 10% of oxygen radicals, and an inter-electrode insulation formed of a radical oxide film having a thickness of 8 nm. A film 109a is formed. As a result, the floating gate electrode 103a has a wide lower portion and a narrow upper portion. The opening width between the inter-electrode insulating films 109a and 109a formed on the side wall surfaces of the adjacent floating gate electrodes 103 and 103 is the film thickness of the inter-electrode insulating film 109a from the minimum distance between the floating gate electrodes 103 and 103. It is wider than the width minus 2 times.

  Thereafter, by using the method as shown in FIGS. 6A and 6B, the memory cell structure as shown in FIG. 3 is completed.

  As shown in FIG. 8C, a CVD oxide film 109b may be deposited after forming the radical oxide film 109a to form a two-layer interelectrode insulating film. In addition, as long as the lowermost layer is formed of a radical oxide film, any insulating film may be formed thereon, or a multilayer may be formed.

  Note that when the interelectrode insulating film 109a or a part thereof is formed by radical oxidation as in this embodiment mode, the interelectrode insulating film 109a can be formed at a relatively low temperature, so that thermal damage to the tunnel oxide film is reduced. As a result, deterioration of the characteristics of the tunnel oxide film can be suppressed. Further, since there is an effect of modifying the surface film quality of the exposed element isolation oxide film, the leakage current between the adjacent floating gate electrodes 103a and 103a can be reduced, and the reliability of the memory cell can be improved.

  Further, as shown in FIG. 8D, when a three-layer interelectrode insulating film composed of the silicon oxide film 109a, the silicon nitride film 109c, and the silicon oxide film 109d is formed, the silicon nitride layer 109c is made of ammonia or a single layer. When thermal nitridation is performed in a gas atmosphere containing nitrogen such as oxynitridation, for example, the nitride film thickness can be reduced to about 1 nm, so that the width of the buried portion of the control gate electrode can be increased. The same effect can be obtained even if the silicon nitride film 109c is formed by radical nitriding.

  When the silicon nitride film 109c in FIG. 8D is formed by CVD using hexachlorodisilane and ammonia as source gases, the electron trap density of the silicon nitride film 109c is high. For example, the nitride film thickness is about 1 nm. The thickness can be reduced and the width of the buried portion of the control gate electrode can be increased. Other combinations of source gases can be applied as long as the film forming method has a high electron trap density of the film.

  Further, the silicon nitride film 109c in FIG. 8D may be an alumina film instead of the silicon nitride film. Since the work function difference between the alumina film and the silicon oxide film is larger than the work function difference between the alumina film and the silicon nitride film, for example, the alumina film thickness can be reduced to about 1 nm, and the width of the buried portion of the control gate electrode can be reduced. Can be wider. Any other insulating film material may be used as long as it has a large work function difference from the silicon oxide film.

  According to the embodiment of the present invention, it is possible to prevent a malfunction of a memory cell by reducing a parasitic capacitance between floating gate electrodes adjacent in the bit line direction while securing a coupling ratio of the memory cell and suppressing an increase in operating voltage. Can be avoided. In addition, a malfunction of the memory cell due to depletion of the buried portion of the control gate electrode can be avoided.

  Further, it is possible to avoid malfunction of the memory cell due to depletion of the control gate electrode while suppressing deterioration of the characteristics of the tunnel insulating film. In addition, since there is an effect of modifying the surface film quality of the element isolation insulating film, it is possible to avoid a leak failure between the floating gate electrodes facing each other. In addition, since the interelectrode insulating film can be thinned, a malfunction of the memory cell due to depletion of the control gate electrode can be avoided.

  In addition, this invention is not limited only to the said embodiment, In the range which does not change a summary, it can deform | transform suitably and can be implemented.

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Tunnel insulating film 3 ... Floating gate electrode 4 ... Element isolation insulating film 5 ... Interelectrode insulating film 6 ... Control gate electrode 101 ... Silicon substrate 102 ... Tunnel insulating film 103 ... Polycrystalline silicon layer 103a ... Floating gate Electrode 104 ... Stopper film 105 ... Mask film 201 ... Side wall part 105a ... Side wall mask film 106 ... Element isolation trench 107a ... Silicon oxide film 109 ... Interelectrode insulating film 110 ... Conductive layer 111 ... Mask film 112 ... Slit part 113 ... Floating gate Electrode 114 ... Control gate electrode 115 ... Silicon oxide film 116 ... Cell diffusion layer 117 ... BPSG film 109a ... Interelectrode insulating film 109b ... CVD oxide film 109c ... Silicon nitride film 109d ... Silicon oxide film

Claims (4)

Forming a plurality of floating gate electrodes made of impurity-doped polycrystalline silicon having an upper region and side portions in the channel width direction on a semiconductor substrate with a tunnel insulating film interposed therebetween;
Forming an element isolation insulating film between the floating gate electrodes facing each other, and covering a part of the side portion of the floating gate electrode with the element isolation insulating film;
The exposed surface layer portion of the floating gate electrode and the exposed surface layer portion of the element isolation insulating film are subjected to a radical oxidation reaction in an oxidizing atmosphere containing oxygen radicals, so that the first insulation serving as the lowest layer of the interelectrode insulating film At the same time as forming a radical oxide film as a film on the floating gate electrode, the width in the channel width direction of the upper region of the floating gate electrode is narrower than the width in the channel width direction of the lower region of the floating gate electrode. In addition, a part of the lower portion of the radical oxide film formed so as to straddle the extended line of the interface between the lower region of the floating gate electrode and the element isolation insulating film is formed on the upper region of the floating gate electrode. Interposing between the side portion and the side portion of the element isolation insulating film ;
Forming a control gate electrode having a portion of the buried floating gate electrode facing each other on the interelectrode insulating film , and the buried portion having a semiconductor containing a dopant impurity ;
A method for manufacturing a semiconductor device, comprising:   A chemical reaction using a gas containing nitrogen is applied to the surface layer portion of the first insulating film to form a second insulating film constituting the interelectrode insulating film on the first insulating film. The method of manufacturing a semiconductor memory device according to claim 1, further comprising a step.   The method further comprises forming a second insulating film constituting the interelectrode insulating film having an electron trap density higher than that of the first insulating film on the first insulating film. Item 14. A method for manufacturing a semiconductor device according to Item 1.   2. The method according to claim 1, further comprising forming a second insulating film having a work function difference from the first insulating film larger than that of the silicon nitride film on the first insulating film. The manufacturing method of the semiconductor device of description.

Images