JPH0936263A - Floating gate nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the ununiformity of tunnel current values between memory cells and, at the same time, to reduce the dielectric breakdown of a gate insulating film and a capacitive coupling insulating film. SOLUTION: A floating gate has a polycrystalline Si layer 31 which is in contact with an SiO2 film 12 constituting a gate insulating film and another polycrystalline Si layer 33 which is in contact with an ONO film 17 constituting a capacitive coupling insulating film and the crystal grain size of the Si layer 31 is smaller than that of the Si layer 33, and then, the impurity concentration in the Si layer 31 is lower than that in the Si layer 33, the ununiformity of impurity concentration in the SiO2 film 12 is small and the growth of crystal grains to projecting states in the Si layer 33 is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating gate type nonvolatile semiconductor memory device having a floating gate between a gate insulating film and a capacitive coupling insulating film.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional example of a floating gate type nonvolatile semiconductor memory device. In this conventional example, as shown in FIG. 2A, the SiO ₂ film 12 on the surface of the Si substrate 11 is a gate insulating film through which a tunnel current should flow, and a polycrystalline Si layer on the SiO ₂ film 12 is formed. 13 is a floating gate.

Further, the ONO film 17 composed of the SiO ₂ film 14, the SiN film 15 and the SiO ₂ film 16 which are sequentially laminated on the polycrystalline Si layer 13 serves as an insulating film for capacitive coupling between the floating gate and the control gate. Has become. Furthermore, the ONO film 17
Polycrystalline Si layer 21 and WSi that are sequentially stacked on top
The tungsten polycide layer 23 formed of the film 22 serves as a control gate, and Si on both sides of the control gate and the like is formed.
The diffusion layers 24 and 25 formed on the substrate 11 serve as a source and a drain, respectively.

By the way, a crystal grain boundary 26 of the polycrystalline Si layer 13 in a portion in contact with the SiO ₂ film 12 is shown in FIG.
As enlargedly shown in (b), the impurities 27 in the polycrystalline Si layer 13 easily segregate at the crystal grain boundaries 26, and the crystal grain boundaries 26
Impurities 27 are also segregated in the SiO ₂ film 12 in the vicinity.

Therefore, if the grain size of the polycrystalline Si layer 13 is large and the grain boundaries 26 are sparsely present, and the concentration of the impurities 27 in the polycrystalline Si layer 13 is high, the grain size of the crystal grains is high. The nonuniformity of the concentration of the impurity 27 in the polycrystalline Si layer 13 due to the segregation of the impurity 27 in the boundary 26 is large, and the nonuniformity of the concentration of the impurity 27 in the SiO ₂ film 12 in contact with the polycrystalline Si layer 13 is large. Is big.

Since a tunnel current easily flows in a portion of the SiO ₂ film 12 where the concentration of the impurities 27 is high, the non-uniformity of the tunnel current value between the memory cells is large and the operation characteristics are poor, and the tunnel current is locally generated. Since the dielectric breakdown of the SiO ₂ film 12 is large due to a large amount of flowing, the reliability is also lowered.

Therefore, conversely, the non-uniformity of the tunnel current value between the memory cells is reduced to improve the operating characteristics, and a large amount of tunnel current locally flows to S.
In order to reduce the dielectric breakdown of the iO ₂ film 12 and enhance the reliability, it is preferable that the crystal grain size of the polycrystalline Si layer 13 is small and the concentration of the impurities 27 in the polycrystalline Si layer 13 is low.

On the other hand, when the surface of the polycrystalline Si layer 13 is thermally oxidized to form the SiO ₂ film 14 of the ONO film 17, the crystal grain size of the polycrystalline Si layer 13 is small and the polycrystalline S layer 13 is small.
When the concentration of the impurities 27 in the i layer 13 is low, a protrusion 28 is formed on the surface of the polycrystalline Si layer 13 as shown in FIG. For this reason, the electric field is concentrated on the protrusion 28, so that the dielectric breakdown of the ONO film 17 increases and the reliability decreases.

Therefore, conversely, in order to reduce the dielectric breakdown of the ONO film 17 due to the concentration of an electric field on the protrusions 28 of the polycrystalline Si layer 13 and improve the reliability, the crystal grains of the polycrystalline Si layer 13 are reduced. It is better that the diameter is large and the concentration of the impurities 27 in the polycrystalline Si layer 13 is high.

That is, the non-uniformity of the tunnel current value between the memory cells is reduced to improve the operation characteristics and S
The conditions required for the floating gate in order to reduce the dielectric breakdown of the iO ₂ film 12 and improve the reliability and the conditions required for the floating gate in order to reduce the dielectric breakdown of the ONO film 17 and improve the reliability are as follows: They are in conflict with each other.

[0011]

However, in the conventional example shown in FIG. 2, the floating gate is a polycrystalline Si layer 1 having a single layer.
Since it is composed of only No. 3, it is impossible to simultaneously satisfy the above-mentioned contradictory conditions, and it is difficult to obtain excellent operating characteristics and high reliability.

It has been proposed that the floating gate be composed of two poly-Si layers to reduce the crystal grain size of the entire floating gate (for example, Proceedings of Spring Society of Applied Physics, 1995 (No. 2). ) P.833, 31a-H-6), as is clear from the above description, the dielectric breakdown of the capacitive coupling insulating film increases and the reliability decreases.

[0013]

According to another aspect of the present invention, there is provided a floating gate non-volatile semiconductor memory device in which a first polycrystalline semiconductor layer in contact with a gate insulating film and an insulating film for capacitive coupling to a control gate are in contact with each other. The floating gate has a second polycrystalline semiconductor layer, and the crystal grain size of the first polycrystalline semiconductor layer is smaller than the crystal grain size of the second polycrystalline semiconductor layer,
The impurity concentration of the first polycrystalline semiconductor layer is lower than the impurity concentration of the second polycrystalline semiconductor layer.

The floating gate non-volatile semiconductor memory device according to a second aspect is the floating gate non-volatile semiconductor memory device according to the first aspect, wherein the second polycrystalline semiconductor layer to the first
Is characterized in that diffusion of impurities into the polycrystalline semiconductor layer is suppressed and an non-insulating interlayer film is provided between the first and second polycrystalline semiconductor layers.

A floating gate non-volatile semiconductor memory device according to a third aspect is the floating gate non-volatile semiconductor memory device according to the second aspect, wherein the polycrystalline Si layer is the first and second polycrystalline semiconductor layers. And Si through which tunnel current can flow
It is characterized in that the O ₂ film is the interlayer film.

In the floating gate type nonvolatile semiconductor memory device according to the first aspect, since the crystal grain boundaries are densely present and the impurity concentration itself is low in the first polycrystalline semiconductor layer of the floating gate, The nonuniformity of the impurity concentration due to the segregation of impurities at the crystal grain boundaries is small.

Therefore, the nonuniformity of the impurity concentration is small even in the gate insulating film in contact with the first polycrystalline semiconductor layer, and the nonuniformity of the tunnel current value depending on the position in the gate insulating film is small. Therefore, the nonuniformity of the tunnel current value between the memory cells is small, and the dielectric breakdown due to the local large amount of tunnel current flowing is small.

Further, in the second polycrystalline semiconductor layer of the floating gate, since the crystal grain size is large and the impurity concentration is high, an insulating film for capacitive coupling which is in contact with the second polycrystalline semiconductor layer is formed. At this time, the growth of crystal grains in the second polycrystalline semiconductor layer is suppressed. Therefore, the dielectric breakdown of the capacitive coupling insulating film due to the concentration of the electric field on the protrusions of the second polycrystalline semiconductor layer is small.

In the floating gate non-volatile semiconductor memory device according to a second aspect of the present invention, the interlayer film for suppressing the diffusion of impurities is provided between the first and second polycrystalline semiconductor layers of the floating gate. It is possible to easily maintain the impurity concentration on the gate insulating film side of the gate lower than the impurity concentration on the capacitive coupling insulating film side. Moreover, since the interlayer film is non-insulating, the interlayer film does not affect the operation.

In the floating gate type non-volatile semiconductor memory device of the third aspect, both the first and second polycrystalline semiconductor layers and the interlayer film can be easily formed, and in particular, the interlayer film is the first layer. Since the polycrystalline semiconductor layer can be easily formed by thermal oxidation, the CVD method, or the like, the floating gate can be easily formed.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION A specific example of the present invention will be described below.
This will be described with reference to FIG. Also in this example, except that the floating gate is composed of the polycrystalline Si layer 31, the SiO ₂ film 32, and the polycrystalline Si layer 33 that are sequentially stacked on the SiO ₂ film 12 that is a gate insulating film. 2 has a configuration substantially similar to that of the conventional example shown in FIG. The film thickness, crystal grain size and impurity concentration of the polycrystalline Si layers 31, 33 and the SiO ₂ film 32 are as follows.

Polycrystalline Si layer 31 Film thickness 15 nm Crystal grain size 20 nm Impurity concentration Phosphorus: 5 × 10 ¹⁹ cm ⁻³

SiO ₂ film 32 film thickness 5 nm

Polycrystalline Si layer 33 Film thickness 20 nm Crystal grain size 300 nm Impurity concentration Phosphorus: 3 × 10 ²⁰ cm ^-3

The crystal grain size of the polycrystalline Si layers 31 and 33 is C
First, an amorphous Si layer is deposited by the VD method.
It can be controlled by solid phase growth of grains from the layer. Further, the impurity concentration of the polycrystalline Si layers 31 and 33 is controlled by diffusing or ion-implanting the impurities after the deposition, adding the impurities from the time of deposition by the CVD method, or the like.

The SiO ₂ film 32 is formed by thermally oxidizing the surface of the polycrystalline Si layer 31 or depositing it by the CVD method.
The film thickness of 5 nm of the SiO ₂ film 32 is a film thickness capable of suppressing the diffusion of phosphorus from the polycrystalline Si layer 33 having a high phosphorus concentration to the polycrystalline Si layer 31 having a low phosphorus concentration. The film thickness is such that a tunnel current can flow between the polycrystalline Si layer 31 and the polycrystalline Si layer 33.

In this specific example, the polycrystalline Si layer 31 is used.
Has a small crystal grain size and a low impurity concentration, the non-uniformity of the tunnel current value between the memory cells is small and the operating characteristics are excellent, and a large amount of tunnel current locally flows in the SiO ₂ film 12. Low dielectric breakdown and high reliability.

Moreover, since the crystal grain size of the polycrystalline Si layer 33 is large and the impurity concentration is high, the surface of the polycrystalline Si layer 33 is thermally oxidized to form the SiO ₂ film 14 of the ONO film 17. It is difficult to form a protrusion on the surface of the polycrystalline Si layer 33, and the electric field is concentrated on the protrusion to turn on.
The reliability is high because the dielectric breakdown of the O film 17 is small.

The polycrystalline Si layers 31, 33 and SiO
_The film thickness, the crystal grain size, and the impurity concentration of the _second film 32 may be values other than those described above, and in particular, the polycrystalline Si layer 31 may not contain any impurities.

[0030]

According to the floating gate type nonvolatile semiconductor memory device of the present invention, since the nonuniformity of the tunnel current value between the memory cells is small, the operating characteristics are excellent, and moreover,
Since the gate insulating film and the insulating film for capacitive coupling have a small dielectric breakdown, the reliability is high.

In the floating gate type nonvolatile semiconductor memory device of the present invention, the impurity concentration on the gate insulating film side of the floating gate is higher than the impurity concentration on the capacitive coupling insulating film side without affecting the operation. Since it can be easily maintained in a low state, excellent operating characteristics and high reliability can be easily maintained.

In the floating gate type non-volatile semiconductor memory device according to the present invention, since the floating gate can be easily formed, the floating gate type nonvolatile semiconductor memory device is manufactured at a low cost in spite of excellent operating characteristics and high reliability. be able to.

[Brief description of drawings]

FIG. 1 is a side sectional view of a specific example of the present invention.

2A and 2B show a conventional example of the invention of the present application, in which FIG. 2A is a side sectional view and FIG. 2B is an enlarged side sectional view of a main part.

[Explanation of symbols]

12 SiO ₂ film 17 ONO film 23 Tungsten polycide layer 31 Polycrystalline Si layer 32 SiO ₂ film 33 Polycrystalline Si layer

Claims (3)

[Claims] 1. The floating gate has a first polycrystalline semiconductor layer in contact with the gate insulating film and a second polycrystalline semiconductor layer in contact with the capacitive coupling insulating film for the control gate. The crystal grain size of the first polycrystalline semiconductor layer is smaller than the crystal grain size of the second polycrystalline semiconductor layer, and the impurity concentration of the first polycrystalline semiconductor layer is the impurity of the second polycrystalline semiconductor layer. A floating gate type nonvolatile semiconductor memory device characterized by being lower than the concentration. 2. The first polycrystalline semiconductor layer to the first polycrystalline semiconductor layer
2. A non-insulating interlayer film is provided between the first and second polycrystalline semiconductor layers while suppressing diffusion of impurities into the polycrystalline semiconductor layer.
A floating gate type nonvolatile semiconductor memory device as described. 3. The polycrystalline Si layer is the first and second polycrystalline semiconductor layers, and the SiO ₂ film through which a tunnel current can flow is the interlayer film. A floating gate type nonvolatile semiconductor memory device as described.