JP4855348B2 - Encoder and decoder, transmitter and receiver - Google Patents

Description

  The present invention relates to error correction coding for digital transmission for wideband transmission, and more particularly to a forward error correction (FEC) type encoder and decoder, and a transmission apparatus and reception apparatus.

  As a powerful error correction code having a performance approaching the Shannon limit, an LDPC (Low Density Parity Check) code was proposed by Gallagher in 1962 (see, for example, Non-Patent Document 1).

  The LDPC code is a linear code defined by a very sparse check matrix H (the elements of the check matrix are 0 and 1 and the number of 1 is very small). An encoding method of the LDPC code will be described. The LDPC code is a linear code, and the relationship of Expression (1) is established among the code word C, the information vector m, and the generator matrix G.

In general, in the linear code, the relationship of Expression (2) is established among the generator matrix G, the check matrix H, and the transposed matrix T.

  By preparing a very sparse check matrix H in advance, obtaining the generator matrix G from Equation (2), and using Equation (1), it is possible to obtain an LDPC-encoded codeword. LDPC codes are classified into regular LDPC codes in which row weights and column weights in the check matrix are constant, and non-regular LDPC codes that are not constant. Various configuration methods have been proposed for the configuration of a parity check matrix used in an LDPC code. A regular LDPC code with column weight 3 has good decoding performance, and a non-regular LDPC code with optimized row / column weights is regular LDPC. It has been reported that decoding performance is better than that of codes (see Non-Patent Document 2, for example).

  FIG. 5 shows an example of a check matrix for a regular LDPC code having a row weight of 4 and a column weight of 3. Also, an LDGM (Low Density Generation Matrix) structure has been proposed that allows a codeword to be obtained directly from a parity check matrix by making the submatrix of the parity check matrix H a lower triangular structure (see Non-Patent Document 3, for example). ).

  The LDPC code is a powerful error correction code that can obtain transmission characteristics approaching the Shannon limit by increasing the code length and using an appropriate check matrix, and is a new European satellite broadcasting standard such as DVB-S2 and broadband wireless access. The LDPC code is also adopted in the standard IEEE 802.16e.

  At present, in order to transmit a wide variety of information in real time, a transmission system that performs time division multiplex transmission of a plurality of types of digital modulation schemes with high coding gain is desired.

R. G. Gallager, “Low-Density Parity-Check Codes,” in Research Monograph series Cambridge, MIT Press, December 1963 D. J. C. MacKay, “Good error-correcting codes based on very sparse matrices,” IEEE Trans. Inform. Theory, vol.45, 1999, p.399−431 M. Rashidpour and S. H. Jamali, “Low-Density Parity-Check codes with Simple Irregular Semi-Random Parity Check Matrix for Finite-Length Applications,” IEEE PIMRC 2003, Proc., September 2003, p.439-443

  Here, based on a frame structure suitable for multiplex transmission, a transmission system that performs time division multiplex transmission of a plurality of types of digital modulation schemes (hereinafter referred to as “multiple modulation / time division multiplex transmission system”, and will be apparent from the following description) Proposed). This multiple modulation / time division multiplexing transmission system handles a multiplexed frame having a huge code length (for example, 44880 bits).

  However, while LDPC codes are used in various transmission systems such as DVB-S2 and IEEE 802.16e, the LDPC codes have different code lengths in various transmission systems, so they are sent in a multi-modulation / time division multiplexing transmission system. There is a difference between the code length of the LDPC code suitable for the amount of information to be used and the code length of the LDPC code used in the conventional standard. Therefore, when the code length of the LDPC code changes, it can be applied to other transmission schemes by adjusting the coding rate by puncture processing or the like, but at the same time, the transmission performance of the LDPC code deteriorates.

  Therefore, in order to perform LDPC coding without degrading the transmission characteristics of the multiple modulation / time division multiplexing transmission system, it is necessary to prepare a parity check matrix of an LDPC code suitable for the frame structure of the transmission system. In this case, in order to obtain a high coding gain of the LDPC code at a specific code length, the position of 1 in the check matrix needs to be appropriately arranged. This is because when a parity check matrix that does not appropriately place 1 at a specific code length is used, a sufficient coding gain cannot be obtained, and this may cause an error floor.

  Further, as a case of the number of one slot assumed in the multiple modulation / time division multiplexing transmission system, when the number of one slot is 44880 bits, the code length corresponding to one slot is 44880 bits. In this case, the size of the parity check matrix is 44880 × 22066 at the coding rate 61/120, and a very large memory space is required for encoding and decoding.

  In order to provide an LDPC coding optimum for a slot structure of a multiple modulation / time division multiplexing transmission system, the present invention improves coding gain at a code length of 48880 bits, suppresses error floor generation, and implements a check matrix It is an object of the present invention to provide an LDPC code encoder and decoder, a transmitting apparatus, and a receiving apparatus that facilitate the expression of the above.

  The present invention generates a parity check matrix used for LDPC encoding from a specific parity check matrix initial value table, thereby enabling encoding with a simple configuration even for an LDPC code having a large code length, and improving the coding gain. By using a parity check matrix initial value table having characteristics that suppress the occurrence of error floors, information transmission is possible even in an environment with a lot of white noise.

  As a means for solving the problem of determining a parity check matrix of an LDPC code that improves the coding gain at a code length of 48880 bits, suppresses the occurrence of error floors, and easily expresses the parity check matrix, code length of 48880 bits is encoded. A parity check matrix of a non-regular LDPC code having a long LDGM structure is used. By using the LDGM structure, it is possible to obtain the codeword directly from the check matrix without calculating the generator matrix. As described above, in the multiple modulation / time division multiplexing transmission system, which will be described later, the code length is as large as 44880 bits, for example, so that the check matrix has a very large structure. In order to solve this problem, in order to determine the position of 1 in the submatrix corresponding to the information length of the parity check matrix (that is, the left side partial matrix of the parity check matrix), the parity check matrix initial values in Tables 1A to 11 described later are used. A method is used in which the position of 1 in the parity check matrix is determined by reading every 374 columns from the top of the table and shifting the initial value read every 374 columns in the column direction. In this way, the parity check matrix is a matrix unique to each coding rate, and one element of the submatrix corresponding to the information length according to the coding rate, using a predetermined parity check matrix initial value table as an initial value. Are arranged at intervals of 374 columns in the column direction. Accordingly, a check matrix having a size of tens of thousands × tens of thousands can be realized from numerical sequences shown in Tables 1A to 11 described later.

  In general, the transmission characteristics of LDPC codes vary greatly depending on the position of 1 in the check matrix. By suitably arranging the row weight of the parity check matrix (the number of 1s in the row direction of the parity check matrix) and the column weight (the number of 1s in the column direction of the parity check matrix), the transmission characteristics can be made closer to the Shannon limit. Become. It is known that if the row weight of the parity check matrix is constant, a parity check matrix having a high coding gain is obtained (see, for example, Non-Patent Document 2), and the column weight is suitably arranged while keeping the row weight constant. A higher coding gain can be obtained. In the present invention, a check matrix in which two or three kinds of column weights are combined while the row weight of a submatrix corresponding to the information length of the check matrix (that is, the left submatrix of the check matrix) is constant at all coding rates. Utilization improves the coding gain of the LDPC code. This is done by using a predetermined parity check matrix initial value table as an initial value and arranging one element of a partial matrix corresponding to the information length according to the coding rate in the column direction at a period of every 374 columns. This can be realized by configuring.

  In addition, one of the causes of transmission characteristic deterioration in the LDPC code is the generation of an error floor. As an error floor generation factor, if the arrangement of 1 included in the check matrix has many shape arrangements of the cycle 4 and the cycle 6 shown in FIG. Therefore, as means for solving this problem, it is possible to obtain a parity check matrix in which cycles 4 and 6 are removed or reduced by suitably arranging values in the parity check matrix initial value table.

  That is, the encoder according to the first aspect of the present invention is an encoder that performs LDPC encoding of predetermined data using at least one check matrix, and the check matrix is unique to each coding rate. 1 element of a submatrix corresponding to the information length corresponding to the coding rate 61/120, with a parity check matrix initial value table defined in advance having a code length of 44880 bits as an initial value. The parity check matrix initial value table (Table 1A), which is referred to as type A among the parity check matrix initial value tables of the coding rate 61/120, is arranged with a period of 374 columns. It consists of a table. The coding rate 61/120 based on the type A parity check matrix initial value table (Table 1A) is expressed as “coding rate 61/120 (A)”.

  Of the parity check matrix initial value tables of the coding rate 61/120, the parity check matrix initial value table (Table 1B) to be referred to as Type B is composed of the following tables. Note that the coding rate 61/120 based on the type B parity check matrix initial value table (Table 1B) is represented as “coding rate 61/120 (B)”.

  Of the parity check matrix initial value tables of the coding rate 61/120, the parity check matrix initial value table (Table 1C) to be referred to as Type C is composed of the following tables. The coding rate 61/120 based on the type C parity check matrix initial value table (Table 1C) is expressed as “coding rate 61/120 (C)”.

  Of the parity check matrix initial value tables of the coding rate 61/120, the parity check matrix initial value table (Table 1D), which is referred to as type D, includes the following tables. The coding rate 61/120 based on the type A parity check matrix initial value table (Table 1D) is represented as “coding rate 61/120 (D)”.

  The encoder according to the second aspect of the present invention is an encoder that performs LDPC encoding of predetermined data using at least one check matrix, and the check matrix is unique to each coding rate. The matrix is a check matrix initial value table predetermined with a code length of 48880 bits, and an element of a submatrix corresponding to the information length corresponding to the coding rate 27/40 is set in the column direction. The parity check matrix initial value table (Table 2) having the coding rate of 27/40 is configured by the following table.

  The encoder according to the third aspect of the present invention is an encoder that performs LDPC encoding of predetermined data using at least one check matrix, and the check matrix is unique to each coding rate. 1 element of a submatrix corresponding to the information length corresponding to the coding rate 89/120, with a parity check matrix initial value table predetermined by a code length of 48880 bits as an initial value. The parity check matrix initial value table (Table 3) having the coding rate of 89/120 is configured by the following table.

  An encoder according to a fourth aspect of the present invention is an encoder that performs LDPC encoding of predetermined data using at least one check matrix, and the check matrix is unique to each coding rate. 1 element of a submatrix corresponding to an information length corresponding to a coding rate of 97/120, using a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. The parity check matrix initial value table (Table 4) having the coding rate of 97/120 is configured by the following table.

  An encoder according to a fifth aspect of the present invention is an encoder that performs LDPC encoding of predetermined data using at least one check matrix, and the check matrix is unique to each coding rate. 1 element of the submatrix corresponding to the information length corresponding to the coding rate 101/120, with a parity check matrix initial value table predetermined with a code length of 48880 bits as an initial value. The parity check matrix initial value table (Table 5) having the coding rate 101/120 is configured by the following table.

  An encoder according to a sixth aspect of the present invention is an encoder that performs LDPC encoding of predetermined data using at least one check matrix, and the check matrix is unique to each coding rate. The matrix is a check matrix initial value table defined in advance with a code length of 48880 bits, and 1 element of the submatrix corresponding to the information length corresponding to the coding rate 7/8 is set in the column direction. The parity check matrix initial value table (Table 6) having a coding rate of 7/8 is composed of the following tables.

  An encoder according to a seventh aspect of the present invention is an encoder that performs LDPC encoding of predetermined data using at least one check matrix, and the check matrix is unique to each coding rate. 1 element of a submatrix corresponding to an information length corresponding to a coding rate of 11/40, with a parity check matrix initial value table defined in advance with a code length of 44880 bits as an initial value. The parity check matrix initial value table (Table 7) having a coding rate of 11/40 is configured with the following table.

  An encoder according to an eighth aspect of the present invention is an encoder that performs LDPC encoding of predetermined data using at least one check matrix, and the check matrix is unique to each coding rate. 1 element of the submatrix corresponding to the information length corresponding to the coding rate 41/120, with a parity check matrix initial value table defined in advance with a code length of 48880 bits as an initial value. The parity check matrix initial value table (Table 8A), which is referred to as type A among the parity check matrix initial value tables of the coding rate 41/120, is configured with a period of 374 columns. It consists of a table. Note that the coding rate 41/120 based on the type A parity check matrix initial value table (Table 8A) is represented as “coding rate 41/120 (A)”.

  Of the parity check matrix initial value tables of the coding rate 41/120, the parity check matrix initial value table (Table 8B) to be referred to as Type B is composed of the following tables. The coding rate 41/120 based on the type B parity check matrix initial value table (Table 8B) is represented as “coding rate 41/120 (B)”.

  Of the parity check matrix initial value tables of the coding rate 41/120, the parity check matrix initial value table (Table 8C) to be referred to as type C is composed of the following tables. The coding rate 41/120 based on the type C parity check matrix initial value table (Table 8C) is expressed as “coding rate 41/120 (C)”.

  An encoder according to a ninth aspect of the present invention is an encoder that performs LDPC encoding of predetermined data using at least one check matrix, and the check matrix is unique to each coding rate. 1 element of a submatrix corresponding to an information length corresponding to an encoding rate of 49/120, with a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. The parity check matrix initial value table (Table 9) having the coding rate of 49/120 is configured by the following table.

  An encoder according to a tenth aspect of the present invention is an encoder that performs LDPC encoding of predetermined data using at least one check matrix, and the check matrix is unique to each coding rate. 1 element of a submatrix corresponding to the information length corresponding to the coding rate 73/120, with a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. The parity check matrix initial value table (Table 10) having the coding rate 73/120 is configured by the following table.

  An encoder according to an eleventh aspect of the present invention is an encoder that performs LDPC encoding of predetermined data using at least one check matrix, and the check matrix is unique to each coding rate. The matrix is a check matrix initial value table predetermined with a code length of 48880 bits, and an element of a submatrix corresponding to the information length corresponding to the coding rate 109/120 is set in the column direction. The parity check matrix initial value table (Table 11) having the coding rate 109/120 is configured by the following table.

  Furthermore, a decoder according to the present invention is characterized in that the data encoded by the encoder according to any one of the first to twelfth aspects according to the present invention is subjected to LDPC decoding based on the check matrix.

  A transmission apparatus according to the present invention includes the encoder according to any one of the first to twelfth aspects according to the present invention.

  The receiving device according to the present invention comprises a decoder according to the present invention.

  A transmission device according to a further aspect of the present invention is a transmission device used in a data transmission system that performs time division multiplex transmission of a plurality of types of digital modulation schemes, and includes a plurality of slots including at least data and LDPC encoded parity, In the case of transmitting multiplexed data framed by a plurality of slots based on transmission control information, the transmission control information includes information on the digital modulation scheme and coding rate, and the first to twelfth aspects according to the present invention Any one of the encoders is provided.

  A receiving apparatus according to a further aspect of the present invention is characterized in that data transmitted by the transmitting apparatus according to the further aspect of the present invention is subjected to LDPC decoding based on the check matrix.

  According to still another aspect of the present invention, there is provided a transmission device including an encoder for LDPC encoding a TMCC signal included in a predetermined transmission signal, and a predetermined number of bits before LDPC encoding the TMCC signal by the encoder. First NULL insertion means for inserting a NULL value into two or more predetermined locations for predetermined data of the TMCC signal, and after the TMCC signal is LDPC-encoded by the encoder, the first NULL insertion means And a first NULL deletion means for deleting the NULL values at two or more places inserted by the above and further encoding the TMCC signal.

  According to still another aspect of the present invention, there is provided a transmission apparatus that performs an LDPC code on a TMCC signal included in a predetermined transmission signal based on a parity check matrix generated from a predetermined parity check matrix initial value table predetermined for each coding rate. The encoder according to any one of the first to eleventh aspects, and a NULL value having a predetermined number of bits according to the predetermined parity check matrix initial value table before LDPC encoding the TMCC signal by the encoder. Is inserted into the predetermined data of the TMCC signal at two or more predetermined locations, and the TMCC signal is LDPC-encoded by the encoder and then inserted by the first NULL insertion unit. And a first NULL deletion means for deleting the NULL values at two or more locations and further encoding the TMCC signal.

  In the transmission device according to still another aspect of the present invention, there are two places where a NULL value is inserted by the first NULL insertion means with respect to predetermined data of the TMCC signal.

  In the transmitter according to yet another aspect of the present invention, a TMCC signal included in a predetermined transmission signal is obtained based on a parity check matrix generated from a predetermined parity check matrix initial value table having a coding rate of 61/120. The LDPC encoding of the first mode, and the LDCC encoding of the TMCC signal by the encoder, the NULL value of a predetermined number of bits according to the predetermined parity check matrix initial value table is set to the TMCC First NULL insertion means for inserting predetermined predetermined data of the signal into a plurality of predetermined locations, and a plurality of NULL values inserted by the NULL insertion means after LDPC encoding of the TMCC signal by the encoder And a first NULL deletion unit that further encodes the TMCC signal, and the first NULL insertion unit includes the detection unit. When the matrix initial value table is a table consisting of Table 1A or Table 1D, 2992 bits are added to the head of the predetermined data of the TMCC signal and 10208 bits are added to the rear of the predetermined data of the TMCC signal. When a NULL value is inserted and the parity check matrix initial value table is a table consisting of Table 1B or Table 1C, 1870 bits at the head of the predetermined data of the TMCC signal and a predetermined value of the TMCC signal A NULL value of 11330 bits is inserted at the rear of the data, and the first NULL deleting means deletes the NULL values at the head and rear of the predetermined data of the TMCC signal inserted by the first NULL inserting means. It is characterized in that 31680-bit encoded data is generated.

  According to another aspect of the present invention, there is provided a receiving apparatus that generates an encoded TMCC signal transmitted from a transmitting apparatus according to an aspect of the present invention from a predetermined parity check matrix initial value table predetermined for each coding rate. A decoder that performs LDPC decoding based on the parity check matrix, and before performing LDPC decoding of the TMCC signal by the decoder, a NULL value having the same number of bits as the number of bits inserted by the first NULL insertion unit is set to the first NULL A second NULL inserting means for inserting at the place inserted by the inserting means; and after decoding the TMCC signal by the decoder, the NULL value at the place inserted by the second NULL inserting means is deleted and the TMCC signal is decoded. And a second NULL deletion unit that performs the second NULL insertion unit. Characterized in that the position values inserted at a position above to LDPC decoding as a probability to the NULL value.

  In a transmitting apparatus according to still another aspect of the present invention, a predetermined check matrix initial value table having a coding rate of 61/120 with respect to an encoded TMCC signal transmitted from the transmitting apparatus according to one aspect of the present invention. A decoder that performs LDPC decoding based on a parity check matrix generated from the check matrix, and before the LDCC decoding of the TMCC signal by the decoder, a NULL value having the same number of bits as the number of bits inserted by the first NULL insertion unit is A second NULL inserting means for inserting into the two places inserted by the first NULL inserting means, and after the LDPC decoding of the TMCC signal by the decoder, the NULL values at the two places inserted by the second NULL inserting means are deleted. And a second NULL deletion means for making 31680-bit decoded data, the decoder The value of the inserted position in the two locations is characterized by LDPC decoding as a probability to be NULL value by said first 2NULL insertion means.

  Transmission using time-division multiplexing of a plurality of types of digital modulation schemes as shown in a multi-modulation and time-division multiplexing transmission system by using an encoder and a decoder according to the present invention, or a transmitter and a receiver according to the present invention. In the system, it is possible to transmit information with excellent resistance to white noise.

  Hereinafter, an encoder and a decoder, a transmission device, and a reception device according to the first embodiment of the present invention will be described.

Example 1
First, as a transmission system according to the first embodiment of the present invention, a multi-modulation / time division multiplexing transmission system using a transmission device having an encoder and a reception device having a decoder will be described.

(Multiple modulation / time division multiplexing transmission system)
First, the configuration of a multiplex frame used in the multiple modulation / time division multiplex transmission system according to the first embodiment will be described.

(Multiple frame configuration)
FIG. 1 is a diagram illustrating a configuration of a multiplexed frame used in the multiple modulation / time division multiplexing transmission system according to the first embodiment. The transmission apparatus according to the first embodiment of the present invention (see FIG. 2 and will be described in detail later) designates a transmission scheme and a coding rate by using the multiplex frame configuration shown in FIG. Then, the receiving apparatus according to the first embodiment of the present invention (see FIG. 3 and described in detail later) performs demodulation and decoding of the error correction code based on this frame configuration.

  In this multiple frame configuration, the slot is configured by control information, data, outer code parity, stuff bit, and inner code parity, and the length is Sl bits, and the number of slots constituting one frame is N. In addition to the slots, synchronization, pilot, and TMCC and their error correction parity are also provided, the lengths of which are Sy bits, Pl bits, and T bits, respectively, and slots # 1 to # N / E. In this case, the numbers of bits of Sy × N / E, Pl × N / E, and T × N / E are allocated, respectively.

  Here, the stuff bit is a bit that is inserted only when necessary to facilitate processing in byte units. For this reason, it is not inserted when it is not necessary to facilitate processing in byte units. For example, it is assumed that the number of bits that can be secured as control information is 182 bits, and the data is followed by X bytes. In this case, since the control information is 182 bits = 22 bytes and 16 bits, when trying to process on a byte unit basis, the subsequent byte unit data is purposely shifted by 2 bits and connected to the last 6 bits of the control information. Thus, it is necessary to write back the data, and the receiving device needs to restore this connection and restore the original data in bytes. In such a case, out of the number of bits that can be used for the control information, it is more advantageous in terms of hardware to use 6 stuff bits that are not used for information transmission.

  The multiple frame configuration according to the first embodiment also includes an inner code parity. For this reason, the rule for inserting a dummy slot only needs to consider the frequency utilization efficiency of the digital modulation scheme (hereinafter also simply referred to as a modulation scheme) itself.

  Also, unlike the known multiple frame configuration, as will be described later, the number of dummy slots assigned to the modulation scheme to be used is determined without depending on the coding rate. Note that information for controlling transmission (hereinafter also referred to as transmission control information) is written in the TMCC signal and has a value corresponding to the transmission mode for specifying the transmission mode for each slot. The transmission mode here can be specified as a combination of a modulation method and an inner code coding rate.

  In FIG. 1, N indicates the number of slots per frame. As the actual value of N, the bit rate per slot is about 1.1 Mbps in ISDB-S, and it is desirable to satisfy this condition.

  Therefore, among the modulation scheme groups employed in the transmission system to be configured, the maximum efficiency modulation scheme is 8PSK (3 bps / Hz), 16APSK (or 16QAM, 4 bps / Hz) and 32APSK (or 32QAM, 5 bps / Hz). In this case, the transmission efficiency is 1.5 times, 2 times, and 2.5 times that of ISDB-S TC8PSK (r: 2/3, 2 bps / Hz). It is desirable that slot × 1.5 = 72 slots, 48 slots × 2 = 96 slots, and 48 slots × 2.5 = 120 slots.

  The reason for providing a dummy area under the area of synchronization, pilot, TMCC and its error correction parity is that for the main signal transmitted in the modulation scheme of maximum efficiency among the modulation scheme groups employed. This is because, in general, a low-efficiency modulation scheme is often employed, and an extra modulation symbol is occupied accordingly, so that this time region is secured. Since the dummy area is virtual and data in this area is not actually transmitted, there is no need to equip a corresponding memory area. The value of E that defines the amount of dummy is the ratio of the frequency utilization efficiency of the modulation scheme that transmits these signals to the frequency utilization efficiency of the modulation scheme having the maximum efficiency in the modulation scheme group to be employed. For example, if the modulation scheme having the maximum efficiency is 32APSK (or 32QAM, 5 bps / Hz) and the modulation scheme for transmitting these signals is BPSK (1 bps / Hz) in the modulation scheme group to be adopted, the value of E is 5 Similarly, if the modulation scheme having the maximum efficiency is 16APSK (or 16 QAM, 4 bps / Hz) and the modulation scheme for transmitting these signals is BPSK (1 bps / Hz), the value of E is used. Becomes 4.

  The slot length Sl depends on the code length (code length). In recent years, in the standardized DVB-S2 system, an LDPC code having a code length of 64,800 bits is used, and this class of codes is expected to become mainstream in the future. For this reason, it is desirable that the slot length S1 be approximately the same as the code length (condition 1).

  In addition, MPEG-2TS (packet length 188 bytes, 187 bytes = 1496 bits excluding the first 1 byte synchronization code) will continue to be the mainstream of digital broadcasting, so one slot data will be excessive or insufficient with multiple modulation methods. It is desirable to be able to transmit without any condition (Condition 2).

  In addition, in order to transmit one slot of data with a plurality of modulation schemes without excess or deficiency, it is necessary to be the least common multiple of the number of bits per modulation symbol of each modulation scheme. For example, the modulation schemes employed in the transmission system are BPSK (1 bit / symbol), QPSK (2 bits / symbol), 8PSK (3 bits / symbol), 16APSK (or 16QAM, 4 bits / symbol) and 32APSK (or 32QAM, 5 bits / symbol), the least common multiple is 2 × 2 × 3 × 5 = 60 bits, and the slot length S1 needs to be an integral multiple of this. If the slot length needs to be in bytes, it must be a multiple of 8, and in that case, it must be an integral multiple of the least common multiple 120 of 60 and 8 (condition 3).

  Further, when a periodic LDPC code as used in DVB-S2 is used as an inner code, the period Mt needs to be around 360 for ease of code creation. In addition, since Mt is a factor of 187 bytes of data unit to be transmitted = 23 × 11 × 17 bits, data and LDPC parity can be allocated flexibly, so this condition is satisfied, and Mt = It is desirable that the slot length S1 is an integer multiple of 374 = 2 × 11 × 17 (condition 4).

In order to satisfy the above conditions 2, 3 and 4, when it is not necessary to process in units of bytes, the slot length is set to LCM (374, 60) = LCM (2 × 11 × 17, 2 × 2 × 3 × 5) = 2 × 2 × 3 × 5 × 11 × 17 = 11220 bits (LCM: least common multiple). Furthermore, in order to satisfy the condition 1, it is only necessary to set 11220 × 5 = 56100 and 11220 × 6 = 67320 as numbers similar to 64800. However, since the latter exceeds 2 ¹⁶ −1 = 65535 that can be expressed by 16 bits, there is a possibility that the scale of hardware may increase rapidly, which is not desirable. Therefore, the slot length S1 is desirably 56100 bits. In order to flexibly allocate LDPC parity as data, the sum of the number of bits of control information, outer code parity, and stuff bits (sum of the number of bits of control information and outer code parity when stuff bits are not used) , The same shall apply hereinafter) must be an integral multiple of the LDPC cycle Mt (= 374). If the unit of data to be transmitted is not 187 bytes, for example, 188 bytes, 189 bytes, 190 bytes, and 192 bytes, the LDPC cycle Mt is 376, 378, 380, and 384, and the slot lengths at this time are 62040, 60480, 63840, and 65280, respectively.

  Further, when it is necessary to process in units of bytes, the slot length is LCM (374, 120) = LCM (2 × 11 × 17, 2 × 2 × 2 × 3 × 5) = 2 × 2 × 2 × 3 × What is necessary is just to make it an integral multiple of 5x11x17 = 22440. Further, there are 22440 × 2 = 44880 and 22440 × 3 = 67320 as numbers similar to 64800 in Condition 1, but the latter is not desirable for the same reason. Therefore, it is desirable that the slot length S1 be 44880. In order to flexibly allocate data and LDPC parity, the sum of the control information, the outer code parity, and the number of stuff bits needs to be an integral multiple of the LDPC cycle Mt (= 374). Therefore, hereinafter, a description will be given of a transmitting apparatus and a receiving apparatus in the case of handling a multiple frame structure with a slot length S1 of 48880 so that data of one slot can be efficiently processed in units of bytes with a plurality of modulation schemes.

  Next, the transmission apparatus according to the first embodiment of the present invention will be described.

(Transmitter)
FIG. 2 is a diagram illustrating the configuration of the transmission apparatus according to the first embodiment of the present invention. The transmission apparatus 1 includes a frame generation unit 10, an LDPC encoding unit (hereinafter also referred to as an encoder) 11-1, 11-2, a BCH encoding unit 11-3, 11-4, an energy spreading unit 12, 13, a switch 14, a mapping unit 15, and a time division multiplexing / orthogonal modulation unit 16, and when transmitting a data stream, from generation of the multiplexed frame signal shown in FIG. 1 to generation of a modulated wave signal Perform a series of processing.

  For the slot S1 bit, the frame generation unit 10 controls the control information and data, the outer code parity in which the control information and data are encoded by the BCH encoding unit 11-3, the stuff bit, and the encoder 11-1. Thus, a frame composed of slots # 1 to #N composed of control information, data, and inner code parity in which outer code parity and stuff bits are LDPC-coded is generated and output to the energy spreading unit 12. Also, the frame generation unit 10 generates a BCH parity for the TMCC signal by the BCH encoding unit 11-4, and further generates an LDPC parity by the encoder 11-2. The multiplexed frame generated by the frame generation unit 10 has the number of slots N, E that defines the amount of dummy, slot length Sl, synchronization bit length Sy, pilot bit length Pl, and TMCC and parity bit length T as described above. Generated to be a number.

  The BCH encoders 11-3 and 11-4 are error correction encoding processes provided as necessary as outer codes, and perform BCH encoding on predetermined data. Details of the BCH encoding will be described later.

  The encoders 11-1 and 11-2 perform LDPC encoding with a period Mt on predetermined data or BCH encoded data as inner codes. Details of LDPC encoding using the parity check matrix of encoders 11-1 and 11-2 according to the present invention will be described later.

The energy spreading unit 12 is configured by the slots # 1 to ## generated by the frame generation unit 10.
N is input, and energy diffusion (bit randomization) is performed on the entire data. This is realized by generating pseudo-random “1” and “0” patterns using M-sequences and adding this with the data in the slot by MOD2. As a result, “1” or “0” does not continue, so that synchronization playback can be stabilized in the receiving apparatus described later.

  The energy spreader 13 receives predetermined control information (information in T bits shown in FIG. 1) # 1 to # N / E corresponding to each slot generated by the frame generator 10, and the energy spreader 12 At the same time, energy diffusion (bit randomization) is performed on the entire data.

  The switch 14 switches slots # 1 to #N according to various modulation schemes while appropriately inserting synchronization and pilot signals, and the mapping unit 15 performs mapping according to the modulation scheme designated by TMCC synchronization. The time division multiplexing / orthogonal modulation unit 16 performs time division multiplexing in units of frames, performs orthogonal modulation, and generates a modulated wave signal.

  For example, when the maximum efficiency modulation scheme is 32APSK (or 32QAM), N = 120, E = 5, S1 = 44880, Sy = 120, Pl = 160, T = 1320, the modulated wave signal is equivalent to one frame. Is divided into # 1 to # 120 modulation slots and transmitted (see FIG. 4). In the odd-numbered modulation slot, first, BPSK-modulated slot synchronization Sync1 (24 symbols) and a pilot signal (32 symbols) corresponding to the modulation scheme of the modulation slot are transmitted. Subsequently, the main signal data (136 symbols) multiplexed with video, audio, data broadcasting, etc., modulated by the modulation method specified by the TMCC signal, and the TMCC signal (4 symbols) modulated by BPSK are alternately displayed. It is transmitted 66 times. In the even-numbered modulation slot, first, BPSK-modulated slot synchronization Sync2 (24 symbols) or its inversion pattern! Sync2 (24 symbols) and a pilot signal (32 symbols) corresponding to the modulation scheme of the modulation slot are transmitted. Subsequently, the main signal data (136 symbols) multiplexed with video, audio, data broadcasting, etc., modulated by the modulation method specified by the TMCC signal, and the TMCC signal (4 symbols) modulated by BPSK are alternately displayed. It is transmitted 66 times.

  The sync pattern Sync1, Sync2, and its inverted pattern! Sync2 needs to have a sharp autocorrelation peak itself and a low cross-correlation with each other in order to avoid pseudo-synchronization. As such a code, 0x36715a = 001101100111000101011010 as Sync1, 0x52f866 = 010100101111100001100110 as Sync2, and 0xad0799 = 101011010000011110011001 as the bit inversion pattern! Sync2 enables reception with less pseudo synchronization.

  By repeating such processing for 120 modulation slots, the information written in the TMCC signal is transmitted to the receiving apparatus described later. Even if various transmission controls are performed in the transmission device 1, the reception device 2 can switch the reception method and the like by continuously monitoring the information of the TMCC signal.

  In summary, the transmission apparatus 1 includes at least a frame generation unit 10, LDPC encoding units 11-1 and 11-2, BCH encoding units 11-3 and 11-4, energy spreading units 12 and 13, a switch 14, and a mapping unit. 15 and a time division multiplexing / orthogonal modulation unit 16, and transmission control in which multiplexed data having a frame configuration in which a plurality of slots composed of at least data, outer code parity and inner code parity are collected is written in a transmission control signal Transmit based on information. In this case, by setting the slot length to 44880 bits, it is possible to transmit 187 bytes of information removed from the MPEG-2 TS without excess or deficiency regardless of the modulation scheme. If the unit of data to be transmitted is not 187 bytes, for example, 188 bytes, 189 bytes, 190 bytes, and 192 bytes, the slot lengths at this time are set to 62040, 64260, 64980, and 65280, respectively. Transmission is possible without excess or deficiency regardless of the modulation method. In addition, when the code length is set in units of bytes, the transmission can be performed without excess or deficiency regardless of the modulation method by setting the values to 62040, 60480, 63840, and 65280, respectively.

  Next, the receiving apparatus according to the first embodiment of the present invention will be described.

(Receiver)
FIG. 3 is a diagram illustrating the configuration of the receiving apparatus according to the first embodiment of the present invention. The receiving device 2 includes a channel selection unit 20, an orthogonal detection unit 21, a transmission control signal decoding unit 22, a decoder 23, an energy despreading unit 24, and an outer code decoding unit 25.

  The channel selection unit 20 receives the modulated wave signal from the transmission apparatus 1, selects a channel of a predetermined frequency band, and converts the signal of the channel into a signal of a predetermined frequency handled by the orthogonal detection unit 21. For example, if the modulated wave signal is a satellite broadcast wave, a 12 GHz band broadcast wave (modulated wave signal) is received by a BS antenna, and a 1 GHz band BS-IF signal is transmitted using a known frequency converter (not shown). Convert to

  The quadrature detection unit 21 receives a signal (for example, a BS-IF signal) of a predetermined frequency of the channel selected by the channel selection unit 20 and converts it into a synchronous baseband signal.

  The transmission control signal decoding unit 22 receives the synchronous baseband signal converted by the quadrature detection unit 21, first detects the synchronous byte of the TMCC signal, and uses the BPSK modulated wave that is periodically multiplexed with reference thereto as a reference. The position of a certain phase reference burst signal is also detected. Also, detection of modulation scheme and error correction information transmitted by the TMCC signal is performed here. The information decoded by the transmission control signal decoding unit 22 is input to the decoder 23, the energy despreading unit 24, and the outer code decoding unit 25.

  The decoder 23 is configured as an LDPC decoder, and receives a synchronous baseband signal from the quadrature detection unit 21 and also receives modulation scheme / error correction information detected by the transmission control signal decoding unit 22 and receives TC8PSK modulation. The part is subjected to TC8PSK decoding, and the QPSK or BPSK modulation part is also decoded accordingly. Details of LDPC decoding using the check matrix of the decoder 23 according to the present invention will be described later.

  The energy despreading unit 24 adds the same pseudorandom code again by MOD2 to restore the process in which the pseudorandom code is added by MOD2 in the energy spreading units 12 and 13 of the transmission apparatus 1, and performs the energy despreading process. Do.

  The outer code decoding unit 25 performs decoding on, for example, a signal that has been BCH encoded by the outer code encoding units 11-3 and 11-4 of the transmission apparatus 1.

  As described above, in the first embodiment according to the present invention, the transmission apparatus 1 can cope with an error correction code such as LDPC having a long code length, and can freely set a modulation scheme and a coding rate. Can be combined. Accordingly, MPEG-2TS and other digital data streams can be efficiently transmitted.

  Next, in the above-described multiple modulation / time division multiplexing transmission system, the processing steps of the encoder and decoder, the transmission device and the reception device according to the present invention will be described.

  First, the process of the encoders 11-1 and 11-2 according to the first embodiment will be described.

(Processing of the encoder)
The code length N of the check matrix H is set to 44880. Further, the LDGM structure is applied to the check matrix H. H = [H _A | H _T ], and a matrix in which the column weight is composed of two or three types of values for each coding rate is applied as the partial matrix H _A. H _T is a submatrix having a lower triangular structure shown in FIG. 7, row degree of H _T all remaining rows weights first line is 1 2, the stairs matrix column weight is 2 in all columns is there.

  Hereinafter, the coding rate 61/120 will be described as an example. FIG. 8 shows a basic structure of parity check matrix H of coding rate 61/120 (A). In this case, the information length (N−P) = 22814 and the parity length P = 222066. FIG. 9 shows the information length (left submatrix) and parity length (right submatrix) for each of the coding rates 61/120, 27/40, 89/120, 97/120, 101/120, and 7/8. The relationship is shown.

  FIG. 13 shows a processing block diagram of the LDPC encoder. FIG. 14 is a flowchart showing the processing procedure of the LDPC encoder. As shown in FIG. 13, the LDPC encoders 11-1 and 11-2 include an arithmetic / control unit 11a that can be configured by a central processing unit (CPU) and the like, and a storage unit 11b that can be configured by a memory or a register. . The storage unit 11b stores the above-described parity check matrix initial value tables (Tables 1A to 11), a control program for causing each unit described later to function under the control of the calculation / control unit 11a, data necessary for encoding processing, and the like. Is stored.

  The arithmetic / control unit 11a executes a control program, and provides an LDPC encoder with coding rate determination means, initial value table reading means, check matrix generation means, information bit string reading means, and encoding / parity calculation means. Can function.

  The coding rate determination means reads the coding rate information included in the transmission control information, determines for each multiplex transmission frame, and determines the coding rate to be encoded.

  The initial value table reading unit reads the coding rate determining unit and the parity check matrix initial value table (Tables 1A to 11) corresponding to the determined coding rate from the storage unit 11b.

  Based on the read parity check matrix initial value table, the parity check matrix generation means arranges one element of the partial matrix corresponding to the information length according to the coding rate in the column direction at a period of every 374 columns, and creates a parity check matrix. Generated and stored in the storage unit 11b.

  The information bit string reading means reads the information bit string from the input data.

  The encoding / parity calculation means reads the check matrix generated by the check matrix generation means from the storage unit 11b, calculates a parity bit string corresponding to the information bit string read by the information bit string reading means based on a predetermined formula, Is generated.

  Furthermore, the LDPC encoder executes a control program such as a control unit for sending an LDPC-encoded signal by the encoding / parity calculation unit to the energy spreading unit, or a control unit for performing various calculations described later. This can be realized.

  The specific processing operation of the LDPC encoders 11-1 and 11-2 will be described in more detail with reference to FIG. The processing of the encoders 11-1 and 11-2 will be described with respect to steps S101 to S106.

  In step S101, a predetermined coding rate is determined by the coding rate determination means. For example, it is set to perform LDPC encoding using a parity check matrix with an encoding rate of 61/120.

  In step S102, a predetermined parity check matrix initial value table (Tables 1A to 11) corresponding to the coding rate determined in step S101 is read from the storage unit 11b by the initial value table reading unit. It is assumed that the encoders 11-1 and 11-2 read a parity check matrix initial value table stored in a predetermined memory area (not shown) in the storage unit 11b. In the case of FIG. 8, since the coding rate is 61/120, the parity check matrix initial value table in Table 1A is used. An explanatory diagram of the parity check matrix initial value table is shown in FIG.

  Next, the operation of the check matrix generation means of the encoders 11-1 and 11-2 will be described in detail. The parity check matrix initial value table is 1 + 374 × 0th column from the top and 1 + 374 × 1 column from the top by the number of column weights of the column having 1 row number in the column direction of the parity check matrix (the first value of the row number is 0). First, 1 + 374 × 2 columns,..., 1 + 374 × k columns. The value of k varies depending on the coding rate. In the case of the coding rate 61/120, k = 60. The relationship of Expression (3) is established between the information length (N−P) and k.

  In the case of Table 1A of the coding rate 61/120, the column weight of the parity check matrix is composed of two types of values: 12 from the first column to the 7106th column, and 3 from the 7107th column to the 22814th column. Focusing on the column weight 12 portion of the parity check matrix initial value table, 7106 = 374 × 19, and therefore, the column from the top to the 19th row corresponds to the column weight 12. Similarly, since 22814-7106 = 374 × 42, the 20th to 61st rows correspond to the column weight 3.

In the case of Table 1A, the first row is 1081, 2460, 2617,..., 16466, 18585, which means that the 1st row position of the first column of the parity check matrix is 1081, 2460, 2617,. It shows that it is in the 16466th and 18585th. When these read row numbers are represented by h _i−j , h _1-1 = 1081, h _1-2 = 2460, h _1-3 = 2617,..., H _1-11 = 16466, and h _{1− 12} = 18585. Here, _i in h _i−j is a row number in the parity check matrix initial value table, and _j in h _i− j is a column number in the parity check matrix initial value table. FIG. 11 shows a list of the row / column overlap and the number of columns of each of the partial matrices H _{A at} the coding rates 61/120, 27/40, 89/120, 97/120, 101/120, and 7/8.

Next, using the row number of the parity check matrix described in the first row of the parity check matrix initial value table read from the predetermined memory area and Equation (4), the parity check matrix in the second column to the 374th column of the parity check matrix The row direction element list H _q−j is obtained (q = 2 to 374). H _q−j indicates the row number of 1 in the q column of the check matrix H. _J of H _q-j indicates the order of the number of elements of the column weight. Therefore, for column weight 7, j = 1-7. q = 1 uses the first row of the parity check matrix initial value table.

  Here, mod (x, y) means a remainder obtained by dividing x by y. Q in equation (4) has a different value for each coding rate, and Q is obtained by equation (5).

  In the case of the coding rate 61/120, Q = 59. FIG. 12 shows a list of k corresponding to each information length of coding rates 61/120, 27/40, 89/120, 97/120, 101/120, and 7/8 and Q corresponding to the parity length. Has been.

When the second column (q = 2) of the parity check matrix is calculated according to equation (4),
H _2-1 = mod {(2300 + mod ((2-1), 374) × 59), 22066} = 2359
_{H 2-2 = mod {(2858 +} mod ((2-1), 374) × 59), 22066} = 2917
H _2-3 = mod {(4470 + mod ((2-1), 374) x 59), 22066} = 4529
H _2-4 = mod {(6268 + mod ((2-1), 374) x 59), 22066} = 6327
H _2-5 = mod {(6454 + mod ((2-1), 374) × 59), 22066} = 6513
H _2-6 = mod {(15878 + mod ((2-1), 374) x 59), 22066} = 15937
H _2-7 = mod {(17242 + mod ((2-1), 374) × 59), 22066} = 17301
These _H2-1 to _H2-7 are used as the row numbers in the second column of the check matrix. For q = 3 to 374, the calculation according to the equation (4) is also performed, and the row numbers of the check matrix from the first column to the 374th column of the check matrix are obtained.

  In step S103, all the row numbers in the column direction of the parity check matrix are calculated by the above-described method using the second row to the k + 1th row (final row) of the parity check matrix initial value table. As described above, all 1 row numbers in the column direction of the parity check matrix H are determined, and all 1 element positions of the parity check matrix H are determined. The check matrix generation means stores the generated check matrix H in the storage unit 11b.

In step S104, the information bit string reading means reads the information bit string from the input data, and the encoding / parity calculation means reads the check matrix H obtained in step S103 from a predetermined memory area in the storage unit 11b. In step S105, since the parity check matrix H uses the LDGM structure, the parity bit string P (P _{1 to} P ₂₂₀₆₆ ) is sequentially determined by the encoding / parity calculation means using Equation (6).

C _i (i = 1 to 44880) is a code word, and C = [I | P]. Parity bit stream P _i for the information bit sequence I _i is, since it sequentially calculated from the equation (6), it is possible to configure a code word C _i.

In step S106, the encoding / parity calculation means adds the parity bit string P _i (i = 1 to 22066) obtained in step S105 to the information bit string I _i (i = 1 to 22814), and the code word of 1 slot. C _i (i = 1 to 44880) is formed.

  In the case of encoding with other encoding rate conditions, it is possible to perform encoding by the processing in steps S101 to S106 by changing the parity check matrix initial value table. In this way, the parity check matrix is a unique matrix for each coding rate, and corresponds to the information length corresponding to the coding rate with a predetermined parity check matrix initial value table (Tables 1A to 11) as an initial value. 1 elements of the partial matrix to be arranged are arranged in a column direction at a period of every 374 columns. Accordingly, since the encoders 11-1 and 11-2 have a code length of 44880 bits, the case of the code length of 44880 bits in the slot structure shown in the multiple modulation / time division multiplexing transmission system (see FIG. 1). When the encoders 11-1 and 11-2 are applied, encoding can be performed by changing the encoding rate for each slot.

  Subsequently, a process of the transmission apparatus according to the first embodiment will be described.

(Processing of transmitter)
A transmission signal generation process of the transmission apparatus will be described with reference to FIG.

  In step S201, the frame generation unit 10 determines a predetermined modulation scheme and coding rate. For example, the determined modulation scheme and coding rate are transmitted to the receiving apparatus by the TMCC signal as transmission control information including transmission mode information.

In step S202, an information bit string I _i (i = 1 to n) is prepared. Here, the information bit string I _i is a bit string composed of 0 and 1, and the length n of the information bit string I _i varies depending on the coding rate. As an assumed information bit string, an MPEG-TS stream or the like can be cited. In order to further improve the transmission performance, the information bit sequence I _i is preliminarily determined by another error correction code (not limited to block coding such as BCH coding or Reed-Solomon coding, but may be a convolutional code or another LDPC code). It is also possible to use an encoded signal (step S203). As an example, the case of applying the 12-bit correctable BCH code Galois formula GF ^{(2 16)} to the information bit _{I i,} configuration diagram of an information bit _{I i} and BCH generator polynomial list shown in FIG. 15. In this case, the net information bit string is I _BCHi (i = 1 to n-192) and the parity string of the BCH code is P _BCHi (i = 1 to 192). Further, since the generator polynomial shown in FIG. 15 has a solution on GF (2 ¹⁶ ), it is possible to perform error correction for the entire information bit string I _i by the correction capability of the BCH code using the generator polynomial of FIG. Become. Further, the generator polynomial shown in FIG. 15 can be used for all coding rates that can be used in the encoders 11-1 and 11-2.

FIG. 16 shows coding rates 61/120, 27/40, 89/120, 97/120, 101/120, and 7/8 that can be used in the present encoder when the BCH code shown in FIG. 15 is applied. An example of a combination of I _BCHi and P _BCHi is shown.

In step S204, as described above, the encoders 11-1 and 11-2 perform LDPC encoding on the information bits I _i (i = 1 to n), and the 1-slot code word C _i (i = 1). ~ 44880).

In step S205, a temporary memory having a two-dimensional structure corresponding to 44880 / M in the horizontal direction and M in the vertical direction is prepared by the switch 14, and the code word C _i (i = 1 to 44880) is stored in the temporary memory from the top. The operation of recording 48880 / M bits in the horizontal direction is performed M times in the vertical direction. Here, M corresponds to the modulation order, and in the case of phase modulation, M = 2 for QPSK, M = 3 for 8PSK, M = 4 for 16APSK, and M = 5 for 32APSK. After the recording is completed, the operation of reading the recorded codeword C _i (i = 1 to 44880) from the top of the temporary memory in the horizontal direction in the vertical direction is repeated 48880 / M times in the horizontal direction. The above operation is called bit interleave processing. FIG. 17 shows a configuration diagram of bit interleaving processing in M-value modulation.

In step S206, the codeword C _i (i = 1 to 44880) subjected to bit interleaving processing read from the temporary memory by the mapping unit 15 is arranged at each phase point determined by the modulation method for each M bits, and the modulation symbol Is generated. Further, since M corresponds to the modulation order, the codeword C _i (i = 1 to 44880) can be arranged at each phase point without excess or deficiency by the above operation.

  In step S207, the time division multiplexing / orthogonal modulation unit 16 performs orthogonal modulation using the modulation symbol in step S206 to generate a transmission signal (that is, a modulated wave signal).

  By repeating the processes in steps S201 to S207, the transmission apparatus can change the modulation scheme and coding rate for every 48880 bits and generate a transmission signal that is LDPC-coded for every 48880 bits.

  The encoders 11-1 and 11-2 have 44880 bits as a basic unit, and 44880 is a value such as 1, 2, 3, 4, 5, 6, 8, 10, 11, 12, 15, 16, etc. It is a value divisible by. Therefore, this transmission apparatus can use a very diverse value as the modulation order M, and a very diverse multi-value such as BPSK, QPSK, 8PSK, 16APSK (16QAM), 32APSK (32QAM), 64QAM, 256QAM, and 1024QAM. It can correspond to a modulation system. Therefore, the transmission apparatus can perform signal transmission combining a very flexible modulation scheme and coding rate. Note that the parity check matrix initial value table for the parity check matrix used in the LDPC encoding in step 204 can be transmitted as auxiliary information from the transmission apparatus to the reception apparatus, or may be held in advance by the reception apparatus. . Alternatively, the check matrix itself can be transmitted from the transmission apparatus to the reception apparatus, or the check matrix itself may be held in advance by the reception apparatus.

  Subsequently, a processing process of the decoder according to the first embodiment will be described.

(Processing of the decoder)
FIG. 19 shows a process performed by the decoder in the transmission apparatus according to the first embodiment of the present invention. Similar to the LDPC encoders 11-1 and 11-2 (FIG. 13) described above, the decoder can be configured by a control unit and a storage unit, and a control program for executing each process by the control unit is stored in the storage unit. Stored.

  In step S301, coding rate information is read from transmission control information decoded through a demodulator (that is, the quadrature detection unit 21 shown in FIG. 3), and a check matrix is determined.

In step S302, the likelihood ratio λ _n (n = 1 to 44880) is calculated based on the transmission symbol x _n and the reception symbol y _n (i = 1 to 44880 / M). Likelihood ratio λ _n is the ratio of the probability of bits 0 and 1 to be sent, and is _expressed by equation (7) using transmission symbol x _n and reception symbol yn.

  In step S303, an LDPC decoding method such as a sum-product decoding method is performed using the likelihood ratio obtained in step S302. At this time, the decoder 23 performs decoding using the parity check matrix determined in the encoders 11-1 and 11-2 of the transmission device 1. The decoder 23 may calculate the parity check matrix using the parity check matrix initial value table as in the case of the encoders 11-1 and 11-2. The number of iteration decoding is an arbitrary value. In LDPC decoding, various means such as a min-sum decoding method other than the sum-product decoding method have been proposed. However, in the method of maximizing the likelihood ratio using a check matrix, the method of the present invention is Applicable.

In step S304, the decoded word C ′ _i (i = 1 to 44880) decoded in step S303 is output. In step S305, steps S301 to S304 are repeated for the sequentially demodulated signals until LDPC decoding by the decoder is completed. If all decoding is completed (Yes in the drawing), a series of LDPC decoding processes are completed.

  Subsequently, processing of the receiving apparatus according to the first embodiment will be described. FIG. 21 shows a processing process of the receiving device 2.

(Processing of receiving device)
In step S401, the modulation signal transmitted from the transmission apparatus 1 is received and demodulated by the demodulator (that is, the quadrature detection unit 21 shown in FIG. 3).

  In step S402, the modulation scheme and coding rate of the received modulation signal are determined in advance, and the transmission control signal decoding unit 22 decodes the TMCC signal demodulated through the channel selection unit 20 and the quadrature detection unit 21. To read the transmission control information. Thereby, the modulation scheme and coding rate information can be read from the transmission mode information of the transmission control information.

In step S403, the channel selection unit 20 and the quadrature detection unit 21 demodulate the signal received by the reception device, and generate reception symbols y _i (i = 1 to 44880 / M).

In step S404, the decoder 23 calculates a likelihood ratio λ _n (n = 1 to 44880) from the received symbol y _i (i = 1 to 44880 / M). The calculation of the likelihood ratio λ _n (n = 1 to 44880) is the same as the processing in step S302 of the present decoder.

In step S405, a temporary memory having a two-dimensional structure corresponding to M in the horizontal direction and 44880 / M in the vertical direction is prepared by the decoder 23 or another deinterleave processing unit (not shown), and the likelihood ratio λ _The operation of recording _n (n = 1 to 44880) M from the top in the horizontal direction of the temporary memory is repeated 44880 / M times in the vertical direction. As an example, FIG. 20 shows a configuration diagram of deinterleave processing in M-value modulation. After the recording is completed, an operation of reading the likelihood ratio λ _n (n = 1 to 44880) every 44880 / M bits from the top in the horizontal direction of the temporary memory in the vertical direction is read M times in the horizontal direction. The above operation is called deinterleave processing.

In step S406, the decoder 23 performs LDPC decoding using the likelihood ratio λ _n (n = 1 to 44880) after the deinterleaving process read in step S405, and the decoded word C ′ _i (i = 1 to 1). 44880) and information bit string I ′ _i (i = 1 to 44880-P) is output.

In step S407, when the information bit string is encoded with another error correction code connected to the LDPC code in the transmission apparatus 1 (for example, BCH code), the information bit string I ′ _i (i = 1 to 44880-P). , The outer code decoding unit 25 performs a decoding process corresponding to the used error correction code, and outputs a decoding result. When the BCH code is used, syndrome calculation is performed from the bit string of the information bit string I ′ _i (i = 1 to 44880-P) subjected to LDPC decoding, and the net information bit string is decoded by the Barencamp-Massie method or the like. Is possible.

  As described above, by repeating Step S401 to Step S407, it is possible to receive the transmission signal generated by this transmission apparatus in units of 48880 bits.

  As described above, the reception device 2 receives transmission signals corresponding to various combinations of coding rates and modulation methods generated by the transmission device 1, and has transmission characteristics of the LDPC code based on the parity check matrix according to the present invention. Thus, signals with various coding rates and modulation schemes can be received.

  Hereinafter, effects of LDPC encoding and decoding according to the first embodiment will be described. 22A and 22B, assuming a case where a random bit stream signal is transmitted / received under white noise using the encoder and decoder according to the first embodiment, and the transmission apparatus and the reception apparatus, a modulation scheme QPSK, Results of calculating Eb / No vs. BER characteristics by computer simulation for 8PSK, 16APSK, 32APSK, and coding rates 61/120 (C), 27/40, 89/120, 97/120, 101/120 and 7/8 Shows about. The decoding algorithm used sum-product decoding method (for example, refer nonpatent literature 1). The number of decoding iterations of the sum-product decoding method is 50 times. It can be seen that the encoding and decoding according to the present invention has a very small error floor.

FIG. 23 shows a coding gain at a bit error rate of 10 ^{−6 with} respect to QPSK, 8PSK, 16APSK, and 32APSK without error correction. FIG. 23 shows that the encoders 11-1 and 11-2 have a high coding gain. From these results, it can be seen that by using this encoder and decoder, a high coding gain peculiar to the LDPC code can be obtained at a code length of 48880 bits.

  In addition, by generating the parity check matrix using the parity check matrix initial value table used in the present invention, the number of cycles 4 and 6 can be reduced as compared with the conventional case. Coding rate 61/120 (A), 61/120 (B), 61/120 (C), 61/120 (D), 27/40, 89/120, 97/120, 101/120, 7/8 The ratio of cycle 4 to cycle 10 of each check matrix is shown in FIG. The ratio of cycle n was defined by equation (8).

  Total number of columns including 1 constituting cycle n / 44880 (8)

  It can be seen from FIG. 24 that the check matrix of the present invention has significantly fewer cycles 4 and 6 at most coding rates.

  Next, a case will be described where a parity check matrix of coding rates 11/40, 41/120, 49/120, 73/120, and 109/120 is used. The parity check matrix initial value tables of the coding rates 11/40, 41/120, 49/120, 73/120, and 109/120 described here are shown in Tables 7 to 11, respectively.

FIG. 25 shows the relationship between the information length (left submatrix) and the parity length (right submatrix) for each of the coding rates 11/40, 41/120, 49/120, 73/120, and 109/120. ing. FIG. 26 shows sub-matrices of coding rates 11/40, 41/120 (A), 41/120 (B), 41/120 (C), 49/120, 73/120, and 109/120. _A list of the row / column overlap and the number of columns of _HA is shown. Further, FIG. 27 shows a list of k corresponding to each information length of coding rates 11/40, 41/120, 49/120, 73/120, and 109/120 and Q corresponding to the parity length.

  The processing procedures of the encoders 11-1 and 11-2 according to Tables 7 to 11 and FIGS. 25 to 27 are the same as steps S <b> 101 to S <b> 106 of FIG. 14 described above.

FIG. 28 shows I _BCHI and P at coding rates _11/40 , _41/120 , _49/120 , _73/120 , and _109/120 that can be used in the present encoder when the BCH code shown in FIG. 15 is applied. A combination example of _BCHi is shown. The transmission signal generation process of the transmission apparatus according to Tables 7 to 11 and FIGS. 25 to 27 is the same as steps S201 to S207 of FIG.

  FIG. 29 shows the check matrix cycles 4 to 4 at coding rates 11/40, 41/120 (A), 41/120 (B), 41/120 (C), 49/120, 73/120, 109/120. The ratio of cycle 12 is shown. The ratio of the cycle n is defined by the above formula (8). From FIG. 29, by configuring the parity check matrix using the parity check matrix initial value tables (Tables 7 to 11) used in the present invention, the number of cycles 4 and 6 can be eliminated at almost all coding rates. I understand that. That is, by eliminating the number of cycles 4 and 6, it is possible to significantly suppress the occurrence of error floors. It is clear from FIG. 30 that it is important to remove the number of cycles 4 and 6.

  FIG. 30 illustrates encoding in the modulation scheme QPSK on the assumption that a random bit stream signal is transmitted / received under white noise using the encoder and decoder according to the first embodiment, and the transmission apparatus and the reception apparatus. The results of Eb / No vs. BER characteristics calculated by computer simulation for rates 11/40, 41/120 (B), 49/120, 73/120, and 109/120 are shown. The number of decoding iterations of the sum-product decoding method is 50 times. It can be seen from FIG. 30 that the error floor is extremely small in the encoding and decoding according to the present invention.

  As described above, the code lengths of 48880 bits are 11/40, 41/120, 49/120, 61/120, 73/120, 27/40, 89/120, 97/120, 101/120, 7 / 8 and 109/120, a partial matrix corresponding to the information length corresponding to the coding rate, with a parity check matrix initial value table (Tables 1A to 11) predetermined based on the coding rate of any one of 109 and 120 as an initial value. By using a check matrix configured by arranging one element of the above in the column direction at intervals of 374 columns, a plurality of types of digital modulation schemes as shown in a multiple modulation / time division multiplex transmission system can be time-shared In a multiplexing transmission system, it is possible to transmit information with excellent resistance to white noise. In particular, in LDPC coding, error correction performance varies greatly depending on the formation method of each cycle depending on the arrangement method of 1 in the check matrix, and it is easy to improve the value of Eb / No even at 0.1 dB. is not. That is, generating a parity check matrix from an optimized parity check matrix initial value table as shown in Tables 1A to 11 has a markedly advantageous effect not found in the prior art, as can be seen from FIGS. 22A, 22B, and 30. It is what is generated.

  Next, a transmission device and a reception device in the transmission system according to the second embodiment of the present invention will be described.

(Example 2)
FIG. 31 is a block diagram illustrating a part of the transmission device and the reception device in the transmission system according to the second embodiment. In FIG. 31, the same components as those in the first embodiment will be described with the same reference numerals.

  The transmission apparatus according to the second embodiment includes a first NULL insertion unit 26 before the LDPC encoder 11-2 and a first NULL deletion unit 27 after the LDPC encoder 11-2 with respect to the transmission apparatus according to the first embodiment. Furthermore, it differs in the point provided. For convenience of the description of the second embodiment, it is assumed that the first NULL insertion means 26 and the first NULL deletion means 27 are provided outside the LDPC encoder 11-2, but the inside of the LDPC encoder 11-2 is described. Can be prepared for.

  The LDPC encoder 11-2 performs LDPC encoding on a TMCC signal included in a predetermined transmission signal based on a parity check matrix generated from a predetermined parity check matrix initial value table predetermined for each coding rate. The same as in the first embodiment.

  The first NULL insertion means 26, before LDPC encoding the TMCC signal by the LDPC encoder 11-2, has a NULL value of a predetermined number of bits corresponding to a predetermined parity check matrix initial value table (ie, “0” as a bit value). ")" Is inserted into two or more predetermined locations for predetermined data of the TMCC signal.

  The first NULL deletion unit 27 performs LDPC encoding on the TMCC signal by the LDPC encoder 11-2, and then deletes the NULL values at two or more places inserted by the first NULL insertion unit 26 to further generate the TMCC signal. Encode.

  The receiving apparatus according to the second embodiment is different from the receiving apparatus according to the first embodiment in that a second NULL inserting unit 29 is further provided in the preceding stage of the LDPC decoder 23 and a second NULL deleting unit 30 is provided in the subsequent stage of the LDPC decoder 23. . For convenience of explanation of the second embodiment, the second NULL insertion unit 29 and the second NULL deletion unit 30 are described as being provided outside the LDPC decoder 23, but can be provided inside the LDPC decoder 23. It is.

  For the encoded TMCC signal transmitted from the transmission apparatus of the second embodiment, the LDPC decoder 23 performs LDPC based on a parity check matrix generated from a predetermined parity check matrix initial value table predetermined for each coding rate. This is the same as in the first embodiment except that the probability that the value of the NULL value inserted by the second NULL insertion means 29 is “0” is 1 and LDPC decoding is performed. .

  The second NULL insertion means 29 is a place where a NULL value having the same number of bits as the number of bits inserted by the first NULL insertion means 27 is inserted by the first NULL insertion means 27 before the LDPC decoder 23 performs LDPC decoding of the TMCC signal. Insert into.

  The second NULL deleting means 30 performs LDPC decoding on the TMCC signal by the LDPC decoder 23 and then deletes the NULL value at the location inserted by the second NULL inserting means 29 to generate decoded data of the TMCC signal.

  As described in the first embodiment, LDPC encoding with an information length of 44880 bits is extremely effective as described in the first embodiment, and it is preferable to perform LDPC encoding with an information length of 44880 bits for a TMCC signal in consideration of system cost. Needless to say. That is, it is preferable that both the LDPC encoder 11-1 and the LDPC encoder 11-2 perform LDPC encoding with an information length of 44880 bits. In order to make error correction more robust, it is preferable to further encode the TMCC signal to establish a more reliable transmission system.

  Here, when performing LDPC encoding with an information length of 44880 bits, a NULL value (that is, as a bit value) of a predetermined number of bits according to a predetermined parity check matrix initial value table at a predetermined position with respect to the information data of the TMCC signal. Optimizing and inserting “0”) is effective for making error correction more robust.

  An example of further encoding of the TMCC signal will be described. FIG. 32 is a diagram illustrating an example of optimization as further coding of the TMCC signal at the coding rate 61/120 (A) or the coding rate 61/120 (D). FIG. 33 is a diagram illustrating an example of optimization as further coding of the TMCC signal at the coding rate 61/120 (B) or the coding rate 61/120 (C).

  That is, when the parity check matrix initial value table is a table made up of Table 1A or Table 1D, the first NULL deleting means 26 has 2992 bits in the head of predetermined data (9614 bits) of the TMCC signal, and TMCC. A NULL value of 10208 bits is inserted at the rear of the predetermined data of the signal (see FIG. 32A). Further, when the parity check matrix initial value table is a table made up of Table 1B or Table 1C, the first NULL deleting means 26 has 1870 bits for the head of predetermined data (9614 bits) of the TMCC signal, and A NULL value of 11330 bits is inserted in the rear part of the predetermined data of the TMCC signal (see FIG. 33A).

  The LDPC encoder 11-2 performs LDPC encoding with an information length of 44880 bits.

  The first NULL deletion unit 27 deletes the NULL values at the head and the rear of the predetermined data (9614 bits) of the TMCC signal inserted by the first NULL insertion unit 26 to obtain 31680 bits (that is, the coding rate 1 / The encoded data of 3) is generated (see FIGS. 32B and 33B).

  On the receiving device side, the second NULL insertion unit 29 inserts the TMCC signal demodulated by the BS-IF demodulation unit 28 (that is, the channel selection unit 20 and the quadrature detection unit 21 shown in FIG. 3) by the first NULL insertion unit 26. A NULL value having the same number of bits as the number of bits is inserted into two or more places inserted by the first NULL insertion means 26. In the LDPC decoder 23, the value of the position inserted at two or more locations is NULL for the signal of information length 44880 bits including the NULL value inserted at two or more locations input from the first NULL insertion means 26. The probability that the value is 1 is set to 1, and the TMCC signal is subjected to LDPC decoding. The second NULL deletion means 30 receives the LDPC-decoded TMCC signal, deletes NULL values at two or more places inserted by the first NULL insertion means 26, and has 31680 bits (ie, coding rate 1/3). The decrypted data is generated.

  Here, as an important element, even if the coding rate is the same, two insertion positions of the optimal NULL value are different depending on the parity check matrix initial value table to be used. In addition, considering that it is necessary to manage addresses in advance under the control of the control unit 11a, for example, it is not preferable to increase the number of locations where the optimal NULL value is inserted.

  In LDPC encoding, it is not easy to improve the value of Eb / No even with 0.1 dB. Depending on the optimized parity check matrix initial value table as shown in Tables 1A to 1D, FIG. As shown in FIG. 33, the encoding of the TMCC signal has a remarkable advantageous effect that is not found in the prior art.

  With respect to the above-described embodiments, a program for causing a computer that functions as an encoder and a decoder and a transmission device and a reception device to be configured, and for causing the encoder and the decoder, and each means of the transmission device and the reception device to function. It can be used suitably. Specifically, the control unit for controlling each means can be constituted by a central processing unit (CPU) in the computer, and at least a storage part for appropriately storing a program necessary for operating each means. A single memory can be used. In other words, the functions of the respective means described above can be realized by causing such a computer to execute the program by the CPU. Furthermore, a program for realizing the function of each unit can be stored in a predetermined area of the storage unit (memory). Such a storage unit can be configured by a RAM or a ROM inside the image decoding device, or can be configured by an external storage device (for example, a hard disk). Such a program can be constituted by a part of software (stored in a ROM or an external storage device) on an OS used in a computer as an image decoding device. Furthermore, a program for causing such a computer to function as each means can be recorded on a computer-readable recording medium. Moreover, each means mentioned above can be comprised as a part of hardware or software, and can also be implement | achieved combining each.

  Although the above embodiments have been described as representative examples, it will be apparent to those skilled in the art that many changes and substitutions can be made within the spirit and scope of the invention. For example, as other error correction coding when combined with LDPC coding, besides BCH coding, not only block coding such as Reed-Solomon coding but also convolutional coding, or other LDPC encoding may be combined. Also, inserting or deleting NULL values at a plurality of locations with respect to predetermined data of the TMCC signal is effective at any coding rate. Accordingly, the invention should not be construed as limited by the embodiments described above, but only by the claims.

  The encoder and decoder, the transmitter, and the receiver according to the present invention are useful in a transmission system that time-division-multiplexes a plurality of types of digital modulation schemes when the code lengths of LDPC codes are different in various transmission schemes.

It is a figure which shows the structure of the multiplex frame in the transmission system of one Example by this invention. It is a block diagram of the transmission apparatus in the transmission system of one Example by this invention. It is a block diagram of the receiver in the transmission system of one Example by this invention. It is a figure which shows an example of the modulation wave signal of one Example by this invention. It is a figure which shows an example of the check matrix of column weight 3 and row weight 4. It is a figure which shows the example of the cycle 4 and the cycle 6. FIG. Is a diagram illustrating a right side partial matrix H _T. It is a figure which shows the basic structure of the parity check matrix for LDPC codes. It is a figure which shows the relationship of each information length and parity length of the encoding rates 61/120, 27/40, 89/120, 97/120, 101/120, 7/8 in the transmission system of one Example by this invention. is there. It is explanatory drawing of the check matrix initial value table (coding rate 61/120 (A)) in the transmission system of one Example by this invention. Coding rates 61/120 (A), 61/120 (B), 61/120 (C), 61/120 (D), 27/40, 89/120, 97 in the transmission system according to an embodiment of the present invention. FIG. 10 is a diagram showing a list of row / column weights of each check matrix of / 120, 101/120, and 7/8. Corresponding to k and parity length corresponding to each information length of coding rate 61/120, 27/40, 89/120, 97/120, 101/120, 7/8 in the transmission system of one embodiment of the present invention It is a figure which shows the list of Q to do. FIG. 3 is a block diagram of an encoder according to an embodiment of the present invention. 4 is a flowchart illustrating a process of an encoder according to an embodiment of the present invention. It is a diagram showing a configuration view and a BCH generator polynomial list of information bits I _i. It is a figure which shows the example of a combination of _IBCH and _PBCH in the encoding rate utilized with the encoder by this invention at the time of applying the BCH code shown in FIG. It is a block diagram of the bit interleaving process in the M value modulation | alteration in the transmitter of one Example by this invention. It is a flowchart which produces | generates the transmission signal in the transmitter of one Example by this invention. It is a flowchart which shows the process of the decoder in the transmitter of one Example by this invention. It is a block diagram of the deinterleaving process in M value modulation in the receiver of one Example by this invention. It is a flowchart which produces | generates the received signal in the receiver of one Example by this invention. Eb / No pairs under white noise for coding rates 61/120 (C), 27/40, 89/120, 101/120, and 7/8 in a modulation scheme QPSK in a transmission system according to an embodiment of the present invention It is a figure which shows a BER characteristic. Eb / No vs. BER characteristics under white noise for coding rates of 27/40, 89/120, 89/120, and 97/120 with modulation schemes 8PSK, 16APSK and 32APSK in the transmission system of one embodiment of the present invention. FIG. It is a figure which shows the encoding gain in the bit error rate ^10-6 point with respect to QPSK, 8PSK, 16APSK, and 32APSK in the transmission system of one Example by this invention without error correction. In a transmission system according to an embodiment of the present invention, coding rates 61/120 (A), 61/120 (B), 61/120 (C), 61/120 (D), 27/40, 89/120, It is a figure which shows the ratio of cycle 4-cycle 10 about each check matrix of 97/120, 101/120, and 7/8. Information length (left submatrix) and parity length (right submatrix) of coding rates 11/40, 41/120, 49/120, 73/120, and 109/120 in the transmission system of one embodiment of the present invention It is a figure which shows the relationship. In the transmission system according to an embodiment of the present invention, the coding rate is 11/40, 41/120 (A), 41/120 (B), 41/120 (C), 49/120, 73/120, 109/120. It is a figure which shows the row | line | column weight list | wrist of each check matrix. List of k corresponding to each information length of coding rate 11/40, 41/120, 49/120, 73/120, 109/120 and Q corresponding to parity length in the transmission system of one embodiment according to the present invention. FIG. When the BCH code shown in FIG. 15 is applied, I _BCH and P at each of the coding rates 11/40, 41/120, 49/120, 73/120, and 109/120 used in the encoder according to the present invention. It is a figure which shows the example of a combination of _BCH . Code rates 11/40, 41/120 (A), 41/120 (B), 41/120 (C), 49/120, 73/120, 109/120 in a transmission system according to an embodiment of the present invention. It is a figure which shows the ratio of cycle 4-cycle 12 about each check matrix. Eb / No pair under white noise for coding rates 11/40, 41/120 (B), 49/120, 73/120, and 109/120 in modulation scheme QPSK in the transmission system of one embodiment of the present invention It is a figure which shows a BER characteristic. It is a block diagram which shows a part of transmitting apparatus and receiving apparatus in the transmission system of one Example by this invention. It is a figure which shows an example optimized in the transmitter in the transmission system of one Example by this invention as a further encoding of a TMCC signal in the coding rate 61/120 (A) or the coding rate 61/120 (D). . It is a figure which shows an example optimized as a further encoding of a TMCC signal in the coding rate 61/120 (B) or the coding rate 61/120 (C) in the transmission apparatus in the transmission system of one Example by this invention. .

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Transmission apparatus 2 Reception apparatus 10 Frame production | generation part 11-1, 11-2 Encoder (LDPC encoding)
11-3, 11-4 Outer code encoder (BCH encoding)
11a control unit 11b storage unit 12, 13 energy spreading unit 14 switch 15 modulation mapping unit 16 time division multiplexing / orthogonal modulation unit 20 channel selection unit 21 orthogonal detection unit 22 transmission control signal decoding unit 23 decoder (LDPC decoding)
24 Energy despreading unit 25 Outer code decoding unit (BCH decoding)
26 First NULL insertion means 27 First NULL deletion means 28 BS-IF demodulator 29 Second NULL insertion means 30 Second NULL deletion means

Claims (22)

An encoder for LDPC encoding predetermined data using at least one parity check matrix,
The parity check matrix is a matrix unique to each coding rate, and corresponds to the information length corresponding to the coding rate 61/120, with a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. 1 elements of the submatrix are arranged in a column direction with a period of every 374 columns,
The parity check matrix initial value table of the coding rate 61/120 is:

Or

Or

Or

An encoder comprising: An encoder for LDPC encoding predetermined data using at least one parity check matrix,
The parity check matrix is a matrix unique to each coding rate, and corresponds to an information length corresponding to a coding rate 27/40, with a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. 1 elements of the submatrix are arranged in a column direction with a period of every 374 columns,
The parity check matrix initial value table of the coding rate 27/40 is:

An encoder comprising: An encoder for LDPC encoding predetermined data using at least one parity check matrix,
The parity check matrix is a matrix specific to each coding rate, and corresponds to an information length corresponding to a coding rate 89/120, with a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. 1 elements of the submatrix are arranged in a column direction with a period of every 374 columns,
The parity check matrix initial value table of the coding rate 89/120 is:

An encoder comprising: An encoder for LDPC encoding predetermined data using at least one parity check matrix,
The parity check matrix is a matrix specific to each coding rate, and corresponds to an information length corresponding to a coding rate 97/120 using a parity check matrix initial value table that is predetermined with a code length of 44880 bits as an initial value. 1 elements of the submatrix are arranged in a column direction with a period of every 374 columns,
The parity check matrix initial value table of the coding rate 97/120 is:

An encoder comprising: An encoder for LDPC encoding predetermined data using at least one parity check matrix,
The parity check matrix is a matrix unique to each coding rate, and corresponds to an information length corresponding to the coding rate 101/120, with a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. 1 elements of the submatrix are arranged in a column direction with a period of every 374 columns,
The parity check matrix initial value table of the coding rate 101/120 is:

An encoder comprising: An encoder for LDPC encoding predetermined data using at least one parity check matrix,
The parity check matrix is a matrix specific to each coding rate, and corresponds to an information length corresponding to a coding rate of 7/8, using a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. 1 elements of the submatrix are arranged in a column direction with a period of every 374 columns,
The parity check matrix initial value table of the coding rate 7/8 is:

An encoder comprising: An encoder for LDPC encoding predetermined data using at least one parity check matrix,
The parity check matrix is a matrix unique to each coding rate, and corresponds to an information length corresponding to a coding rate 11/40, with a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. 1 elements of the submatrix are arranged in a column direction with a period of every 374 columns,
The parity check matrix initial value table of the coding rate 11/40 is:

An encoder comprising: An encoder for LDPC encoding predetermined data using at least one parity check matrix,
The parity check matrix is a matrix specific to each coding rate, and corresponds to an information length corresponding to a coding rate 41/120, with a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. 1 elements of the submatrix are arranged in a column direction with a period of every 374 columns,
The parity check matrix initial value table of the coding rate 41/120 is:

Or

Or

An encoder comprising: An encoder for LDPC encoding predetermined data using at least one parity check matrix,
The parity check matrix is a matrix specific to each coding rate, and corresponds to an information length corresponding to a coding rate 49/120, with a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. 1 elements of the submatrix are arranged in a column direction with a period of every 374 columns,
The parity check matrix initial value table of the coding rate 49/120 is:

An encoder comprising: An encoder for LDPC encoding predetermined data using at least one parity check matrix,
The parity check matrix is a matrix specific to each coding rate, and corresponds to the information length corresponding to the coding rate 73/120, with a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. 1 elements of the submatrix are arranged in a column direction with a period of every 374 columns,
The parity check matrix initial value table of the coding rate 73/120 is:

An encoder comprising: An encoder for LDPC encoding predetermined data using at least one parity check matrix,
The parity check matrix is a matrix unique to each coding rate, and corresponds to an information length corresponding to the coding rate 109/120, with a parity check matrix initial value table predetermined with a code length of 44880 bits as an initial value. 1 elements of the submatrix are arranged in a column direction with a period of every 374 columns,
The parity check matrix initial value table of the coding rate 109/120 is:

An encoder comprising:   The decoder characterized by performing LDPC decoding of the data encoded by the encoder in any one of Claims 1-11 based on the said check matrix.   A transmission apparatus comprising the encoder according to claim 1.   A receiving apparatus comprising the decoder according to claim 12. A transmission device used in a data transmission system for time division multiplex transmission of a plurality of types of digital modulation schemes,
In the case where a plurality of slots including at least data and LDPC encoded parity are configured, and the multiplexed data configured as a frame by the plurality of slots is transmitted based on transmission control information, the transmission control information includes the digital modulation scheme and code Information on the conversion rate,
A transmission apparatus comprising the encoder according to claim 1.   The decoder characterized by performing LDPC decoding of the data transmitted by the transmission apparatus of Claim 15 based on the said check matrix. An encoder for LDPC encoding a TMCC signal included in a predetermined transmission signal;
A first NULL inserting means for inserting a NULL value of a predetermined number of bits into two or more predetermined locations for predetermined data of the TMCC signal before LDPC encoding the TMCC signal by the encoder;
First NULL deleting means for further decoding the TMCC signal by deleting NULL values at two or more locations inserted by the first NULL inserting means after LDPC encoding the TMCC signal by the encoder; A transmission apparatus comprising: The TMPC signal included in a predetermined transmission signal is LDPC-encoded based on a parity check matrix generated from a predetermined parity check matrix initial value table predetermined for each coding rate. The described encoder;
Before LDPC encoding of the TMCC signal by the encoder, a predetermined number of NULL values corresponding to the predetermined parity check matrix initial value table are set to two or more predetermined values for the predetermined data of the TMCC signal. First NULL insertion means for insertion into the location;
First NULL deleting means for further decoding the TMCC signal by deleting NULL values at two or more locations inserted by the first NULL inserting means after LDPC encoding the TMCC signal by the encoder; A transmission apparatus comprising:   The transmitting apparatus according to claim 17 or 18, wherein there are two places where a NULL value is inserted by the first NULL inserting means for predetermined data of a TMCC signal. The code according to claim 1, wherein the TMCC signal included in the predetermined transmission signal is LDPC-encoded based on a parity check matrix generated from a predetermined parity check matrix initial value table having a coding rate of 61/120. And
Before LDPC encoding of the TMCC signal by the encoder, a NULL value having a predetermined number of bits corresponding to the predetermined parity check matrix initial value table is inserted into a plurality of predetermined positions for predetermined data of the TMCC signal. First NULL insertion means for
After the LDCC encoding of the TMCC signal by the encoder, a plurality of NULL values inserted by the NULL insertion unit are deleted, and a first NULL deletion unit for further encoding the TMCC signal,
The first NULL insertion means includes
When the parity check matrix initial value table is a table comprising Table 1A or Table 1D, 2992 bits are added to the head of the predetermined data of the TMCC signal, and 10208 bits are added to the rear of the predetermined data of the TMCC signal. If the parity check matrix initial value table is a table consisting of Table 1B or Table 1C, 1870 bits are added to the head of the predetermined data of the TMCC signal, and the TMCC signal Insert a NULL value of 11330 bits at the rear of the given data,
The first NULL deletion means includes:
A transmission apparatus characterized in that 31680-bit encoded data is generated by deleting NULL values of the head and rear of predetermined data of the TMCC signal inserted by the first NULL insertion means. A decoder that performs LDPC decoding on a coded TMCC signal transmitted from the transmission device according to claim 18 based on a parity check matrix generated from a predetermined parity check matrix initial value table predetermined for each coding rate When,
A second NULL insertion unit for inserting a NULL value having the same number of bits as the number of bits inserted by the first NULL insertion unit before the LDCC decoding of the TMCC signal by the decoder at a position inserted by the first NULL insertion unit; ,
After the LDCC decoding of the TMCC signal by the decoder, the NULL value of the place inserted by the second NULL insertion means is deleted, and the second NULL deletion means for decoding the TMCC signal,
The receiving apparatus, wherein the decoder performs LDPC decoding with a probability that a value of a position inserted at two or more locations by the second NULL inserting unit is a NULL value is 1. The encoded TMCC signal transmitted from the transmission apparatus according to claim 20 is subjected to LDPC decoding based on a parity check matrix generated from a predetermined parity check matrix initial value table having a coding rate of 61/120. A decoder;
Before performing LDPC decoding of the TMCC signal by the decoder, a second NULL insertion is performed in which a NULL value having the same number of bits as the number of bits inserted by the first NULL insertion unit is inserted into two places inserted by the first NULL insertion unit. Means,
A second NULL deletion unit that deletes NULL values at two locations inserted by the second NULL insertion unit after LDPC decoding of the TMCC signal by the decoder, and obtains 31680-bit decoded data;
The decoding apparatus according to claim 1, wherein the decoder performs LDPC decoding with a probability that a value of a position inserted at two locations by the second NULL insertion unit is a NULL value as 1.

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