JP4851922B2 - Distance measuring device - Google Patents

Description

  The present invention detects a time difference between a time when a pulsed laser beam is irradiated to a distance measuring object and a time when a signal from the distance measuring object due to reflection is detected, thereby detecting a distance to the distance measuring object. It is related with the distance measuring device which measures.

  This type of conventional distance measuring device uses a distance measuring counter to measure the time from the first reference clock to the clock signal that performs sampling closest to the time when the level of the received signal from the distance measuring object reaches the peak value. The distance to the object is measured by adding the time from the above time to the time when the level of the received signal reaches the peak value.

  In the latter addition time, the number of sample hold circuits corresponding to the distance resolution holds the level of the received signal by the sample clock whose phase is equally divided by the clock cycle, and the analog multiplexer uses the select counter to The output is sequentially switched, and the analog encoder generates a digital encoding signal of the number of quantization bits in comparison with the reference voltage string from the reference voltage generating resistor network with respect to the output of the analog multiplexer. The count value of the select counter when it matches the data pattern corresponding to the peak value of the received signal is obtained.

  The reference voltage generating resistor network is composed of a plurality of sets of voltage dividing resistors corresponding to the reference voltage string, and the analog encoder includes a reference voltage, a one-to-one correspondence switching transistor, a common bias resistor, and a constant current source. The number of circuits corresponding to the set of reference voltage trains.

Japanese Patent Laying-Open No. 2005-345320 (pages 6-9, FIG. 1)

  However, the above-described conventional distance measuring device uses a sample-and-hold circuit, an analog multiplexer, and an analog encoder to specify a clock signal that performs sampling closest to the time when the level of the received signal reaches a peak value. Since the method of comparing the output patterns of the encoder while changing the reference voltage pattern inputted to the input circuit is adopted, there is a first problem that the analog circuit is complicated and the number of elements of the circuit increases.

  In addition, many resistors are used in switching transistors, bias resistors, and reference voltage generating resistor networks that are components of analog encoders. Furthermore, since transistors are used in a constant current system, a standby state cannot be created, and means for reducing power consumption. Since it cannot be found, there is a second problem that when the number of quantization bits increases, the number of constant current transistors increases and the current consumption increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a distance measuring device with a simple circuit configuration and reduced power consumption.

  The distance measuring device according to the present invention counts the time difference between the time when the object is irradiated with the pulsed laser beam and the time when the received signal due to the reflection from the object is detected, by using the reference clock, thereby measuring the distance to the object. In the distance measuring apparatus for measuring the distance measurement counter (see FIG. 1), it counts for each reference clock from the start signal for recognizing the laser light generation timing to the stop signal for informing the reception timing of the reception signal. 19), the high-order register (20 in FIG. 1) that holds the count result in the distance measurement counter, and the last reference at which the distance measurement counter stopped counting by the stop signal due to the detection of switching of the magnitude transition state of the sampling data with respect to the received signal A correction circuit that measures the time from the clock to the time when the received signal reaches its peak value 3, 10 to 18, 30), and the distance to the object is measured by correcting the count result held by the upper register by a correction circuit.

  Preferably, the correction circuit generates a sample clock generator (3, FIG. 1) that generates N sample clocks whose phases are shifted by (N + 1) equal to the period of the reference clock determined according to the distance resolution. 30), and a reference voltage generation circuit (11 in FIG. 1) that generates M reference voltages according to a desired resolution by resistance-dividing the voltage conversion value of the maximum amplitude level of the received signal from the object, The M comparators (10 in FIG. 1) that compare the amplitude value of the received signal with each reference voltage, and each holds M comparison results in all comparators in response to the sample clock. A shift register group (12 in FIG. 1) that shifts the stored data serially in the previous direction by a shift clock generated M times (12 in FIG. 1), and a shift register in response to the shift clock. The shift register (14 in FIG. 1) that holds the output of the first-stage shift register of the data group, and the output and shift of the first-stage shift register in response to the comparison control signal generated every time the shift clock is generated M times The comparison circuit (13 in FIG. 1) that compares the output of the register, the comparison number counter (15 in FIG. 1) that counts the number of comparison control signals and is cleared by the reference clock, and the magnitude relationship in the comparison circuit is reversed. And a lower register (18 in FIG. 1) that holds the count in the comparison number counter.

  The delay line constituting the sample clock generator generates N delay times with respect to the reference clock synchronized with the reference trigger signal. This delay time is a value obtained by dividing the period of the ranging counter clock signal by (N + 1) as one step, and a sample clock with N different delay times samples the received signal from the distance measurement object. And hold the result. The stored amplitude values before and after the time when the received signal reaches the peak value are subjected to level comparison by the comparison circuit. The closest time to the peak of the received signal is calculated based on the number of comparisons required until the position containing the peak level is specified in the register data that holds the sampling results from the clocks with each delay time. The result gives low-order data indicating the time from the rising edge of the reference clock to the peak value reception time.

  The first effect of the present invention is that power consumption can be reduced. This is because the analog signal is not handled at all after the input of the comparator of the received signal, so that the transistor that has been increased with the increase in the number of quantization bits by the conventional sampling becomes unnecessary.

  The second effect is that the circuit of the part that measures the distance resolution of one cycle or less of the clock signal counted by the distance measuring counter and uses it as the lower data is simplified. The reason is that a method of detecting the time when the received signal reaches the peak level is realized by extracting the sampling result of the received signal and its changing point.

  Next, the overall configuration of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of a distance measuring device of the present invention. This distance measuring device generates a pulsed laser beam, irradiates it toward the object 0 for distance measurement, and receives an optical signal reflected from the object 0 for distance measurement. And the distance to the ranging object 0 is measured by detecting the time from the time when the laser beam is transmitted to the time when the received signal is received.

  In order to perform the distance measurement, the distance measuring apparatus includes a clock generator 1, a pulse generator 2, N delay lines 3-1 to 3-N, a logic gate 30, a laser generator 4, and a transmission optical system 5. , Light receiving optical system 6, detector 7, amplifier 8, peak detector 9, M comparators 10-1 to 10-M, reference voltage generating circuit 11, (N + 1) shift registers 12-1 to 12 -(N + 1), comprising a comparison circuit 13, a shift register 14, a comparison counter 15, a two-stage flip-flop (FF1 and FF2) 16, a logic gate 17, a lower register 18, a distance measuring counter 19 and an upper register 20 Is done.

  The clock generator 1 generates a reference clock for measuring the time from the time when the laser beam is irradiated toward the distance measuring object 0 to the reception time of the received light signal, and sends it to the pulse generator 2 and the distance measuring counter 19. Output.

  Based on the reference clock BCK from the clock generator 1, the pulse generator 2 generates a laser emission control signal necessary for laser light generation in the laser generator 4, and at the same time, a reference trigger signal synchronized with the laser light generation timing. And a sample clock SCK in phase with the reference clock BCK, and a start signal for recognizing the laser light generation timing. The reference trigger signal is output to the shift register 14, the sample clock SCK is output to the delay lines 3-1 to 3-N and the logic gate 30, and the start signal is output to the distance measuring counter 19.

  The pulse generator 2 generates M shift clocks SFCK during T / (N + 1), where T is the reference clock period, and performs comparison control every time M shift clocks SFCK are generated. Generate a signal. The shift clock SFCK is output to the shift registers 12-1 to 12- (N + 1), and the comparison control signal is output to the comparison circuit 13 and the comparison number counter 15.

  Further, the pulse generator 2 generates a sample stop signal SSP and a clear signal CLR at the timing of the peak detection signal input from the peak detector 9. The sample stop signal SSP is output to the logic gate 30, and the clear signal CLR is output to the peak detector 9, the distance measuring counter 19 and the upper register 20.

  The delay lines 3-1 to 3-N output sample clocks SCK1 to SCKN that give N delay times in response to the sample clock SCK. The sample clocks SCK1 to SCKN each have a delay time of T × K / (N + 1) [K = 1, 2,... N], where T is the period of the reference clock BCK. Here, N is determined according to the distance resolution required for the apparatus. The logic gate 30 outputs the sample clock SCK0 as it is to the sample clock SCK to the shift register 12-1, and outputs the sample clocks SCK1 to SCKN to the shift registers 12-2 to 12- (N + 1).

  When the laser emission control signal is input from the pulse generator 2, the laser generator 4 generates a pulse laser, and this pulse laser passes through the transmission optical system 5 and is irradiated toward the distance measuring object 0. The light receiving optical system 6 receives a signal reflected from the distance measuring object 0 and guides it to the detector 7. The detector 7 converts a weak input signal due to light into an electric signal, and then outputs it to the amplifier 8 and simultaneously outputs a stop signal notifying the reception timing of the received signal to the distance measuring counter 19.

  The output of the amplifier 8 is output to the peak detector 9 and the comparators 10-1 to 10-M. The peak detector 9 outputs a peak detection signal to the pulse generator 2 at the timing when the amplifier output reaches the peak level. The peak detector 9 is cleared by a clear signal CLR input from the pulse generator 2.

  FIG. 2 shows the laser transmission / reception timing and the distance measurement target section. The distance measuring counter 19 counts every time the reference clock rises from the rise of the start signal to the fall of the stop signal, and registers the result in the upper register 20. At this time, the laser emission control signal and the emitted pulse laser are synchronized with the reference clock BCK, and the time difference from the center of the laser transmission pulse (timing t0) to the first reference clock BCK (timing t1) is always a fixed value. It becomes. Further, the time from the first reference clock BCK (timing t1) to the last reference clock BCK (timing t2) can be known by counting in the distance measuring counter 19. The distance measuring counter 19 and the upper register 20 are cleared by a clear signal CLR input from the pulse generator 2.

  Since the distance measurement distance required by this distance measuring device is from the laser transmission time (timing t0) to the time when the received signal reaches its peak (timing t3), the distance measurement counter 19 has stopped counting by the stop signal. This can be determined by measuring the time from the rise of the reference clock BCK (timing t2) to the time (timing t3) at which the received signal reaches its peak value. Each component of the reference numbers 10-18 demonstrated below plays this role.

  The comparators 10-1 to 10-M compare the analog signal input level of the amplifier 8 output with the reference level from the reference voltage generation circuit 11 at high speed. When the input level is higher than the reference level, the digital signal “1” is output. If it is smaller, “0” is output. Here, the setting accuracy of the reference voltage is determined by determining the value of M in accordance with the detection accuracy required for the distance measuring device.

  The reference voltage generation circuit 11 generates M reference voltages by dividing the voltage conversion value by M resistors in consideration of the maximum amplitude level of the received signal. -1 to 10-M, and is compared with the amplitude value of the received signal input from the amplifier 8. The digital outputs of the comparators that change every moment depending on the amplitude value are input to M-bit shift registers 12-1 to 12- (N + 1), respectively.

  The sample clock SCK generated by the pulse generator 2 is input to each of the delay lines 3-1 to 3-N, and the logic stop 30 is ANDed with the sample stop gate, and sampling with N delay times is performed. Clocks SCK1 to SCKN. SCK0 is input to the shift register 12-1, and SCK1 to SCKN are input to the shift registers 12-2 to 12- (N + 1). Each of these shift registers 12-1 to 12- (N + 1) has an M-bit width according to the resolution of the reference voltage by the parallel holding function, and holds M comparison results at each sample timing. To do. FIG. 3 is a timing chart thereof.

  When this holding operation is completed, the distance measuring apparatus performs the following operation before starting transmission / reception of the next cycle. The pulse generator 2 outputs a comparison control signal to the comparison circuit 13 and a shift clock SFCK to the shift registers 12-1 to 12- (N + 1). In the M-bit shift register 14, all M bits are set to “0” at the timing of the reference trigger signal as an initial value for the comparison circuit 13 to perform comparison. Thereafter, the shift register 12 is synchronized with the shift clock SFCK. -1 output is input. The comparison circuit 13 outputs “1” to the flip-flop FF1 when the hold value of the shift register 12-1 is larger than the hold value of the shift register 14, and “0” when it is smaller.

  The shift register 12 serially shifts the data held in the preceding direction by the shift clock SFCK, and thereafter, the comparison control signal is input to the comparison circuit 13 every M times of the shift clock SFCK, and the comparison operation is repeated. Here, the comparison circuit 13 continues to output “1” while the reception signal is increasing, but starts to output “0” when the reception signal reaches the peak value and starts decreasing.

  The flip-flop FF2 outputs the input from the flip-flop FF1 at the timing of the shift clock SFCK, and the logic gate 17 takes the exclusive logic of both outputs of the flip-flops FF1 and FF2, and outputs the result to the lower register 18. Therefore, the logic gate 17 outputs “1 (L → H)” only at the timing when the output level of the received signal has changed from increasing to decreasing.

  Each time the comparison control signal is input, the comparison counter 15 counts the rising edge and outputs the result to the lower register 18. When the holding signal output from the logic gate 17 is input, the lower register 18 temporarily registers the count result input from the comparison counter 15. The comparison counter 15 and the lower register 18 are cleared by the reference clock input from the pulse generator 2.

  The data registered in the lower register 18 is the peak level data of the received signal held in any of the shift registers 12-1 to 12- (N + 1), and the shift register 14 and the shift register 12- This indicates how many times the comparison operation has been performed before moving to 1. For this reason, the delay lines 3-1 to 3-N specify how much delay time is provided to sample the data closest to the peak level of the received signal by the sample clock.

  Data obtained by counting the time from the start signal to the stop signal in units of the reference clock BCK by the distance measurement counter 19 becomes registration data of the upper register 20 and is combined with the data of the lower register 18 to become distance measurement data.

  Next, as an embodiment of the present invention, a case will be described where there are seven delay lines 3 (the lower part of the distance measurement data is 3 bits) and the peak level of the received signal appears at a position closest to the timing of the delay line 3-1. To do.

  If the frequency of the reference clock is 10 MHz (one cycle of 100 nsec), the delay time given to the sample clock by the delay line 3 is set in 1/8 nsec units. There are 16 types (16 bits) of reference voltages to compare the received signal sampling results. If the period of the reference clock is T, the delay lines 3-1 to 3-7 set the delay time in units of T × K / 8 [K = 1, 2,... 7], that is, 12.5 nsec.

  The setting accuracy of the reference voltage is set according to the detection accuracy required for the distance measuring system. Here, assuming that there are 16 stages, the output of the amplifier 8 is the peak detector 9 and the comparators 10-1 to 10-. Input to 16. The reference voltage generating circuit 11 considers the maximum amplitude level of the received signal and divides the converted voltage value by 16 resistors to generate 16 reference voltages, and these reference voltages are comparators 10-1 to 10-10, respectively. -16 and is compared with the amplitude value input from the amplifier 8.

  The digital outputs of the comparators 10-1 to 10-16 that change every moment depending on the amplitude value enter the shift registers 12-1 to 12-8. The sample clock SCK generated by the pulse generator 2 is input to the logic gate 30 and the delay lines 3-1 to 3-7, and the logic gate 30 takes the “AND” logic with the sample stop signal. As a result, the sample clocks SCK0 to SCK7 have eight delay times, and SCK0 is input to the shift register 12-1, and SCK1 to SCK7 are input to the shift registers 12-2 to 12-8.

  The shift registers 12-1 to 12-8 have a 16-bit width corresponding to the resolution of the reference voltage by the parallel holding function, and hold 16 comparison results at each sample timing. When this holding operation ends, the following operation is performed before the measurement apparatus starts transmission / reception of the next cycle.

  The pulse generator 2 outputs a comparison control signal to the comparison circuit 13 and a shift clock SFCK to the shift registers 12-1 to 12-8. In the shift register 14, all 16 bits are set to “0” at the timing of the reference trigger signal as an initial value to be compared by the comparison circuit 13. The comparison circuit 13 outputs “1” to the flip-flop FF1 when the hold value of the shift register 12-1 is larger than the hold value of the shift register 14, and “0” when it is smaller.

  The shift registers 12-1 to 12-8 serially shift the data held in the preceding direction by the shift clock SFCK, and thereafter, the comparison control signal is input to the comparison circuit 13 every M shift clocks SFCK and the comparison operation is repeated. Is done. Here, the comparison circuit 13 continues to output “1” while the reception signal is increasing, but starts to output “0” when the reception signal reaches the peak value and starts decreasing.

  The flip-flop FF2 outputs the input of the flip-flop flip-flop FF1 at the timing of the shift clock SFCK, and the logic gate 17 takes the exclusive logic of both outputs of the flip-flops FF1 and FF2, and outputs the result to the lower register. Therefore, the logic gate outputs “1 (L → H)” only at the timing when the reception output level changes from increase to decrease.

  The comparison counter 15 counts the rise every time a comparison control signal is input and outputs the result to the lower register 18. When the holding signal output from the logic gate is input, the lower register 18 temporarily registers the value. What data is registered until the peak level data of the received signal held in any of the shift registers 12-1 to 12-8 shifts to the shift register 14 and the shift register 12-1 to be compared. In order to indicate whether the comparison operation has been performed a number of times, it is specified how much delay time is provided by the delay lines 3-1 to 3-7 and the data closest to the peak level of the received signal is sampled by the sample clock.

  Data obtained by counting the time from the start signal to the stop signal by the distance measurement counter 19 in units of the reference clock BCK becomes registration data of the upper register 20 and is combined with the data of the lower register 18 to become distance measurement data. Data obtained by counting the time from the start signal to the stop signal in units of 100 nsec (assuming that the data that has completed the counter is “1000” as an example) becomes the registration data of the upper register 20 and the data of the lower register 18. Is combined with the distance measurement data.

  In this case, the distance data actually measured by the high-order register 20 is 3 × 10 8 (light speed) × 100 nsec (clock cycle) × 1000 (count value) / 2 (reciprocal correction) = 15000 m. Further, the distance data measured by the lower register 18 assumes that the peak level of the received signal appears at a position closest to the timing of the delay line 3-1, based on the assumption at the beginning. Therefore, 3 × 10 8 (light speed) × 12.5nsec (delay line setting unit) ÷ 2 (round trip correction) = 1.875m. Therefore, the distance measurement target distance to be calculated is 15001.875 m.

The block diagram which shows embodiment of the distance measuring device of this invention Explanatory drawing of laser transmission / reception timing and distance measurement target section in the present invention The figure which shows the holding state after the sampling and peak level of the received signal in this invention

Explanation of symbols

0 Ranging object 1 Clock generator 2 Pulse generator 3 Delay line 4 Laser generator 5 Transmission optical system 6 Light receiving optical system 7 Detector 8 Amplifier 9 Peak detector 10 Comparator 11 Reference voltage generation circuit 12 Shift register 13 Comparison circuit 14 Shift register 15 Comparison counter 16 Flip-flop 17 Logic gate 18 Lower register 19 Ranging counter 20 Upper register 30 Logic gate

Claims (1)

A distance measuring device for measuring the distance to the object by counting the time difference between the time when the object is irradiated with the pulsed laser beam and the time when the received signal reflected by the object is detected with a reference clock In
A distance measuring counter that counts for each reference clock between a start signal for recognizing laser light generation timing and a stop signal for notifying the reception timing of the reception signal;
An upper register for holding a count result in the distance measuring counter;
A correction circuit for measuring a time from the last reference clock at which the distance measurement counter stops counting by the stop signal to a time when the reception signal becomes a peak value by detecting the switching of the magnitude transition state of the sampling data with respect to the reception signal; With
Measure the distance to the object by correcting the count result held by the upper register by the correction circuit ;
The correction circuit includes:
The phase of the reference clock is determined according to the distance resolution.
A sample clock generator for generating sample clocks;
A voltage-converted value of the maximum amplitude level of the received signal from the object is divided by resistance.
A reference voltage generating circuit for generating M reference voltages according to a desired resolution;
M comparators that compare the amplitude value of the received signal with each reference voltage;
Each of the sample clocks shows M comparison results for all the comparators.
Held in response to the clock and held by the shift clock generated M times during the sample clock.
Shift consisting of (N + 1) shift registers that serially shift the stored data in the previous direction
Registers and
In response to the shift clock, the output of the first shift register of the shift register group
A shift register that holds
In response to a comparison control signal generated every time the shift clock is generated M times,
A comparison circuit for comparing the output of the shift register and the output of the shift register;
Counts the number of comparison control signals and counts the number of comparisons cleared by the reference clock
And
Count in the comparison counter when the magnitude relationship in the comparison circuit is reversed
And a low-order register for holding a distance measuring device.

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