JP4842783B2 - Information processing apparatus, information processing method, and program - Google Patents

Description

  The present invention relates to an information processing apparatus that performs simulation.

In a simulation using conventional trace information, for example, a CPU is obtained by operating an application system of a parallel computer to be evaluated on a real machine, and collecting message transmission / reception information together with time information at that time. (Central Processing Unit) Obtaining the usage time, the system performance was evaluated by replacing it with the CPU performance in the hardware environment to be simulated (for example, Patent Document 1).
In the instruction level simulator, a method is also proposed in which a performance evaluation target program is run on the instruction level simulator, and the CPU usage time is estimated by counting the number of instructions to evaluate the performance (for example, Patent Document 2).
JP-A-6-59939, pages 2-4, FIG. JP-A-10-78892, pages 2-4, FIG.

The conventional simulation method for performance prediction / performance evaluation has the following problems.
(1) Since a real system is operated on a real machine to acquire a trace log and the like, the hardware architecture to be performance-predicted is fixed, and performance prediction for other hardware architectures cannot be performed.
(2) Since the real system is operated to acquire a trace log and the like, performance prediction cannot be performed for a system where the real system does not exist yet (no actual program exists).
(3) In order to grasp the operation at the instruction level of the processor in order to increase the accuracy of performance prediction, a large amount of trace logs are required when targeting a large-scale and complicated system, and performance prediction is performed. Takes time.

The main object of the present invention is to solve the above-described problems, and specifically, the following are the main objects.
(1) The target system is divided into functional blocks of an arbitrary scale, and the hardware is arranged in units of the functional blocks, thereby enabling performance prediction for various hardware architectures.
(2) In reality, an unimplemented function is assumed for each functional block, and the performance prediction of the entire system is made possible by using the predicted performance information or target performance information of the functional block.
(3) By acquiring trace information in units of arbitrary functional blocks, the amount of trace is reduced and the performance prediction time is shortened. In addition, once the trace information is acquired, it can be used to repeatedly perform performance prediction on various hardware architectures.
(4) A benchmark program is created in units of functional blocks, is run on real hardware, performance information is collected, and the performance information is used for performance simulation to improve performance prediction accuracy.
(5) When performance evaluation that affects functions is performed, it is possible to automatically reset function parameters and function models in function simulation using the performance information as feedback information.
By realizing these, it is possible to realize an information processing apparatus and the like that can efficiently perform pre-system / post-system verification and future system design support.

An information processing apparatus according to the present invention includes:
A function simulation unit that executes a simulation of a target program composed of a plurality of function blocks, and generates trace information indicating transitions of the function blocks in the executed simulation;
A performance selection unit that selects a target hardware architecture for performance prediction;
Predictive execution for generating predicted execution performance information indicating the predicted execution performance of the target hardware architecture when the target program is executed according to the transition of the functional block indicated by the trace information using the target hardware architecture And a performance information generation unit.

  According to the present invention, when the simulation for the target program is executed and the trace information is generated, it is possible to repeatedly perform performance prediction for various hardware architectures, and to perform performance prediction for various hardware architectures. Based on the result, it is possible to design an appropriate system.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram illustrating an operation principle of the information processing apparatus 100 according to the present embodiment.
In FIG. 1, a function selection unit 1 is a man model for an operator operating the information processing apparatus 100 to instruct / confirm a function model for function simulation, function parameter selection, simulation target scenario specification, and the like. Means with a machine interface.
The function simulation unit 2 is a means for simulating a function to be verified with a function model and function parameters specified by the function selection unit 1 according to a given scenario.
The scenario data 3 is data in which initial settings for performing a functional simulation are stored.
The execution result 4 is data such as a result of a function simulation executed based on the scenario data 3.
The trace information 5 is data storing the execution contents of the function simulation that is equivalent to the execution history of an arbitrary function block in the simulation target system.
The performance information database 6 is a database in which the amount of hardware resources used in each functional block is recorded for each of various hardware architectures.
The performance information conversion unit 7 is means for converting the trace information 5 into the trace / performance parameter information 10 by the performance information database 6.
The performance selection unit 8 includes a man-machine interface for the operator to select and confirm the hardware architecture for performing the performance simulation and the allocation of each functional block to the hardware architecture. It is.
The performance simulation unit 9 is a means for performing a performance simulation of the target system by calculating the resource usage based on the trace / performance parameter information using a specified hardware architecture.
The trace / performance parameter information 10 is data generated and stored by the performance information conversion unit 7.
The performance result 11 is data such as an execution result of the performance simulation unit 9.
The performance feedback unit 12 stores performance values that affect the functions detected by the performance simulation unit in the feedback information database 13 and automatically resets the function model and function parameters of the function simulation unit 2, 9 is a means for automatically resetting the hardware architecture.

  The function simulation is a simulation of a simulation target program (a simulation target program) according to the scenario data 3, the function model, and the function parameters. The performance simulation is a hardware architecture that is a target of performance prediction. Is used to simulate the performance of the hardware architecture such as resource usage when the simulation target system is executed in accordance with the order of transition of the functional blocks indicated in the trace information 5.

Although details will be described later, an operation example of the information processing apparatus 100 according to the present embodiment will be outlined here.
The function simulation unit 2 executes a simulation of a simulation target program (target program) including a plurality of functional blocks, and generates trace information 5 indicating the transition of the functional blocks in the executed simulation.
The performance selection unit 8 selects a hardware architecture (target hardware architecture) that is a target of performance prediction, and the performance information conversion unit 7 (predicted execution performance information generation unit) determines that the target program is the target hardware. Generates trace / performance parameter information 10 (predicted execution performance information) indicating the performance information (predicted execution performance) of the target hardware architecture when executed in accordance with the function block transition indicated in the trace information 5 using the architecture To do.
The trace / performance parameter information 10 displays the performance information of the target hardware in accordance with the functional block transition indicated in the trace information 5.
The performance information database 6 stores the predicted execution performance for each functional block of each hardware architecture when the target program is executed for each of a plurality of hardware architectures. Extracts the predicted execution performance of the target hardware architecture for each functional block indicated in the trace information from the performance information database 6 to generate trace / performance parameter information.

  Next, a hardware configuration example of the information processing apparatus 100 according to the present embodiment and the following embodiments will be described.

FIG. 19 is a diagram illustrating an example of hardware resources of the information processing apparatus 100 according to the present embodiment and the embodiments described below. Note that the configuration in FIG. 19 is merely an example of the hardware configuration of the information processing apparatus 100, and the hardware configuration of the information processing apparatus 100 is not limited to the configuration illustrated in FIG. Also good.
In FIG. 19, the information processing apparatus 100 includes a CPU 911 (also referred to as a central processing unit, a central processing unit, a processing unit, a processing unit, a microprocessor, a microcomputer, and a processor) that executes a program. The CPU 911 is connected to, for example, a ROM (Read Only Memory) 913, a RAM (Random Access Memory) 914, a communication board 915, a display device 901, a keyboard 902, a mouse 903, and a magnetic disk device 920 via a bus 912. Control hardware devices. Further, the CPU 911 may be connected to an FDD 904 (Flexible Disk Drive), a compact disk device 905 (CDD), a printer device 906, and a scanner device 907. Further, instead of the magnetic disk device 920, a storage device such as an optical disk device or a memory card read / write device may be used.
The RAM 914 is an example of a volatile memory. The storage media of the ROM 913, the FDD 904, the CDD 905, and the magnetic disk device 920 are an example of a nonvolatile memory. These are examples of a storage device or a storage unit.
The communication board 915, the keyboard 902, the scanner device 907, the FDD 904, and the like are examples of an input unit and an input device.
Further, the communication board 915, the display device 901, the printer device 906, and the like are examples of an output unit and an output device.

The communication board 915 may be connected to a network. For example, the communication board 915 may be connected to a LAN (local area network), the Internet, a WAN (wide area network), or the like.
The magnetic disk device 920 stores an operating system 921 (OS), a window system 922, a program group 923, and a file group 924. The programs in the program group 923 are executed by the CPU 911, the operating system 921, and the window system 922.

The program group 923 stores programs that execute the functions described as “units” in the present embodiment and the following description of the embodiments. The program is read and executed by the CPU 911.
In the file group 924, “determination of”, “calculation of”, “comparison of”, “evaluation of”, “extraction of”, “setting of”, “ Information, data, signal values, variable values, and parameters indicating the result of the processing described as “Registration” and the like are stored as items of “˜file” and “˜database”. The “˜file” and “˜database” are stored in a recording medium such as a disk or a memory. Information, data, signal values, variable values, and parameters stored in a storage medium such as a disk or memory are read out to the main memory or cache memory by the CPU 911 via a read / write circuit, and extracted, searched, referenced, compared, Used for CPU operations such as calculation, calculation, processing, editing, output, printing, and display. Information, data, signal values, variable values, and parameters are stored in the main memory, registers, cache memory, and buffers during the CPU operations of extraction, search, reference, comparison, calculation, processing, editing, output, printing, and display. It is temporarily stored in a memory or the like.
The arrows in the flowchart described below mainly indicate input / output of data and signals. The data and signal values are the RAM 914 memory, FDD 904 flexible disk, CDD 905 compact disk, magnetic disk device 920 magnetic disk, In addition, it is recorded on a recording medium such as an optical disc, a mini disc, or a DVD. Data and signals are transmitted online via a bus 912, signal lines, cables, or other transmission media.

  In addition, what is described as “to part” in the description of the present embodiment and the following embodiment is “to circuit”, “to device”, “to device”, and “to means”. Also, “˜step”, “˜procedure”, and “˜processing” may be used. That is, what is described as “˜unit” may be realized by firmware stored in the ROM 913. Alternatively, only software, hardware such as elements, devices, substrates, and wirings, a combination of software and hardware, or a combination of firmware may be used. Firmware and software are stored as programs in a recording medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD. The program is read by the CPU 911 and executed by the CPU 911. That is, the program causes the computer to function as “to part” of the present embodiment and the embodiments described below. Alternatively, it causes a computer to execute the procedures and methods of “to part” of the present embodiment and the embodiments described below.

  As described above, the information processing apparatus 100 shown in the present embodiment and the embodiments described below includes a CPU as a processing device, a memory as a storage device, a magnetic disk, etc., a keyboard as an input device, a mouse, a communication board, and an output device. The computer includes a display device, a communication board, and the like, and implements the functions indicated as “˜unit” using the processing device, the storage device, the input device, and the output device as described above.

  Next, an operation example (information processing method) of the information processing apparatus 100 according to the present embodiment will be described with reference to the flowchart of FIG.

First, the function selection unit 1 specifies a function model to be simulated, a function parameter, a scenario used for the simulation, and the like based on an instruction from an operator who operates the information processing apparatus 100, and initializes the function simulation unit 2. Do.
Next, the function simulation unit 2 reads the initially set scenario as scenario data 3 (S1801), executes a function simulation according to the function model and function parameters (S1802) (function simulation step), and executes the result as an execution result 4 And the function simulation unit 2 outputs an execution history in units of function blocks as trace information 5 (S1803) (function simulation step).
Here, as shown in FIG. 2, the simulation target system (target program) is divided into a plurality of functional blocks, and exchanges data between the functional blocks in response to measurement data input from an external device. A control system that gives a control instruction to the device is assumed. The measurement data that is an input to the simulation target system is defined by the scenario data 3. The control instruction that is the output can be referred to as the execution result 4, and the execution history is Trace information 5 is output in accordance with the data transition of the function blocks A to H.
As the trace information 5, as shown in the example of FIG. 3, which functional block is executed in time series is recorded.
In the example of FIG. 3, the start time and end time of each functional block are shown, but these may be omitted. That is, the trace information 5 only needs to indicate the transition (order) of the function blocks in the function simulation, and may indicate only the function block ID.

Next, the performance selection unit 8 designates a hardware architecture to be a performance prediction simulation target based on an instruction from the operator (S1804) (performance selection step), and performs an initial setting of the performance simulation unit 9.
This operation can be performed before the function simulation, that is, simultaneously with the initial setting of the function simulation unit 2 via the function selection unit 1.
Next, the performance information conversion unit 7 extracts the performance data of the performance information database 6 corresponding to the trace information 5 based on the hardware architecture of the performance prediction target selected by the performance selection unit 8 (S1805) ( (Predicted execution performance information generation step), trace / performance parameter information 10 is generated (S1806) (predicted execution performance information generation step), and trace / performance parameter information 10 is output (S1807).
The performance simulation unit 9 executes the performance simulation with the trace / performance parameter information 10 output from the performance information conversion unit 7 as an input, outputs the result as a performance result 11, and functions via the performance feedback unit 12. Feedback is performed to the simulation unit 2 as initial setting of the function model and function parameters.

Details of the performance simulation by the performance simulation unit 9 and details of feedback to the function simulation unit 2 by the performance feedback unit 12 will be described in the following embodiments.
Here, the operation of the performance information conversion unit 7 will be described.
As shown in the example of FIG. 4, the performance information database 6 records which functional blocks and how many CPUs are required for each hardware architecture.
Further, the trace / performance parameter information 10 indicates which function block is executed in time series as shown in the example of FIG. 5, and how much CPU is required at that time.
The performance information conversion unit 7 inputs the trace information 5 indicating the transition of the functional block as a result of simulating the simulation target system (target program), and the hardware architecture (target) selected by the performance selection unit 8 (Hardware architecture) information is input, and the performance information data corresponding to the function information indicated in the trace information 5 is extracted from the performance information database 6 to generate the trace / performance parameter information 10.
The trace / performance parameter information 10 indicates the predicted execution performance of the hardware architecture when the simulation target system is executed according to the function block transition indicated in the trace information 5 using the selected hardware architecture. 5 is shown in accordance with the transition of the functional block shown in FIG.
If the performance simulation unit 9 analyzes the trace / performance parameter information 10 and determines that it is not necessary to re-execute the function simulation or regenerate the trace / performance parameter information 10, the trace / performance parameter information 10 The result 11 is output and the operator of the information processing apparatus 100 refers to the CPU time and the like of each functional block when the simulation target system is executed using the hardware architecture selected by the performance selection unit 8. Can do.
When a function simulation is performed for the system shown in FIG. 2 and a hardware architecture with one CPU is selected in the performance information conversion unit 9, the trace / performance parameter information 10 shown in FIG. Suppose that it was generated.
In the predicted execution performance information analysis unit of the performance simulation unit 9, it is read from the trace / performance parameter information 10 that measurement data is input to the function block A at a cycle of 30 msec, and is shown in FIG. The calculation which solves the CPU usage time chart of each functional block is performed, and the elapsed time from the input of arbitrary measurement data until the control instruction is issued is predicted.

As described above, in this embodiment, since the function simulation and the performance evaluation for the hardware architecture are divided, once the function simulation is executed and the trace information is acquired, this is used. It is possible to repeatedly perform performance prediction for various hardware architectures.
In addition, since it is not necessary to perform a function simulation for each hardware architecture, the CPU load and memory usage can be reduced as an overall process, and the use efficiency of finite resources of the computer can be improved. Is obtained.

  In addition, by acquiring trace information in units of functional blocks, it is possible to reduce the amount of tracing and shorten the performance prediction execution time.

Embodiment 2. FIG.
In the first embodiment described above, the CPU usage time in units of functional blocks is stored and used in the performance information database, but an embodiment in the case of improving the accuracy of performance prediction will be described below.
The configuration of the information processing apparatus 100 according to the present embodiment is the same as that shown in FIG.

In the present embodiment, the functional block is further divided into a plurality of sub-functional blocks. Specifically, the division into sub-functional blocks is performed by dividing the functional block into branch patterns in units where a difference in processing performance occurs due to a difference in input data as shown in FIG.
The function simulation unit 2 records which branch pattern is executed, and outputs trace information 5 indicating the executed branch pattern as shown in FIG. In the example of FIG. 7, for example, the branch pattern 2 of the plurality of branch patterns is executed for the functional block A, and the branch pattern 1 of the plurality of branch patterns is executed for the functional block C. It has been shown.
As shown in FIG. 8, the performance information database 6 holds the usage amount of hardware resources for each branch pattern.
FIG. 8 shows an example in which not only the CPU usage time but also the memory usage amount, the IO amount, and the like are held as hardware resources.

The operation of the information processing apparatus 100 according to the present embodiment is basically the same as that of the first embodiment.
That is, the function simulation unit 2 generates the trace information 5 indicating the transition of the function block in a branch pattern (sub function block) unit,
The performance information conversion unit 7 extracts the performance information data (predicted execution performance) of the target hardware architecture for each branch pattern (sub function block) indicated in the trace information 5 from the performance information database 6, and the target program is The predicted execution performance of the target hardware architecture when executed according to the function block transition indicated in the trace information 5 using the target hardware architecture is indicated according to the branch pattern (sub-function block) transition indicated in the trace information. Trace / performance parameter information 10 is generated.
In the present embodiment, the performance information conversion unit 7 generates the trace / performance parameter information 10 as shown in FIG. 9, for example, based on the trace information in FIG. 7 and the performance information data in the performance information database 6 in FIG. .

  As described above, according to the present embodiment, it is possible to improve the accuracy of performance prediction by refining trace information and refining resource usage items in the performance information database.

Embodiment 3 FIG.
In the first embodiment, the performance information database 6 uses a fixed value for each hardware architecture. Next, an embodiment in which performance prediction is performed with higher accuracy will be described. Show.
The configuration of the information processing apparatus 100 according to the present embodiment is the same as that shown in FIG.

FIG. 10 shows the trace information 5 according to the present embodiment, FIG. 11 shows the data of the performance information database 6 according to the present embodiment, and FIG. 12 shows the trace / performance parameter information according to the present embodiment. 10 examples are shown.
In the present embodiment, as shown in FIG. 11, the usage amount of hardware resources can be specified by an arithmetic expression instead of a fixed value, and parameter values that affect the usage amount of hardware resources are shown in FIG. The trace information 5 can be recorded.
As a result, the performance information conversion unit 7 calculates how much hardware resources are required when each functional block is executed, and converts it into the trace / performance parameter information of FIG.
Here, the parameter value X shown in FIG. 10 is a value determined after the function simulation by the function simulation unit 2.
10 to 12, parameter values, calculation formulas, and prediction performance values are shown for each branch pattern. However, parameter values, calculation formulas, and predictions for each functional block without sub-classification into branch patterns. You may make it show a performance value.

The operation of the information processing apparatus 100 according to the present embodiment is basically the same as that of the first embodiment.
That is, the function simulation unit 2 generates trace information in which parameter values that can affect the execution performance of the hardware architecture are indicated for each function block or branch pattern (sub function block).
The performance information database 6 is a calculation formula (predicted execution performance calculation formula) for calculating the predicted execution performance of each hardware architecture when the target program is executed for each of a plurality of hardware architectures. Is stored for each functional block or branch pattern (sub-functional block), and the performance information conversion unit 7 applies the target for each functional block or branch pattern (sub-functional block) indicated in the trace information 5 from the performance information database 6. Using hardware architecture calculation formulas and using the calculated formulas and parameter values of corresponding functional blocks or branch patterns (sub functional blocks) shown in trace information 5 to calculate predicted execution performance Thus, the trace / performance parameter information 10 is generated.

  As described above, according to the present embodiment, it is possible to predict performance with higher accuracy by making it possible to set an arithmetic expression of hardware resource usage for parameter values that affect performance.

Embodiment 4 FIG.
Next, an embodiment in which the convenience of performance prediction is improved by making it possible to specify the hardware architecture more flexibly will be described.
The configuration of the information processing apparatus 100 according to the present embodiment is the same as that shown in FIG.

FIG. 13 is a conceptual diagram of performance simulation target hardware that is the target of generation of trace / performance parameter information by the information processing apparatus 100 according to the present embodiment.
In the performance simulation target hardware shown in FIG. 13A, two processor boards connected by a bus are used, and functional blocks operating on each processor board are fixedly assigned. Similarly, in the performance simulation target hardware of FIG. 13B, two server computers connected by a LAN are used, and functional blocks operating on each server computer are fixedly assigned.
In each example, two processor boards, two server computers may have the same hardware architecture, or different hardware architectures can be designated.
Further, the function blocks allocated on each hardware architecture can be freely reassigned by the operator via the performance selection unit 8.

  At the same time, in the function selection unit 1, the function blocks A, C, E, and G cannot be operated in parallel because the same processor is used as a model of the control system in advance. Similarly, the function blocks B, D, F, and H The model setting that each parallel operation cannot be performed is performed, the function simulation by the function simulation unit 2 is performed, the trace information 5 is acquired, and the performance simulation unit 9 for both hardware architectures based on the trace information 5 Perform performance simulation by

That is, in the present embodiment, the function selection unit 1 specifies the hardware allocation mode of each functional block of the target program, and the function simulation unit 2 matches the hardware allocation mode specified by the function selection unit 1. A simulation for the target program is executed, and trace information 5 indicating the transition of functional blocks in the executed simulation is generated.
The performance selection unit 8 selects a hardware architecture that matches the hardware allocation form specified by the function selection unit 1 as the target hardware architecture, and the performance information conversion unit 7 Trace / performance parameter information 10 indicating the predicted execution performance of the hardware architecture that conforms to the specified hardware allocation form is generated according to the transition of the functional block indicated by the trace information 5.

As described above, according to the present embodiment, the hardware architecture can be freely selected, the hardware block can be arranged in function block units, and the hardware architecture is not fixed. Performance prediction by combination of hardware and architecture is possible, improving convenience.
In the function simulation, the function selection unit 1 sets the operation condition of the function block as a model of the control system, so that the performance simulation for different hardware architectures under the same condition is obtained from a single function simulation. Implementation is possible based on information 5, and the verification time can be shortened.

Embodiment 5 FIG.
Next, an embodiment in which the accuracy of the performance information data held in the performance information database 6 is further increased will be described.
The configuration of the information processing apparatus 100 according to the present embodiment is the same as that shown in FIG.

FIG. 14 shows the concept of a benchmark program (simulation program) having a portion that performs the same processing as the main processing corresponding to each functional block.
In this example, except for the data transmission / reception part, the actual function block processing is performed, and instead of performing data transmission / reception, the simulation data corresponding to the reception data is read from the file etc., and the result is output. The program is a benchmark program.
A plurality of simulation data to be prepared are selected so as to pass through all the branch patterns in the functional block.
The benchmark program is operated on various hardware architectures, the amount of hardware resources used for each branch pattern is measured, and the result is used as performance information data of the corresponding hardware architecture in the performance information database 6. .

  In other words, in the present embodiment, the performance information database 6 is the functional block or branch pattern of each hardware architecture when the benchmark program (simulated program) of the target program is executed as the performance information data (predicted execution performance). The actual value of execution performance for each (sub-function block) is stored, and the performance information conversion unit 7 performs the performance information data of the corresponding functional block or branch pattern from the performance information database 6 as in the preceding embodiment. (Actual value for the benchmark program) is extracted to generate the trace / performance parameter information 10.

  As described above, according to the present embodiment, even when using a benchmark program, the performance information data (actually measured value) corresponding to the benchmark program is used to predict the performance when the corresponding hardware architecture is used. The accuracy can be significantly improved compared to performance information data created from catalog information.

Embodiment 6 FIG.
Next, an embodiment in which control parameters are reset from the performance simulation unit 9 to the function simulation unit 2 via the performance feedback unit 12 will be described.
The configuration of information processing apparatus 100 according to the present embodiment is the same as that shown in FIG.
In the present embodiment, the performance simulation unit 9 analyzes the result of the function simulation of the target program by the function simulation unit 2, changes any parameter value used for the simulation of the target program, and the performance feedback unit. 12, the function simulation unit 2 is instructed to re-execute the function simulation of the target program using the changed parameter value. In the present embodiment, the performance simulation unit 9 functions as a simulation analysis unit.
In the present embodiment, the function simulation unit 2 re-executes the function simulation of the target program using the changed parameter value instructed by the performance simulation unit 9, and the function block transition in the re-executed function simulation. The performance information conversion unit 7 generates the trace / performance parameter information 10 using the trace information 5 generated when the function simulation unit 2 re-executes the simulation.

FIG. 15 is an example of a functional block program that requires control parameters.
In this example, a “Recursive Search” function for performing a route search recursively is set, and is called when a certain condition is satisfied or the control parameter “MAX_SEARCH_LEVEL” does not satisfy the recursive execution count.
This control parameter “MAX_SEARCH_LEVEL” usually represents processing time constraints.
In this example, if the function block E is periodically executed, “MAX_SEARCH_LEVEL” needs to be set so that the processing is completed within the cycle as the recursive processing limit number.
The performance simulation unit 9 detects that the functional block E that operates periodically cannot finish the process within the period time, and notifies the performance feedback unit 12 of the numerical value N indicating how many times the recursive process has been processed, The performance feedback unit 12 provides the scenario data used in the function simulation unit 2, the configuration / arrangement of the hardware architecture used in the performance simulation unit, and the value N corresponding to the control parameter “MAX_SEARCH_LEVEL” as a feedback information database. 13, “MAX_SEARCH_LEVEL” which is a control parameter of the function simulation unit 2 is reset to N so that the function simulation can be re-executed. That is, the function simulation unit 2 performs the function simulation by changing “MAX_SEARCH_LEVEL” to the value N without changing other parameters of the scenario data 3.
Then, the performance information conversion unit 7 inputs the trace information 5 indicating the result of the function simulation in which “MAX_SEARCH_LEVEL” is the value N, and generates the trace / performance parameter information 10 based on the trace information 5.

  As described above, according to this embodiment, a feedback mechanism from performance simulation to function simulation is provided, and the result of the trial is saved, so that it is optimal for the target hardware architecture. Therefore, it is possible to derive a control parameter, and the convenience of design support is improved.

Embodiment 7 FIG.
Next, an embodiment in which the hardware configuration is reset in the performance simulation unit 9 from the performance simulation unit 9 via the performance feedback unit 12 will be described.
The configuration of information processing apparatus 100 according to the present embodiment is the same as that shown in FIG.
In the present embodiment, the performance simulation unit 9 analyzes the trace / performance parameter information 10 generated by the performance information conversion unit 7, changes the hardware configuration of the target hardware architecture, and changes the hardware configuration. The performance information conversion unit 7 is instructed to regenerate the trace / performance parameter information 10 when the target hardware architecture after the change is used. In the present embodiment, the performance simulation unit 9 functions as a predicted execution performance information analysis unit.
In this embodiment, the performance information conversion unit 7 regenerates the trace / performance parameter information 10 when the target hardware architecture after the hardware configuration change instructed by the performance simulation unit 9 is used.

FIG. 16 is an example of an H / W configuration that is a target of performance prediction in the present embodiment.
In FIG. 16A, when the performance simulation was executed with the initial number of processors set to four, it was detected that the processing was completed within the target requested execution time and there was a margin, and the initial As shown in FIG. 16B, the number of processors that have been executed by four processors is changed to two so that the performance simulation can be re-executed.
That is, the performance simulation unit 9 analyzes the trace / performance parameter information 10 generated by the performance information conversion unit 7 for the hardware configuration with four processors, and as a result, the process is performed within the target requested execution time. When the performance simulation unit 9 detects that the situation is complete and there is more room, the performance simulation unit 9 changes the hardware configuration to a configuration with two processors as shown in FIG. The performance information conversion unit 7 is instructed to regenerate the parameter information 10.
Then, the performance information conversion unit 7 extracts performance information data when there are two processors from the performance information database 6 and generates trace / performance parameter information 10 when there are two processors.

  As described above, according to the present embodiment, by providing a feedback mechanism from the performance simulation result, it is possible to derive an optimal hardware architecture, and the convenience of design support is improved.

Embodiment 8 FIG.
Next, another embodiment in which the hardware configuration is reset in the performance simulation unit 9 from the performance simulation unit 9 via the performance feedback unit 12 will be described.
Also in the present embodiment, the configuration of the information processing apparatus 100 is the same as that shown in FIG.
Also in the present embodiment, the performance simulation unit 9 functions as a predicted execution performance information analysis unit.

FIG. 17 is an example of the H / W configuration that is the target of performance prediction in the present embodiment.
In FIG. 17A, when the performance simulation was executed with the initial number of processors set to two, it was detected that the processing was not completed within the target requested execution time, and was initially executed with two processors. As shown in FIG. 17B, the number of processors is changed to four so that the performance simulation can be re-executed.
That is, the performance simulation unit 9 analyzes the trace / performance parameter information 10 generated by the performance information conversion unit 7 for the hardware configuration with two processors, and as a result, the process is performed within the target requested execution time. When it is detected that the processing has not been completed, the performance simulation unit 9 regenerates the trace / performance parameter information 10 by changing the hardware configuration to four configurations as shown in FIG. 17B. The performance information conversion unit 7 is instructed as follows.
Then, the performance information conversion unit 7 extracts performance information data when there are four processors from the performance information database 6 and generates trace / performance parameter information 10 when there are four processors.

  As described above, according to the present embodiment, by providing a feedback mechanism from the performance simulation result, it is possible to derive an optimal hardware architecture, and the convenience of design support is improved.

Embodiment 9 FIG.
Next, an embodiment in the case where performance prediction is performed mainly for redesign support of a part of functions of the simulation target system will be described.
Also in the present embodiment, the configuration of the information processing apparatus 100 is the same as that shown in FIG.
Also in the present embodiment, the performance simulation unit 9 functions as a predicted execution performance information analysis unit.

When the functional block C which is a part of the existing system shown in FIG. 21A is replaced with the functional block C ′ and a partial function is redesigned as shown in FIG. 21B, first, FIG. ) To execute the functional simulation of the existing system and generate trace information.
Next, the predicted execution performance information generation unit generates predicted execution performance information using the performance target value of the unimplemented function block C ′ instead of the performance information related to the function block C.
A performance simulation is performed using the predicted execution performance information.

  As described above, according to the present embodiment, by providing a mechanism for generating predicted execution performance information with an arbitrary performance value without using information in the performance information database, the performance target of each functional block is valid. This makes it possible to verify whether or not the design support is convenient.

  Here, the characteristics of the information processing apparatus described in the first to ninth embodiments will be described again.

In the first to ninth embodiments, the following functional units are provided, and the functions realized by software and the performance resulting from the hardware architecture can be verified or evaluated independently or in conjunction with each other. The information processing apparatus has been described.
(A) a function selection unit for selecting and setting a model of a control system to be simulated and a control parameter in the function simulation unit;
(B) A function simulation unit that simulates the function of a control system configured by a plurality of control programs, outputs the simulation execution contents as trace information, and outputs the execution results;
(C) a performance selection unit that selects a hardware architecture to be subjected to performance simulation;
(D) a performance information conversion unit that extracts the performance of the hardware specified by the performance selection unit from the performance information database and combines it with the trace information to generate trace / performance parameter information;
(E) a performance simulation unit that receives the trace / performance parameter information as input and outputs a performance result by calculating the use of hardware resources in the simulation target hardware architecture and outputs feedback information to the performance feedback unit;
(F) A performance feedback unit that automatically resets the control parameters of the function simulation unit based on feedback information input from the performance simulation unit.

  In addition, the information processing apparatus according to Embodiments 1 to 9 is a logic that can determine the execution order of each functional block as trace information in a functional block in units of an arbitrary scale program in a control system to be simulated. It is characterized in that typical time information is recorded in time series.

  In addition, the information processing apparatuses according to Embodiments 1 to 9 are characterized by recording a branch pattern in a functional block as time-series trace information.

  In addition, the information processing apparatuses according to Embodiments 1 to 9 are characterized in that, as time-series trace information, runtime parameters that can affect execution time performance are recorded together.

  In addition, the information processing apparatuses according to the first to ninth embodiments are characterized by recording the size, number of times, in / out, IO target, and the like of IO as time-series trace information.

  In addition, the information processing apparatuses according to the first to ninth embodiments are characterized in that the performance information database includes performance information data in each functional block regarding a plurality of hardware architectures.

  In addition, the information processing apparatuses according to Embodiments 1 to 9 are characterized in that the CPU usage time in the functional block is recorded as performance information data in the performance information database.

  In addition, the information processing apparatuses according to Embodiments 1 to 9 are characterized by recording hardware resource usage such as memory and IO bandwidth in each functional block as performance information data of the performance information database.

  In addition, the information processing apparatus according to the first to ninth embodiments records the calculation formula corresponding to the runtime parameter as the hardware resource usage amount in each functional block as the performance information data of the performance information database. Features.

  In addition, the information processing apparatuses according to Embodiments 1 to 9 have, as trace / performance parameter information, logical time information in units of functional blocks similar to the trace information output by the functional simulation unit, and the functional blocks are arbitrary. It is characterized in that the amount of resource consumption consumed on the hardware architecture is maintained in time series.

  In addition, the information processing apparatus according to Embodiments 1 to 9 consumes on any hardware architecture not as a function block unit but as a unit divided by a branch pattern in a function block as trace / performance parameter information. It is characterized by holding the resource usage amount.

  In addition, the information processing apparatus according to the first to ninth embodiments is characterized in that it is possible to individually specify a function block as a unit for acquiring trace information to operate on an arbitrary hardware architecture. To do.

  The information processing apparatuses according to Embodiments 1 to 9 are characterized in that the user can specify the configuration and arrangement of the hardware architecture via the performance selection unit.

  In addition, the information processing apparatus according to the first to ninth embodiments is not limited to the performance information data calculated using the hardware architecture catalog specification in order to generate the performance information data stored in the performance information database. Accuracy of performance simulation by collecting performance information data by actually running benchmark programs created by cutting out the control program used in the target control system in units of functional blocks on the corresponding hardware architecture It is characterized by raising.

  Further, the information processing apparatus according to the first to ninth embodiments uses a performance selection unit so as to use a part or all of a fictitious hardware architecture in which fictitious performance information data not stored in the performance information database is set. It is possible to specify performance with a performance simulation for a fictitious hardware architecture.

  In addition, the information processing apparatus according to Embodiments 1 to 9 performs performance simulation when the function verified by the function simulation unit is evaluated by the performance simulation unit, and as a result, performance cannot be satisfied. It receives the feedback information from the unit via the performance feedback unit, automatically resets the function parameters in the function simulation unit, and can execute the function simulation again.

  In addition, the information processing apparatus according to the first to ninth embodiments performs performance evaluation on the function verified by the function simulation unit by the performance simulation unit, and as a result, uses hardware resources (number of CPUs, etc.) and requests. If the performance cannot be satisfied, it is characterized in that the performance simulation unit again performs the performance evaluation after resetting the allocation method of the functional blocks to the hardware resources and the number of hardware resources to be used.

  Further, the information processing apparatus according to the first to ninth embodiments associates feedback information from the performance simulation unit with the scenario data and the hardware architecture information that has performed the performance simulation in the performance feedback unit. It is characterized by storing as.

FIG. 11 is a diagram illustrating a configuration example of an information processing device according to Embodiments 1 to 9; 1 is a diagram illustrating an example of a simulation target system according to Embodiment 1. FIG. FIG. 5 is a diagram showing an example of trace information according to the first embodiment. The figure of the example of the performance information data of the performance information database which concerns on Embodiment 1. FIG. 6 is a diagram showing an example of trace / performance parameter information according to the first embodiment. FIG. 6 shows an example of a branch pattern according to the second embodiment. FIG. 10 is a diagram illustrating an example of trace information according to the second embodiment. The figure of the example of the performance information data of the performance information database which concerns on Embodiment 2. FIG. 10 is a diagram showing an example of trace / performance parameter information according to the second embodiment. FIG. 10 shows an example of trace information according to the third embodiment. The figure of the performance information data of the performance information database which concerns on Embodiment 3. FIG. 10 is a diagram showing an example of trace / performance parameter information according to the third embodiment. FIG. 10 is a diagram illustrating an example of performance simulation target hardware according to the fourth embodiment. FIG. 20 is a diagram showing an example of a benchmark program according to the fifth embodiment. FIG. 10 is a diagram illustrating an example of functional blocks that require control parameters according to the sixth embodiment. The figure which shows the example by which the hardware architecture which concerns on Embodiment 7 is reset. The figure which shows the example by which the hardware architecture which concerns on Embodiment 8 is reset. FIG. 3 is a flowchart showing an operation example of the information processing apparatus according to the first embodiment. FIG. 10 is a diagram illustrating a hardware configuration example of the information processing apparatus according to the first to ninth embodiments. FIG. 6 is a diagram for explaining a calculation example for solving the CPU usage time chart of each functional block according to the first embodiment. FIG. 25 shows an example of redesigning part of functional blocks according to the ninth embodiment.

Explanation of symbols

  1 function selection unit, 2 function simulation unit, 3 scenario data, 4 execution result, 5 trace information, 6 performance information database, 7 performance information conversion unit, 8 performance selection unit, 9 performance simulation unit, 10 trace / performance parameter information, 11 performance result, 12 performance feedback unit, 13 feedback information database, 100 information processing apparatus.

Claims (10)

A function simulation unit that executes a simulation of a target program composed of a plurality of function blocks, and generates trace information indicating transitions of the function blocks in the executed simulation;
A performance selection unit that selects a target hardware architecture for performance prediction;
Predictive execution for generating predicted execution performance information indicating the predicted execution performance of the target hardware architecture when the target program is executed according to the transition of the functional block indicated by the trace information using the target hardware architecture A performance information generator ,
A performance information database that stores, for each functional block, a predicted execution performance formula for calculating a predicted execution performance of each hardware architecture when executing the target program for each of a plurality of hardware architectures; Have
The predicted execution performance generation unit
From the performance information database, a predicted execution performance calculation formula of the target hardware architecture is extracted for each functional block indicated in the trace information, and a predicted execution performance is calculated using the extracted predicted execution performance calculation formula to be predicted. An information processing apparatus that generates execution performance information . The function simulation unit
Generates trace information where parameter values that can affect the execution performance of the hardware architecture are shown for each functional block,
The predicted execution performance generation unit
2. The information processing according to claim 1 , wherein the predicted execution performance is calculated using a predicted execution performance calculation formula extracted from the performance information database and a parameter value of a corresponding functional block indicated in the trace information. apparatus. The function simulation unit
Execute a simulation for the target program that contains any number of sub function blocks in the function block, generate trace information indicating the transition of the sub function block,
The performance information database is
Store the predicted execution performance formula for each sub-function block,
The predicted execution performance generation unit
From the performance information database, extract the predicted execution performance calculation formula of the target hardware architecture for each sub-function block indicated in the trace information,
A predicted execution performance calculation formula obtained by extracting the predicted execution performance of the target hardware architecture when the target program is executed according to the transition of the sub-function block indicated in the trace information using the target hardware architecture. It is calculated by using information processing apparatus according to claim 1, wherein the generating a predicted execution performance information. The function simulation unit
Generates trace information with parameter values that can affect the execution performance of the hardware architecture shown for each sub-function block,
The predicted execution performance generation unit
The information according to claim 3 , wherein the predicted execution performance is calculated using a predicted execution performance calculation formula extracted from the performance information database and a parameter value of a corresponding sub-function block indicated in the trace information. Processing equipment. The function simulation unit
Execute a simulation for the target program that contains a branch pattern as a sub-function block in the function block, generate trace information indicating the transition of the branch pattern
The predicted execution performance information generation unit
Generating predicted execution performance information indicating the predicted execution performance of the target hardware architecture when the target program is executed according to a branch pattern transition indicated in the trace information using the target hardware architecture; The information processing apparatus according to claim 3. The information processing apparatus further includes:
A function selection unit for designating a hardware allocation form of each functional block of the target program;
The function simulation unit
Execute a simulation for the target program in accordance with the hardware allocation form specified by the function selection unit, generate trace information indicating the transition of the function block in the executed simulation,
The performance selector is
As the target hardware architecture, select a hardware architecture that matches the hardware allocation form specified by the function selection unit,
The predicted execution performance information generation unit
The predicted execution performance information indicating the predicted execution performance of the hardware architecture that matches the hardware allocation mode specified by the function selection unit according to the transition of the function block indicated in the trace information is generated. The information processing apparatus according to 1. The information processing apparatus further includes:
Analyzing the simulation result of the target program by the functional simulation unit, changing any parameter value used for the simulation of the target program, and re-executing the simulation of the target program using the changed parameter value A simulation analysis unit for instructing the function simulation unit,
The function simulation unit
Re-execute the simulation of the target program using the changed parameter value instructed by the simulation analysis unit, and generate trace information indicating the transition of the functional block in the re-executed simulation,
The predicted execution performance information generation unit
The information processing apparatus according to claim 1, wherein predicted execution performance information is generated using trace information generated when the simulation is re-executed by the function simulation unit. The information processing apparatus further includes:
Analyzing the predicted execution performance information generated by the predicted execution performance information generation unit, changing the hardware configuration of the target hardware architecture, and using the target hardware architecture after the hardware configuration change A predicted execution performance information analysis unit that instructs the predicted execution performance information generation unit to regenerate predicted execution performance information;
The predicted execution performance information generation unit
The information processing apparatus according to claim 1, wherein the predicted execution performance information when the target hardware architecture after the hardware configuration change instructed by the predicted execution performance information analysis unit is used is regenerated. A functional simulation step in which a computer executes a simulation of a target program composed of a plurality of functional blocks, and generates trace information indicating a transition of functional blocks in the executed simulation;
A performance selection step in which the computer selects a target hardware architecture for performance prediction;
A computer generates predicted execution performance information indicating the predicted execution performance of the target hardware architecture when the target program is executed according to the transition of the functional block indicated in the trace information using the target hardware architecture have a prediction execution performance information generating step of,
In the predicted execution performance information generation step,
Computer
From a performance information database that stores, for each functional block, a predicted execution performance formula for calculating the predicted execution performance of each hardware architecture when executing the target program for each of a plurality of hardware architectures ,
A predicted execution performance calculation formula of the target hardware architecture is extracted for each functional block indicated in the trace information, and a predicted execution performance is calculated using the extracted predicted execution performance calculation formula to generate predicted execution performance information . An information processing method characterized by the above. A function simulation process for executing a simulation of a target program composed of a plurality of functional blocks and generating trace information indicating the transition of the functional blocks in the executed simulation
A performance selection process for selecting a target hardware architecture for performance prediction;
Predictive execution for generating predicted execution performance information indicating the predicted execution performance of the target hardware architecture when the target program is executed according to the transition of the functional block indicated by the trace information using the target hardware architecture A program for causing a computer to execute performance information generation processing ,
In the predicted execution performance information generation process,
On the computer,
From a performance information database that stores, for each functional block, a predicted execution performance formula for calculating the predicted execution performance of each hardware architecture when executing the target program for each of a plurality of hardware architectures ,
The predicted execution performance calculation formula of the target hardware architecture is extracted for each functional block indicated in the trace information, and the predicted execution performance information is generated by using the extracted predicted execution performance calculation formula to generate the predicted execution performance information. A program characterized by letting

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