JP2009258831A - Simulation device, simulation method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform performance simulation for more precisely estimating the performance of an evaluation object system. <P>SOLUTION: A sequence information input part 18 inputs a plurality of sequence information showing a sequence to be used for performance simulation, and a performance selection part 8 selects a scheduling algorithm in performance simulation by using a plurality of sequence determination standards such as the priority of a function block, the processing time of the function block, and the input sequence of the sequence information, and a processing selection part 13 determines the simulation performance sequence of the function block based on the functioning block shown by each sequence information and the scheduling algorithm, and a processing performance part 14 changes the simulation performance sequence of the function block according to the scheduling algorithm by performing performance simulation according to the determined simulation performance sequence. Thus, it is possible to precisely estimate the performance of the evaluation object system from various points of view. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a performance simulation for estimating the performance of an evaluation target system, for example, at the initial stage of system design before system construction.

Conventionally, when estimating the performance of an evaluation target system, trace information at the time of executing an application program is acquired, and performance simulation is performed based on the trace information to predict the performance of the evaluation target hardware architecture.
An example of such a performance simulation method is described in JP-A-6-59939 (Patent Document 1).
The performance simulation method described in Patent Document 1 accumulates trace information when an application program is executed on a real machine, and the calculation time and communication time of the trace information are changed to the calculation performance and communication performance of the hardware to be simulated. The estimated time is obtained by replacing and simulating.
In addition, an example of a performance simulation method in a system in which a real-time OS (Operating System) taking into account a scheduling method, a queuing method, and the like is described in JP-A-2002-140208 (Patent Document 2).
The performance simulation method described in Patent Document 2 determines the execution order of processes to be executed from priority information in a task according to a schedule method in the real-time OS function.
JP-A-6-59939 JP 2002-140208 A

In the performance simulation method described in Patent Document 1, the performance simulation is executed only in accordance with the execution order of the trace information acquired when executing the application program.
In the performance simulation method described in Patent Document 2, the task execution order is determined using priority information in a task by selecting a schedule method in the real-time OS function.
However, the execution order of the acquired trace information and the OS function are changed by changing the hardware architecture that executes the processing function in the application program and the calculation performance of the hardware according to the change of the hardware architecture for simulation evaluation. Processing may be executed in a different order from the determination method by selection of a certain schedule method.
There are a plurality of methods for determining which processing is prioritized in the evaluation target system by a scheduling algorithm, such as an input order, a priority order, a processing time order, a sequence ID order, and combinations thereof. As a result of the change, the processing may be executed in an order different from the execution order of the acquired trace information and the determination method by selecting the schedule method in the OS function, so that the accuracy of the estimation result by the performance simulation is not good. There is.

  One of the main objects of the present invention is to solve the above-mentioned problems. The scheduling algorithm in the performance simulation is selected, and the performance simulation is executed in accordance with the selected scheduling algorithm. The purpose is to estimate well.

The simulation apparatus according to the present invention is
A simulation device that performs a performance simulation of processing performance of a hardware platform for a data processing sequence including a plurality of data processing components and defining an execution order of the plurality of data processing components,
For multiple target data processing sequences selected as targets for performance simulation, for each target data processing sequence, input the data processing sequence information indicating the multiple target data processing components included in the target data processing sequence and their execution order A data processing sequence information input unit,
A scheduling algorithm selector for selecting a scheduling algorithm in performance simulation;
Based on the execution order of the target data processing components in each target data processing sequence indicated in the data processing sequence information and the scheduling algorithm selected by the scheduling algorithm selection unit, the target data processing in units of the plurality of target data processing sequences A scheduling unit that determines the simulation execution order of components;
And a simulation execution unit that performs a performance simulation in the simulation execution order determined by the scheduling unit.

  According to the present invention, since the scheduling algorithm is selected and the simulation execution order of the target data processing component is determined according to the selected scheduling algorithm, the simulation is executed. The order can be changed, and the performance of the evaluation target system can be accurately estimated from various viewpoints.

Embodiment 1 FIG.
In this embodiment, the trace information is divided into independent data processing sequences for each scenario data that is input data in the operation of the evaluation target system, element information related to scheduling for determining the execution order of the processing is acquired, and scheduling is performed. A simulation apparatus for accurately estimating the performance of an evaluation target system by performing a performance simulation according to the algorithm selection will be described.

The simulation apparatus according to the present embodiment performs a performance simulation on the processing performance of the hardware platform for an evaluation target system including a plurality of functional blocks as shown in FIG. 3, for example.
In the system to be evaluated shown in FIG. 3, a plurality of paths (function block execution order, processing steps) from when measurement data is input to the function block A until a control instruction is output from the function block E or the function block F ) Exists. Each path is referred to as a data processing sequence (hereinafter also referred to as a processing sequence or a sequence).
In addition, functional blocks constituting each processing sequence are also referred to as data processing components.
Further, the evaluation target system shown in FIG. 3 has a large number of processing sequences. Of these many processing sequences, a processing sequence selected as a performance simulation target is also referred to as a target data processing sequence. A functional block included in the target data processing sequence is also referred to as a target data processing component.
Details of FIG. 3 will be described later.

FIG. 1 is a configuration block diagram showing a configuration example of a performance simulation apparatus 100 according to the present embodiment.
In FIG. 1, a function selection unit 1 performs a function model and function setting of an evaluation target system composed of a plurality of functions divided into arbitrary function block units.
The function simulation unit 2 executes function verification based on the function model and function settings.
The scenario data 3 is used for evaluating the functional operation of the evaluation target system and the performance for the operation.
The trace information 4 is a transition information or function indicating which function block is executed and transitioned to the next function block when a function block divided into a plurality in the evaluation target system is executed according to the scenario data in the function simulation. Shows execution history such as branch information in a block.
The trace dividing unit 5 divides the trace information 4 acquired by the function simulation into independent processing sequences for each scenario data. The trace information 4 divided by the trace division unit 5 is called sequence information. One sequence information indicates one processing sequence. The sequence information indicates a plurality of functional blocks included in the target processing sequence and their execution order.

The performance information database 6 is a database that stores performance parameter information 7.
The performance parameter information 7 indicates the result of measuring the processing amount required for processing on each hardware block on various hardware platforms. For example, the prediction processing time for each functional block is shown. The performance parameter information 7 also includes element information related to scheduling for determining the simulation execution order of functional blocks. Furthermore, information for predicting the processing time such as the specification of the hardware platform that executes the evaluation target system is also included.

The performance selection unit 8 specifies on which hardware module each functional block of the evaluation target system is executed, specifies the connection between the hardware modules, and selects and sets a scheduling algorithm for determining the processing execution order. Do.
The performance selection unit 8 includes, for example, the input order of each sequence information to the sequence information input unit 18 described later, the priority order set for each functional block, the length of the prediction processing time of each functional block, and each data A scheduling algorithm is selected using an arbitrary order determination criterion in the order of sequence IDs (Identification) set in the processing sequence.
Further, when combining the above two or more order determination criteria, the performance selection unit 8 determines a priority between the two or more order determination criteria and selects a scheduling algorithm.
The performance selection unit 8 is an example of a scheduling algorithm selection unit.

  The performance simulation unit 9 includes a performance model (scheduling algorithm) constructed based on the performance setting, an independent processing sequence (processing sequence indicated in the sequence information) for each scenario data divided by the trace dividing unit 5, and performance parameter information. To perform a performance simulation.

In the performance simulation unit 9, the sequence information input unit 18 inputs the sequence information divided by the trace division unit 5.
The sequence information input unit 18 is an example of a data processing sequence information input unit.

  The scheduling element information acquisition unit 10 is an element related to scheduling for determining the execution order of processes, such as ID information (sequence information ID), function block priority information, and processing time information of independent processing sequences for each scenario data. Get information.

  The scheduling element selection unit 11 selects necessary scheduling element information from a plurality of scheduling element information acquired by the scheduling element information acquisition unit 10 based on the selection setting of the scheduling algorithm specified by the performance selection unit 8.

The queue model 12 selects and executes a process to be executed when there is a process execution request by a plurality of process sequences, and waits for execution of other processes.
The queue model 12 includes a process selection unit 13 and a process execution unit 14.

The process selection unit 13 selects a process to be executed based on the scheduling element information selected by the scheduling element selection unit 11 when there is a process execution request by a plurality of process sequences.
In other words, the process selection unit 13 simulates the function block in units of a plurality of process sequences based on the execution order of the function blocks in each process sequence indicated by the sequence information and the scheduling algorithm selected by the performance selection unit 8. Determine the execution order.
The process selection unit 13 is an example of a scheduling unit.

The process execution unit 14 assumes that the process selected by the process selection unit 13 has been executed, and allows the process time for the process to elapse.
That is, the process execution unit 14 performs a performance simulation in the simulation execution order determined by the process selection unit 13.
The process execution unit 14 is an example of a simulation execution unit.

Next, the operation will be described.
FIG. 2 is a flowchart showing an operation example of the simulation apparatus 100 according to the present embodiment.
Moreover, an example of the evaluation object system which estimates processing time by performance simulation is shown in FIG.
The evaluation target system shown in FIG. 3 inputs measurement data, performs a function of the function block in accordance with the measurement data, and performs an operation such as transition to the next function block and execution until a control instruction.
As an example of evaluation by the performance simulation method according to the present embodiment, for each scenario data when three scenario data (1) to (3) are simultaneously input to the evaluation target system ( Assume that the processing time for each processing sequence is estimated by performance simulation.
As shown in FIG. 4, scenario data (1) to (3) indicate the execution order of the functional blocks of the evaluation target system up to the control instruction.

The simulation apparatus 100 according to the present embodiment performs a function model and function setting for the evaluation target system in FIG. 3 in order to execute a function simulation (step S1).
A functional simulation is executed when the three scenario data shown in FIG. 4 are input, and trace information is output (steps S2, S3, and S4).
The trace information acquired by executing the function simulation is shown in FIG.
The trace information describes the function block ID executed when three scenario data are input, branch pattern information in the function block, and other information at the time of function block execution.
Sequence information divided for each of the three scenario data from the trace information is created in the trace dividing unit 5 (step S5).
FIG. 6 shows the sequence information divided for each of the three scenario data.
The processing sequence indicated in each sequence information corresponds to the target data processing sequence, and the functional block indicated in each sequence information corresponds to the target data processing component.

  Next, the performance selection unit 8 designates on which hardware module each functional block of the evaluation target system is executed, and selects and sets a scheduling algorithm for determining the execution order of the processing (step S6). (Scheduling algorithm selection step).

FIG. 7 shows a diagram in which each functional block of the evaluation target system is assigned to the hardware module to be a performance simulation target.
In FIG. 7, in the server computer 1 constituted by one CPU (Central Processing Unit), all the functional blocks A to F are specified to be executed.

FIG. 8 shows an example of scheduling algorithm selection settings.
The scheduling algorithm indicates a guideline for determining which functional block is to be processed first when two or more processing execution requests are simultaneously issued to the server computer 1 and the processing requests are in conflict. .
The scheduling algorithm includes one or more ordering criteria.
As an example of order determination criteria, processing is performed in the order of input access of processing (order in which sequence information input unit 18 inputs sequence information) (input order), and priority is assigned to each functional block. To be processed according to the order of priority (in order of priority), to be processed from the one with the shortest prediction processing time for the functional block (in order of short processing time), or from the one with the fastest ID number attached to the sequence information created in the trace division unit 5 (Sequence ID order).
The performance selection unit 8 selects a scheduling algorithm when deciding which process is to be executed first from among competing process requests.
As shown in FIG. 8, when a plurality of order determination criteria are selected, a priority order indicating which order determination criteria are used preferentially is set.
In the example of the scheduling algorithm shown in FIG. 8, three order determination criteria are specified: input order, priority order, and processing time order, and among these three order determination criteria, the priority order has the highest priority, The shortest time order is the second highest priority, and the input order is the lowest priority.
Such a scheduling algorithm determines the simulation execution order between functional blocks included in the three processing sequences.

In the simulation apparatus 100, when executing the performance simulation, the sequence information input unit 18 inputs the sequence information (divided trace information) created in the trace dividing unit 5 (data processing sequence information input step), and the server computer 1 The performance parameter information indicating the processing amount required for the processing of each functional block is input to the performance simulation unit 9 and the performance simulation is executed (steps S7, S8, S9).
The performance parameter information is, for example, information shown in FIG. 9 and indicates the prediction processing time for each functional block.
The performance parameter information may include element information related to scheduling for determining the execution order of the processes. For example, as shown in FIG. 10, the performance parameter information indicates the priority of each functional block along with the predicted processing time for each functional block.

Next, a performance simulation execution procedure will be specifically described.
In this embodiment, a performance simulation execution procedure when only the input order is designated as the scheduling algorithm will be described.

When the sequence information input unit 18 of the performance simulation unit 9 inputs the sequence information divided for each of the three scenario data shown in FIG. 6, the processing request of the functional block to be executed at the beginning of each sequence is accepted.
Assume that the input order in which the processing requests are received is the order of sequence information (1), sequence information (2), and sequence information (3).
In the sequence information (1), there is a processing request for the function block A, and the scheduling element information acquisition unit 10 includes the sequence information (1) input order (first), the sequence information (1) ID, and the performance parameter information. The processing time of a certain function block A and the priority of the function block A are acquired as scheduling element information (step S10).
Next, the scheduling element selection unit 11 inputs the sequence information (1) from the scheduling element information acquired by the scheduling element information acquisition unit 10 in accordance with the selection of the scheduling algorithm designated by the performance selection unit 8 as the input order. The order (first) is selected and output to the queue model 12 (step S11).
Similarly, in the sequence information (2), there is a processing request for the function block A, which is the first processing request, and the scheduling element information acquisition unit 10 acquires the same scheduling element information as in the case of the sequence information (1), and selects the performance. According to the selection of the scheduling algorithm designated as the input order in the unit 8, the scheduling element selection unit 11 selects the input order (second) of the sequence information (2) from the scheduling element information and outputs it to the queuing model 12. (Step S11).
Similarly, in the sequence information (3), there is a processing request for the function block A, which is the first processing request, and the scheduling element information acquisition unit 10 acquires the same scheduling element information as in the case of the sequence information (1), and selects the performance. According to the selection of the scheduling algorithm designated as the input order in the part 8, the scheduling element selection part 11 selects the input order (third) of the sequence information (3) from the scheduling element information and outputs it to the queue model 12 (Step S11).

FIG. 11 is a diagram for explaining the simulation execution order of each functional block of the sequence information (1) to (3).
No. of FIG. The first function block (function block A) of sequence information (1) to (3) and the input order thereof are shown in line 1.
The process selection unit 13 compares the input order information for the accesses of the sequence information (1) to (3), and selects the sequence information (1) with the earlier input order (step S12) (scheduling step).
In the process execution part 14, if the process with respect to the functional block A of sequence information (1) was performed, the process time with respect to the process will be made to pass time (step S13) (simulation execution step).
FIG. 12 shows a time chart in which the processing time 4 [msec] for the functional block A in the sequence (1) is elapsed. In FIG. 12, the processing for the functional block A is represented as processing A.

While there is a processing request, the process returns to step S10 to perform the next process (step S14).
When the processing of the functional block A of the sequence information (1) is completed, a processing request for the next functional block B is received from the sequence information (1). The input order of the function block B of the sequence information (1) is the fourth.
As a result, No. 1 in FIG. As shown in line 2, the input order of function block B, which is the first functional block of sequence information (1), is fourth, and the input order of function block A, which is the first functional block of sequence information (2), is Second, the input order of the functional block A, which is the first functional block of the sequence information (3), is third.
At this stage, the process selection unit 13 selects the sequence information (2) with the earliest input order from these, and the process execution unit 14 executes the process for the functional block A of the sequence information (2). The processing time for is elapsed.
By repeating this operation until there is no processing request, the estimated processing time for each sequence is 27 [msec] for sequence (1) and 32 for sequence (2) as shown in the time chart of FIG. [Msec], the sequence (3) can obtain a result of 31 [msec]. In FIG. 12, the processes for the functional blocks A to F are denoted as processes A to F.

As described above, when the access input order is selected as the scheduling algorithm, the processing time for each of the scenario data (1) to (3) can be estimated.
Therefore, the estimated processing time can be obtained for each scenario data to be evaluated by the performance simulation.

As described above, in the present embodiment, for a system composed of a plurality of functions divided into arbitrary functional block units, the system performance is determined according to the trace information indicating the execution order of the functional blocks and the performance information database for the functional blocks. In the performance simulation to estimate
Means to divide the trace information into independent processing sequences for each input data to be input to the program of the target system, and information that is a judgment factor in deciding which processing is to be executed for a plurality of divided processing sequences In a configuration comprising scheduling element information acquisition means for acquiring and means for selecting only necessary scheduling element information from scheduling element information according to the design of the scheduling algorithm,
A performance simulation method that can accurately estimate the performance of the system corresponding to the design of the scheduling algorithm is described.

Embodiment 2. FIG.
In executing the performance simulation, when the priority order and the input order are selected as the order determination criteria of the scheduling algorithm described with reference to FIG. 8, the priority order is 1 and the input order is 2, that is, the priority order. When the order is the same, a scheduling algorithm that determines the process to be executed will be described according to the input order.

When the sequence information input unit 18 of the performance simulation unit 9 inputs the sequence information divided for each of the three scenario data shown in FIG. 6, the processing request for the functional block to be executed first is received for each sequence information.
Assume that the input order in which the processing requests are received is the order of sequence information (1), sequence information (2), and sequence information (3).
In the sequence information (1), there is a processing request for the functional block A. As in the first embodiment, the scheduling element information acquisition unit 10 determines the order of input of the sequence information (1) (first), sequence information (1 ), The processing time of the functional block A in the performance parameter information, and the priority (priority 3) of the functional block A are acquired as scheduling element information (step S10).
Next, the scheduling element selection unit 11 is in the performance parameter information from the scheduling element information acquired by the scheduling element information acquisition unit 10 in accordance with the selection of the scheduling algorithm designated by the performance selection unit 8 as the priority order and the input order. The order of input (first) of priority information (priority 3) and sequence information (1) of the function block A is selected and output to the queue model 12 (step S11).
Similarly, in the sequence information (2), the priority information (priority 3) which is the scheduling element information for the function block A and the input order (second) of the sequence information (2) are selected and output to the queue model 12 (Step S11).
Similarly, in the sequence information (3), the priority information (priority 3) which is scheduling element information for the functional block A and the input order (third) of the sequence information (3) are selected and output to the queue model 12 (Step S11).

FIG. 13 is a diagram for explaining the simulation execution order of each functional block of the sequence information (1) to (3).
No. in FIG. The first function block (function block A) of sequence information (1) to (3) and its priority are shown in line 1.
The process selection unit 13 compares the priority information of the function blocks of the sequence information (1) to (3) with the input order information, and selects a sequence with a high priority. If there is no difference in priority, the sequence with the fastest input order is selected.
In this case, since all three priority levels are “3”, the sequence information (1) with the earlier input order is selected (step S12).
In the process execution part 14, suppose that the process with respect to the functional block A of sequence information (1) was performed, the process time with respect to the process is made to pass time (step S13).
FIG. 14 shows a time chart in which the processing time 4 [msec] for the function block A of the sequence information (1) is elapsed.

When the processing of the functional block A of the sequence information (1) is completed, a processing request for the next functional block B is received from the sequence information (1). The priority of the function block B is “1”.
For this reason, No. 1 in FIG. As shown in the row 2, the priority of the functional block B that is the first functional block of the sequence information (1) is “1”, and the first functional block of the sequence information (2) and the sequence information (3) is the first functional block. The priority of a certain function block A is “3”.
The process selection unit 13 selects sequence information (1) having a high priority from the above, and the process execution unit 14 executes the process for the function block B of the sequence information (1). Let time elapse.
By repeating such an operation until there is no processing request, the estimated processing time for each sequence is 12 [msec] for sequence (1) and 32 for sequence (2) as shown in the time chart of FIG. [Msec], the sequence (3) can obtain a result of 28 [msec].
In FIG. 14, processes for the functional blocks A to F are denoted as processes A to F.

As described above, when the priority order is selected as the scheduling algorithm, the processing time for each of the scenario data (1) to (3) can be estimated.
In addition, when estimating the difference in processing time due to changes in the priority of each functional block, it is only necessary to perform a performance simulation by changing the priority of each functional block in the performance parameter information. The processing time due to the change can be easily estimated.
Therefore, the estimated processing time can be obtained for each scenario data to be evaluated by the performance simulation.

  As described above, in this embodiment, by adding priority information indicating which functional block processing is preferentially performed to a functional block, the system performance corresponding to the scheduling algorithm based on the priority for the functional block is added. The performance simulation method that can estimate

Embodiment 3 FIG.
When executing the performance simulation, the order of the shortest processing time and the input order are selected as the criteria for determining the order of the scheduling algorithm described in FIG. 8, and the two priorities are the order of the shortest processing time and the input order is 2. That is, the scheduling algorithm for determining the processing to be executed according to the input order when the processing time is the same in short order will be described.

When the sequence information input unit 18 of the performance simulation unit 9 inputs the sequence information divided for each of the three scenario data shown in FIG. 6, the processing request for the functional block to be executed first is received for each sequence information.
Assume that the input order in which the processing requests are received is the order of sequence information (1), sequence information (2), and sequence information (3).
In the sequence information (1), there is a processing request for the functional block A. As in the first embodiment, the scheduling element information acquisition unit 10 determines the order of input of the sequence information (1) (first), sequence information (1 ), The processing time (4 [msec]) of the function block A in the performance parameter information, and the priority of the function block A are acquired as scheduling element information (step S10).
Next, the performance parameter information is selected from the scheduling element information acquired in the scheduling element information acquisition unit 10 by the scheduling element selection unit 11 according to the selection of the scheduling algorithm designated by the performance selection unit 8 in the order of short processing time and input order. The input order (first) of the processing time information (4 [msec]) and sequence information (1) of the functional block A is selected and output to the queue model 12 (step S11).
Similarly, in the sequence information (2), the processing time information (4 [msec]) which is the scheduling element information for the function block A and the input order (second) of the sequence information (2) are selected, and the queue model 12 is selected. Output (step S11).
Similarly, in the sequence information (3), the processing time information (4 [msec]) that is scheduling element information for the function block A and the input order (third) of the sequence information (2) are selected, and the queue model 12 is selected. Output (step S11).

FIG. 15 is a diagram for explaining the simulation execution order of each functional block of the sequence information (1) to (3).
No. in FIG. The first function block (function block A) of sequence information (1) to (3) and its processing time are shown in line 1.
The processing selection unit 13 compares the processing time information of the functional blocks of the sequence information (1) to (3) with the input order information, and selects a sequence with a short processing time. If there is no difference in processing time, a sequence with the fastest input order is selected.
In this case, since all three processing times are 4 [msec], the sequence information (1) with the earlier input order is selected (step S12).
In the process execution part 14, suppose that the process with respect to the functional block A of sequence information (1) was performed, the process time with respect to the process is made to pass time (step S13).
FIG. 16 shows a time chart in which the processing time 4 [msec] for the function block A of the sequence information (1) is elapsed.

When the processing of the functional block A of the sequence information (1) is completed, a processing request for the next functional block B is received from the sequence information (1). The processing time of the function block B is 2 [msec].
For this reason, No. 1 in FIG. As shown in the row 2, the processing time of the functional block B which is the first functional block of the sequence information (1) is 2 [msec], and the first functional block of the sequence information (2) and the sequence information (3) The processing time of the functional block A is 4 [msec].
The process selection unit 13 selects the sequence information (1) having a short processing time from the list, and the process execution unit 14 executes the process for the function block B of the sequence information (1). Let time elapse.
By repeating this operation until there is no processing request, the estimated processing time for each sequence is 32 [msec] for sequence (1) and 26 for sequence (2) as shown in the time chart of FIG. [Msec], Sequence (3) can obtain a result of 17 [msec].
In FIG. 16, processes for the functional blocks A to F are denoted as processes A to F.

As described above, when the order of short processing time is selected as the scheduling algorithm, the processing time for each of the scenario data (1) to (3) can be estimated.
Further, when the performance is estimated based on the difference in the hardware to be simulated, the processing time of each functional block corresponding to the hardware to be simulated can be obtained from the performance information database 6. It is possible to easily and accurately obtain an estimate of the processing time due to the change of the wear.
Therefore, the estimated processing time can be obtained for each scenario data to be evaluated by the performance simulation.

  As described above, in this embodiment, the performance simulation method that can estimate the system performance corresponding to the scheduling algorithm that preferentially processes the functional block with a short processing time from the information in the performance information database for the functional block is described. did.

Embodiment 4 FIG.
In performing the performance simulation, the ID sequence of the processing sequence is selected as the scheduling algorithm order determination criterion described with reference to FIG. 8, that is, the scheduling algorithm that determines the processing to be executed according to the order of the ID of the processing sequence will be described.

When the sequence information input unit 18 of the performance simulation unit inputs the sequence information divided for each of the three scenario data shown in FIG. 6, the processing request for the functional block to be executed first is received.
Assume that the input order in which the processing requests are received is the order of sequence information (1), sequence information (2), and sequence information (3).
In the sequence information (1), there is a processing request for the functional block A, and as in the first embodiment, the scheduling element information acquisition unit 10 determines the order of input of the sequence information (1), the ID of the sequence information (1), The processing time of the functional block A and the priority of the functional block A in the performance parameter information are acquired as scheduling element information (step S10).
Next, the scheduling element selection unit 11 selects the sequence ID information (1) from the scheduling element information acquired by the scheduling element information acquisition unit 10 in accordance with the selection of the scheduling algorithm designated as the sequence ID order by the performance selection unit 8 And output to the queue model 12 (step S11).
Similarly, in the sequence information (2), the sequence ID information (2) that is the scheduling element information for the function block A is selected and output to the queue model 12 (step S11).
Similarly, in the sequence information (3), the sequence ID information (3) which is the scheduling element information for the functional block A is selected and output to the queue model 12 (step S11).

FIG. 17 is a diagram illustrating the simulation execution order of each functional block of the sequence information (1) to (3).
No. in FIG. The first functional block (functional block A) of sequence information (1) to (3) and its sequence ID information are shown in line 1.
The process selection unit 13 compares the sequence ID information of the sequence information (1) to (3), and selects the sequence information having an earlier (smaller) sequence ID.
In this case, the sequence information (1) whose sequence ID is “1” is selected (step S12).
In the process execution part 14, suppose that the process with respect to the functional block A of sequence information (1) was performed, the process time with respect to the process is made to pass time (step S13).
FIG. 18 shows a time chart in which the processing time 4 [msec] for the functional block A of the sequence information (1) is elapsed.

When the processing of the functional block A of the sequence information (1) is completed, a processing request for the next functional block B is received from the sequence information (1). The sequence ID information of the functional block B is “1”.
For this reason, No. 1 in FIG. As shown in the row 2, the sequence ID of the functional block B which is the first functional block of the sequence information (1) is “1”, and the first functional block of the sequence information (2) and the sequence information (3) The sequence IDs of a certain functional block A are “2” and “3”, respectively.
The process selection unit 13 selects the sequence information (1) with the earlier sequence ID from these, and the process execution unit 14 executes the process for the functional block B of the sequence information (1). Let time elapse.
By repeating this operation until there is no processing request, the estimated processing time for each sequence is 12 [msec] for sequence (1) and 25 for sequence (2) as shown in the time chart of FIG. [Msec], the sequence (3) can obtain a result of 32 [msec].
In FIG. 18, processes for the functional blocks A to F are denoted as processes A to F.

As described above, when the processing sequence ID order is selected as the scheduling algorithm, the processing time for each of the scenario data (1) to (3) can be estimated.
Therefore, the estimated processing time can be obtained for each scenario data to be evaluated by the performance simulation.

  As described above, in the present embodiment, the performance capable of estimating the system performance corresponding to the scheduling algorithm that preferentially processes the processing sequence having a smaller processing sequence number than the processing sequence order information obtained by dividing the trace information. The simulation method has been described.

Embodiment 5 FIG.
In executing the performance simulation, the priority order, the shortest processing time order, and the input order are selected as the order determination criteria of the scheduling algorithm described in FIG. 8, and the three priority orders are the priority order, and the processing time is the shortest order. When the input order is 3, that is, when the priority order is the same, the scheduling algorithm determines the processing to be executed according to the order of short processing time, and further according to the input order when the order of short processing time is the same. Give an explanation.

When the sequence information input unit 18 of the performance simulation unit 9 inputs the sequence information divided for each of the three scenario data shown in FIG. 6, the processing request for the functional block to be executed first is received for each sequence information.
Assume that the input order in which the processing requests are received is the order of sequence information (1), sequence information (2), and sequence information (3).
In the sequence information (1), there is a processing request for the functional block A. As in the first embodiment, the scheduling element information acquisition unit 10 determines the order of input of the sequence information (1) (first), sequence information (1 ), The processing time of the functional block A (4 [msec]) in the performance parameter information, and the priority (priority 3) of the functional block A are acquired as scheduling element information (step S10).
Next, the scheduling element selection unit 11 selects the scheduling element information acquired by the scheduling element information acquisition unit 10 in accordance with the selection of the scheduling algorithm designated by the performance selection unit 8 as priority order, processing time order, and input order. From the function block priority information (priority level 3), processing time information (4 [msec]), sequence information (1) input order (first) in the performance parameter information, and to the queue model 12 Output (step S11).
Similarly, in the sequence information (2), the priority order information (priority 3) of the functional block, which is scheduling element information for the functional block A, the processing time information (4 [msec]), and the order of input of the sequence information (2) ( 2nd) is selected and output to the queue model 12 (step S11).
In the sequence information (3), the function block priority information (priority 3), processing time information (4 [msec]), and sequence information (3) input order (scheduling element information for the function block A) 3rd) is selected and output to the queue model 12 (step S11).

FIG. 19 is a diagram illustrating the simulation execution order of each functional block of the sequence information (1) to (3).
No. in FIG. The first function block (function block A) of sequence information (1) to (3), its priority, and processing time are shown in line 1.
The process selection unit 13 compares the priority information, the processing time information, and the input order information of the functional blocks of the sequence information (1) to (3), and selects a sequence with a high priority.
If there is no difference in priority, a sequence with a short processing time is selected.
Further, when there is no difference in processing time, a sequence with an earlier input order is selected.
In this case, the priority is “3” for all three, and the processing time for all three is 4 [msec], so the sequence information (1) in the order of input is selected (step S12).
In the process execution part 14, suppose that the process with respect to the functional block A of sequence information (1) was performed, the process time with respect to the process is made to pass time (step S13).
FIG. 20 shows a time chart in which the processing time 4 [msec] for the functional block A in the sequence (1) is elapsed.

When the processing of the functional block A of the sequence information (1) is completed, a processing request for the next functional block B is received from the sequence information (1).
The priority of the functional block B is “1”, and the processing time is 2 [msec].
Therefore, the functional block, priority, and processing time of each sequence information at this stage are shown in No. It looks like 2 rows.
The process selection unit 13 selects sequence information (1) having a high priority from the above, and the process execution unit 14 executes the process for the function block B of the sequence information (1). Let time elapse.
By repeating this operation until there is no processing request, the estimated processing time for each sequence is 12 [msec] for sequence (1) and 32 for sequence (2) as shown in the time chart of FIG. [Msec], the sequence (3) can obtain a result of 23 [msec].
In FIG. 20, processes for the functional blocks A to F are denoted as processes A to F.

As described above, when the scheduling algorithm is selected by combining the order of priority and the order of short processing time, the processing time for each of the scenario data (1) to (3) can be estimated.
Therefore, the estimated processing time can be obtained for each scenario data to be evaluated by the performance simulation.

  As described above, in the present embodiment, a plurality of scheduling elements are obtained from a plurality of scheduling element information such as priority information indicating which functional blocks are preferentially processed with respect to the functional blocks, and performance information database information for the functional blocks. The performance simulation method that can estimate the performance of the system corresponding to the algorithm obtained from the combination of the algorithms was explained.

Embodiment 6 FIG.
FIG. 22 shows a configuration example of the simulation apparatus 100 according to the present embodiment.
The simulation apparatus 100 according to the present embodiment has the same configuration as that shown in FIG. 1 except that a performance feedback unit 15 and a feedback information database 16 are added.

The performance feedback unit 15 obtains the best setting by the performance selection unit 8 by changing the setting by the performance selection unit 8 and repeating the acquisition of the performance simulation result.
More specifically, the performance feedback unit 15 compares the processing performance obtained as a result of the performance simulation by the processing execution unit 14 with a predetermined target performance every time the performance simulation is performed by the processing execution unit 14. The scheduling algorithm is repeatedly changed until the processing performance obtained as a result of the performance simulation by the execution unit 14 matches the target performance.
The performance feedback unit 15 is an example of a scheduling algorithm changing unit.
The feedback information database 16 is a database for storing performance simulation results when the performance feedback unit 15 is executed.

FIG. 23 is a flowchart showing an operation example of the simulation apparatus 100 according to the present embodiment.
The flow shown in FIG. 23 is the same as that shown in FIG. 2 except that the processes of S16 and S17 are added.
Hereinafter, S16 and S17 will be described.

  Here, when the three scenario data (1) to (3) are simultaneously input to the evaluation target system, the performance feedback unit 15 performs the scenario data (1) and the scenario data ( An example of obtaining a scheduling algorithm for 3) satisfying the target performance will be described.

The performance feedback unit 15 determines whether the result of the performance simulation satisfies the target performance. If not, the selection of the scheduling algorithm is changed and the performance simulation is performed again.
Scheduling to determine the execution order of processes such as ID information of independent processing sequences, priority information of function blocks, and processing time information for each scenario data obtained from performance simulation results when changing the selection of scheduling algorithm The performance feedback unit 15 selects a scheduling algorithm based on the element information regarding
In the following, the performance feedback unit 15 sets the target performance that the processing time for the sequence information (1) is 20 [msec] or less and the processing time for the sequence information (3) is 30 [msec] or less, and the performance feedback unit 15 An example of obtaining a scheduling algorithm for satisfying the target performance for the sequence information (1) and the sequence information (3) will be described.

For example, assume that the input order is first selected as the scheduling algorithm, and the performance simulation unit 9 executes the performance simulation according to the scheduling algorithm in the input order as shown in the first embodiment.
As a result of the performance simulation, as shown in FIG. 12, the sequence information (1) is determined to be 27 [msec] and the sequence information (3) is determined to be 31 [msec], and the performance feedback unit 15 determines that the target performance is not satisfied. The results are stored in the feedback information database 16 and the scheduling algorithm selection is changed (steps S16, S17, S6).
In the scheduling algorithm to be changed, the scheduling algorithm is determined based on the element information related to scheduling for determining the execution order of the processing obtained from the performance simulation result.
As shown in FIG. 21, the total value of the priority values for the executed function blocks is obtained for each sequence information from the performance simulation result.
In addition, the total processing time for the executed function block is obtained for each sequence information.
The processing sequence ID information is 1 for sequence information (1), 2 for sequence information (2), and 3 for sequence information (3).

From the above, the performance feedback unit 15 adds the sequence information (1) and the sequence information (3) together in order to satisfy the target performance of the sequence information (1) and the sequence information (3) compared to the sequence information (2). Select a scheduling algorithm with a low value.
Therefore, in the sequence ID order, the sequence information (3) is excluded from the selection because the value of the processing sequence ID information is larger than the sequence information (2).
Since the total processing time for the sequence information (1) is not much different from the sequence information (2), the performance feedback unit 15 finally selects the priority order as the scheduling algorithm compared to the order of priority in the order of shorter processing times. To do.

And the performance simulation part 9 performs the performance simulation by priority order as a scheduling algorithm.
As a result of the performance simulation, scenario data (1) is 12 [msec] and scenario data (3) is 28 [msec] as shown in FIG. 14, and the performance feedback unit 15 determines that the target performance is satisfied and ends ( Step S18).

  As described above, by performing the performance simulation by the feedback process, a scheduling algorithm that satisfies the target performance can be derived for the evaluation target.

  As described above, in the present embodiment, the performance that can lead to the best scheduling algorithm corresponding to the evaluation target data by changing the selection setting of a plurality of scheduling algorithms and repeatedly executing the performance simulation and storing the results. The simulation method has been described.

Finally, a hardware configuration example of the simulation apparatus 100 shown in the first to sixth embodiments will be described.
FIG. 24 is a diagram illustrating an example of hardware resources of the simulation apparatus 100 illustrated in the first to sixth embodiments.
Note that the configuration in FIG. 24 is merely an example of the hardware configuration of the simulation apparatus 100, and the hardware configuration of the simulation apparatus 100 is not limited to the configuration illustrated in FIG. .

In FIG. 24, the simulation apparatus 100 includes a CPU 911 (also referred to as a central processing unit, a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, and a processor) that executes a program.
The CPU 911 is connected to, for example, a ROM (Read Only Memory) 913, a RAM (Random Access Memory) 914, a communication board 915, a display device 901, a keyboard 902, a mouse 903, and a magnetic disk device 920 via a bus 912. Control hardware devices.
Further, the CPU 911 may be connected to an FDD 904 (Flexible Disk Drive), a compact disk device 905 (CDD), a printer device 906, and a scanner device 907. Further, instead of the magnetic disk device 920, a storage device such as an optical disk device or a memory card (registered trademark) read / write device may be used.
The RAM 914 is an example of a volatile memory. The storage media of the ROM 913, the FDD 904, the CDD 905, and the magnetic disk device 920 are an example of a nonvolatile memory. These are examples of the storage device.
A communication board 915, a keyboard 902, a mouse 903, a scanner device 907, an FDD 904, and the like are examples of input devices.
The communication board 915, the display device 901, the printer device 906, and the like are examples of output devices.

  The communication board 915 is connected to the network. For example, the communication board 915 is connected to a LAN (local area network), the Internet, a WAN (wide area network), or the like.

The magnetic disk device 920 stores an operating system 921 (OS), a window system 922, a program group 923, and a file group 924.
The programs in the program group 923 are executed by the CPU 911 using the operating system 921 and the window system 922.

The RAM 914 temporarily stores at least part of the operating system 921 program and application programs to be executed by the CPU 911.
The RAM 914 stores various data necessary for processing by the CPU 911.

The ROM 913 stores a BIOS (Basic Input Output System) program, and the magnetic disk device 920 stores a boot program.
When the simulation apparatus 100 is activated, the BIOS program in the ROM 913 and the boot program in the magnetic disk device 920 are executed, and the operating system 921 is activated by the BIOS program and the boot program.

  The program group 923 stores a program for executing the function described as “˜unit” in the description of the first to sixth embodiments. The program is read and executed by the CPU 911.

In the file group 924, in the description of the first to sixth embodiments, “determination of”, “calculation of”, “comparison of”, “evaluation of”, “update of”, “setting of” ”,“ Registration of ”,“ Selection of ”, etc. Information, data, signal values, variable values, and parameters indicating the results of the processing are indicated as“ ˜file ”and“ ˜database ”items. It is remembered.
The “˜file” and “˜database” are stored in a recording medium such as a disk or a memory. Information, data, signal values, variable values, and parameters stored in a storage medium such as a disk or memory are read out to the main memory or cache memory by the CPU 911 via a read / write circuit, and extracted, searched, referenced, compared, and calculated. Used for CPU operations such as calculation, processing, editing, output, printing, and display.
Information, data, signal values, variable values, and parameters are stored in the main memory, registers, cache memory, and buffers during the CPU operations of extraction, search, reference, comparison, calculation, processing, editing, output, printing, and display. It is temporarily stored in a memory or the like.
The arrows in the flowcharts described in the first to sixth embodiments mainly indicate input / output of data and signals. The data and signal values are the RAM 914 memory, the FDD 904 flexible disk, the CDD 905 compact disk, and the magnetic field. Recording is performed on a recording medium such as a magnetic disk of the disk device 920, other optical disks, mini disks, DVDs, and the like. Data and signals are transmitted online via a bus 912, signal lines, cables, or other transmission media.

  In addition, what is described as “to part” in the description of the first to sixth embodiments may be “to circuit”, “to device”, “to device”, and “to step”, It may be “˜procedure” or “˜processing”. That is, what is described as “˜unit” may be realized by firmware stored in the ROM 913. Alternatively, it may be implemented only by software, only hardware such as elements, devices, substrates, wirings, etc., or a combination of software and hardware, and further a combination of firmware. Firmware and software are stored as programs in a recording medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD. The program is read by the CPU 911 and executed by the CPU 911. That is, the program causes the computer to function as “to part” in the first to sixth embodiments. Alternatively, the computer executes the procedure and method of “to unit” in the first to sixth embodiments.

  As described above, the simulation apparatus 100 according to the first to sixth embodiments includes a CPU that is a processing device, a memory that is a storage device, a magnetic disk, a keyboard that is an input device, a mouse, a communication board, and a display device that is an output device, and a communication board. As described above, the function indicated as “to part” is realized by using these processing device, storage device, input device, and output device.

FIG. 3 shows a configuration example of a simulation apparatus according to the first embodiment. FIG. 3 is a flowchart showing an operation example of the simulation apparatus according to the first embodiment. FIG. 3 is a diagram illustrating an example of an evaluation target system according to the first embodiment. FIG. 4 shows an example of scenario data according to the first embodiment. FIG. 5 is a diagram showing an example of trace information according to the first embodiment. FIG. 4 is a diagram showing an example of sequence information according to the first embodiment. FIG. 3 is a diagram illustrating an example of performance simulation target hardware according to the first embodiment. FIG. 3 shows an example of a scheduling algorithm according to the first embodiment. FIG. 4 is a diagram showing an example of performance parameter information according to the first embodiment. FIG. 4 is a diagram showing an example of performance parameter information according to the first embodiment. FIG. 4 is a diagram illustrating an example of an execution order of performance simulation according to the first embodiment. FIG. 6 is a diagram illustrating an example of a performance simulation result according to the first embodiment. FIG. 10 is a diagram illustrating an example of an execution order of performance simulation according to the second embodiment. FIG. 10 is a diagram illustrating an example of a result of performance simulation according to the second embodiment. FIG. 10 is a diagram illustrating an example of an execution order of performance simulation according to the third embodiment. FIG. 10 is a diagram illustrating an example of a performance simulation result according to the third embodiment. FIG. 10 is a diagram illustrating an example of an execution order of performance simulation according to the fourth embodiment. FIG. 10 is a diagram illustrating an example of a performance simulation result according to the fourth embodiment. FIG. 10 is a diagram illustrating an example of an execution order of performance simulation according to the fifth embodiment. FIG. 10 is a diagram illustrating an example of a performance simulation result according to the fifth embodiment. The figure which shows the example of the sum total of the priority which concerns on Embodiment 6, and processing time. FIG. 10 illustrates a configuration example of a simulation apparatus according to a sixth embodiment. FIG. 10 is a flowchart showing an operation example of the simulation apparatus according to the sixth embodiment. The figure which shows the hardware structural example of the simulation apparatus which concerns on Embodiment 1-6.

Explanation of symbols

  1 function selection unit, 2 function simulation unit, 3 scenario data, 4 trace information, 5 trace division unit, 6 performance information database, 7 performance parameter information, 8 performance selection unit, 9 performance simulation unit, 10 scheduling element information acquisition unit, DESCRIPTION OF SYMBOLS 11 Scheduling element selection part, 12 Queue model, 13 Process selection part, 14 Process execution part, 15 Performance feedback part, 16 Feedback information database, 18 Sequence information input part, 100 Simulation apparatus.

Claims (9)

A simulation device that performs a performance simulation of processing performance of a hardware platform for a data processing sequence including a plurality of data processing components and defining an execution order of the plurality of data processing components,
For multiple target data processing sequences selected as targets for performance simulation, for each target data processing sequence, input the data processing sequence information indicating the multiple target data processing components included in the target data processing sequence and their execution order A data processing sequence information input unit,
A scheduling algorithm selector for selecting a scheduling algorithm in performance simulation;
Based on the execution order of the target data processing components in each target data processing sequence indicated in the data processing sequence information and the scheduling algorithm selected by the scheduling algorithm selection unit, the target data processing in units of the plurality of target data processing sequences A scheduling unit that determines the simulation execution order of components;
And a simulation execution unit that performs a performance simulation in the simulation execution order determined by the scheduling unit. The scheduling algorithm selection unit includes:
The simulation apparatus according to claim 1, wherein a scheduling algorithm is selected using an arbitrary order determination criterion among a plurality of order determination criteria for determining a simulation execution order. The scheduling algorithm selection unit includes:
Input order of each data processing sequence information to the data processing sequence information input unit, priority order set for each target data processing component, length of prediction processing time of each target data processing component, and each target data processing The simulation apparatus according to claim 2, wherein a scheduling algorithm is selected using an arbitrary order determination criterion among sequences of sequence IDs (Identification) set in the sequence. The scheduling algorithm selection unit includes:
3. When combining two or more order determination criteria among a plurality of order determination criteria, a priority is determined between the two or more order determination criteria, and a scheduling algorithm is selected. 3. The simulation apparatus according to 3. The simulation apparatus further includes:
A scheduling algorithm changing unit for changing the scheduling algorithm selected by the scheduling algorithm selecting unit when the processing performance obtained as a result of the performance simulation by the simulation executing unit does not match a predetermined target performance;
The scheduling unit includes
Based on the scheduling algorithm after the change by the scheduling algorithm change unit, determine the simulation execution order of the target data processing component,
The simulation execution unit
The simulation apparatus according to claim 1, wherein the performance simulation is performed in a simulation execution order determined by the scheduling unit based on the changed scheduling algorithm. The scheduling algorithm changing unit includes:
Each time performance simulation is performed by the simulation execution unit, the processing performance obtained as a result of the performance simulation by the simulation execution unit is compared with the target performance, and the processing performance obtained as a result of the performance simulation by the simulation execution unit. The simulation apparatus according to claim 5, wherein the scheduling algorithm is repeatedly changed until the target performance matches the target performance. The simulation execution unit
7. The processing time when the hardware platform executes a plurality of target data processing components in the simulation execution order determined by the scheduling unit is predicted as performance simulation. The simulation apparatus described. A computer simulation method for performing performance simulation on processing performance of a hardware platform for a data processing sequence including a plurality of data processing components and defining an execution order of the plurality of data processing components,
Data processing in which a plurality of target data processing sequences included in the target data processing sequence and their execution order are indicated for each target data processing sequence for the plurality of target data processing sequences selected by the computer as performance simulation targets A data processing sequence information input step for inputting sequence information;
A scheduling algorithm selection step in which the computer selects a scheduling algorithm in performance simulation;
The computer uses the plurality of target data processing sequence units based on the execution order of the target data processing components in each target data processing sequence indicated in the data processing sequence information and the scheduling algorithm selected by the scheduling algorithm selection step. Scheduling step for determining the simulation execution order of the target data processing component in
A simulation method characterized in that the computer has a simulation execution step of performing a performance simulation in the simulation execution order determined by the scheduling step. A computer that performs a performance simulation on the processing performance of the hardware platform for a data processing sequence that includes a plurality of data processing components and that defines the execution order of the plurality of data processing components.
For multiple target data processing sequences selected as targets for performance simulation, for each target data processing sequence, input the data processing sequence information indicating the multiple target data processing components included in the target data processing sequence and their execution order Data processing sequence information input processing,
Scheduling algorithm selection processing for selecting a scheduling algorithm in performance simulation;
Based on the execution order of the target data processing components in each target data processing sequence indicated in the data processing sequence information and the scheduling algorithm selected by the scheduling algorithm selection processing, the target data processing in units of the plurality of target data processing sequences A scheduling process for determining the simulation execution order of components;
A program for executing a simulation execution process for performing a performance simulation in a simulation execution order determined by the scheduling process.

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