JP4840938B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to an operation control circuit of a semiconductor memory device having a plurality of operation modes, for example.

  There are SRAM and DRAM as typical semiconductor memory devices which can be randomly accessed. SRAM has faster read / write operations than DRAM and does not require a refresh operation like DRAM, so it has the advantages of being easy to handle and having a small data retention current in the standby state. In order to construct an SRAM, six transistors are required for each memory cell, and therefore there is a problem that the chip size is larger and the price is higher than that of a DRAM.

  In contrast, since a DRAM memory cell can be composed of one capacitor and one transistor, a large-capacity memory can be constructed with a small chip size, and a semiconductor memory device having the same storage capacity can be constructed. If so, DRAM is cheaper than SRAM. However, the DRAM separately supplies a row address and a column address as addresses, and requires a RAS (row address strobe) signal and a CAS (column address strobe) signal as signals for defining the fetch timing of these addresses. Since a control circuit for periodically refreshing the memory cells is required, there are problems that the timing control is more complicated and the current consumption becomes larger than that of the SRAM.

  By the way, SRAM is currently the mainstream of semiconductor memory devices employed in portable electronic devices typified by cellular phones. This is because SRAM has low standby current and low power consumption, so it is suitable for mobile phones that want to extend continuous talk time and continuous standby time as much as possible, and conventional mobile phones have only simple functions. The reason for this is that a large-capacity semiconductor memory device is not necessary, and that the SRAM is easy to handle in terms of timing control.

  On the other hand, recent mobile phones are equipped with a function for sending and receiving e-mail and a function for simplifying and displaying the contents of a homepage by accessing a WEB server on the Internet. It is also assumed that it will be possible to freely access homepages on the Internet in the same way. In order to realize such a function, graphic display for providing various multimedia information to users is indispensable, and a large amount of data received from a public network or the like is temporarily stored in a mobile phone. Therefore, it becomes necessary to provide a large capacity semiconductor memory device.

  On the other hand, portable electronic devices are required to be small, light, and have low power consumption. Therefore, even if the capacity of a semiconductor memory device is increased, the size, weight, and power consumption of the device itself must be avoided. Therefore, an SRAM is preferable as a semiconductor memory device mounted on a portable electronic device in view of ease of handling and power consumption, but a DRAM is preferable from the viewpoint of large capacity. In other words, it can be said that a semiconductor memory device incorporating the advantages of SRAM and DRAM is most suitable for future portable electronic devices.

  As such a semiconductor memory device, a so-called “pseudo SRAM” having substantially the same specifications as an SRAM when viewed from the outside while using the same memory cells as those employed in a DRAM is disclosed in Patent Document 1. ~ 5 etc.

  However, since this pseudo SRAM has the same memory cell as the DRAM, it is necessary to always perform a refresh operation in order to retain the data stored in the memory cell. For this reason, even though it operates in the same manner as an SRAM, there is no particular standby mode as used in conventional SRAMs. As long as the pseudo SRAM is operated with the same specifications as those of the conventional SRAM, it is desirable to prepare a low power consumption mode equivalent to the standby mode of the general-purpose SRAM even in terms of usability.

  From this point of view, the applicant has a standby mode equivalent to the standby mode of the general-purpose SRAM and a unique low power consumption mode that is not found in existing semiconductor memory devices, with respect to the semiconductor device using the pseudo SRAM. The invention of the semiconductor memory device is proposed in Japanese Patent Application No. 2000-363664. According to the present invention, a power supply mode equivalent to that of a normal DRAM and a standby mode for guaranteeing data retention of the memory cell by supplying power to a circuit required for refreshing the memory cell, and a refresh of the memory cell The deep standby mode is set in which the power supply is stopped even for the circuits necessary for this, and the data retention of the memory cells is not guaranteed.

  In the deep standby mode, data in the memory cell cannot be retained, but a refresh operation is not necessary, and current consumption can be reduced compared to the standby mode. This deep standby mode is based on the premise that the entire memory cell array can be written during the transition from the standby state to the active state, and is suitable for the case where a semiconductor memory device is used as a buffer. Mode.

FIG. 10 is a block diagram showing an example of a main configuration of a conventional pseudo SRAM. In FIG. 10, the voltage level control circuit 1 generates an internal voltage level control signal A for controlling the level of the boost voltage V _bt applied to the word line of the memory cell array 2 based on the reference voltages V _ref1 and V _ref2. Output to the oscillator 3. The ring oscillator 3 is activated and oscillates when the internal voltage level control signal A output from the voltage level control circuit 1 is “H” (high level), and outputs the oscillation output B to the booster circuit 4.

The booster circuit 4 includes a charge pump circuit that generates a boost voltage _Vbt as an internal voltage, and boosts the power supply voltage V _DD stepwise using the oscillation output B of the ring oscillator 3 to drive the word line. The boost voltage _Vbt to be generated is generated and output to the word decoder 5. The boost voltage V _bt is set to a voltage higher than the power supply voltage V _DD , for example, about V _DD + 1.5V or V _DD + 2V. The word decoder 5 supplies the boost voltage _Vbt to the word line selected by the output from the row decoder 6. The memory cell array 2 has a configuration similar to that of a DRAM memory cell array.

  The refresh timing generation circuit 7 generates a refresh signal for refreshing the memory cells in the memory cell array 2 and a refresh address for designating the address of the memory cell to be refreshed at regular time intervals. The refresh signal is output to the row enable generation circuit 8, and the refresh address is output to the row decoder 6. The row enable generation circuit 8 generates a row enable signal LT at a timing when the refresh timing generation circuit 7 generates a refresh signal.

  The row enable generation circuit 8 receives the write enable signal WE, the chip select signal CS, and the read / write address Add of the memory cell array 2, and outputs a row enable signal LT every time the address Add changes. The row enable signal LT is input to the voltage level control circuit 1 and the row decoder 6.

  FIG. 11 is a timing chart for explaining the operation in the standby mode in the circuit shown in FIG. Hereinafter, a boost voltage generating operation for refreshing a memory cell will be described with reference to FIGS.

When the pseudo SRAM device is set in the standby state, a refresh signal is output from the refresh timing generation circuit 7 to the row enable generation circuit 8 at a constant cycle (for example, 16 μsec). The row enable generation circuit 8 receives this refresh signal, generates a row enable signal LT, and outputs it to the voltage level control circuit 1. The voltage level control circuit 1 is activated by the low enable signal LT, and the voltage level control circuit 1 performs a comparison operation between the boost voltage _Vbt and the reference voltages V _ref1 and V _ref2 . When the boost voltage _Vbt is lower than the reference voltage _Vref1 , the internal voltage level control signal A becomes “H”, the ring oscillator 3 starts oscillating, and the oscillation output B is output to the booster circuit 4.

The booster circuit 4 boosts the boost voltage _Vbt using this oscillation output B. When the boost voltage V _bt rises and reaches the reference voltage V _ref2 , the voltage level control circuit 1 sets the internal voltage level control signal A to “L” (low level). As a result, the oscillation of the ring oscillator is stopped and the boosting operation of the booster circuit 4 is stopped. During this period, the memory cell refresh operation is executed in the memory cell array 2.

As described above, in the standby mode, a regular refresh timing is automatically generated in the device within a range in which data retention is guaranteed to power on the voltage level control circuit 1, and the word level is set to the reference voltage V _ref1 or higher. At the same time, the voltage level control circuit 1 is powered off during times other than the refresh timing to guarantee data retention and reduce current consumption.

Further, when this pseudo SRAM shifts from the standby state to the active state, the chip select signal CS rises, and then the address signal Add changes, the row enable generation circuit 8 detects this change and outputs the signal LT to output the voltage level. The control circuit 1 is activated. Therefore, in the active state, the boosting operation of boost voltage _Vbt is executed every time the memory is accessed.

  FIG. 12 is a block diagram showing a conventional timing cycle generation circuit in the refresh timing generation circuit 7. The OR gate 11 receives a mode signal MODE and a chip select signal CS for switching between the deep standby mode and the standby mode, and the OR gate 11. And a timer 12 that operates when H is "H" and outputs a timer signal TN having a fixed period necessary for refresh.

The timer signal TN sets the memory self-refresh cycle in the standby mode. FIG. 13 is a timing chart for explaining the operation when the timing cycle generation circuit shown in FIG. 12 is used for the pseudo SRAM shown in FIG.
JP-A 61-5495 Japanese Patent Laid-Open No. 62-188096 JP-A 63-206994 Japanese Patent Laid-Open No. 4-243087 JP-A-6-36557

As shown in FIG. 13, in the deep standby mode, the power supply to the pseudo SRAM of FIG. 10 is stopped, and the power supply is also stopped to the circuit necessary for self-refresh. _{Vbt is} also lowered to the ground potential. When switching from the deep standby mode to the standby mode, power supply to the pseudo SRAM of FIG. 10 is resumed, and power is also supplied to the circuit necessary for self-refresh. The refresh signal is output and the boost voltage _Vbt of the booster circuit 4 also rises.

Then, when the boost voltage V _bt rises to the reference voltage V _ref1 , the transition to the standby state is completed, and an active operation such as memory access becomes possible. However, as shown in FIG. 13, it takes time to increase the boost voltage _Vbt from the deep standby state where the boost voltage _Vbt is substantially reduced to the ground potential to the reference voltage _{Vref1 in the} standby state.

  For this reason, normally, as a standby time until the pseudo SRAM is started up to be in a memory accessible state, a time of about 200 μsec is set for the voltage startup, and the active operation cannot be executed during that time. There's a problem. In the future, it is conceivable that the memory capacity will be further increased. In that case, the load on the boost circuit is further increased, so that it takes more time to start up the standby state. It is expected that it will be difficult to start up to the standby state.

  In view of the above problems, the present invention provides a semiconductor memory device in which an operation mode in which power supply to a predetermined circuit is stopped and an operation mode in which power is supplied to the predetermined circuit are set. An object of the present invention is to provide means for shortening the return time from the operation mode in which the supply is stopped to the operation mode in which the power is supplied.

  In a semiconductor memory device having a plurality of operation modes, a semiconductor memory device of the present invention generates a first cycle generating means for generating a timing pulse having a predetermined cycle and a timing pulse having a cycle shorter than the predetermined cycle. Second period generating means, internal voltage generating means that operates when a timing pulse is input from the first or second period generating means, and generates a predetermined internal voltage, and an operation mode of the semiconductor memory device Timing pulse switching means for selecting a timing pulse from the second period generating means and outputting it to the internal voltage generating means when a certain mode is switched to another mode. It is characterized by.

  The one mode in the present invention is an operation mode for stopping power supply to a predetermined circuit, and the other mode is an operation mode for supplying power to the predetermined circuit, or the one mode The mode is an operation mode that does not guarantee the retention of data stored in the memory cell, and the other mode is an operation mode that guarantees the retention of data stored in the memory cell.

  More specifically, the semiconductor memory device of the present invention includes a standby mode for guaranteeing retention of data stored in the memory cell by supplying power to a circuit necessary for refreshing the memory cell, and the memory In a semiconductor memory device having a plurality of memory cells set to a deep standby mode in which power supply to a circuit necessary for cell refresh is also stopped and the retention of data stored in the memory cells is not guaranteed, An internal voltage generating means for generating a predetermined internal voltage by operating at a synchronized timing; and a timing period generating circuit for controlling an operating period of the internal voltage generating means, wherein the timing period generating circuit is configured to be in the standby mode. Sometimes the operating cycle of the internal voltage generating means is the same as the refresh cycle. A first timer that is set at the timing, and an operation cycle of the internal voltage generating means that operates at the time of switching from the deep standby mode to the standby mode to quickly return the internal voltage to a predetermined value. It has the 2nd timer set to a period shorter than a refresh period, It is characterized by the above-mentioned.

  According to another aspect of the present invention, there is provided a semiconductor memory device having a plurality of memory cells set in a standby mode for guaranteeing retention of data stored in the memory cells by supplying power to a circuit necessary for refreshing the memory cells. The semiconductor memory device includes: an internal voltage generating unit that generates a predetermined internal voltage by operating at a timing synchronized with the refresh cycle; and a timing cycle generating circuit that controls an operating cycle of the internal voltage generating unit. The timing cycle generating circuit includes a first timer that sets an operation cycle of the internal voltage generating means to a timing synchronized with the refresh cycle in the standby mode, and when the power source is switched from an off state to an on state. The operation cycle of the internal voltage generating means is changed to the refresh cycle. Wherein the remote has a second timer for returning in a short time to the predetermined internal voltage by setting a short period.

  As the internal voltage generating means in the present invention, a boost voltage generating circuit for generating a boost voltage applied to the word line of the memory cell, an internal voltage reducing circuit for stepping down an external power supply voltage and supplying it to an internal circuit such as a memory, or A substrate back bias generation circuit for supplying a back bias voltage lower than the ground level to the semiconductor substrate.

  According to the present invention, when the power is turned on or when switching from the deep standby mode to the standby mode, a timer cycle shorter than the timer cycle used for operating in the standby mode and supplying a periodic refresh voltage to the memory is used. Thus, the refreshable voltage can be restored at a high speed, so that the time for switching from the power-on or deep standby mode to the standby mode can be shortened.

  Also, a device having a standby mode that guarantees data retention of memory cells and a deep standby mode that does not guarantee data retention of memory cells, and a time for switching from the standby mode to the deep standby mode or from the power-on time is set in advance. In this case, even when the memory capacity of the device needs to be increased to expand the function, it is possible to cope with the start-up to the standby mode within the set time.

  FIG. 1 is a block diagram of a timing period generation circuit showing a first embodiment of the present invention.

  The timing cycle generation circuit of the present embodiment operates when the mode signal MODE for switching between the deep standby mode and the standby mode and the chip select signal CS are input, and operates when the OR gate 11 is “H”. The timer 12 outputs a timer signal TN having a period (16 μsec), the logic circuit 13 to which the mode signal MODE and the output of the one-shot pulse generation circuit 16 are input, and operates when the output G of the logic circuit 13 is “H”. The timer 14 that outputs the timer signal TR having the second period shorter than the first period, and the timer signal TR that is reset by the signal that the output G of the logic circuit 13 rises to “H” and output from the timer 14 When the count value reaches a preset value, it becomes “H” and the timer output is turned off. The counter 15 that outputs the replacement signal C, the multiplexer (MUX) 17 that receives the switching signal C from the counter 15 and selects either the timer 12 or the timer 14 and outputs the timer output TO, and the counter 15 And a one-shot pulse generation circuit 16 that outputs a one-shot pulse D to the logic circuit 13 in response to the switching signal C from

  FIG. 2 is a timing chart for explaining the operation when the timing cycle generation circuit of this embodiment is used for the pseudo SRAM shown in FIG. The operation of this embodiment will be described below with reference to FIGS.

In the deep standby mode, power is supplied only to the minimum necessary circuit, the power for operating the timing cycle generating circuit is also cut off, and the boost voltage _Vbt is lowered to the ground potential. When the standby mode is switched from this state, power is supplied to the timing cycle generation circuit, the mode signal MODE is “H”, the output G of the logic circuit 13 is “H”, and the timers 12 and 14 are started. Outputs TN and TR are output.

  On the other hand, the counter 15 has its output C at “L” when the mode signal MODE becomes “H”, and after the current count value is reset by a signal at which the output G of the logic circuit 13 switches to “H”. The timer signal TR output from the timer 14 is counted. When the count value of the counter 15 matches the preset value, the counter output C is switched to “H”. The output C of the counter 15 is input to the multiplexer 17 as a timer switching control signal.

The multiplexer 17 selects and outputs the timer output TR of the timer 14 when the output C of the counter 15 is “L”, and selects and outputs the timer output TN of the timer 12 when the output C of the counter 15 is “H”. To do. Therefore, immediately after switching from the deep standby mode to the standby mode, the timer output TR of the timer 14 that outputs a timing signal having a cycle shorter than the self-refresh cycle is selected and output, and the booster circuit 4 of FIG. As a result, the boosting operation is executed in a cycle shorter than the refresh cycle, so that the output voltage _Vbt of the booster circuit 4 is quickly restored to the voltage necessary for refreshing the memory cells.

  Thereafter, when the count value of the counter 15 becomes a preset value and the counter output C is switched to “H”, the multiplexer 17 selects and outputs the timer output TN of the timer 12. Therefore, in the subsequent standby mode, the output voltage of the booster circuit 4 is maintained at a predetermined voltage by the timer output TN having a fixed period (16 μsec) necessary for self-refresh, and the refresh operation of the memory cell is executed. Data retention is guaranteed.

  The output C of the counter 15 is also input to the one-shot pulse generation circuit 16, and the one-shot pulse generation circuit 16 outputs a one-shot pulse D when the output C of the counter 15 is switched to "H". The one-shot pulse D is input to the logic circuit 13 and the output G of the logic circuit 13 is switched to “L”. By switching the output G of the logic circuit 13 to “L”, supply of the operating current to the timer 14 is stopped, and unnecessary current consumption is suppressed.

  In the embodiment, the operation when switching from the deep standby mode to the standby mode has been described. For example, the timing period of the present invention is also generated when the boost voltage is raised when the power supply to the device including the pseudo SRAM is turned on. A circuit can be applied. In that case, a power-on signal is used instead of the mode switching signal MODE.

  As described above, in the present embodiment, when switching from the deep standby mode to the standby mode or when the power is turned on, the timer period is shorter than the timer period used for operating in the standby mode and supplying the periodic refresh voltage to the memory. Since the timer period is used to quickly return to a refreshable voltage, the time for switching from the deep standby mode or the power-on time to the standby mode can be shortened.

  Note that the timer 14 that operates when switching from the deep standby mode to the standby mode or when the power is turned on is omitted, and the timing period of the timer 12 that is used to operate in the standby mode and supply a periodic refresh voltage to the memory. It is not impossible to generate a memory refresh cycle and a timing signal having a cycle shorter than the memory refresh cycle by only the timer 12 by controlling the timer, but in general, the timer generator is composed of an analog circuit and the cycle changes. Therefore, it is more effective to use independent period generating means as in this embodiment in order to switch timing periods more quickly.

  Also, a device having a standby mode that guarantees data retention of memory cells and a deep standby mode that does not guarantee data retention of memory cells, and a time for switching from the standby mode to the deep standby mode or from the power-on time is set in advance. In this case, even when the memory capacity of the device needs to be increased to expand the function, it is possible to cope with the start-up to the standby mode within the set time.

  FIG. 3 is a block diagram of a timing period generation circuit showing a second embodiment of the present invention.

  The timing cycle generation circuit of the present embodiment operates when the mode signal MODE for switching between the deep standby mode and the standby mode and the chip select signal CS are input, and operates when the OR gate 11 is “H”. The timer 12 that outputs a timer signal TN having a period (16 μsec), the logic circuit 18 to which the mode signal MODE and the chip select signal CS are input, and the first circuit that operates when the output G of the logic circuit 18 is “H”. A timer 14 for outputting a timer signal TR having a second period shorter than the period of the timer, and a multiplexer for selecting one of the timer 12 and the timer 14 by the output G of the logic circuit 18 and outputting a timer output TO ( MUX) 17.

  FIG. 4 is a timing chart for explaining the operation when the timing cycle generation circuit of this embodiment is used for the pseudo SRAM shown in FIG. Hereinafter, the operation of the present embodiment will be described with reference to FIGS. 3 to 4 and FIG. 10.

In the deep standby mode, power is supplied only to the minimum necessary circuit, the power for operating the timing cycle generating circuit is also cut off, and the boost voltage _Vbt is lowered to the ground potential. When switching from this state to the standby mode, power is supplied to the timing cycle generation circuit, the mode signal MODE becomes “H”, the output of the OR circuit 11 and the output G of the logic circuit 13 become “H”, and the timer 12 and 14 is activated, and timer outputs TN and TR are output, respectively.

  The output G of the logic circuit 18 is input to the multiplexer 17 as a timer switching control signal. The multiplexer (MUX) 17 selects and outputs the timer output TR of the timer 14 when the output G of the logic circuit 18 is “H”. When the output G of the logic circuit 18 is “L”, the timer output TN of the timer 12 is selected and output.

Therefore, immediately after switching from the deep standby mode to the standby mode, the timer output TR of the timer 14 that outputs a timing signal having a cycle shorter than the self-refresh cycle is selected and output, and the booster circuit 4 in FIG. As a result, the boosting operation is executed in a cycle shorter than the refresh cycle, so that the output voltage _Vbt of the booster circuit 4 is quickly restored to a voltage necessary for refreshing the memory cells.

  Thereafter, when the chip select signal CS is switched to “H” to enter the active mode, the multiplexer 17 selects and outputs the timer output TN of the timer 12. Since the logic circuit 18 is configured to switch from “L” to “H” only when the mode signal MODE changes from “L” to “H”, the chip select signal CS becomes “L” thereafter. Even when the active mode is switched to the standby mode, the output G of the logic circuit 18 remains “L” and the timer 14 is not started.

  Accordingly, even if the mode is switched between the standby mode and the active mode thereafter, the timer output TN of the timer 12 is selected by the multiplexer 17 and the timer output TN of the constant period (16 μsec) necessary for the self-refreshing is used. Since the boosting operation is executed and the output voltage of the boosting circuit 4 is maintained at a predetermined voltage, the subsequent self-refresh operation in the standby mode is normally executed, and the data retention of the memory is guaranteed.

  In the embodiment, the operation when switching from the deep standby mode to the standby mode has been described. However, the timing cycle generation circuit of the present invention is also used when the boost voltage is raised when the power supply to the device including the pseudo SRAM is turned on. Can be applied. In that case, a power-on signal is used instead of the mode switching signal MODE.

  In the present embodiment, the timer 14 continues to operate until the first chip select signal CS is input after switching to the standby mode from the deep standby mode or the power-on time, and the operating current is supplied during that time. Although the current consumption is slightly increased as compared with the first embodiment, the time for switching from the deep standby mode or the power-on time to the standby mode can also be shortened in this embodiment.

  Also, a device having a standby mode that guarantees data retention of memory cells and a deep standby mode that does not guarantee data retention of memory cells, and a time for switching from the standby mode to the deep standby mode or from the power-on time is set in advance. In this case, even when the memory capacity of the device needs to be increased to expand the function, it is possible to cope with the start-up to the standby mode within the set time.

FIG. 5 is a circuit diagram showing an embodiment in which the timing period generating circuit of the present invention is applied to an internal step-down circuit for supplying a step-down voltage V _INT obtained by stepping down an external power supply voltage to an internal circuit such as a DRAM or a pseudo SRAM. is there.

The internal voltage down converter includes a differential amplifier 22 in which a reference voltage V _REF is input to an inverting input terminal and an internal voltage V _INT is input to a non-inverting input terminal, a source electrode connected to an external power supply voltage V _DD , and a gate electrode A P-channel MOS field effect transistor (hereinafter referred to as a PMOS transistor) 23 that receives the output of the dynamic amplifier 22 and outputs an internal voltage V _INT obtained by stepping down the external power supply voltage V _DD from the drain electrode. An internal circuit 21 such as a DRAM or a pseudo SRAM is connected to the output line of the internal voltage down converter, and the internal voltage V _{INT that} is stepped down is supplied to the internal circuit 21.

The differential amplifier 22 includes an N-channel MOS field effect transistor (hereinafter referred to as NMOS transistor) 25 whose gate electrode receives a reference voltage V _REF, an NMOS transistor 26 whose gate electrode receives an internal voltage V _INT, and an NMOS transistor Current source NMOS transistor 24 connected between the common source electrodes 25 and 26 and the ground potential, and a PMOS having a current mirror configuration connected between the external power supply voltage V _DD and the drain electrodes of the NMOS transistors 25 and 26 The drain electrode of the NMOS transistor 25 is connected to the gate electrode of the step-down PMOS transistor 23.

In the differential amplifier 22, the internal voltage V _INT on the output line is compared with the reference voltage V _REF . For example, when the internal power supply voltage V _INT drops below the reference voltage V _REF , the output voltage (NMOS) of the differential amplifier 22 is compared. As the drain voltage of the transistor 25 decreases, the PMOS transistor 23 transitions in the ON direction, increasing the current from the external power supply voltage V _DD and increasing the internal voltage V _INT .

On the other hand, when the internal voltage V _INT rises above the reference voltage V _REF , the output voltage of the differential amplifier 22 rises, so that the PMOS transistor 23 transitions in the off direction and the current from the external power supply voltage V _DD decreases. The internal voltage V _INT is decreased. By this negative feedback action, the internal voltage V _INT is controlled to be equal to the reference voltage V _REF .

The internal circuit 21 such as a DRAM or a pseudo SRAM consumes only a minute current such as a device leakage current when it is in an inactive state in which refresh or access is not performed. When the signal pulse is input and the internal circuit 21 is activated, the internal current of the internal circuit 21 increases and the internal voltage V _INT decreases. Along with this, the PMOS transistor 23 is turned on by the negative feedback action of the internal step-down circuit, the current from the external power supply voltage V _DD increases, and the internal voltage V _INT rises to the reference voltage V _REF .

  The timing cycle generation circuit 20 has the configuration shown in FIG. 1 or 3, and the timer output TO is input to the gate electrode of the current source NMOS transistor 24 in the differential amplifier 22. Therefore, the differential amplifier 22 is periodically controlled in operation and non-operation by the timer output TO output from the timing cycle generation circuit 20.

  FIG. 6 is a timing chart for explaining the operation when the timing period generation circuit of this embodiment is used for the internal voltage down converter shown in FIG. The operation of this embodiment will be described below with reference to FIGS. 6 shows the operation when the circuit of the second embodiment shown in FIG. 3 is used as the timing cycle generation circuit 20, the timing cycle generation circuit of the first embodiment shown in FIG. 1 is used. Even in this case, the same operation is possible. Further, the operation in the timing cycle generation circuit 20 is the same as the operation shown in FIG. 2 or FIG.

In the deep standby mode, power is supplied only to the minimum necessary circuits, and the power for operating the timing cycle generation circuit 20 and the differential amplifier 22 is also cut off. Therefore, the internal voltage V _INT is almost the ground potential, and no data is held in the memory cells in the internal circuit 21.

When the standby mode is switched from this state, power is supplied to the timing cycle generation circuit 20 and the differential amplifier 22, the mode signal MODE becomes "H", and the differential amplifier 22 immediately after switching from the deep standby mode to the standby mode. A timer output TR having a cycle shorter than the self-refresh cycle is selected and output to the gate electrode of the current source NMOS transistor 24. In the differential amplifier 22, the internal voltage V _INT and the reference voltage V _REF are compared each time the short cycle timer output TR is input, so that the internal voltage V _INT is quickly restored to the reference voltage V _REF. To do.

After that, when the chip select signal CS is switched to “H” and the active mode is set, the timing cycle generation circuit 20 outputs a timer output TN having a constant cycle necessary for self-refresh, and the differential amplifier 22 outputs this timer output. Each time TN is input, the internal voltage V _INT and the reference voltage V _REF are compared to maintain the internal voltage V _INT at the reference voltage V _REF . Even if the standby mode and the active mode are subsequently switched, the timing cycle generation circuit 20 outputs a timer output TN having a constant cycle necessary for self-refresh, and the internal voltage V _INT is maintained at the reference voltage V _REF. The

Further, when the internal circuit 21 is inactive in the standby mode, the current consumed by the internal circuit 21 is a minute value such as a leak current, and the decrease in the internal voltage V _INT is small. Therefore, by applying the timing period generation circuit 20 of the present invention to the voltage comparison operation in the differential amplifier 22, the differential amplifier 22 is in an inoperative state during the interval time of the pulse generated by the timer 12 synchronized with the refresh. To do. During this time, therefore, the connection with the external power source V _DD is cut and current consumption is reduced. In addition, when switching from the deep standby mode to the standby mode, it is possible to speed up the internal voltage rise and speed up the return to the standby mode.

  In the embodiment, the operation at the time of switching from the deep standby mode to the standby mode has been described. However, for example, when the internal voltage rises when the power supply to the device including the internal circuit 21 such as DRAM or pseudo SRAM is turned on. The timing cycle generation circuit of the present invention can be applied. In that case, a power-on signal is used instead of the mode switching signal MODE.

  FIG. 7 is a block diagram showing an embodiment in which the timing period generation circuit of the present invention is applied to a substrate back bias generation circuit that supplies a back bias voltage lower than the ground level to the semiconductor substrate.

The substrate back bias generation circuit 30 uses the external power supply voltage V _DD and the ground level (GND), operates by the timer output TO from the timing cycle generation circuit 20, and is lower than GND (for example, -1V). The back bias voltage V _BBG Is generated as an internal reference voltage. The output of the back bias generation circuit 30 is connected to a region to which the back bias voltage V _{BBG is} to be applied, for example, a semiconductor substrate, and the semiconductor substrate is set to a back bias voltage V _BBG lower than the ground level.

FIG. 8 is a circuit diagram showing an example of the back bias generation circuit 30, which is controlled by the transfer transistor 31 and the precharge transistors 32 and 33, which are PMOS transistors, the control logic block 36, and the control logic block 36, and its output. A first output drive circuit 34 that outputs the external power supply voltage V _DD and the ground level (GND) to the terminal P1, and a control logic block 36, and the output terminal P2 has a voltage V _BB lower than the external power supply voltage V _DD. Between the output terminal P1 of the first output drive circuit 34, the gate electrode of the transfer transistor 31 and the drain electrode of the precharge transistor 32, and the second output drive circuit 35 that outputs a ground level (GND). A first capacitor C1 connected between the second output driving circuit 35 and the second output driving circuit 35; Composed of connected second capacitor C2 Metropolitan between the connection point N2 of the drain electrode of the output terminal P2 and the source electrode and the precharge transistors 33 of the transfer transistor 31.

A capacitor C3 is a capacitor of the semiconductor substrate to which the back bias voltage V _BBG is supplied. Further, the control logic block 36 receives the timer output TO of the timing cycle generation circuit 20 and controls the precharge transistors 32 and 33 and the first and second output drive circuits 34 and 35.

  FIG. 9 is a time chart showing an outline of the operation of the back bias generation circuit 30 shown in FIG. Hereinafter, the operation will be described with reference to FIGS. 9 shows the operation when the circuit of the second embodiment shown in FIG. 3 is used as the timing cycle generation circuit 20, the timing cycle generation circuit of the first embodiment shown in FIG. 1 is used. Even in this case, the same operation is possible. Further, the operation in the timing cycle generation circuit 20 is the same as the operation shown in FIG. 2 or FIG.

In the deep standby mode, power is supplied only to the minimum necessary circuits, and the power for operating the timing cycle generation circuit 20 and the back bias generation circuit 30 is also cut off. Therefore, the back bias voltage V _BBG is almost the ground potential.

  When the standby mode is switched from this state, power is supplied to the timing cycle generation circuit 20 and the back bias generation circuit 30, the mode signal MODE becomes “H”, and the back bias is generated immediately after switching from the deep standby mode to the standby mode. A timer output TR having a cycle shorter than the self-refresh cycle is selected and output to the control logic block 36 of the circuit 30. In the control logic block 36, the following control is executed for the transfer transistor 31, the precharge transistors 32 and 33, and the first and second output drive circuits 34 and 35 every time the timer output TR having a short period is input. To do.

First, the output voltages of the output terminals P1 and P2 of the first and second output drive circuits 34 and 35 are set to V _DD and V _BB (V _DD > V _BB ), respectively, and the precharge transistors 32 and 33 are turned on. The first and second capacitors C1 and C2 are charged with voltages of V _DD and V _BB , respectively. Next, the output voltages of the output terminals P1 and P2 of the first and second output drive circuits 34 and 35 are set to the ground potential, and the precharge transistors 32 and 33 are turned off. Accordingly, the voltages V _DD and V _BB charged in the capacitors C 1 and C 2 respectively drive the voltage at the connection point N 1 to −V _DD and the voltage at the connection point N 2 to −V _BB .

On the other hand, since −V _DD <−V _BB at this time, the transfer transistor 31 is turned on, and the voltage of −V _BB charged in the capacitor C2 is transferred to the substrate capacitor C3 via the transfer transistor 31. As a result, the substrate capacitance C3 is charged to a negative potential, and the back bias voltage V _BBG is lowered to a negative potential. By repeating the above operation every time the timing pulse TR from the timing cycle generation circuit 20 is input, the back bias voltage V _BBG is returned to a constant voltage of approximately −V _BB at a high speed as shown in FIG.

After that, when the chip select signal CS is switched to “H” and the active mode is set, the timing cycle generation circuit 20 outputs a timer output TN having a fixed cycle necessary for self-refresh. The back bias generation circuit 30 uses this timer. Each time the output TN is input, the voltage of −V _BB charged in the capacitor C2 is transferred to the substrate capacitor C3 via the transfer transistor 31, and the back bias voltage V _BBG is maintained at a constant voltage of approximately −V _BB. .

Even if the standby mode and the active mode are subsequently switched, the timing cycle generation circuit 20 outputs the timer output TN having a constant cycle necessary for self-refreshing, and the back bias voltage V _BBG of the semiconductor substrate is substantially −V. It is maintained at a constant voltage of _BB .

According to the present embodiment, in the standby mode, the operation of charging the substrate capacitance C3 to −V _BB is executed every interval time of a pulse generated by a timer synchronized with the refresh in the timing cycle generation circuit 20. The current consumption can be reduced, and at the time of switching from the deep standby mode to the standby mode, it is possible to speed up the rise of the back bias voltage and to speed up the return to the standby mode.

  In the embodiment, the operation at the time of switching from the deep standby mode to the standby mode has been described. For example, the timing cycle generation circuit of the present invention can also be applied when the back bias voltage is raised when the power is turned on. it can. In that case, a power-on signal is used instead of the mode switching signal MODE.

  In each of the above embodiments, the case where the deep standby mode and the standby mode are set as the operation mode of the semiconductor memory device has been described. However, the deep standby mode that does not guarantee the data retention of the memory cell is further subdivided, for example, refresh The operation mode for stopping only the power supply to the refresh control circuit necessary for the operation and the operation mode for stopping all the power supply to the refresh control circuit, the boost voltage generation circuit, and the substrate voltage generation circuit are set, and these modes are switched. The present invention can also be applied when the internal voltage is raised.

1 is a block diagram of a timing period generation circuit showing a first embodiment of the present invention. 6 is a timing chart for explaining an operation when the timing cycle generation circuit of the first embodiment is used for a pseudo SRAM. FIG. 5 is a block diagram of a timing period generation circuit showing a second embodiment of the present invention. 6 is a timing chart for explaining an operation when the timing period generation circuit of the second embodiment is used for a pseudo SRAM. It is a circuit diagram which shows embodiment which applied the timing period generation circuit of this invention with respect to the internal voltage-down converter. 6 is a timing chart for explaining an operation when the timing period generation circuit of the present embodiment is used for an internal voltage down converter. It is a block diagram which shows embodiment which applied the timing period generation circuit of this invention to the board | substrate back bias generation circuit. It is a circuit diagram which shows an example of the back bias generation circuit to which the timing period generation circuit of this invention is applied. 3 is a time chart showing an outline of the operation of the back bias generation circuit to which the timing period generation circuit of the present invention is applied. It is a block diagram which shows an example of a principal part structure of the conventional pseudo SRAM. 3 is a timing chart for explaining the operation of a pseudo SRAM. It is a block diagram which shows the prior art example of a timing period generation circuit. 7 is a timing chart for explaining an operation when a conventional timing cycle generation circuit is used for a pseudo SRAM.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Voltage level control circuit 2 Memory cell array 3 Ring oscillator 4 Booster circuit 5 Word decoder 6 Row decoder 7 Refresh timing generation circuit 8 Row enable generation circuit 11 OR circuit 12, 14 Timer 13, 18 Logic circuit 15 Counter 16 One shot pulse generation circuit DESCRIPTION OF SYMBOLS 17 Multiplexer 20 Timing period generation circuit 21 Internal circuit 22 Differential amplifier 23,27,28,31-33 PMOS transistor 24-26 NMOS transistor 30 Back bias generation circuit 34,35 Output drive circuit 36 Control logic block

Claims (11)

Standby mode that guarantees retention of data stored in the memory cell by supplying power to the circuit necessary for refreshing the memory cell, and power supply to the circuit necessary for refreshing the memory cell are also stopped. In a semiconductor memory device having a plurality of memory cells set with a deep standby mode that does not guarantee the retention of data stored in the memory cells ,
An internal voltage generating means for generating a predetermined internal voltage by operating at a timing synchronized with the refresh cycle,
; And a timing cycle generating circuit for controlling the operation cycle of said internal voltage generating means,
The timing cycle generation circuit includes:
A first timer for setting an operation cycle of the internal voltage generating means at a timing synchronized with the refresh cycle in the standby mode;
Operates at the time of switching from the deep standby mode to the standby mode, and sets the operation cycle of the internal voltage generating means to a cycle shorter than the refresh cycle, thereby returning to the predetermined internal voltage in a short time the semiconductor memory device characterized by comprising a <br/> the second timer. The timing cycle generation circuit includes:
Logic circuit
Further comprising
It said first timer, the deep standby mode and the mode signal also switching between the standby mode in response to the switch Ppuserekuto signal, and outputs a first timer signal synchronized with the refresh cycle,
Said logic circuit, said mode signal and the one-shot pulse is input, outputs one of the levels of the signal when the mode signal is switched to the standby mode from the deep standby mode, the one-shot pulse is input and outputs the other level signal when the,
The second timer, the output level of the logic circuit operates when the one level and outputs a second timer signal having a period shorter than the refresh cycle,
The timing cycle generation circuit includes:
Counter the reset when the output level of the logic circuit is switched to the level of the one to count the second timer signal, the count value is output timer output switching signal when a preset value When,
Multiplexer for outputting as a signal for receiving said timer output switching signal from the counter to select any one of the timer signal of said first and second timer signal, for controlling the operation cycle of said internal voltage generating means When,
Receiving the timer output switching signal from the counter and outputting the one-shot pulse to the logic circuit;
The semiconductor memory device according to claim 1, further comprising: The timing cycle generation circuit includes:
Logic circuit
Further comprising
It said first timer, the deep standby mode and the mode signal also switching between the standby mode in response to the switch Ppuserekuto signal, and outputs a first timer signal synchronized with the refresh cycle,
The logic circuit receives the mode signal and the chip select signal, outputs a signal of one level when the mode signal switches from the deep standby mode to the standby mode, and receives the chip select signal. and it outputs the other level signal when,
The second timer, the output level of the logic circuit operates when the one level and outputs a second timer signal having a period shorter than the refresh cycle,
The timing cycle generation circuit includes:
A multiplexer for outputting as said select one of the timer signal of said first and second timer signal in accordance with the output level of the logic circuit, signals for controlling the operation cycle of said internal voltage generating means
The semiconductor memory device according to claim 1, further comprising: In a semiconductor memory device having a plurality of memory cells set in a standby mode for guaranteeing retention of data stored in the memory cells by supplying power to a circuit necessary for refreshing the memory cells ,
An internal voltage generating means for generating a predetermined internal voltage by operating at a timing synchronized with the refresh cycle,
; And a timing cycle generating circuit for controlling the operation cycle of said internal voltage generating means,
The timing cycle generation circuit includes:
A first timer for setting an operation cycle of the internal voltage generating means at a timing synchronized with the refresh cycle in the standby mode;
To operate when the power source is switched from the off state to the on state, and to set the operation cycle of the internal voltage generating means to a cycle shorter than the refresh cycle, thereby returning to the predetermined internal voltage in a short time the semiconductor memory device characterized by comprising a second timer with <br/>. The timing cycle generation circuit includes:
Logic circuit
Further comprising
Said first timer, power-on signal or in response to Chi Ppuserekuto signal, and outputs a first timer signal synchronized with the refresh cycle,
The logic circuit, said power-on signal and the one-shot pulse is input,
The second timer, the output level of the logic circuit operates when the one level and outputs a second timer signal having a period shorter than the refresh cycle,
The timing cycle generation circuit includes:
Counter the reset when the output level of the logic circuit is switched to the level of the one to count the second timer signal, the count value is output timer output switching signal when a preset value When,
Multiplexer for outputting as a signal for receiving said timer output switching signal from the counter to select any one of the timer signal of said first and second timer signal, for controlling the operation cycle of said internal voltage generating means When,
Receiving the timer output switching signal from the counter and outputting the one-shot pulse to the logic circuit;
The semiconductor memory device according to claim 4, further comprising: The timing cycle generation circuit includes:
Logic circuit
Further comprising
Said first timer, power-on signal or in response to Chi Ppuserekuto signal, and outputs a first timer signal synchronized with the refresh cycle,
The logic circuit outputs one of the levels of the signal when the power-on signal is input, and outputs the other level of the signal when the chip select signal is input,
The second timer, the output level of the logic circuit operates when the one level and outputs a second timer signal having a period shorter than the refresh cycle,
The timing cycle generation circuit includes:
A multiplexer for outputting as said select one of the timer signal of said first and second timer signal in accordance with the output level of the logic circuit, signals for controlling the operation cycle of said internal voltage generating means
The semiconductor memory device according to claim 4, further comprising:   7. The semiconductor memory device according to claim 1, wherein the internal voltage generation means is a boost voltage generation circuit that generates a boost voltage to be applied to a word line of the memory cell.   The semiconductor memory device according to claim 1, wherein the internal voltage generation unit is an internal voltage down converter that steps down an external power supply voltage and supplies the voltage to an internal circuit.   7. The semiconductor memory device according to claim 1, wherein the internal voltage generation means is a substrate back bias generation circuit that supplies a back bias voltage lower than a ground level to the semiconductor substrate. .   The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a pseudo SRAM device.   A portable electronic device comprising the semiconductor memory device according to claim 1.

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