JP4840095B2 - Manufacturing method of semiconductor laminated structure - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor multilayer structure such as a semiconductor laser element, and more particularly to a method for manufacturing a semiconductor multilayer structure capable of realizing a steep interface.

  The semiconductor laser element has a semiconductor laminated structure made of a compound. For example, a semiconductor multilayer structure made of a III-V group compound is composed of several types of semiconductor layers in which a group III In, Ga, Al or the like and a group V P, As or the like are combined.

As a method for producing such a semiconductor laminated structure, there is a metalorganic chemical vapor deposition (hereinafter referred to as MOCVD) method excellent in mass productivity (for example, see Patent Document 1). In the MOCVD method, an organic metal such as TMIn (trimethylindium) or TMGa (trimethylgallium) or a hydride such as PH ₃ (phosphine) or AsH ₃ (arsine) is used as a raw material. Then, these raw materials are converted into gas and supplied to the reaction furnace, and the semiconductor thin film grows on the substrate through a thermal decomposition reaction. The composition and growth rate of the semiconductor to be grown are determined by the raw material supply amount, and are controlled by opening and closing the valve of the raw material gas introduced into the reactor.

JP-A-62-183110

One of the challenges in creating a semiconductor stacked structure is the realization of a steep interface. For example, a III-V compound semiconductor has a large ratio (V / III ratio) between a Group V material such as PH ₃ and AsH ₃ and a Group III material (V / III ratio), and it is necessary to supply a large amount of source gas into the reactor. For this reason, during the growth of the semiconductor multilayer structure, the source gas cannot sufficiently follow the valve opening and closing and remains in the reaction furnace. If these residual elements are taken into the interface and the next different semiconductor layer, a steep hetero interface cannot be realized. Thus, conventionally, the growth was interrupted when the raw material gas was switched, and the intake of residual elements was suppressed by optimizing the purge amount and time, but it was difficult to completely prevent it. In addition, when the growth is interrupted, the outermost surface atoms are replaced with the atoms in the purge atmosphere, and there are problems of incorporation and accumulation of impurity elements in the purge atmosphere on the outermost surface (interface).

In addition to the group V elements, the residual elements at the time of forming these semiconductor laminated structures are also problematic in group II, group IV, and group VI elements that are doped as p-type and n-type impurities. In particular, Cp ₂ Mg (cyclopentadienylmagnesium), which is a raw material when doping Mg, is likely to remain in the reaction furnace. For this reason, for example, in a structure having an undoped layer on the doping layer, it is difficult to realize a steep doping profile because residual elements are taken into the undoped layer.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a method for manufacturing a semiconductor multilayer structure capable of realizing a steep interface.

A method for manufacturing a semiconductor multilayer structure according to the present invention is a method for manufacturing a semiconductor multilayer structure having an interface between a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer is formed by introducing a source gas into a reaction furnace. A step of forming a dummy layer composed of all or part of the elements constituting the second semiconductor layer by introducing a source gas into the reaction furnace continuously after forming the first semiconductor layer; Introducing the etching gas into the reaction furnace to remove the dummy layer; and removing the dummy layer and then introducing the source gas into the reaction furnace to form the second semiconductor layer on the first semiconductor layer; have a, the first semiconductor layer and the second semiconductor layer is a compound semiconductor layer composed of different elements. Other features of the present invention will become apparent below.

  According to the present invention, it is possible to obtain a method for manufacturing a semiconductor multilayer structure capable of realizing a steep interface.

Embodiment 1 FIG.
A method for manufacturing a semiconductor multilayer structure according to the first embodiment of the present invention will be described with reference to the drawings. In the present embodiment, a semiconductor multilayer structure having a heterointerface between an InGaAs layer (first semiconductor layer) and an InP layer (second semiconductor layer) which are compound semiconductor layers made of different elements is manufactured.

First, as shown in FIG. 1, a source gas (TMIn, TMGa, AsH ₃ ) is introduced into a reaction furnace 10 to form an InGaAs layer 11.

Next, as shown in FIG. 2, after the InGaAs layer 11 is formed, a source gas (TMIn, PH ₃ ) is introduced into the reaction furnace 10 to form a dummy layer 12 made of InP. At this time, a region close to the InP / InGaAs interface in the dummy layer 12 is captured by As as a result of AsH ₃ remaining in the reaction furnace 10, and the metamorphic layer 12 a (for example, In _1-x Ga _x As _y P _{1 A −y} layer (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) is formed.

Next, as shown in FIG. 3, HCl gas is introduced as an etching gas into the reaction furnace 10, and the dummy layer 12 including the metamorphic layer 12a is removed by etching. At this time, the etching is performed in a group V semiconductor material atmosphere for growing an InP layer later, that is, a PH ₃ atmosphere. The etching rate is controlled by the temperature in the reaction furnace 10 or the flow rate of HCl gas. In the etching, not only the dummy layer 12 but also a part of the InGaAs layer 11 may be removed. In this case, when the InGaAs layer 11 is grown, the layer thickness is set in consideration of the removed portion.

Next, as shown in FIG. 4, a source gas (TMIn, PH ₃ ) is introduced into the reaction furnace 10 to form an InP layer 13 on the InGaAs layer 11. Through the above steps, an InP / InGaAs heterostructure is manufactured.

  FIG. 5 is a diagram comparing the SIMS analysis As concentration profile of the InP / InGaAs heterointerface manufactured by the manufacturing method of the present invention with that of the conventional manufacturing method. As can be seen from this result, according to the present invention, it is possible to obtain a steep density profile as compared with the prior art.

  Therefore, according to the present embodiment, it is possible to realize a steep interface when manufacturing a semiconductor stacked structure having a heterointerface of compound semiconductor layers made of different elements.

  This embodiment can be applied not only to the InP / InGaAs heterostructure, but also to the manufacture of all semiconductor heterostructures such as AlInAs / InP, AlGaInP / GaAs, and InP / AlInGaAs. The present embodiment can be applied not only to the production of III-V compound semiconductors but also to the production of I-VII and II-VI compound semiconductor stacks. The present embodiment can be applied not only to the semiconductor laser but also to the manufacture of any semiconductor stacked structure.

  Further, the dummy layer is not necessarily a layer having the same constituent elements and composition ratio as the second semiconductor layer, and may be a layer made of all or part of the elements constituting the second semiconductor layer. For example, when AlGaInP is grown as the second semiconductor layer, GaInP may be grown as the dummy layer.

Embodiment 2. FIG.
A method for manufacturing a semiconductor multilayer structure according to Embodiment 2 of the present invention will be described with reference to the drawings. In the present embodiment, a semiconductor multilayer structure having a heterointerface between an Mg-doped InP layer (first semiconductor layer) as an impurity and an undoped InGaAs layer (second semiconductor layer) is manufactured.

First, as shown in FIG. 6, source gas (TMIn, PH ₃ ) and Mg source Cp ₂ Mg are introduced into a reaction furnace 10 to form an Mg-doped InP layer 21.

Next, as shown in FIG. 7, after the Mg-doped InP layer 21 is formed, a source gas (TMIn, TMGa, AsH ₃ ) is introduced into the reaction furnace 10 to form a dummy layer 22 made of undoped InGaAsP. Form. At this time, a region 22 a in which Mg is taken in due to the influence of Cp ₂ Mg remaining in the reaction furnace 10 is formed in a region near the undoped InGaAs / Mg-doped InP interface in the dummy layer 22.

Next, as shown in FIG. 8, the crystal growth is interrupted, HCl gas is introduced into the reaction furnace 10 as an etching gas, and the dummy layer 22 including the region 22a into which Mg has been taken in is removed by etching. At this time, the etching is performed in a group V semiconductor material atmosphere for growing an InP layer later, that is, an AsH ₃ atmosphere. The etching rate is controlled by the temperature in the reaction furnace 10 or the flow rate of HCl gas. In the etching, not only the dummy layer 22 but also a part of the InP layer 21 may be removed. In this case, when the InP layer 21 is grown, the layer thickness is set in consideration of the removed amount.

Next, as shown in FIG. 9, a source gas (TMIn, TMGa, AsH ₃ ) is introduced into the reaction furnace 10 to form an undoped InGaAs layer 23 on the Mg-doped InP layer 21. Through the above steps, an undoped InGaAs / Mg-doped InP heterostructure is manufactured.

  Therefore, according to the present embodiment, a steep interface can be realized when manufacturing a semiconductor stacked structure having a heterointerface between a first semiconductor layer doped with impurities and an undoped second semiconductor layer.

  This embodiment can be applied not only to the InGaAs / InP heterostructure, but also to the manufacture of all semiconductor heterostructures such as AlInAs / InP, AlGaInP / GaAs, InP / AlInGaAs, and InGaAsP / InP. In addition, this embodiment can be applied not only to the heterostructure, but also to the manufacture of any compound semiconductor homostructure such as undoped InP / Mg-doped InP. In the present embodiment, not only Mg doping but also all elements such as Zn (zinc), Be (beryllium), S (sulfur), Si (silicon), Fe (iron), and C (carbon) are doped. The present invention can be applied to manufacturing a structure in which an undoped semiconductor layer is grown on a semiconductor layer. The present embodiment can be applied to the production of heterostructures / homostructures in which layers doped with different kinds of elements such as A doping layer / B doping layer are stacked. The present embodiment can be applied not only to the production of III-V compound semiconductors but also to the production of I-VII and II-VI compound semiconductor stacks. The present embodiment can be applied not only to the semiconductor laser but also to the manufacture of any semiconductor stacked structure.

  Further, the dummy layer is not necessarily a layer having the same constituent elements and composition ratio as the second semiconductor layer, and may be a layer made of all or part of the elements constituting the second semiconductor layer. For example, when AlGaInP is grown as the second semiconductor layer, GaInP may be grown as the dummy layer.

Embodiment 3 FIG.
A method for manufacturing a semiconductor multilayer structure according to Embodiment 3 of the present invention will be described with reference to the drawings. In the present embodiment, a semiconductor stacked structure having a heterointerface between an AlInAs layer (first semiconductor layer) and an InP layer (second semiconductor layer) having different growth temperatures is manufactured.

First, as shown in FIG. 10, a source gas (TMAl, TMIn, AsH ₃ ) is introduced into the reaction furnace 10 to form an AlInAs layer 31 at a growth temperature T _g1 (first temperature).

Next, as shown in FIG. 11, after the AlInAs layer 31 is formed, the source gas (TMIn, PH ₃ ) is introduced into the reaction furnace 10 to form the dummy layer 32 made of InP at the growth temperature T _g1 . Form. At this time, a region near the InP / AlInAs interface in the dummy layer 32 is captured by As as a result of AsH ₃ remaining in the reaction furnace 10, and the metamorphic layer 32 a (for example, Al _1-x In _x As _y P _{1). -Y} layer (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) is formed, and the crystallinity of the dummy layer 32 is not good because the growth temperature _Tg1 is not appropriate as the growth temperature of InP.

Next, as shown in FIG. 12, the AlInAs layer 31 and the dummy layer 32 are lowered to the growth temperature T _g2 (second temperature) of the InP layer 33 to be formed later. While the crystal growth is interrupted due to the temperature lowering, a group V semiconductor material atmosphere for growing the InP layer 33 later, that is, a PH ₃ atmosphere is used. Then, HCl gas is introduced as an etching gas into the reaction furnace 10, and the dummy layer 32 including the metamorphic layer 32a is removed by etching. At this time, the etching is performed in a group V semiconductor material atmosphere for growing the InP layer 33 later, that is, a PH ₃ atmosphere. The etching rate is controlled by the temperature in the reaction furnace 10 or the flow rate of HCl gas. In the etching, not only the dummy layer 32 but also a part of the AlInAs layer 31 may be removed. In this case, when the AlInAs layer 31 is grown, the layer thickness is set in consideration of the removed amount.

Next, as shown in FIG. 13, a source gas (TMIn, PH ₃ ) is introduced into the reaction furnace 10 to form an InP layer 33 on the AlInAs layer 31 at a growth temperature _Tg2 . Here, FIG. 14 shows the growth temperature, the growth of the InP layer / AlInAs layer, and the etching removal in this embodiment as the growth time elapses. Through the above steps, an InP / AlInAs heterostructure is manufactured.

  Therefore, according to the present embodiment, when a semiconductor multilayer structure having a heterointerface between the first semiconductor layer and the second semiconductor layer having different growth temperatures is affected by the atmosphere at the time of growth interruption and residual impurities. A steep interface without an interface can be realized.

  This embodiment can be applied not only to the manufacture of InP / AlInAs heterostructures, but also to the manufacture of any semiconductor heterostructure such as AlGaInAs / InP and AlGaInP / GaAs. In addition, this embodiment can be applied not only to the production of semiconductor heterostructures but also to the production of semiconductor homostructures. This embodiment can be applied not only to the production of III-V compound semiconductors but also to the production of I-VII and II-VI compound semiconductor stacks. Further, this embodiment can be applied not only to lowering the temperature, but also to manufacturing a semiconductor multilayer structure in which growth interruption is performed during crystal growth, such as temperature increase or gas replacement. The present embodiment can be applied not only to the semiconductor laser but also to the manufacture of any semiconductor stacked structure.

  Further, the dummy layer is not necessarily a layer having the same constituent elements and composition ratio as the second semiconductor layer, and may be a layer made of all or part of the elements constituting the second semiconductor layer. For example, when AlGaInP is grown as the second semiconductor layer, GaInP may be grown as the dummy layer.

Embodiment 4 FIG.
A method for manufacturing a semiconductor multilayer structure according to Embodiment 4 of the present invention will be described with reference to the drawings. In the present embodiment, a semiconductor stacked structure having a heterointerface between an InP layer (first semiconductor layer) and an AlInAs layer (second semiconductor layer) having different growth temperatures is manufactured.

First, as shown in FIG. 15, a source gas (TMIn, PH ₃ ) is introduced into the reaction furnace 10 to form an InP layer 41 at a growth temperature T _g1 (first temperature).

Next, as shown in FIG. 16, the InP layer 41 is heated to the growth temperature T _g2 (second temperature) of the AlInAs layer 42 to be formed later. While the crystal growth for temperature rise is interrupted, the group V semiconductor material atmosphere for growing the AlInAs layer 42 later, that is, the AsH ₃ atmosphere, the PH ₃ atmosphere during the growth of the InP layer 41, or a mixed atmosphere of both is used. . At this time, the outermost surface 41a of the InP layer 41 is exposed to an environment inappropriate for InP growth. For this reason, separation of P on the outermost surface, substitution of P with an element (for example, As) in the atmosphere at the time of growth interruption, accumulation of residual impurities in the reaction furnace 10 on the surface, and the like occur. The crystallinity of the surface 41a deteriorates.

Next, as shown in FIG. 17, the surface of the InP layer 41 including the outermost surface 41a is etched by introducing HCl gas as an etching gas into the reaction furnace 10 while the InP layer 41 is set at the temperature _Tg2. Remove. At this time, the etching is performed in a group V semiconductor material atmosphere for growing the AlInAs layer 42 later, that is, an AsH ₃ atmosphere. The etching rate is controlled by the temperature in the reaction furnace 10 or the flow rate of HCl gas. Then, when the InP layer 41 is grown, the layer thickness is set in consideration of the removed portion.

Next, as shown in FIG. 18, to form the raw material gas into the reaction furnace _{10 (TMAl, TMIn, AsH 3} ) an AlInAs layer 42 on the InP layer 41 is introduced at the growth temperature _{T g2.} Here, FIG. 19 shows the growth temperature, the growth of the InP layer / AlInAs layer, and the etching removal in this embodiment as the growth time elapses. Through the above steps, an AlInAs / InP heterostructure is manufactured.

  Therefore, according to the present embodiment, when a semiconductor multilayer structure having a heterointerface between the first semiconductor layer and the second semiconductor layer having different growth temperatures is affected by the atmosphere at the time of growth interruption and residual impurities. A steep interface without an interface can be realized.

  This embodiment can be applied not only to the AlInAs / InP heterostructure, but also to the production of any semiconductor heterostructure such as AlGaInAs / InP and AlGaInP / GaAs. In addition, this embodiment can be applied not only to the production of semiconductor heterostructures but also to the production of semiconductor homostructures. This embodiment can be applied not only to the production of III-V compound semiconductors but also to the production of I-VII and II-VI compound semiconductor stacks. In addition, the present embodiment can be applied to the manufacture of a semiconductor stacked structure in which growth is interrupted during crystal growth, such as temperature decrease and gas replacement, as well as temperature increase. The present embodiment can be applied not only to the semiconductor laser but also to the manufacture of any semiconductor stacked structure.

It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 1 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 1 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 1 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 1 of this invention. It is the figure which compared the SIMS analysis As concentration profile of the InP / InGaAs hetero interface manufactured with the manufacturing method of this invention with the thing by the conventional manufacturing method. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 2 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 2 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 2 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 2 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 3 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 3 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 3 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 3 of this invention. It is the figure which represented the growth temperature in Embodiment 3 of this invention, the growth of InP layer and AlInAs layer, and etching removal according to progress of growth time. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 4 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 4 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 4 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor laminated structure which concerns on Embodiment 4 of this invention. It is a figure showing growth temperature, growth of an InP layer / AlInAs layer, and etching removal in Embodiment 4 of the present invention according to progress of growth time.

Explanation of symbols

10 Reactor 11 InGaAs layer (first semiconductor layer)
12, 22, 32 Dummy layer 13 InP layer (second semiconductor layer)
21 Mg-doped InP layer (first semiconductor layer)
23 Undoped InGaAs layer (second semiconductor layer)
31 AlInAs layer (first semiconductor layer)
33 InP layer (second semiconductor layer)
41 InP layer (first semiconductor layer)
42 AlInAs layer (second semiconductor layer)

Claims (4)

A method for manufacturing a semiconductor multilayer structure having an interface between a first semiconductor layer and a second semiconductor layer,
Introducing a source gas into the reaction furnace to form a first semiconductor layer;
Continuously forming the first semiconductor layer and introducing a source gas into the reaction furnace to form a dummy layer made of all or part of the elements constituting the second semiconductor layer;
Introducing an etching gas into the reactor to remove the dummy layer;
After removing the dummy layer, by introducing a raw material gas into the reaction furnace possess and forming the second semiconductor layer on the first semiconductor layer,
The method for producing a semiconductor multilayer structure, wherein the first semiconductor layer and the second semiconductor layer are compound semiconductor layers made of different elements . 2. The method of manufacturing a semiconductor multilayer structure according to claim 1 , wherein the first semiconductor layer is a semiconductor layer doped with impurities, and the second semiconductor layer is an undoped semiconductor layer. Forming the first semiconductor layer and the dummy layer at a first temperature;
Changing the temperature of the first semiconductor layer and the dummy layer to a second temperature when removing the dummy layer;
The method for manufacturing a semiconductor multilayer structure according to claim 1, wherein the second semiconductor layer is formed at the second temperature. The method for manufacturing a semiconductor multilayer structure according to claim 1 , wherein HCl gas is used as the etching gas.

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