JP4836659B2 - DC / DC converter - Google Patents

Description

  The present invention relates to a DC / DC converter for a vehicle having a single-phase full-bridge inverter.

  In general, a single-phase full-bridge inverter that simultaneously outputs ON and OFF switching elements at diagonal positions and outputs positive and negative rectangular wave voltages, and rectifies and outputs the AC output of this full-bridge inverter to a predetermined voltage DC In a DC / DC converter for a vehicle, when the switching element becomes inoperative due to an open phase, the inverter output current of the full bridge inverter flows only positively or negatively. Therefore, conventionally, the current state is detected to detect the phase loss.

  However, a DC / DC converter for a vehicle has a very high switching frequency on the order of kHz, and it is difficult to correctly detect a high-frequency current waveform by software with slow sampling, for example.

  The present invention has been made in view of the above-described problems of the prior art, and in a DC / DC converter having a full-bridge inverter that operates at a high frequency, there is no false detection of phase loss, and phase loss is eliminated. It is an object to provide a DC / DC converter that can be easily detected.

  One feature of the present invention is that a DC / DC converter having a single-phase full-bridge inverter that simultaneously outputs ON / OFF switching elements at diagonal positions and outputs positive and negative rectangular wave voltages, the full-bridge inverter includes: An inverter current detection circuit for detecting a current flowing through the output; a first current comparison circuit for comparing a detection current value of the inverter current detection circuit with a preset inverter current comparison value; and a detection current of the inverter current detection circuit A second current comparison circuit for comparing a positive / negative inverted value of the value with the inverter current comparison value; and a first OFF delay circuit having a predetermined delay time connected to the output of the first current comparison circuit; A second OFF delay circuit having a predetermined delay time connected to the output of the second current comparison circuit; In that a phase loss detection circuit for detecting loss of phase by one of the outputs of the second OFF delay circuit is OFF continuously.

  Another feature of the present invention is that a DC / DC converter having a single-phase full-bridge inverter that simultaneously outputs ON / OFF switching elements at diagonal positions and outputs positive and negative rectangular wave voltages, the full-bridge inverter includes: An inverter current detection circuit for detecting a current flowing through the output; a first current comparison circuit for comparing a detection current value of the inverter current detection circuit with a preset inverter current comparison value; and a detection current of the inverter current detection circuit A first current comparison circuit that compares a positive / negative inverted value of the value with the inverter current comparison value; and a first current comparison circuit that is connected to an output of the first current comparison circuit and has an OFF delay characteristic longer than a sampling time. An OFF delay circuit longer than the sampling time connected to the output of the OFF delay circuit and the second current comparison circuit. A second OFF delay circuit having characteristics, and a phase loss detection circuit that detects a phase loss by continuously turning off the output of one of the first and second OFF delay circuits. is there.

  According to still another aspect of the present invention, in the DC / DC converter having a single-phase full-bridge inverter that outputs switching between positive and negative rectangular wave voltages, the switching elements in the diagonal positions simultaneously turn on and off, and the full-bridge inverter. An inverter current detection circuit for detecting a current flowing through the output of the inverter, a first current comparison circuit for comparing a detection current value of the inverter current detection circuit with a comparison value, and a positive / negative inversion of a detection current value of the inverter current detection circuit A second current comparison circuit for comparing a value with the comparison value, a first OFF delay circuit connected to an output of the first current comparison circuit and having an OFF delay characteristic longer than a switching period; A second OFF delay circuit having an OFF delay characteristic longer than the switching cycle, connected to the output of the current comparison circuit of 2 Is to have a phase loss detection circuit for detecting loss of phase by one of the outputs of said first and second OFF delay circuit is OFF continuously.

  According to the DC / DC converter of the present invention, when the full bridge inverter operates at a high frequency, there is no erroneous detection of the phase loss, and the phase loss can be easily detected.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  (First Embodiment) FIG. 1 shows a circuit configuration of a DC / DC converter according to a first embodiment of the present invention. The DC / DC converter has, as a main circuit configuration, a single-phase full-bridge inverter 1 in which switching elements at diagonal positions simultaneously turn on and off to output positive and negative rectangular wave voltages, a transformer 2, and the transformer 2 The rectifier circuit 3 rectifies the secondary current.

  In the DC / DC converter of the present embodiment, the inverter current detector 11 that detects the output current Iinv of the full-bridge inverter 1 every predetermined sampling period, and the inverter current comparison value I1 for comparison with the inverter detection current value Iinv A comparison value setting unit 12 for setting is provided. Further, the DC / DC converter compares the inverter detection current value Iinv of the inverter current detector 11 with the inverter current comparison value I1 by the comparison value setter 12 for detecting the phase loss, and the inverter detection current value Iinv> inverter current. A comparison circuit 14 that outputs a signal when the comparison value I1 is established, an inverter circuit 13 that inverts the polarity of the inverter detection current value Iinv of the inverter current detector 4, and an inverter detection current value that is inverted by the inverter circuit 13- Comparison circuit 14A that compares Iinv with inverter current predetermined value I1 and outputs a signal when inverting inverter detection current value -Iinv> inverter current comparison value I1 is established, and further outputted from comparison circuit 14 and comparison circuit 14A Delay the signal by a predetermined time set in advance by the inverter 1 It has a FF delay circuit 15,15A.

  In the DC / DC converter, the exclusive OR circuit 16 that calculates the exclusive OR of the outputs of the OFF delay circuits 15 and 15A, and the exclusive OR circuit 16 continues to be high (H) for a predetermined time or more. The ON delay circuit 17 that outputs high (H) when outputting, and low (L) when not, and the low (L) output of the ON delay circuit 17 determines that the phase is out of phase, and outputs the gate OFF signal of the inverter 1. A gate OFF output circuit 20 for outputting is provided.

  Next, the phase loss detection operation by the DC / DC converter having the above configuration will be described with reference to timing charts of FIGS.

  FIG. 2 is a diagram showing a relationship between the inverter detection current value Iinv and the inverter current predetermined value I1 in the normal state, the output −Iinv of the inverting circuit 13, the outputs of the comparison circuits 14 and 14A, and the outputs of the OFF delay circuits 15 and 15A. . The comparison circuit 14 compares the inverter detection current value Iinv with the inverter current comparison value I1, and outputs a high (H) signal when the inverter detection current value Iinv> the inverter current comparison value I1 is satisfied. The comparison circuit 14A compares the inversion detection current value −Iinv by the inversion circuit 13 with the inverter current predetermined value I1, and outputs a high (H) signal when the inversion inverter detection current value −Iinv> the inverter current comparison value I1. To do. Each of the OFF delay circuits 15 and 15A delays the high (H) signal output from the comparison circuit 14 and the comparison circuit 14A, and continues to maintain the high (H) signal for a predetermined time.

  As a result, the exclusive OR circuit 16 calculates the exclusive OR of the outputs of the OFF delay circuits 15 and 15A, and since both the high (H) signals are input, the high (H) signal is continuously output. Since the ON delay circuit 17 continues to receive a high (H) signal, there is no phase loss and the gate OFF signal is not output and the operation of the inverter 1 is continued.

  FIG. 3 is a diagram showing the relationship between the inverter detection current value Iinv and the inverter current predetermined value I1 at the time of phase loss, the output −Iinv of the inverting circuit 13, the outputs of the comparison circuits 14 and 14A, and the outputs of the OFF delay circuits 15 and 15A. is there. The comparison circuit 14 changes its output when the inverter detection current value Iinv is equal to or greater than the inverter current comparison value I1. Conversely, in the negative current detection system of the inverter 1, the comparison circuit 14A changes its output when the inversion current value -Iinv is equal to or less than the inverter current comparison value I1, but when an open phase occurs, 3, for example, the inversion detection current value -Iinv by the inversion circuit 13 does not become larger than the inverter current predetermined value I1, and as a result, the output of the comparison circuit 14A does not become high (H). , Continue to be low (L). For this reason, one OFF delay circuit 15 continues to output a high (H) signal, but the output of the other OFF delay circuit 15A remains low (L).

  As a result, since the outputs of the OFF delay circuits 15 and 15A are in different states, the exclusive OR circuit 16 continuously changes the output for a certain period of time, the output of the ON delay circuit 17 also changes, and the gate OFF output. As a result, the circuit 20 regards the full-bridge inverter 1 as a phase loss detection and stops the full-bridge inverter 1 by turning off the gate.

  As described above, according to the DC / DC converter of the present embodiment, the phase loss can be detected not by the high-frequency current waveform but by the output of the OFF delay circuits 14 and 14A that are direct current values. Phase loss can be detected.

  (Second Embodiment) Next, a second embodiment of the present invention will be described. The configuration of the DC / DC converter of the present embodiment is the same as that of the DC / DC converter of FIG. 1 used in the first embodiment. In the DC / DC converter according to the present embodiment, the inverter current detector 11 uses the delay time of the OFF delay circuits 15 and 15A shown in FIG. It is characterized in that the time is longer than the sampling time for current detection of the inverter 1.

  According to the DC / DC converter of the present embodiment, the phase loss of the switching element of the full bridge inverter 1 can be detected not by the high-frequency current waveform but by the outputs of the OFF delay circuits 15 and 15A which are direct current values. Therefore, phase loss can be detected easily.

  (Third Embodiment) Next, a DC / DC converter according to a third embodiment of the present invention will be described. The configuration of the DC / DC converter of the present embodiment is the same as that of the DC / DC converter of FIG. 1 used in the first embodiment. In the DC / DC converter of the present embodiment, the delay time of the OFF delay circuits 15 and 15A shown in FIG. It is characterized by a longer time.

  According to the DC / DC converter of the present embodiment, the phase loss can be detected not by the high-frequency current waveform but by the outputs of the OFF delay circuits 15 and 15A, which are direct current values, so that the phase loss can be easily detected. .

  (Fourth Embodiment) Next, a DC / DC converter according to a fourth embodiment of the present invention will be described. FIG. 4 shows a circuit configuration of a DC / DC converter according to a fourth embodiment of the present invention. The DC / DC converter of the present embodiment is characterized by masking phase loss detection when the output load current Icnv is small. The load current detector 21 and the load detection current detected by the load current detector 21 are masked. Load current comparison value setter 22 for setting load current comparison value I2 for value Icnv, load current comparator 23 for comparing load detection current value Icnv and load current comparison value I2, and output of load current comparator 23 Therefore, an AND circuit 24 for prohibiting the output of the gate OFF output circuit 20 is additionally provided. In FIG. 4, elements common to the first embodiment shown in FIG. 1 are denoted by the same reference numerals.

  Next, the phase loss detection operation of the DC / DC converter of this embodiment will be described. The load current comparison circuit 21 compares the load detection current value Icnv detected by the load current detector 21 with the load current comparison value I2 from the load current comparison value setter 22, and when Icnv <I2, the load current comparator 23 Becomes low (L), and the AND circuit 24 masks the function of detecting phase loss. As a result, when the load detection current value I2 is extremely small, there is a possibility of erroneous detection of phase loss. Thus, as with the first embodiment, phase loss detection can be easily performed, and unnecessary error can be detected when the load current is low. Detection can be prevented.

  Even in the present embodiment, the delay time of the OFF delay circuits 15 and 15A is the sampling period of the inverter current detector 11 or the same as in the second and third embodiments with respect to the first embodiment. It can be set to a time longer than the switching period of the full bridge inverter 1.

  (Fifth Embodiment) Next, a DC / DC converter according to a fifth embodiment of the present invention will be described. FIG. 5 shows a circuit configuration of the DC / DC converter of the present embodiment. The main circuit configuration in the DC / DC converter of the present embodiment is the same as that of the first embodiment shown in FIG.

  The DC / DC converter according to the present embodiment is characterized in that the phase loss is determined by comparing the value obtained by multiplying the load current Icnv by the coefficient K with the inverter detection current value Iinv and its inverted value -Iinv as a comparison value. The inverter current detector 11 that detects the output current of the full-bridge inverter 1 every predetermined sampling period, the load current detector 21 that similarly detects the load current every predetermined sampling period, and the output of the load detection detector 21 The coefficient multiplier 25 that multiplies the load detection current value I2 to be multiplied by the coefficient K and outputs the result as a comparison value K * Icnv, the inverter detection current value Iinv of the inverter current detector 11 and the comparison value K * Icnv from the coefficient multiplier 25 The comparison circuit 14 outputs a signal when the inverter detection current value Iinv> comparison value K * Icnv is satisfied, and The inverter circuit 13 for inverting the polarity of the inverter detection current value Iinv of the barter current detector 4, the inverter detection current value −Iinv inverted by this inverting circuit 13 and the comparison value K * Icnv are compared, and the inverter detection current is inverted A comparison circuit 14A is provided that outputs a signal when value -Iinv> comparison value K * Icnv is satisfied. Further, the DC / DC converter of this embodiment includes OFF delay circuits 15 and 15A, an exclusive OR circuit 16, an ON delay circuit 17, and a gate OFF output circuit 20 similar to those of the first embodiment. .

  Next, the phase loss detection operation by the DC / DC converter having the above configuration will be described with reference to timing charts of FIGS. 6 shows the relationship between the inverter current Iinv when the load current Icnv is small, the comparison value K * Icnv, and the outputs of the comparison circuits 14 and 14A, and FIG. 7 shows the inverter current when the load current Icnv is large and the comparison The relationship between the value and the comparison circuit output is shown.

  When the comparison circuit 14 satisfies the inverter detection current value Iinv> the comparison value K * Icnv, the comparison circuit 14 outputs a high (H) signal. The inverter detection current value Iinv is inverted by the inversion circuit 13 and input to the comparison circuit 14A, and the comparison value 14Ia and the comparison value K * Icnv are compared with each other. When -Iinv> K * Icnv is established, a high (H) signal is output from the comparison circuit 14A.

  The signals output from the comparison circuits 14 and 14A are input to the OFF delay circuits 15 and 15A, respectively. When the delay time of the OFF delay circuits 15 and 15A is longer than a preset delay time, the outputs of the OFF delay circuits 15 and 15A are continuously high (H). When the phase of the switching element is lost, the condition of the comparison circuit 14 or the comparison circuit 14A is not satisfied, so that the output of the OFF delay circuit 15 or the OFF delay circuit 15A is continuously low (L). When the outputs of the OFF delay circuits 15 and 15A are input to the exclusive OR 16 and continue for a time determined by the ON delay circuit 17, the output changes to become a phase loss detection signal, and the gate OFF output circuit 20 is a full bridge. A gate OFF signal is output to the inverter 1 to stop it.

  In the present embodiment, the positive current detection system of full-bridge inverter 1 changes its output when inverter detection current value Iinv is equal to or greater than comparison value K * Icnv obtained by multiplying load detection current value Icnv by K. . Similarly, the negative current detection system of the inverter 1 changes its output when the inverting inverter detection current value -Iinv is equal to or less than the comparison value K * Icnv. The outputs of the positive and negative current detection systems are input to the OFF delay circuits 15 and 15A, respectively. When the outputs of the two OFF delay circuits 15 and 15A are input to the exclusive OR circuit 16 and when they are in different states, the outputs change, and the ON delay circuit 17 continues the state for a certain period of time. In addition, the output changes and phase loss is detected, and the full bridge inverter 1 can be stopped.

  According to the present embodiment, as shown in FIGS. 6 and 7, the comparison level with respect to the inverter current Iinv for detecting the open phase can be changed according to the magnitude of the load current Icnv, and thereby the load current Icnv is When the load current is large, malfunctions are unlikely to occur, and even when the load current is small, an open phase can be detected reliably. Furthermore, since the outputs of the OFF delay circuits 15 and 15A are direct current, it is possible to detect a phase loss even with software with slow sampling.

  Even in this embodiment, the delay times of the OFF delay circuits 15 and 15A are made longer than the switching period of the inverter 1, as in the second and third embodiments with respect to the first embodiment. Or it can be made longer than the sampling period of the inverter current detector 11.

  (Sixth Embodiment) Next, a DC / DC converter according to a sixth embodiment of the present invention will be described with reference to FIG. This embodiment is characterized in that the phase loss detection is masked when the load current Icnv is small, as in the fourth embodiment shown in FIG. 4 with respect to the first embodiment shown in FIG. For the circuit elements of the DC / DC converter of the fifth embodiment shown in FIG. 5, the load current comparison value setting unit 22 for setting the load current comparison value I2 and the output Icnv of the load current detector 21 are A load current comparator 23 for comparing with the load current comparison value I2 and an AND circuit 24 for prohibiting the output of the gate OFF output circuit 20 by the output of the load current comparator 23 are additionally provided. In FIG. 8, elements common to the fifth embodiment shown in FIG. 5 are denoted by the same reference numerals.

  According to the DC / DC converter of the present embodiment, the load detection current value Icnv is compared with the load current comparison value I2, and when Icnv <I2, the output of the load current comparator 23 is set to low (L). The AND circuit 24 inhibits the output of the gate OFF output circuit 20. As a result, the function of detecting phase loss can be masked when the load current Icnv is small, and unnecessary erroneous detection can be prevented when the load current is small.

  Even in this embodiment, the delay times of the OFF delay circuits 15 and 15A are made longer than the switching period of the inverter 1, as in the second and third embodiments with respect to the first embodiment. Or it can be made longer than the sampling period of the inverter current detector 11.

The block diagram of the DC / DC converter of the 1st Embodiment of this invention. The wave form diagram which shows the relationship between the inverter electric current at the time of the normal inverter by the DC / DC converter of the said embodiment, predetermined value, an inverting circuit output, a comparison circuit output, and an OFF delay circuit output. The wave form diagram which shows the relationship between the inverter electric current at the time of the inverter phase loss by the DC / DC converter of the said embodiment, a predetermined value, an inverting circuit output, a comparison circuit output, and an OFF delay circuit output. The block diagram of the DC / DC converter of the 4th Embodiment of this invention. The block diagram of the DC / DC converter of the 5th Embodiment of this invention. The wave form diagram which shows the relationship between the inverter electric current in case the load current by the DC / DC converter of the said embodiment is small, a comparison value, and a comparison circuit output. The wave form diagram which shows the relationship between the inverter current in case the load current by the DC / DC converter of the said embodiment is large, a comparison value, and a comparison circuit output. The block diagram of the DC / DC converter of the 6th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Full bridge inverter 2 Transformer 3 Rectifier circuit 2 Comparison value 11 Inverter current detector 12 Inverter current comparison value setter 13 Inversion circuit 14, 14A Comparison circuit 15, 15A OFF delay circuit 16 Exclusive OR circuit 17 ON delay circuit 20 Gate OFF output circuit 21 Load current detector 22 Load current comparison value setter 23 Load current comparator 24 AND circuit 25 Coefficient multiplier

Claims (6)

In a DC / DC converter having a single-phase full-bridge inverter in which switching elements at diagonal positions simultaneously turn on and off and output positive and negative rectangular wave voltages,
An inverter current detection circuit for detecting a current flowing through the output of the full bridge inverter;
A first current comparison circuit that compares a detected current value of the inverter current detection circuit with a preset inverter current comparison value;
A second current comparison circuit that compares positive and negative inversion values of the detected current value of the inverter current detection circuit with the inverter current comparison value;
A first OFF delay circuit having a predetermined delay time connected to the output of the first current comparison circuit;
A second OFF delay circuit having a predetermined delay time connected to the output of the second current comparison circuit;
A DC / DC converter, comprising: a phase loss detection circuit that detects phase loss when the output of either of the first and second OFF delay circuits is continuously turned OFF. In a DC / DC converter having a single-phase full-bridge inverter in which switching elements at diagonal positions simultaneously turn on and off and output positive and negative rectangular wave voltages,
An inverter current detection circuit for detecting a current flowing through the output of the full bridge inverter;
A first current comparison circuit that compares a detected current value of the inverter current detection circuit with a preset inverter current comparison value;
A second current comparison circuit that compares positive and negative inversion values of the detected current value of the inverter current detection circuit with the inverter current comparison value;
A first OFF delay circuit connected to the output of the first current comparison circuit and having an OFF delay characteristic longer than a sampling time;
A second OFF delay circuit connected to the output of the second current comparison circuit and having an OFF delay characteristic longer than the sampling time;
A DC / DC converter, comprising: a phase loss detection circuit that detects phase loss when the output of either of the first and second OFF delay circuits is continuously turned OFF. In a DC / DC converter having a single-phase full-bridge inverter in which switching elements at diagonal positions simultaneously turn on and off and output positive and negative rectangular wave voltages,
An inverter current detection circuit for detecting a current flowing through the output of the full bridge inverter;
A first current comparison circuit that compares a detection current value of the inverter current detection circuit with a comparison value;
A second current comparison circuit that compares positive and negative inversion values of the detection current value of the inverter current detection circuit with the comparison value;
A first OFF delay circuit connected to the output of the first current comparison circuit and having an OFF delay characteristic longer than a switching period;
A second OFF delay circuit connected to an output of the second current comparison circuit and having an OFF delay characteristic longer than a switching period;
A DC / DC converter, comprising: a phase loss detection circuit that detects phase loss when the output of either of the first and second OFF delay circuits is continuously turned OFF. A load current detection circuit for detecting an output current of the DC / DC converter;
A phase loss detection limiting circuit that prohibits the phase loss detection operation from being performed with respect to the phase loss detection circuit when a detection current value detected by the load current detection circuit is equal to or less than a preset load current comparison value. The DC / DC converter according to any one of claims 1 to 3. A load current detection circuit for detecting an output current of the DC / DC converter;
The first current comparison circuit compares the load detection current value of the load current detection circuit with the inverter detection current value of the inverter current detection circuit instead of the inverter current comparison value,
The second current comparison circuit compares a load detection current value of the load current detection circuit with a positive / negative inverted value of the inverter detection current value of the inverter current detection circuit instead of the inverter current comparison value. The DC / DC converter according to any one of claims 1 to 3. An open phase detection limiting circuit is provided that prohibits the open phase detection operation for the open phase detection circuit when a detection current value detected by the load current detection circuit is equal to or less than a preset load current comparison value. The DC / DC converter according to claim 5.

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