JP4834951B2 - LED element forming method - Google Patents

Description

The present invention relates to a LED element formed how, and in particular LED elements forming how having a step of forming a bump at a predetermined position such as a semiconductor growth substrate using a damascene method.

  Conventionally, in the process of manufacturing a light-emitting diode (LED), after growing an n-clad layer, an active layer, and a p-clad layer on a semiconductor growth substrate, to reduce the contact resistance with an electrode A contact metal was formed on the uppermost layer, and a bump reaching the contact metal was formed by a damascene method. In order to form a bump at the position where the contact metal is formed, it is necessary to pattern the resist with precision at the position of the contact metal to open the via. Conventionally, it is selected using an aligner or a stepper. Were exposed to light and developed.

  On the other hand, semiconductor elements such as light emitting diodes are also decreasing in chip size year by year, and at the same time, the area of contact metal formed on a semiconductor growth substrate is becoming smaller. In order to reduce the manufacturing cost, in order to increase the number of elements taken out from one semiconductor growth substrate, it is necessary to reduce the distance between the elements. It gets smaller.

  FIG. 12 is a schematic cross-sectional view illustrating a state in which a via is formed by a conventional element forming method in order to form a bump by a damascene method on a contact metal formed on a semiconductor growth substrate. As shown in the figure, an n-clad layer 2, an active layer 3, and a p-clad layer 4 of gallium nitride (GaN) are stacked and grown on a semiconductor growth substrate 1 such as a sapphire substrate. A metal layer such as nickel (Ni) is formed on the p-cladding layer 4, a resist is applied, a mask is applied, and photolithography such as exposure and development is performed to form a contact metal 5. After the contact metal 5 is formed, a resist layer 6 is applied on the p-cladding layer 4 and the contact metal 5, and a via 7 is opened by photolithography in accordance with the position of the contact metal 5 using an aligner or a stepper.

  As shown in FIG. 12, the via 7 is opened corresponding to the position of the contact metal 5. For example, in a light emitting diode having a side of 15 μm square, the width of the contact metal 5 is about 5 μm. The width is about 3 μm and the height is about 5 μm. As described above, the via 7 formed by the conventional element forming method has an area smaller than the area of the contact metal 5 in consideration of an error in alignment by an aligner or a stepper.

  However, in the conventional element formation method described above, the element is downsized, the contact metal area is reduced, and the distance between adjacent contact vias is reduced, so that it is necessary to align the fine pattern with high accuracy. There is a problem that alignment during via formation becomes difficult. In addition, as shown in FIG. 12, in consideration of errors in alignment, when forming a via with an opening smaller than the area of the contact metal, an aspect that is a ratio of the via opening area to the via depth. Since the resist patterning has a high ratio, it is difficult to form a via by photolithography.

  In addition, when the target for forming a via is, for example, a gallium nitride-based light emitting device, the substrate is warped in the process of growing a crystal on the semiconductor growth substrate, and the distance between the mask and the substrate surface is not constant. In addition, there is a problem that high-precision alignment becomes difficult. Furthermore, if the contact metal is used as an alignment mark if the surface morphology of the substrate is poor, the reflected light from the contact metal will be irregularly reflected, resulting in reduced recognition accuracy and difficulty in high-precision alignment. There was also a problem.

  Furthermore, exposure to light by photolithography attenuates light at the resist layer, so it is difficult to obtain a forward-tapered pattern with a negative resist, and a reverse-tapered pattern is difficult to obtain with a positive resist. It had been.

Accordingly, the present invention is a fine pattern and even a high aspect ratio pattern, and an object thereof is to provide a simple and LED element formed how capable of performing alignment with high accuracy.

In order to solve the above problems, an LED element forming method of the present invention includes a step of forming a semiconductor layer including an active layer by crystal growth on a growth substrate, a step of forming a contact metal on the semiconductor layer, and a contact metal A step of performing vertical etching on a semiconductor layer formed on the growth substrate to a deeper region than the active layer is used as a mask.
In addition, after applying a negative resist layer on the etched region and the contact metal, light that is transmitted through the growth substrate and blocked by the pattern film is irradiated from the opposite side of the growth substrate on which the resist layer is applied. Exposing.
Also, after the exposure, the resist layer is developed and cured, the cured resist layer is heated and deformed, and a bump is formed by depositing a metal layer in the contact via formed by the development and curing. ,including.

By using the contact metal as a mask and exposing the growth substrate from the side opposite to the surface on which the resist layer is applied, the resist can be easily and accurately exposed even on a fine pattern. Since the contact metal is used as a mask, the opening portion of the formed via has approximately the same area and approximately the same shape as the mask, and it is easy to ensure electrical connection when bumps are formed on the via.

Further, by etching the growth substrate using the contact metal as a mask before applying the resist layer, the resist layer can be formed to the etched depth of the growth substrate. By performing the etching at this time to a region deeper than the active layer formed on the growth substrate, the area of the active layer can be reduced, and the amount of light absorbed by the active layer in the exposure light can be reduced. The resist layer can be exposed efficiently. Also, even when the active layer emits light due to exposure light, the light emitted from the active layer can be blocked by the pattern film, so that the traveling direction of the light for exposing the resist layer can be controlled. it can.

In addition, by using the contact metal as a mask and using a negative photosensitive material as the resist layer, the exposure region can be formed in a forward tapered shape by attenuation of light for exposure in the resist layer. By forming the exposure area in a forward tapered shape, the resist layer is developed and cured after the exposure process to form a contact via, and a metal layer is deposited in the contact via to form a bump. Since a contact via having a taper shape in the direction can be formed, it is easy to deposit a metal for forming a bump. On the other hand, the pattern film is an insulating film, and a positive photosensitive material is used as the resist layer, so that the tapered tapered exposure region and the contact via can be formed.

Further, development is performed with hardening of the resist layer after exposure, heating the hardened resist layer be to deformation, and to smooth the surface of the cured resist layer, it is possible to cause a slight deformation . By deforming the resist layer, the hardened resist layer partially overlaps the contact metal, and the exposed area of the contact metal is reduced. However, it is possible to reliably insulate the components other than the contact metal. become able to do.

Furthermore, a crystal may be selectively grown in a predetermined region on the growth substrate to form a three-dimensional structure element, and a contact metal may be formed on the three-dimensional structure element. Using contact metal as a mask, exposure is performed from the opposite side of the growth substrate to which the resist layer is applied, so that even a three-dimensional element can be easily and highly accurately formed on a fine pattern. Exposure can be performed. Examples of the three-dimensional element at this time include a hexagonal pyramid-shaped gallium nitride-based light-emitting element.

Using a contact Metall formed on the substrate as a mask, the resist of the substrate to perform exposure from the opposite side to the coated surface, to the resist exposure of easily and highly accurately even on a fine pattern Can do. To have a contact Metall a mask, an opening portion of the formed vias as a mask substantially the same area and approximately the same shape, it becomes easy to ensure the electrical connections in the case of forming a bump in the via.

Hereinafter, an element formation method and a wiring formation method to which the present invention is applied will be described in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably. In addition to the light emitting diode, the element forming method and the wiring forming method of the present invention include a laser diode and a light receiving element, FET (field-effect transistor), HEMT (high electron mobility transistor), HBT (heterobipolar transistor), bipolar device, In the process of manufacturing various devices such as TFT (thin film transistor), MOS (metal-oxide semiconductor), MIS (Metal-Insulator-Semiconductor) and Schottky junctions, solar cells, various sensors, quantum effect devices, etc. Can be used. In addition to compound semiconductors, it can also be used for via formation using materials such as silicon germanium (SiGe), silicon carbide (SiC), diamond, amorphous semiconductors, polycrystalline semiconductors, strong and paraelectric, and superconducting materials. is there.
[First embodiment]

  1 to 8 are process cross-sectional views for forming bumps using a damascene method when forming a light emitting diode on a semiconductor growth substrate as an element forming method of the present invention.

  First, as shown in FIG. 1, an n-clad layer 12 in which n-type doping is performed on gallium nitride (GaN) is grown on a growth substrate 11 such as a sapphire substrate, and an active layer 13 is grown on the n-cladding layer 12. A p-clad layer 14 obtained by p-type doping gallium nitride is grown on the active layer 13. Here, a sapphire substrate is exemplified as the growth substrate 11, but silicon carbide (SiC) or another compound semiconductor substrate may be used, and the material is not limited. In addition, each layer grown on the growth substrate 11 is not limited to gallium nitride, and various materials such as gallium arsenide (GaAs) and gallium indium phosphorus (GaInP) may be used. In addition, the layer formed by crystal growth on the growth substrate 11 is not limited to the order of the n-clad layer 12, the active layer 13, and the p-clad layer 14, and the vertical positions of the n-clad layer 12 and the p-clad layer 14 are reversed. In this case, a multilayer structure having a plurality of layers may be further grown.

  Next, a metal film such as nickel (Ni) is formed on the p-cladding layer 14 using a technique such as sputtering or vapor deposition, a resist is applied on the metal film, and exposure is performed through a mask for development. By removing the metal film in the region where the resist has been removed by etching, a contact metal 15 having a position and shape corresponding to the mask is formed on the p-cladding layer 14 as shown in FIG. The contact metal 15 may be made of a metal that can reduce the contact resistance with the p-clad layer 14 such as nickel, platinum (Pt), and gold (Au) in addition to single nickel.

  Next, as shown in FIG. 3, using the contact metal 15 as a mask, the p-cladding layer 14, the active layer 13 and the n-cladding layer 12 are partially etched to form a metal isolation groove 16. For the etching, a method suitable for the material constituting the p-cladding layer 14, the active layer 13, and the n-cladding layer 12 is used, and the type of etching solution used for the etching is not limited. Since etching is performed using the contact metal 15 as a mask, the metal separation groove 16 has an opening having the same area as the contact metal 15 reaching the n-clad layer 12 as shown in the figure. Therefore, by forming the metal isolation groove 16, the contact metal 15, the p-cladding layer 14, and the active layer 13 are separated for each light emitting element. Here, an example in which the metal separation groove 16 is opened to the vicinity of the surface layer portion of the n-cladding layer 12 is shown, but it is sufficient that the metal separation groove 16 is opened at least to a position deeper than the active layer 13. The metal separation groove 16 may be opened until it reaches.

  Next, as shown in FIG. 4, a negative resist layer 17 is applied on the contact metal 15, the resist layer 17 is filled in the metal separation groove 16, and the resist layer 17 is also deposited on the contact metal 15. . For the application of the resist layer 17, a normal spin coating method or the like can be used.

  Next, as shown in FIG. 5, ultraviolet light is irradiated from the growth substrate 11 side to partially expose the resist layer 17 to form an exposure region 18. The light irradiated by this exposure is transmitted through the growth substrate 11 and the n-clad layer 12, but light having a wavelength that is blocked by the contact metal 15 is selected. For example, when the growth substrate 11 is a silicon substrate, infrared light is selected. For a substrate using other materials, light having a wavelength suitable for the material of the substrate is used. Therefore, the contact metal 15 functions as a pattern film that blocks light irradiated from the growth substrate 11 side.

  In addition, since the resist layer 17 filling the metal separation groove 16 is positioned on the growth substrate 11 side with respect to the contact metal 15, the entire region in the metal separation groove 16 is exposed. When exposure is performed from the growth substrate 11 side, ultraviolet light irradiated to the active layer 13 may be absorbed by the active layer 13, or the active layer 13 may emit light. However, since the contact metal 15 located closer to the resist layer 17 than the active layer 13 is used as a mask, the light reaching the resist layer 17 can be kept parallel even when the active layer 13 emits light. Thus, the shape of the exposure region 18 can be adjusted. Moreover, since the ultraviolet light absorbed by the active layer 13 can be reduced, efficient exposure can be performed. The light irradiated from the growth substrate 11 side at the time of exposure is parallel light, but attenuates when the light travels to the upper part of the resist layer 17, so that the exposed area becomes smaller on the upper part of the resist layer 17. A forward tapered exposure area 18 as shown in the figure is formed.

  Next, as shown in FIG. 6, the exposed region 18 of the resist layer 17 exposed from the growth substrate 11 side is developed and cured to form an insulating layer 19, and the resist layer 17 is removed to form a contact via 20. . Since the insulating layer 19 is a layer cured by exposing the resist layer 17, the insulating layer 19 is formed in a forward tapered shape similar to the exposed region 18. Since the contact metal 15 is used as a mask to irradiate light from the growth substrate 11 side and the unexposed region becomes the contact via 20, the opening region of the contact via 20 has substantially the same area and substantially the same shape as the contact metal 15. .

  After the insulating layer 19 is formed, the surface of the insulating layer 19 may be smoothed by heating in a reflow furnace or the like, or the insulating layer 19 may overlap the contact metal 15 by causing some shape deformation. . If the insulating layer 19 is deformed by overheating and the insulating layer 19 is overlapped on a part of the contact metal 15, the exposed area of the contact metal 15 is reduced, but the insulation from the components other than the contact metal 15 is ensured. To be able to do it.

  Next, as shown in FIG. 7, a metal such as copper (Cu) is deposited on the contact metal 15 and the insulating layer 19 by sputtering to form a seed metal 21, and a bump metal 22 such as copper is formed on the seed metal 21. Is formed by electrolytic plating. As a material for the seed metal 21 and the bump metal 22, a metal such as nickel (Ni) or aluminum (Al) may be used in addition to copper. Since the insulating layer 19 is formed in a forward tapered shape, the seed metal 21 can be formed on the entire side wall portion of the contact via 20 even when the seed metal 21 is formed by sputtering.

  Next, as shown in FIG. 8, the bump metal 22 and the seed metal 21 formed above the top region of the insulating layer 19 are removed by the damascene method, and the bump metal 22 formed in the contact via 20 is individualized. To do. Thereafter, an element isolation groove is formed at the position of the insulating layer 19 by dicing or etching, and then the growth substrate 11 is peeled to separate the elements individually to form an element of a light emitting diode.

As described above, by performing exposure from the growth substrate side using the contact metal as a mask, even a fine pattern can be patterned with high positional accuracy and high aspect ratio by self-alignment. Also, patterning can be performed with high positional accuracy even under conditions where positioning by an aligner is difficult, such as when the semiconductor wafer is warped or when the surface morphology is poor.
[Second Embodiment]

  FIG. 9 is a cross-sectional view illustrating a case where a hexagonal pyramid light emitting diode is formed on a semiconductor growth substrate and bumps are formed using a damascene method as an element forming method of the present invention. The element forming method of the present invention can be used not only for an element having a flat structure but also for an element having a three-dimensional structure, and is simply and highly accurately patterned by the same procedure as in the first embodiment described above. Can be done.

  As shown in FIG. 9, a hexagonal pyramidal light emitting element 32 is formed on a growth substrate 31 such as sapphire, and a contact metal 33 is formed in the top region of the light emitting element 32. The hexagonal pyramid light-emitting element 32 is, for example, a gallium nitride-based light-emitting diode, and is formed by appropriately selecting a crystal plane of a growth substrate and performing selective growth in which a crystal growth region is limited.

  Next, a resist layer is applied by spin coating or the like so as to cover the light emitting element 32 and the contact metal 33, and exposure using the contact metal 33 as a mask is performed by irradiating ultraviolet light from the growth substrate 31 side. Thereafter, the resist layer is developed and cured to form an insulating layer 34, and the resist layer on the contact metal 33 is removed to form a contact via 35 that is an opening reaching the contact metal 33.

  As in the first embodiment described above, light having a wavelength that is transmitted through the growth substrate 31 but blocked by the contact metal 33 is selected as the light used for the exposure. Therefore, the contact metal 33 functions as a pattern film that blocks light irradiated from the growth substrate 31 side. The light irradiated from the growth substrate 31 side at the time of exposure is parallel light, but attenuates when the light travels to the upper part of the resist layer, so that the exposed area becomes smaller on the upper part of the resist layer. The contact via 35 having a forward taper as shown in FIG.

  After the contact via 35 is formed, the contact via 35 is filled with a metal, bumps are formed using the damascene method, an element isolation groove is formed by dicing or etching at the position of the insulating layer 34, and then the growth substrate 31 is peeled off. Thus, the elements are individually separated to form a light emitting diode element.

By performing exposure from the growth substrate 31 side using the contact metal 33 as a mask, it is possible to perform patterning with high positional accuracy and high aspect ratio by self-alignment even with a fine pattern with a three-dimensionally structured element. Here, a hexagonal pyramid light emitting diode is shown as a light emitting element having a three-dimensional structure, but high-precision patterning can be easily performed even in structures having other shapes.
[Third embodiment]

  FIG. 10 is a process cross-sectional view illustrating a case where a wiring via is formed on a wiring pattern after an insulating layer is formed on a wiring board as a wiring forming method of the present invention. In this embodiment, the element forming method of the present invention described above is applied to a wiring pattern on a substrate, not a semiconductor element.

  As shown in FIG. 10A, a substrate is prepared in which a base wiring layer 42 having a predetermined pattern is formed on a wiring substrate 41 formed of an insulator. The underlying wiring layer 42 may be formed by a commonly used method such as lift-off processing, and becomes a foundation on which a metal layer is laminated on the underlying wiring layer 42 in a later process, so that light for exposure can be blocked. Any thickness is acceptable. Further, the wiring board 41 does not need to be formed of an insulator, and may be made of a semiconductor or a superconductor. The underlying wiring layer 42 may be made of a material such as titanium and gold, copper, or aluminum. After the base wiring layer 42 is formed on the wiring substrate 41, annealing may be performed to improve the adhesion between the base wiring layer 42 and the wiring substrate.

  Next, as shown in FIG. 10B, a resist layer 43 is applied on the wiring substrate 41 and the underlying wiring layer 42, and exposure is performed from the wiring substrate 41 side using the underlying wiring layer 42 as a mask. As light used for exposure, light having a wavelength that passes through the wiring substrate 41 but is blocked by the underlying wiring layer 42 is selected. Next, as shown in FIG. 10C, the resist layer 43 is developed and cured to make the resist layer 43 an insulating layer 44, and the resist layer 43 on the base wiring layer 42 is removed to remove the base wiring layer 42. A wiring groove (via) 45 is formed thereon. Next, as shown in FIG. 10D, a metal wiring layer 46 is formed by filling the wiring groove 45 with a metal such as aluminum by plating or the like.

By using the base wiring layer 42 on the wiring board 41 as a mask and exposing from the opposite side of the resist coated surface of the wiring board 41, the metal wiring layer 46 is formed on the base wiring layer 42 with a fine wiring rule. Even when it is desired to form the pattern, the pattern can be formed easily and with high accuracy. By forming the thick metal wiring layer 46 after the thin base wiring layer 42 is formed in advance, it is possible to improve the adhesion with the wiring substrate 41 and increase the cross-sectional area of the wiring to reduce the resistance. .
[Fourth embodiment]

  FIG. 11 is a process cross-sectional view illustrating a case where an insulating layer is used as a mask after an insulating layer is formed on a substrate as the element forming method of the present invention. This embodiment can be used when a contact via having a taper in the reverse direction is formed using a positive resist.

  As shown in FIG. 11A, a semiconductor substrate 51 having a multilayer structure such as a light emitting element is prepared, an insulating mask 52 is formed on the semiconductor substrate 51 with an insulating material, and an opening is formed in a predetermined pattern. Then, a contact metal 53 is formed by laminating a metal film in the opening. The insulating mask 52 is formed by a method such as photolithography. The contact metal 53 is made of nickel, nickel, platinum, gold, or the like, and the type of metal is not particularly limited.

  Next, as shown in FIG. 11B, a resist layer 54 is applied on the insulating mask 52 and the contact metal 53 by spin coating or the like, and exposure is performed from the side opposite to the surface on which the resist layer 54 of the semiconductor substrate 51 is applied. Do. At this time, light having a wavelength that is transmitted through the semiconductor substrate 51 and the contact metal 53 but is blocked by the insulating mask 52 is selected. Further, a positive resist material is used for the resist layer 54. Therefore, the contact metal 53 functions as a pattern film that blocks light irradiated from the semiconductor substrate 51 side.

  The light irradiated from the semiconductor substrate 51 side during the exposure is parallel light, but the light is attenuated as it travels to the upper part of the resist layer 54, so that the exposed area becomes smaller on the upper part of the resist layer 54. Since the photosensitive region gradually decreases from the region where the contact metal 53 is formed, an exposure region having a taper in the opposite direction is formed.

  Next, as shown in FIG. 11C, the resist layer 54 is developed and cured to form the resist layer 54 on the insulating mask 52 as the insulating layer 55, and the resist layer 54 on the opening 53 is removed to remove the contact via. The bump metal 56 is formed by filling the contact via with a metal such as copper, nickel, or aluminum. The bump metal 56 may be formed by a method such as formation of a seed metal by sputtering, formation of the bump metal 56 by plating, and individualization of the bump metal 56 by a damascene method. Thereafter, the elements are separated by dicing or etching at the position of the insulating layer 55, whereby the elements are individually separated to form a light emitting diode element.

  The resist layer 54 is formed of a positive resist material, and exposure is performed from the opposite side of the semiconductor substrate 51 using the insulating mask 52 as a mask, so that the insulating layer 55 is cured without being exposed to the resist layer 54 and is reversely moved. It is formed in a tapered shape. Since the insulating mask 52 is used as a mask and the contact metal 53 is a region through which light is transmitted, the exposed region becomes a contact via. Therefore, the bump metal 56 has a substantially the same area as the contact metal 53 and has substantially the same shape. It is formed.

  As described above, by performing exposure of the positive resist from the growth substrate side using the insulating mask as a mask, even a fine pattern can be patterned with high positional accuracy and high aspect ratio by self-alignment. Also, patterning can be performed with high positional accuracy even under conditions where positioning by an aligner is difficult, such as when the semiconductor wafer is warped or when the surface morphology is poor.

It is process sectional drawing which shows the element formation method in 1st embodiment of this invention, and has shown the state which formed the n clad layer, the active layer, and the p clad layer on the growth substrate. It is process sectional drawing which shows the element formation method in 1st embodiment of this invention, and has shown the state in which the contact metal was formed. It is process sectional drawing which shows the element formation method in 1st embodiment of this invention, and has shown the state which formed the metal isolation | separation groove | channel and isolate | separated the n clad layer, the active layer, and the p clad layer for every element . It is process sectional drawing which shows the element formation method in 1st embodiment of this invention, and has shown the state which apply | coated the resist on the p clad layer. It is process sectional drawing which shows the element formation method in 1st embodiment of this invention, and has shown the state exposed from the growth board | substrate side using the contact metal as a mask. It is process sectional drawing which shows the element formation method in 1st embodiment of this invention, and has shown the state which performed the development and hardening of the resist, and formed the via | veer. It is process sectional drawing which shows the element formation method in 1st embodiment of this invention, and has shown the state which filled the metal into the via | veer and formed bump metal. It is process sectional drawing which shows the element formation method in 1st embodiment of this invention, and has shown the state which removed the bump metal upper layer by the damascene method, and individualized the bump metal. It is sectional drawing which shows the element formation method in 2nd embodiment of this invention, and shows the case where a hexagonal pyramid-shaped light emitting diode is formed on a semiconductor growth substrate, and a bump is formed using the damascene method. . It is a process perspective view which shows the wiring formation method in 3rd embodiment of this invention, and shows the case where the wiring groove | channel for wiring is formed on a wiring pattern after forming an insulating layer on a wiring board. . It is process sectional drawing which shows the element formation method in the 4th Embodiment of this invention, and shows the case where an insulating film is used as a mask after forming an insulating layer on a board | substrate. It is sectional drawing which shows the manufacturing process of the light emitting diode in the case of positioning using a stepper or an aligner as the conventional element formation method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor growth substrate 2,12 n clad layer 3,13 active layer 4,14 p clad layer 5,15,33,53 contact metal 6,17,43,54 resist layer 7 via 11,31 growth substrate 16 metal separation groove 18 Exposed areas 19, 34, 44, 55 Insulating layers 20, 35 Contact via 21 Seed metal 22 Bump metal 32 Light emitting element 41 Wiring substrate 42 Underlying wiring layer 45 Wiring groove 46 Metal wiring layer 51 Semiconductor substrate 52 Insulating mask 56 Bump metal

Claims (3)

Forming a semiconductor layer including an active layer by crystal growth on a growth substrate;
Forming a contact metal on the semiconductor layer;
Performing vertical etching on the semiconductor layer formed on the growth substrate to a region deeper than the active layer, using the contact metal as a mask;
After applying a negative resist layer on the etched region and the contact metal, the growth substrate is transmitted through the growth substrate and blocked by the contact metal from the opposite side of the growth substrate to which the resist layer is applied. An exposure step of irradiating with light;
Performing development and curing of the resist layer after the exposure, and heating and deforming the cured resist layer;
Depositing a metal layer in contact vias formed by the development and curing to form bumps;
LED element formation method containing. The LED element formation method according to claim 1, wherein a crystal is selectively grown in a predetermined region on the growth substrate to form a three-dimensional element, and the contact metal is formed on the three-dimensional element.   The LED element forming method according to claim 2, wherein the element having the three-dimensional structure is a hexagonal pyramidal gallium nitride-based light emitting element.