JP4831157B2 - Format instruction method - Google Patents

Description

The present invention relates to a format instruction method for executing a format of an electronic device having a nonvolatile storage unit storing information updated in an initial process.

  In recent years, an IEEE (Institute of Electrical Engineers) 1394 data interface is known as a digital data interface. The IEEE 1394 data interface has a data transfer rate higher than that of, for example, SCSI, and is known to be capable of isochronous communication in which it is guaranteed that a required data size is periodically transmitted and received. For this reason, the IEEE 1394 data interface is advantageous for transferring stream data such as AV (Audio / Video) in real time.

  Against the background of such technology, electronic data such as various digital AV devices and personal computer devices are connected to each other via a data bus conforming to a data interface standard such as IEEE 1394, so that AV data can be transferred between the devices. An AV system capable of transmitting and receiving has been proposed.

  As the AV system described above, for example, an amplifier device is mainly used. By connecting various AV source output devices such as a CD player and a DVD player to a video device, for example, via a data bus. It is possible to construct a system.

  The role of the amplifier device in this AV system is to input AV source information transmitted from the AV source output device via the data bus, and finally output it as an audio signal to a speaker or the like. For this reason, the amplifier device has a function for selectively inputting one AV source output device from among a plurality of AV source output devices existing on the data bus, for example. That is, it has an input source selection function. This is because, for example, in accordance with the input source selection operation performed by the user on the amplifier device, a logical interconnection relationship on the data bus is established with the AV source output device specified by the selection operation. Realized.

With the development of AV devices and data network systems, digital data can be easily copied and transmitted, and copyright protection of digital data content such as music and video has become a big problem. .
For this reason, in order to protect the copyright of content data, various technologies have been proposed and implemented, such as data encryption, authentication between devices at the time of device connection, and a device exclusion method inappropriate for copyright protection. Further, for example, the following Patent Document 1 describes a technique for preventing unauthorized duplication.
JP 2000-306332 A

Even when the devices according to IEEE 1394 are connected to each other, particularly between devices in which audio data and video data are transmitted, it is assumed that the devices are mutually legitimate devices (for example, having a correct copyright protection function) by the authentication processing between the devices. Data transmission or the like is performed on the condition that authentication of a licensed device) is performed.
For example, audio data or the like is encrypted and transmitted, and when the above authentication process is completed, an encryption key is passed from the transmission side to the reception side, whereby the reception side is encrypted and transmitted. Can be deciphered. This suppresses unlimited transmission and copying of content data and realizes a copyright protection function.

By the way, in such an electronic device, a nonvolatile memory (NV-RAM) is often used to store various types of information using a characteristic that data is not lost even when the power is turned off. Various coefficients for operation of the device, setting values, information used for authentication, and the like may be stored.
For information stored in the nonvolatile memory, for example, initial processing is performed when a device is turned on, and necessary updates are performed.

By the way, in a factory that manufactures electronic devices, it is desired to confirm that the contents of the nonvolatile memory can be properly initialized before shipping.
For example, after the electronic device stores a program for executing the initial processing for the nonvolatile memory when the power is turned on, the data in the nonvolatile memory can be initialized by turning on the electronic device. it can.
However, the non-volatile memory mounted in the manufacturing process is of course indefinite contents, so there is no compensation for correctly performing the initial process of reading and determining the data contents and updating the data. .
In addition, since the execution contents are not displayed on the display unit or the like, for example, there is no means for confirming even in the factory.
For this reason, there is a possibility that the data content of the nonvolatile memory used for the copyright protection function is not necessarily in an appropriate data state before shipping.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to make the data contents of the nonvolatile storage means appropriate before shipment from the factory, and to realize process efficiency.

The formatting method of the present invention is a non-volatile storage for storing information updated in initial processing in an electronic device that establishes a communication state by performing authentication with an external electronic device connected via a data bus in a predetermined communication format . As a formatting method of the storage means, the initial processing for the non-volatile storage means is executed at a predetermined time based on the stored initial processing program, and the formatting is performed regardless of whether or not the initial processing is being executed. In response to the input of the instruction, a format process for the nonvolatile storage means is executed based on the stored format program, and the format instruction is transmitted to the external device via the data bus in the predetermined communication format. It is input from.
In an electronic device that establishes a communication state by performing authentication with an external electronic device connected by a data bus having a predetermined communication format, the format instruction is a data bus having the predetermined communication format, or The data is input by a data bus having a communication format different from the predetermined communication format.
The format instruction is input by a radio signal receiving unit or a reading unit that reads information from a recording medium.

In the case of the present invention as described above, in the electronic device, the initial process program and the format process can be executed by storing the initial process program and the format program.
The initial process is, for example, a process of reading data stored in the nonvolatile storage unit and updating the data when the power is turned on.
The format process is, for example, a process executed once before shipment from the factory, and is a process of writing an initial value of information contents in the nonvolatile storage means.
By performing the formatting process first, it is possible to obtain an appropriate data state for the nonvolatile storage means whose data content is indefinite. That is, it is possible to eliminate uncertainty due to the initial processing being performed on the nonvolatile storage means whose data content is indefinite.
Further, the format process can be executed more efficiently by interrupting the process even if the initial process is being executed based on the format instruction.

According to the present invention, the electronic device executes the initial processing based on the initial processing program at a predetermined time such as when the power is turned on. Based on the format processing, it is executed. Therefore, it is possible to format the nonvolatile storage means by inputting a format instruction when the power is turned on at the time after storing the initial processing program and the format program at the stage before factory shipment. As a result, there is an effect that the nonvolatile storage means having undefined data contents can be brought into an appropriate data state. That is, it is possible to eliminate uncertainty due to the initial processing being performed on the nonvolatile storage means whose data content is indefinite.
Further, the format process can be executed more efficiently by interrupting the process even if the initial process is being executed based on the format instruction. That is, the initial processing program is started when the electronic device is turned on, but the initial processing can be interrupted to execute the format processing, thereby shortening the process time.

  Also, the format instruction is input in an encrypted state using ID information unique to the electronic device, and the electronic device side performs decryption using the ID information to recognize the format instruction. It is possible to prevent the user from starting the format program. That is, the format processing of the nonvolatile storage means can be performed only at the factory side, and inappropriate data writing on the user side can be prevented.

  The format instruction (format trigger) is input by a data bus having a predetermined communication format, a data bus having a communication format different from the predetermined communication format, a radio signal receiving unit, or a reading unit that reads information from a recording medium. The That is, by diversifying the format instruction input paths, various apparatuses (apparatuses having various information output forms) can be used as apparatuses for inputting the format instruction to the electronic device. For example, it is not always necessary to use an instruction device compatible with the IEEE 1394 bus, and a convenient device can be used at the process site, so that manufacturing costs can be reduced and work efficiency can be improved.

  In addition, after transmitting the initial processing program, the format program, and the ID information to the electronic device, information is transmitted / received to detect the activation of the electronic device, and the activation of the electronic device is detected. By transmitting the format instruction, it is possible to cause the electronic device to execute the format process most efficiently.

Embodiments of the present invention will be described below. The description will be given in the following order.
1. AV system 1-1 Overall configuration 1-2 STR (front panel)
1-3 STR compatible disk drive (front panel)
1-4 STR (internal)
1-5 STR compatible disk drive (internal)
2. Data communication 2-1 according to the present embodiment according to IEEE1394 2-1 Overview 2-2 Stack model 2-3 Signal transmission mode 2-4 Bus connection between devices 2-5 Packet 2-6 Transaction rule 2-7 Addressing 2-8 CIP ( Common Isochronous Packet)
2-9 Connection Management 2-10 Command and Response in FCP 2-11 AV / C Command Packet SRM
4). NV-RAM Format Processing 4-1 Configuration of Initial Processing and Format Processing Processing System 4-2 Initial Processing 4-3 Format Trigger Corresponding Processing 4-4 Format Trigger Input Path Example 4-5 Format Trigger Transmission Processing Example

1. AV System 1-1 Overall Configuration FIG. 1 shows a configuration example of an electronic device system including an electronic device according to an embodiment of the present invention.
This electronic device system is constructed by connecting a plurality of AV devices and the like through an IEEE 1394 interface data bus so that they can communicate with each other.

  In FIG. 1, STR (Stereo Tuner Receiver) 60, STR compatible disk drive 30, identical manufacturer device 100, and other manufacturer device 110 are shown as devices constituting the AV system.

The STR 60 functions as the center of the AV system shown in FIG. 1, and mainly includes a tuner function, an external source input selection function, and an amplifier function. For example, the speaker SP corresponding to 5-channel stereo sound as shown in the figure. (FL), SP (FR), SP (SL), SP (SR), and SP (C) can be connected.
Speaker SP (FL) is front left channel speaker, speaker SP (FR) is front right channel speaker, speaker SP (SL) is surround left channel speaker, speaker SP (SR) is surround right channel speaker, speaker SP (C) is Center channel speaker.
Note that other speaker configurations are possible, such as adding a subwoofer speaker to form a so-called 5.1 channel speaker system.

  Although the detailed configuration will be described later, in the STR 60, a broadcast signal received by the internal tuner unit, an analog audio signal input, a digital audio signal input, and a plurality of audio sources input from the outside via the IEEE 1394 bus 116 are also described. It is configured so that selection can be made and finally this can be output as audio from the speaker SP.

  This figure also shows a remote controller RM for performing an operation on the STR 60. The STR 60 receives an operation command signal transmitted in response to an operation performed on the remote controller RM, and executes a required operation according to the content of the operation command signal. In this figure, only the remote controller RM corresponding to the STR 60 is shown, but actually, other devices may be operable by the remote controller.

  Further, here, a STR compatible disk drive 30 is shown as a model that can realize various convenient system functions by connecting with the STR 60. The STR compatible disk drive 30 is, for example, the same manufacturer as STR60.

The STR compatible disc drive 30 has a function as a disc player that can handle each of, for example, a CD (Compact Disc), a SACD (Super Audio CD), and a DVD (Digital Versatile Disc). Perform playback.
Then, audio data obtained by reproducing from the disc can be transmitted and output via the IEEE 1394 bus 116.
As is well known, audio data reproduced from a CD is linear PCM data with a sampling frequency of 44.1 KHz and 16-bit quantization.
When a DVD is reproduced, not only audio data but also video data may be reproduced. Therefore, the STR compatible disk drive 30 has a video decoding function. Although not shown in FIG. 1, for example, a display device such as a CRT, a liquid crystal display, or the like is connected to the STR compatible disk drive 30, so that video reproduced from a DVD can be displayed and output.
SACD is a medium using a 1-bit digital audio signal system (DSD: Direct Stream Digital) using ΣΔ modulation. This DSD signal is 1-bit quantized digital audio data with a sampling frequency as high as 64 times the CD sampling frequency fs (fs = 44.1 KHz), and enables signal reproduction beyond the audible frequency band.
In order to support such an SACD, the STR compatible disk drive 30 has a decoding function compatible with the DSD signal.

  By connecting such a STR compatible disk drive 30 to the STR 60 via the IEEE 1394 bus 116, it becomes possible to execute reproduction output of CD, DVD, and SACD by a speaker system connected to the STR 60.

The same manufacturer device 100 is a digital AV device which is the same manufacturer as the STR 60 and the STR compatible disk drive 30 and has a communication function corresponding to the IEEE 1394 interface. The actual manufacturer device 100 here is not particularly mentioned, but may be a CD player, an MD recorder / player, a digital VTR, or the like.
The same manufacturer device 100 is not particularly configured to be provided with system component functions centered on the STR 60 when compared with, for example, the STR compatible disk drive 30 and the STR compatible MD 1. Different.
However, depending on the transmission / reception of a command (referred to as a Vender Dependent Command) that is valid only within the manufacturer, it operates together with the STR 60, the STR compatible disk drive 30, and the STR compatible MD device 1 so as to have a specific function defined by the manufacturer. It is possible to do that.
For example, if a manual operation is performed on the STR 60 so that data as an audio source transmitted from the same manufacturer's device 100 is selected and received and input, the STR 60 can be monitored or recorded as audio. Etc. are possible.

  The other manufacturer's device 110 is also a digital AV device having a communication function corresponding to the IEEE 1394 interface, but the manufacturer is different from the STR 60 and the STR compatible disk drive 30. In this case, the other manufacturer's equipment 110 may be a CD player, an MD recorder / player, a digital VTR, or the like. However, in the case of the other manufacturer device 110, in principle, it is not possible to support the Vender Dependent Command defined by the manufacturer of the STR 60 described above.

  Although not shown here, for example, each AV device shown in FIG. 1 is provided with a power outlet for inputting power from a commercial AC power source. Alternatively, a battery can be stored in a configuration that can be driven by a battery. That is, each device can obtain power independently.

1-2 STR (front panel)
Next, each of the front panel parts will be described as an external configuration of the STR 60 and the STR compatible disk drive 30 that forms a component system with the STR 60, which is the main component in configuring the system shown in FIG. .

FIG. 2 shows the state of the front panel portion of the STR 60 main body.
A power key 120 is provided on the lower left side of the front panel. By operating the power key 120, the power supply of the STR 60 is switched on / off. Note that the state where the power source is off here refers to a so-called standby state in which the standby power source is operating, and is different from, for example, a state where the supply of commercial AC power source (or battery) is cut off. In this respect, the same applies to the STR compatible disk drive 30 described below.
Further, although detailed description is omitted here, the STR 60 is also provided with a sleep mode for setting a sleep state, so that power saving is considered.
A headphone jack 86 is provided on the left side of the power key 120.

A display unit 87 is disposed substantially at the center of the front panel.
As the display unit 87 in this case, an FL tube display unit 87A for mainly displaying characters is provided, and here, display for 14 characters per line is performed. In addition, a segment display portion 87B is provided around the periphery, and a predetermined content, which is not shown, is displayed by the segment.
A display key 127 is provided on the left side of the display unit 87.
The display key 127 is basically for changing the display contents on the display unit 75.

Further, the jog dial 125 is shown on the right side of the FL tube display portion 87A, and the tuning mode key 121, the tuner key 122, the function / menu key 123, and the enter key 124 are shown on the upper side.
The tuning mode key 121 and the tuner key 122 are keys related to the tuner function of the STR 60, and are used when switching between the reception band and the tuner mode, respectively.
The function / menu key 123 is a key for performing function selection or menu selection, and the enter key 124 is used for performing a determination operation.
The jog dial 125 is used together with the above keys under a predetermined operation procedure, so that the user can perform various actual operations.

As an example, every time the function / menu key 123 is pressed, the display content of the FL tube display portion 87A changes with a toggle in the order of FUNCTION → SOUND → SETUP.
For example, when the jog dial 125 is rotated while the function is displayed on the FL tube display 87A, the selection of the source input by the STR 60 and output as the monitor sound can be changed. At this time, the FL source display portion 87A displays the name of the input source currently selected according to the rotation operation of the jog dial 125. Depending on this operation, for example, it is possible to sequentially select tuner audio, analog input, optical digital input, and each source (device) input via the IEEE 1394 bus according to a predetermined order.
For example, the keys such as the tuning mode key 121, the tuner key 122, the function / menu key 123, the enter key 124 are provided with decorative LEDs on the back side thereof, and are lit, flashing, etc. according to the operating state. It is also to be done.

  The volume jog 126 is provided as a dial key for adjusting the audio signal level output from the STR 60, that is, the volume output from the speaker SP, for example.

1-3 STR compatible disk drive (front panel)
FIG. 3 shows a front panel portion of the STR compatible disk drive 30.
First, a power key 150 for power on / off (standby) is also provided on the lower left side of the front panel of the STR compatible disk drive 30.

  Further, a disc insertion / removal unit 159 for inserting / ejecting a disc as a CD, SACD, or DVD is provided at the upper center of the front panel of the STR compatible disc drive 30. For example, in order to eject a CD or the like stored in and loaded in the disk insertion / removal unit 159, the eject key 151 disposed on the right side of the disk insertion / removal unit 159 is operated.

Below the disk insertion / removal unit 159, a display unit 47 including, for example, an FL tube display unit 47A capable of displaying 14 characters per line and a segment display unit 47B is provided. In this case, the FL tube display 47A is recorded on a disc such as a CD or information indicating the playback status such as the track number and playback time of a track to be played on a currently loaded CD, for example. Text data etc. are displayed as characters. The segment display section 47B shows a playback mode and the like.
The display content on the FL tube display unit 47A can be switched by operating a display key 156 arranged on the left side of the display unit 47.

  On the right side of the front panel, a play / pause key 152, a stop key 153, a cue / fast forward / rewind key 154, 155 are provided as keys related to CD playback.

A HATS key 157 is provided on the left side of the front panel. The HATS key 157 is an operation key for turning on / off the HATS function.
HATS (High Quality Digital Audio Transmission System) is a function that prevents deterioration of digital audio signal quality due to the influence of jitter of a transmission clock.
For example, when audio data is transmitted from the STR compatible disk drive 30 to the STR 60 through the IEEE 1394 bus 116, fluctuations in the time axis direction occur in the received audio data on the STR 60 side due to jitter of the transmission clock. Therefore, the STR 60 side temporarily stores the received audio data in the buffer memory based on the transmission clock, and reads it based on the crystal clock to eliminate the fluctuation of the audio data in the time axis direction. . When the HATS function is on, a signal for flow control is exchanged between the STR compatible disk drive 30 and the STR 60.

  Here, as can be seen from the state of the front panel shown in FIGS. 2 and 3, each of the STR 60 and the STR compatible disk drive 30 has display portions 75 and 47 for the own device. In other words, for example, when a system composed of STR and STR compatible devices is considered as one audio component system, there is no display part integrated as this component system. This corresponds to the fact that, for example, devices connected via IEEE 1394 are inherently independent from each other.

1-4 STR (internal)
Next, each internal configuration of the STR 60 and the STR compatible disk drive 30 will be described.

First, an internal configuration example of the STR 60 is shown in the block diagram of FIG.
In the STR 60, as an audio source, an audio signal transmitted via the IEEE 1394 bus 116, an audio signal of a tuner provided therein, an external digital audio signal input from the optical digital input terminal 67, and an analog input terminal 78 4 types of external analog audio signals input from the input can be input.

The IEEE 1394 interface 61 is provided for transmitting and receiving data to and from other external devices via the IEEE 1394 bus 116. Accordingly, the STR 60 is configured to be capable of transmitting / receiving AV data to / from the outside and transmitting / receiving various commands.
The IEEE 1394 interface 61 demodulates a packet received via the IEEE 1394 bus 116 and extracts data contained in the demodulated packet. The extracted data is converted into data in a format compatible with internal data communication and output.
For example, it is assumed that audio data is transmitted from another AV device via the IEEE 1394 bus 116. The IEEE 1394 interface 61 receives the transmitted audio data and performs demodulation processing on the packet.
When CD or DVD playback data is received when the transmission source device is considered as a STR compatible disk drive 30, for example, it is converted into audio data TD1 in a digital audio data interface format called IEC60958, for example. Output.
In this case, the audio data TD1 is supplied to the demodulation processing unit 66. In the demodulation processing unit 66, the input audio data TD1 is subjected to necessary demodulation processing according to, for example, the IEC60958 format, and is output to the PCM selector 69 as, for example, linear PCM data (PCM1).

  The external digital audio signal input from the optical digital input terminal 67 is also, for example, data in IEC60958 format, and the input from the optical digital input terminal 67 is also demodulated by the demodulation processing unit 66 and linear PCM data. (PCM1) is supplied to the PCM selector 69.

SACD playback data is encrypted and transmitted.
When the IEEE 1394 interface 61 receives SACD playback data via the IEEE 1394 bus 116, the IEEE 1394 interface 61 performs packet demodulation processing, decryption processing, and the like to perform 1-bit quantization by 64fs and ΣΔ modulation. The DSD signal TD3 is output.
The DSD signal TD3 is supplied to the decimation filter 65, converted into linear PCM data (PCM3) by the decimation filter 65, and supplied to the PCM selector 69.

The PLL 63 generates a clock for packet demodulation processing based on the transmission clock. When the above-described HATS function is OFF, the DSD signal TD3 and the IEC60958 data TD1 based on the clock generated by the PLL 63 are output.
The RAM 62 functions as a transmission / reception data buffer in the IEEE 1394 interface 61.
The clock oscillator 64 generates a crystal clock.

When the above-described HATS function is turned on and the reproduction data of CD and DVD is received by the IEEE 1394 interface 61, the data is once written in the RAM 62 and then the crystal clock from the clock oscillator 64. Is read based on In particular, the IEEE 1394 interface 61 also has a demodulation function for IEC60958 data. When this HATS is on, the data read from the RAM 62 is demodulated and output as linear PCM data (PCM2), which is output as a PCM selector. 69.
Also, when the HATS function is turned on and SACD playback data is received by the IEEE 1394 interface 61, the data is once written in the RAM 62 and then based on the crystal clock from the clock oscillator 64. Read out. In this case, the read DSD signal TD3 is supplied to the decimation filter 65, converted into linear PCM data (PCM3) by the decimation filter 65, and supplied to the PCM selector 69.

The tuner unit 77 is provided in the STR 60 and performs channel selection, demodulation processing, and the like on radio broadcast waves received by the antenna 76 and outputs them to the selector 79 as an analog audio signal, for example.
An analog audio signal input via the analog audio signal input terminal 78 is also input to the selector 79.

  In the selector 79, for example, according to control of the system controller 70, either the tuner unit 77 or the analog audio signal input terminal 78 is selected as an input source, and the selected analog audio signal is sent to the A / D converter 68. Supply. The A / D converter 68 converts the input analog audio signal into linear PCM data (PCM4) and supplies it to the PCM selector 69.

The PCM selector 69 selects each linear PCM data shown as PCM1, PCM2, PCM3, PCM4 under the control of the system controller 70. That is, the selection is to switch the input function.
The linear PCM data selected by the PCM selector 69 is supplied to the audio decoder 80.
The audio decoder 80 is formed by a DSP (Digital Signal Processor), and performs various necessary signal processing and speaker channel separation on audio data.
Further, the output of the audio decoder 80 is subjected to equalizing processing and other sound field processing in a stream processor. The audio data of, for example, 5 channels subjected to the required signal processing is converted into an analog audio signal by the D / A converter 82 and amplified by the power amplifier unit 83.
The audio signal processed by the power amplifier unit 83 is supplied to the speaker unit SP connected to the speaker connection terminal 84 in the STR 80 and output as audio. The speaker unit SP corresponds to the speakers SP (FL), SP (FR), SP (SL), SP (SR), and SP (C) shown in FIG. Are provided corresponding to each speaker.
The output of the power amplifier unit 83 is also supplied to the headphone jack 86, so that headphone output is possible.

By the way, when the audio data input to the STR 60 is output to an external device via the IEEE 1394 bus 116, the data output from the audio decoder 80 is supplied to the IEEE 1394 interface 61 via the selector 85. Alternatively, the output of the demodulation processing unit 66 is supplied to the IEEE 1394 interface 61 via the selector 85.
In this case, the data supplied to the IEEE 1394 interface 61 is in a form in which modulation processing conforming to the format of a digital audio data interface such as IEC60958 is performed.
The IEEE 1394 interface 61 performs necessary processing such as packetization on the supplied data using, for example, the RAM 62, and converts the data into a format compatible with the IEEE 1394 format. Then, transmission output is performed to the target device via the IEEE 1394 bus 116.

The system controller 70 includes, for example, a CPU (Central Processing Unit), ROM, RAM, flash memory, and the like, and executes various operation controls for the entire STR 60.
The system controller 70 performs control corresponding to user operation and display output to the user as user interface control. That is, information from the receiving unit 89 and the operation unit 88 is input to the system controller 70. For example, the reception unit 89 receives a wireless command signal transmitted from the remote controller RM, and the received command signal is supplied to the system controller 70.
The operation unit 88 includes various keys provided on the front panel as shown in FIG. 2, for example, and operation information corresponding to the operation performed on the operation unit 88 is supplied to the system controller 70. .
The system controller 70 executes various control processes so as to obtain a required operation in response to the command signal and operation information input as described above.
In addition, the system controller 70 performs display control on the display unit 87 so that, for example, the above-described command signal and operation information, and the required contents according to the current operation status are displayed. As described above, the display unit 87 includes, for example, an FL tube display unit 87A and a segment display unit 87B.
The system controller 70 controls the IEEE 1394 interface 61 and controls the communication operation by the IEEE 1394 bus 116.
For example, the IEEE 1394 interface 61 receives data such as a command and response transmitted from an external device, or transmits a command and response to the external device. Necessary processing is also executed for response transmission / reception processing.
The system controller 70 also performs initial processing, formatting processing, and the like for the NV-RAM 74 described later.

The program memory 73 stores a program for the system controller 70 to realize various operation controls in the STR 60.
In addition, a program for initial processing for NV-RAM 74, which will be described later when the power is turned on, and for formatting processing for initializing NV-RAM 74 at the time of factory shipment are also stored.

Since the NV-RAM (nonvolatile memory) 74 is a storage area that can hold data even when the power is turned off, various set control constants, SRM data to be described later, and the like are stored.
The program memory 73 and the NV-RAM 74 may be formed as a storage area inside the chip as the system controller 70, or may be separate chips.

1-5 STR compatible disk drive (internal)
Next, the internal configuration of the STR compatible disk drive 30 will be described with reference to the block diagram of FIG.
A disc 91 such as a CD, SACD, or DVD is inserted into the reproducible position by being inserted from the disc insertion / removal unit 159 of the main body front panel.
The disk 91 loaded in the reproducible position is rotationally driven by the spindle motor 31 at a constant linear velocity (CLV) during the CD reproducing operation. Then, the data recorded in the pit form (emboss pit, phase change pit, dye change pit, etc.) on the disk 91 is read by the optical head 32 and supplied to the RF amplifier 35. In the optical head 32, the objective lens 32a is held by a biaxial mechanism 32b and can be displaced in the tracking and focusing directions.
The optical head 32 can be moved in the radial direction of the disk 91 by the thread mechanism 34.

In addition to the reproduction RF signal, the RF amplifier 35 generates a focus error signal and a tracking error signal, and these error signals are supplied to the servo circuit 36.
The servo circuit 36 generates various drive signals such as a focus drive signal, a tracking drive signal, and a thread drive signal from the focus error signal and the tracking error signal, and controls the operations of the biaxial mechanism 32b and the thread mechanism 34. That is, focus servo control and tracking servo control are executed.
The reproduced RF signal binarized by the RF amplifier 35 is also output to the timing generator 40. The timing generator 40 generates a timing signal based on the waveform timing of the reproduced RF signal. To the CLV processor 41. The CLV processor 41 generates a drive signal for controlling the rotation of the spindle motor 31 at a required CLV speed based on the input timing signal, and supplies the drive signal to the spindle motor. Thus, spindle servo control for rotating the disk 91 by CLV is executed.
Further, the system controller 50 controls the servo circuit 36 and the timing generator 40 so as to perform necessary processing such as spindle start / stop, servo settling, track jump, access, and the like.

The reproduction RF signal is supplied to the DSD decoder 37 and the AV decoder 38.
It is controlled by the system controller 50 so that the AV decoder 38 functions during playback of CDs and DVDs, and so that the DSD decoder 37 functions during playback of SACDs.
The AV decoder 38 performs EFM demodulation, error correction decoding, descrambling, and the like on a reproduction signal (EFM signal) reproduced from the CD and binarized. Also, EFM + demodulation, error correction decoding, descrambling, etc. are performed on the reproduced signal (EFM + modulated signal) reproduced from the DVD.
Thus, for example, audio data in a format of 16-bit quantization and 44.1 kHz sampling is decoded and supplied to the IEEE 1394 interface 39.
The AV decoder 38 also has a function as a video decoder, and also decodes a video signal during DVD reproduction. The decoded video signal is supplied from a video output terminal 53 to a video monitor device (not shown) and output as a video.

The DSD decoder 37 decodes the DSD signal from the reproduction signal reproduced from the SACD and binarized. The DSD signal is supplied to the IEEE 1394 interface 39.
Note that the SACD has a two-layer recording surface, and one layer records DSD data and the other layer records CD data. When a layer in which CD format data is recorded is reproduced, the decoding process is performed in the AV decoder 38.

Further, the AV decoder 38 and the DSD decoder 37 adopt a configuration capable of extracting control data such as a subcode.
For example, TOC (Table Of Contents) information recorded in, for example, a subcode form in the lead-in area of the disk 91 is also extracted. These subcode data and TOC are supplied to the system controller 50 and used for various controls, for example.

The reproduced RF signal binarized by the RF amplifier 35 is also supplied to the PLL circuit 55.
The PLL circuit 55 outputs a clock synchronized with the channel bit of the input EFM signal. This clock is used as a clock of a signal processing circuit system after the DSD decoder 37 and the AV decoder 38, for example.

The audio data decoded and input to the IEEE 1394 interface 39 is converted into data conforming to the IEEE 1394 format, and transmitted to an external device via the IEEE 1394 bus 116.
Note that the data is encrypted when the DSD data is transmitted and output.
Although not shown, a digital interface and an optical digital output terminal may be provided so that audio data output from the AV decoder 38 or the DSD decoder 37 is output as digital data.
Further, a D / A converter and an analog output terminal may be provided to convert the decoded audio data into an analog audio signal and output it to an external device.

The system controller 50 is a microcomputer including a CPU, a RAM, a ROM, and the like, and controls various operations described above.
When reproducing the disk 91, it is necessary to read out the management information recorded on the disk 91, that is, the TOC. The system controller 50 discriminates the number of tracks recorded on the disk 91, the address of each track, etc. according to this management information, and controls the reproduction operation. For this reason, when the disk 91 is loaded, the system controller 50 reads out by executing the reproducing operation on the innermost circumference (lead-in area) of the disk on which the TOC is recorded, and extracts the TOC information as described above. . The TOC is stored in, for example, an internal RAM so that it can be referred to in the reproduction operation for the disk 91 thereafter.

Further, the system controller 50 performs control corresponding to user operations and display output to the user. That is, information from the receiving unit 45 and the operation unit 48 is input to the system controller 50. For example, the receiving unit 45 receives a wireless command signal transmitted from the remote controller RM, and the received command signal is supplied to the system controller 50.
The operation unit 48 includes various keys provided on the front panel as shown in FIG. 3, for example, and operation information corresponding to the operation performed on the operation unit 48 is supplied to the system controller 50. .
The system controller 50 executes various control processes so as to obtain a required operation in response to the command signal and the operation information input as described above.
In addition, the system controller 50 performs display control on the display unit 47 so that, for example, the above-described command signal and operation information, and the required contents according to the current operation status are displayed.
For example, the display unit 47 displays various information such as time information such as the total playing time of the disc, progress time during playback and recording, name information such as track number, disc name and track name, operation status, and operation mode. It is.
As described above, the display unit 47 includes, for example, an FL tube display unit 47A and a segment display unit 47B.
In addition, the system controller 50 controls the IEEE 1394 interface 61 and controls the communication operation by the IEEE 1394 bus 116.
For example, the IEEE 1394 interface 39 receives data such as a command and a response transmitted from an external device, or transmits a command and a response to the external device. Necessary processing is also executed for the transmission / reception processing.
The system controller 50 also performs initial processing, formatting processing, and the like for the NV-RAM 43 described later.

The program memory 44 stores a program for the system controller 50 to implement various operation controls in the STR compatible disk drive 30.
In addition, an initial processing for the NV-RAM 43 executed when the power is turned on, which will be described later, and a format processing program for initializing the NV-RAM 43 at the time of factory shipment are also stored.

Since the NV-RAM (nonvolatile memory) 43 is a storage area that can hold data even when the power is turned off, various set control constants, SRM data to be described later, and the like are stored.
The NV-RAM 43 and the program memory 44 may be formed as a storage area inside the chip as the system controller 50, or may be separate chips.

2. Data Communication According to IEEE 1394 According to this Embodiment 2-1 Outline Hereinafter, data communication according to the IEEE 1394 standard as this embodiment will be described.

IEEE 1394 is one of serial data communication standards.
As a data transmission method according to IEEE 1394, there are an isochronous communication method in which communication is performed periodically and an asynchronous communication method in which communication is performed asynchronously regardless of this cycle. In general, the Isochronous communication method is used for data transmission / reception, and the Asynchronous communication method is used for transmission / reception of various control commands. A single cable can be used to perform transmission and reception by these two types of communication methods.
Therefore, hereinafter, the description will be made on the premise of the transmission mode of the present embodiment according to the above-described IEEE 1394 standard.

2-2 Stack Model FIG. 6 shows an IEEE 1394 stack model to which the present embodiment corresponds.
The IEEE 1394 format is roughly divided into an Asynchronous system (400) and an Isochronous system (500).
Here, as a layer common to the Asynchronous system (400) and the Isochronous system (500), the Physical Layer (301) (physical layer) is provided in the lowest layer, and the Link Layer (302) (link layer) is provided in the upper layer. It is done. The Physical Layer (301) is a layer for managing hardware-like signal transmission, and the Link Layer (302) is a layer having a function for converting the IEEE 1394 bus into, for example, an internal bus defined for each device. The

The Physical Layer (301), the Link Layer (302), and the Transaction Layer (401) described below are linked to the Serial Bus Management 303 by the Event / Control / Configuration line.
AV Cable / Connector 304 indicates a physical connector and cable for AV data transmission.

  A transaction layer (401) is provided above the link layer (302) in the asynchronous system (400). The Transaction Layer (401) is a layer that prescribes a data transmission protocol as IEEE 1394. As basic asynchronous transactions, a write transaction, a read transaction, and a lock transaction are defined as described later.

  And FCP (Function Control Protocol) (402) is prescribed | regulated with respect to the upper layer of Transaction Layer (401). The FCP (402) can execute command control for various AV devices by using a control command defined as an AV / C Command (AV / C Digital Interface Command Set) (403). Yes.

  Further, for the upper layer of the transaction layer (401), a plug control register (404) for setting a plug (logical device connection relationship in IEEE 1394) to be described later using the connection management procedure (505). It is prescribed.

  In the upper layer of the Link Layer (302) in the Isochronous system (500), the CIP Header Format (501) is defined, and is managed by the CIP Header Format (501). The SD-DVCR Realtime Transmission (502), HD Transmission protocol such as DVCR Realtime Transmission (503), SDL-DVCR Realtime Transmission (504), MPEG2-TS Realtime Transmission (505), Audio and Music Realtime Transmission (506), etc.

SD-DVCR Realtime Transmission (502), HD-DVCR Realtime Transmission (503), and SDL-DVCR Realtime Transmission (504) are data transmission protocols corresponding to digital VTR (Video Tape Recorder), respectively.
Data handled by the SD-DVCR Realtime Transmission (502) is a data sequence (SD-DVCR data sequence (507)) obtained in accordance with the provisions of the SD-DVCR recording format (508).
The data handled by the HD-DVCR Realtime Transmission (503) is a data sequence (SD-DVCR data sequence (509)) obtained in accordance with the definition of the HD-DVCR recording format (510).
Data handled by the SDL-DVCR Realtime Transmission (504) is a data sequence (SD-DVCR data sequence (511)) obtained in accordance with the provisions of the SDL-DVCR recording format (512).

  MPEG2-TS Realtime Transmission (505) is a transmission protocol corresponding to, for example, a tuner corresponding to digital satellite broadcasting, and the data handled by this is data obtained in accordance with the provisions of DVB recording format (514) or ATV recording format (515). A sequence (MPEG2-TS data sequence (513)) is used.

  Also, Audio and Music Realtime Transmission (506) is a transmission protocol corresponding to all digital audio devices including the MD system of this embodiment, for example, and the data handled by this is in accordance with the provisions of Audio and Music recording format (517). The obtained data sequence (Audio and Music data sequence) is used.

2-3 Signal Transmission Mode FIG. 7 shows an example of the structure of a cable that is actually used as an IEEE 1394 bus.
In this figure, connectors 600A and 600B are connected via a cable 601, and here, a case where 6 pins of pin numbers 1 to 6 are used as pin terminals of connectors 600A and 600B is shown. .
For each pin terminal provided on the connectors 600A and 600B, pin number 1 is power (VP), pin number 2 is ground (VG), pin number 3 is TPB1, pin number 4 is TPB2, pin number 5 is TPA1, pin Number 5 is TPA2.
And the connection form of each pin between the connectors 600A-600B is:
Pin number 1 (VP)-Pin number 1 (VP)
Pin number 2 (VG)-Pin number 2 (VG)
Pin number 3 (TPB1)-Pin number 5 (TPA1)
Pin number 4 (TPB2)-Pin number 6 (TPA2)
Pin number 5 (TPA1)-Pin number 3 (TPB1)
Pin number 6 (TPA2)-Pin number 3 (TPB2)
It is like this. And, among the set of pin connections,
Pin number 3 (TPB1)-Pin number 5 (TPA1)
Pin number 4 (TPB2)-Pin number 6 (TPA2)
A signal line 601A for mutually transmitting signals differentially is formed by a set of two twisted wires,
Pin number 5 (TPA1)-Pin number 3 (TPB1)
Pin number 6 (TPA2)-Pin number 3 (TPB2)
A signal line 601B for mutually transmitting signals differentially is formed by a set of two twisted lines.

The signals transmitted through the two sets of signal lines 601A and 601B are a data signal (Data) shown in FIG. 8A and a strobe signal (Strobe) shown in FIG. 8B.
The data signal shown in FIG. 8A is output from the TPBs 1 and 2 using one of the signal line 601A and the signal line 601B and input to the TPAs 1 and 2.
The strobe signal shown in FIG. 8B is a signal obtained by performing a predetermined logical operation on the data signal and the transmission clock synchronized with the data signal, and has a frequency lower than that of the actual transmission clock. Have. The strobe signal is output from the TPA 1 and 2 using the other signal line not used for data signal transmission out of the signal line 601A or the signal line 601B, and is input to the TPB 1 and 2.

For example, if the data signal and the strobe signal shown in FIGS. 8A and 8B are input to a certain IEEE 1394 compatible device, the input data signal and the strobe signal are A predetermined logical operation is performed on the signal to generate a transmission clock (Clock) as shown in FIG. 8C, which is used for required input data signal processing.
In the IEEE 1394 format, by adopting such a hardware data transmission form, it is not necessary to transmit a transmission clock with a high-speed cycle between devices by a cable, and the reliability of signal transmission is improved.
In the above description, the specification of 6 pins is described. However, in the IEEE 1394 format, the power supply (VP) and the ground (VG) are omitted, and the 4 pins consisting of only two signal lines 601A and 601B, which are twisted lines. There is also a specification. For example, in the MD recorder / player 1 of the present embodiment, in practice, consideration is given to the provision of a simpler system for the user by using this 4-pin cable.

2-4 Bus Connection Between Devices FIG. 9 schematically shows an example of a connection between devices using the IEEE 1394 bus. This figure shows a case where five devices (Node), devices A, B, C, D, and E, are connected by an IEEE 1394 bus (that is, a cable) so that they can communicate with each other.
The IEEE 1394 interface enables so-called “daisy chain connection” in which the devices are connected in series by the IEEE 1394 bus like the devices A, B, and C. In the case of FIG. 9, as shown in the connection form between the device A and the devices B, D, and E, so-called “branch connection” in which a certain device and a plurality of devices are connected in parallel is also possible. It is said.
As a whole system, a maximum of 63 devices (Nodes) can be connected by using this branch connection and the above daisy chain connection together. However, up to 16 units (16 pops) can be connected depending on the daisy chain connection. In addition, the terminator required for SCSI is not required for the IEEE1394 interface.
In the IEEE 1394 interface, it is possible to perform mutual communication between devices connected by daisy chain connection or branch connection as described above. That is, in the case of FIG. 9, mutual communication between any plural devices among the devices A, B, C, D, and E is possible.

Further, in a system in which a plurality of devices are connected via the IEEE 1394 bus (hereinafter also referred to as an IEEE 1394 system), a process for setting a Node ID assigned to each device is actually performed. This process is schematically shown in FIG.
Here, in the IEEE 1394 system according to the connection form shown in FIG. 10A, it is assumed that there are plugging / unplugging of a cable, power on / off of a certain device in the system, spontaneous generation processing in PHY (Physical Layer Protocol), and the like. In the IEEE 1394 system, a bus reset occurs. As a result, processing for notifying all devices via the IEEE 1394 bus between the devices A, B, C, D, and E is executed.

  As a result of this bus reset notification, a parent-child relationship is defined between adjacent device terminals by performing communication (Child-Notify) as shown in FIG. That is, a tree structure between devices in the IEEE 1394 system is constructed. Then, a device as a route is defined according to the construction result of the tree structure. A route is a device in which all terminals are defined as children (Ch; Child). In the case of FIG. 10B, device B is defined as a route. In other words, for example, the terminal of the device A connected to the device B as the route is defined as a parent (P; Parent).

  When the tree structure and route in the IEEE 1394 system are defined as described above, then, as shown in FIG. 10 (c), each device receives a Self-ID packet as a declaration of its own Node-ID. Is output. The route sequentially grants the Node-ID, whereby the address of each device in the IEEE 1394 system, that is, the Node-ID is determined.

2-5 Packet In the IEEE 1394 format, transmission is performed by repeating the cycle of Isochronous cycle (nominal cycle) as shown in FIG. In this case, 1 Isochronous cycle is set to 125 μsec, and the band corresponds to 100 MHz. It is specified that the period of Isochronous cycle may be other than 125 μsec. Then, data is packetized for each Isochronous cycle and transmitted.

As shown in this figure, a cycle start packet indicating the start of one isochronous cycle is arranged at the head of the isochronous cycle.
Although the detailed description here is omitted, the generation timing of this cycle start packet is instructed by one specific device in the IEEE 1394 system defined as the cycle master.
Following the cycle start packet, an isochronous packet is preferentially arranged. As shown in the figure, the Isochronous Packet is packetized for each channel and then arranged and transferred in a time-sharing manner (Isochronous subactions). In addition, a pause interval (for example, 0.05 μsec) called an isochronous gap is provided at the delimiter for each packet in the isochronous sub-actions.
As described above, in the IEEE 1394 system, it is possible to transmit and receive isochronous data in multiple channels through one transmission line.

Here, for example, when it is considered that compressed audio data (hereinafter also referred to as ATRAC data) supported by the MD recorder / player of the present embodiment is transmitted by the isochronous method, the ATRAC data is transferred at a single rate of 1.4 Mbps. Assuming that at least about 20 bytes of ATRAC data is transmitted as an isochronous packet every 1 isochronous cycle period of 125 μsec, time-series continuity (real-time property) is ensured.
For example, when a certain device transmits ATRAC data, detailed explanation here is omitted, but Isochronous is sufficient to ensure real-time transmission of ATRAC data to an IRM (Isochronous Resource Manager) in the IEEE 1394 system. Request packet size. In the IRM, the current data transmission status is monitored to give permission / non-permission, and if permission is granted, ATRAC data can be packetized and transmitted to an isochronous packet by a designated channel. This is called bandwidth reservation in the IEEE 1394 interface.

Asynchronous sub-actions, that is, Asynchronous packet transmission, is performed using the remaining band that is not used by Isochronous sub-actions within the band of Isochronous cycle.
FIG. 11 shows an example in which two Asynchronous Packets of Packet A and Packet B are transmitted. The Asynchronous Packet is accompanied by a signal called ACK (Acknowledge) with a pause period of ack gap (0.05 μsec). As will be described later, ACK is a signal output from the receiving side (Target) in hardware in order to notify the transmitting side (Controller) that there has been reception of any Asynchronous data in the Asynchronous Transaction process. is there.
In addition, before and after the data transmission unit including Asynchronous Packet and subsequent ACK, there is provided a pause period called “substitution gap” of about 10 μsec.
Here, if the ATRAC data is transmitted by the Isochronous Packet and the AUX data file that is attached to the ATRAC data is transmitted by the Asynchronous Packet, it is possible to transmit the ATRAC data and the AUX data file at the same time. It is possible.

2-6 Transaction Rule The process transition diagram in FIG. 12A shows basic communication rules (transaction rules) in asynchronous communication. This transaction rule is defined by the FCP.
As shown in FIG. 12A, first, in step S11, the Requester (transmission side) transmits a Request to the Responder (reception side). When the responder receives the request (step S12), the responder first returns an acknowledge to the requester (step S13). The transmission side recognizes that the Request is received by receiving the Acknowledge (step S14).
Thereafter, the responder transmits a response to the requester as a response to the request received in the previous step S12 (step S15). In the requester, the response is received (step S16), and in response to this, an acknowledge is transmitted to the responder (step S17). The responder recognizes that the response has been received on the transmission side by receiving the acknowledgement.

As shown in the left side of FIG. 12B, the Request Transaction transmitted according to FIG. 12A is broadly defined as three types: Write Request, Read Request, and Lock Request.
Write Request is a command for requesting data writing, and Read Request is a command for requesting reading of data. The Lock Request is a command for a swap compare, a mask, etc., although a detailed description is omitted here.

  Further, three types of Write Request are further defined according to the data size of a command (operand) stored in an Asynchronous Packet (AV / C Command Packet) described later. Write Request (data quadlet) transmits a command only by the header size of Asynchronous Packet. Write Request (data block: data length = 4 bytes), Write Request (data length: data length ≠ 4 bytes) are sent with a data block as an asynchronous packet, and a data block is sent with the data block as an asynchronous packet. The data size of the operand stored in is different from 4 bytes or more.

  Similarly, Read Request (Read quad (data block: data length) = Read byte (data block): Read request (data quad :), Read bit (data bit: data bit), Read request (data bit: data byte = 4 bytes), Read request (data quad: data length: 4 bytes). Are defined.

Further, the Response Transaction is shown on the right side of FIG.
For the three types of Write Requests described above, Write Response or No Response is defined.
Also, Read Response (data quadlet) is defined for Read Request (data quadlet), and Read Request (data block: data length = 4 bytes), or Read Request (data block: data 4) , Read Response (data block) is defined.

  A Lock Response is defined for the Lock Request.

2-7 Addressing FIG. 13 shows the addressing structure of the IEEE1394 bus.
As shown in FIG. 13A, in the IEEE 1394 format, 64 bits are prepared as a register (address space) for a bus address.
The upper 10-bit area of this register indicates a bus ID for identifying the IEEE 1394 bus. As shown in FIG. 13B, a total of 1023 bus IDs of bus # 0 to # 1022 can be set as the bus ID. It is said. The bus # 1023 is defined as a local bus.

In FIG. 13A, a 6-bit area following the bus address indicates a Node ID of a device connected to each IEEE 1394 bus indicated by the bus ID. As shown in FIG. 13C, the Node IDs can identify 63 Node IDs from Node # 0 to Node # 62.
The 16-bit area indicating the bus ID and Node ID corresponds to the destination ID in the header of the AV / C Command Packet, which will be described later. It is specified on the IEEE 1394 system.

In FIG. 13A, the 20-bit area following the Node ID is a register space, and the 28-bit area following the register space is a register address.
The value of register space is [F FF FFh] at the maximum, indicating the register shown in FIG. 13 (d), and the contents of this register are defined as shown in FIG. 13 (e). The register address specifies the address of the register shown in FIG.

Briefly, by referring to the Serial Bus-dependent Registers starting from, for example, the address 512 [0 00 02 00h] in the register shown in FIG. .
In addition, the configuration ROM starting from the address 1024 [0 00 04 00h] stores necessary information related to the node such as the node unique ID and the subunit ID.
These Node Unique ID and subunit ID are required when establishing the connection when the device is actually connected to the IEEE 1394 bus.

  The Node Unique ID is unique to each device and is device information represented by 8 bytes. There is no other device having the same Node Unique ID even if the same model is used. .

  The unit ID is formed with information such as Vender Name (module_vender_ID) indicating the name of the manufacturer of the device as the Node and Model Name (model_ID) indicating the model name of the device as the Node.

The Node Unique ID is unique to each device and is device identification information expressed by 8 bytes. It is assumed that there is no device having the same Node Unique ID even between the same models.
Vender Name is information indicating the manufacturer name of the Node, and Model Name is information indicating the model of the Node. Therefore, there are devices that have these Vender Name and Model Name in common.
Therefore, by referring to the contents of the Configuration ROM, the Node Unique ID attached to the model can be identified, and the manufacturer and model of the Node are identified from the contents of the subunit ID. It becomes possible. The Node Unique ID is indispensable, while the Vender Name and Model Name are optional and are not necessarily set for the device.

2-8 CIP (Common Isochronos Packet)
FIG. 14 shows the structure of CIP (Common Isochronos Packet). That is, the data structure of the Isochronous Packet shown in FIG.
As described above, ATRAC data (audio data), which is one of the recording / playback data supported by the MD recorder / player of the present embodiment, is transmitted / received by isochronous communication in IEEE 1394 communication. . That is, the amount of data that can maintain the real-time property is stored in this Isochronous Packet, and is sequentially transmitted every 1 Isochronous cycle.

The first 32 bits (1 quadlet) of the CIP are a 1394 packet header.
In the 1394 packet header, the 16-bit area from the top is data_Length, the subsequent 2-bit area is tag, the subsequent 6-bit area is channel, the subsequent 4 bits are tcode, and the subsequent 4 bits are sy.
A header_CRC is stored in the 1 quadlet area following the 1394 packet header.

The 2 quadlet area following header_CRC is the CIP header.
In the upper 2 bits of the upper quadlet of the CIP header, “0” and “0” are stored, respectively, and the subsequent 6-bit area indicates the SID (transmission node number). The 8-bit area following the SID is DBS (data block size), and indicates the size of the data block (packetization unit data amount). Subsequently, areas of FN (2 bits) and QPC (3 bits) are set, FN indicates the number of divisions when packetized, and QPC indicates the number of quadlets added for division. Indicated.
The flag of the header of the source packet is shown in SPH (1 bit), and the value of the counter that detects the loss of the packet is stored in DBC.

In the upper 2 bits of the lower quadlet of the CIP header, “0” and “0” are stored. Following this, areas of FMT (6 bits) and FDF (24 bits) are provided. A signal format (transmission format) is indicated in the FMT, and a data type (data format) stored in the CIP can be identified by a value shown here. Specifically, MPEG stream data, Audio stream data, digital video camera (DV) stream data, etc. can be identified. The data format indicated by this FMT is, for example, SD-DVCR Realtime Transmission (502), HD-DVCR Realtime Transmission (503), SDL-DVCR Realtime Transmission managed by CIP Header Format (401) shown in FIG. (504), MPEG2-TS Realtime Transmission (505), and Audio and Music Realtime Transmission (506).
The FDF is a format-dependent field, and is an area indicating a further subdivided classification for the data format classified by the FMT. If it is data relating to audio, it is possible to identify whether it is linear audio data or MIDI data, for example.
For example, in the case of ATRAC data according to the present embodiment, FMT first indicates that the data is in the category of audio stream data, and a specific value in accordance with the FDF is stored, so that the audio stream data is stored. Is ATRAC data.

  Here, for example, when FMT indicates MPEG, synchronization control information called TSF (time shift flag) is stored in FDF. Further, when the FMT indicates that it is a DVCR (digital video camera), the FDF is defined as shown in the lower part of FIG. Here, in order from the top, 50/60 (1 bit) defines the number of fields per second, TYPE (5 bits) indicates whether the video format is SD or HD, and SYT A time stamp for synchronization is shown.

Following the CIP header, data indicated by FMT and FDF is stored in a sequence of n data blocks. When the FMT and FDF indicate that the data is ATRAC data, the ATRAC data is stored in the area as the data block.
Then, after the data block, data_CRC is arranged at the end.

2-9 Connection Management In the IEEE 1394 format, the connection relationship between devices connected by the IEEE 1394 bus is defined by a logical connection concept called “plug”.
FIG. 15 shows an example of connection relationships defined by plugs. In this case, VTR1, VTR2, a set top box (STB; digital satellite broadcast tuner), a monitor device (Monitor), an IEEE 1394 bus, In addition, a system configuration in which a digital still camera (Camera) is connected is shown.

Here, there are two forms of connection using IEEE 1394 plugs: point to point-connection and broadcast connection.
The point to point-connection is a connection form in which the relationship between the transmission device and the reception device is specified, and data transmission is performed between the transmission device and the reception device using a specific channel.
On the other hand, the broadcast connection is a transmission device that performs transmission without specifying a receiving device and a use channel. The receiver side performs reception without identifying the transmitting device, and if necessary, performs necessary processing according to the content of the transmitted data.
In the case of FIG. 15, as a point-to-point-connection, the STB is transmitted, the VTR1 is received, and data is transmitted using the channel # 1, and a digital still camera. Shows a state in which the transmission is performed and the VTR 2 is received and the data transmission is performed using the channel # 2.
Also, the digital still camera shows a state in which data transmission is set also by broadcast connection. Here, the monitor device receives the data transmitted by the broadcast connection and a required response is received. The case where processing is performed is shown.

The connection form (plug) as described above is established by a PCR (Plug Control Register) provided in the address space of each device.
16A shows the structure of oPCR [n] (output plug control register), and FIG. 16B shows the structure of iPCR [n] (input plug control register). The sizes of these oPCR [n] and iPCR [n] are both 32 bits.
In the oPCR of FIG. 16A, for example, if “1” is stored for the on-line of the upper 1 bit, it indicates that the plug is online capable of transmitting isochronous data, and continues. If '1' is stored in the broadcast connection counter (1 bit), it is indicated that the transmission is based on the broadcast connection. The subsequent point to point connection counter (6 bits) indicates the number of point to point connections applied to the plug. Then, it is indicated that transmission is performed through a channel indicated by a channel number in a 6-bit area from the upper 11th bit.
Also, in the iPCR of FIG. 16B, for example, if “1” is stored for the on-line of the upper 1 bit, it is indicated that the plug is online capable of receiving isochronous data. When “1” is stored in the subsequent broadcast connection counter (1 bit), it is indicated that the transmission is based on the broadcast connection. In the subsequent point to point connection counter (6 bits), the number of point to point connections attached to the plug is indicated, and transmitted by a channel indicated by the channel number in the 6-bit area from the upper 11 bits. Is shown to do.

The broadcast connection counter in the oPCR in FIG. 16A and the iPCR in FIG. 16B stores the number of nodes that have a broadcast connection in the case of transmission / reception by the broadcast connection.
In addition, in the point to point connection counter in the oPCR in FIG. 16A and the iPCR in FIG. 16B, the number of nodes that have point to point in the case of transmission / reception by the point to point connection. Is shown.

2-10 Command and Response in FCP Data transmission by asynchronous communication is defined by the FCP (402) shown in FIG. Therefore, here, a transaction defined by FCP will be described.

As the FCP, Write Transaction (see FIG. 12) defined in Asynchronous communication is used. Therefore, transmission of AUX data in this embodiment is also performed by using Write Transaction in Asynchronous communication by this FCP.
A device that supports FCP includes a Command / Response register, and implements a transaction by writing a Message to the Command / Response register as described with reference to FIG.

  In the process transition diagram of FIG. 17, as shown in step S <b> 21, first, as a process for COMMAND transmission, the controller generates a transaction request and transmits a write request packet to the target. In step S22, the target receives this write request packet and writes data to the command / response register. At this time, the Target transmits Acknowledge to the Controller, and the Controller receives the Acknowledge (S23 → S24). A series of processes so far is a process corresponding to transmission of COMMAND.

Subsequently, as a process for RESPONSE in response to COMMAND, a write request packet is transmitted from the target (S25). The controller receives this, and writes data to the Command / Response register (S26). In addition, the Controller transmits Acknowledge to the Target in response to the reception of the Write Request Packet (S27). By receiving this Acknowledge, the Target knows that the Write Request Packet has been received by the Controller (S28).
That is, the COMMAND transmission processing from the controller to the target and the RESPONSE transmission processing from the target to the controller in response to this are the basics of data transmission (transaction) by FCP.

2-11 AV / C Command Packet As described with reference to FIG. 6, in the asynchronous communication, the FCP can communicate with various AV devices using the AV / C command.
In Asynchronous communication, three types of transactions, Write, Read, and Lock, are defined as described with reference to FIG. 12, and in actuality, Write Request / Response Packet and Read Request / Response according to each transaction. Packet, Lock Request / Response Packet is used. And in FCP, as mentioned above, Write Transaction is used.
Accordingly, FIG. 18 shows a format of a write request packet (Asynchronous Packet (Write Request for Data Block)). In the present embodiment, this Write Request Packet is used as an AV / C command packet.

The upper 5 quadlet (first to fifth quadlet) in the write request packet is set as a packet header.
The upper 16-bit area in the first quadlet of the packet header is destination_ID, which indicates the Node ID of the data transfer destination (destination). The subsequent 6-bit area is tl (transact label) and indicates a packet number. The subsequent 2 bits are rt (retry code), which indicates whether the packet is transmitted for the first time or retransmitted. In the subsequent 4-bit area, tcode (transaction code) indicates a command code. The subsequent 4-bit area is pri (priority) and indicates the priority of the packet.

The upper 16-bit area in the second quadlet is source_ID, which indicates Node_ID of the data transfer source.
In addition, the lower 16 bits in the second quadlet and the total 48 bits of the entire third quadlet are set to destination_offset, and indicate the addresses of the COMMAND register (FCP_COMMAND register) and the RESPONSE register (FCP_RESPONSE register).
The destination_ID and destination_offset correspond to a 64-bit address space defined in the IEEE 1394 format.

The upper 16-bit area of the fourth quadlet is data_length, and indicates the data size of datafield (area surrounded by a thick line in FIG. 18) to be described later.
The subsequent lower 16-bit area is an extended_tcode area and is an area used when extending tcode.

  A 32-bit area as the fifth quadlet is header_CRC, and stores a CRC calculation value for performing a checksum of the packet header.

A data block is arranged from the sixth quadlet following the packet header, and a data field is formed at the head in the data block.
A CTS (Command and Transaction Set) is described in the upper 4 bits of the sixth quadlet that is the head of datafield. This indicates the ID of the command set of the Write Request Packet. For example, if the value of this CTS is set to [0000] as shown in the figure, the contents described in the datafield are AV / C commands. Will be defined as being. That is, this Write Request Packet indicates that it is an AV / C command packet. Therefore, in this embodiment, since the FCP uses the AV / C command, [0000] is described in this CTS.

  In the 4-bit area following the CTS, a response indicating a ctype (Command type; command function classification) or a processing result (response) corresponding to the command is described.

FIG. 19 shows the definition contents of the above ctype and response.
[0000] to [0111] can be used as ctype (Command), [0000] is defined as CONTROL, [0001] is defined as STATUS, [0010] is defined as INQUIRY, and [0011] is defined as NOTIFY. ] To [0111] are currently undefined (reserved).
CONTROL is a command for controlling the function from the outside, STATUS is a command for checking the state from the outside, INQUIRY is a command for inquiring from the outside whether the control command is supported, and NOTIFY is a request for notifying the outside of the change of the state It is a command to do.
[1000] to [1111] are used as responses, [1000] is NOT IMPLEMENTED, [1001] is ACCEPTED, [1010] is REJECTED, [1011] is IN TRANSITION, and [1100] is IMPLEMENTED / STABLE, [1101] is defined as CHANGED, [1110] is reserved, and [1111] is defined as INTERIM.
These responses are properly used according to the type of command. For example, as a response corresponding to a CONTROL command, one of four of NOT IMPLEMENTED, ACCEPTED, REJECTED, or INTERIM is used depending on the situation on the responder side.

In FIG. 18, subunit-type is stored in a 5-bit area following ctype / response. “Subunit-type” indicates what the destination of COMMMAND or the source of RESPONSE is (device). In the IEEE 1394 format, the device itself is referred to as a unit, and the type of functional device unit provided in the unit (device) is referred to as a subunit. For example, taking a general VTR as an example, a unit as a VTR includes two subunits, a tuner that receives terrestrial waves and satellite broadcasts, and a video cassette recorder / player.
Subunit-type is defined, for example, as shown in FIG. That is, [00000] is a Monitor, [00001] to [00010] are reserved, [00011] is a Disc recorder / player, [00100] is a VCR, [00101] is a Tuner, [00111] is a Camera, [01000] to [01000]. 11110] is defined as reserved, and [11111] is defined as a unit used when no subunit exists.

  In FIG. 18, the 3 bits following the above-unit-type store an id (Node_ID) for specifying each subunit when there are a plurality of same-type subunits.

In the 8-bit area following id (Node_ID), opcode is stored, and in the subsequent 8-bit area, operand is stored.
The opcode is an operation code (Operation Code), and information (parameter) required by the opcode is stored in the operand. These opcodes are defined for each subunit, and have a table of a list of unique opcodes for each subunit. For example, if subunit is a VCR, various commands such as PLAY (playback) and RECORD (record) are defined as opcode as shown in FIG. 20B, for example. The operand is defined for each opcode.

As the datafield in FIG. 18, the 32 bits of the sixth quadlet are indispensable. If necessary, an operand can be added (Additional operands).
Following datafield, data_CRC is arranged. If necessary, padding can be arranged before data_CRC.

3. SRM
Next, SRM will be described. SRM is an abbreviation of System Renewability Messages. It is information for copyright protection used in devices that support FULL authentication with 5C-DTCP (Digital Transmission Content Protection) compatible devices (IEEE 1394, USB, MOST, etc.). is there. It also includes the contents of a so-called black list of devices that are not compatible with copyright protection.
The SRM is one piece of information used during authentication processing between devices (referred to during authentication processing).

The SRM data is issued to the approved electronic device by the SRM issuing organization 115 shown in FIG.
First, it is assumed that the devices A, B, and C shown in FIG. 21 are devices that are approved (licensed) by the SRM issuing organization 115 as appropriate 5C-DTCP compatible devices. The SRM issuing organization 115 issues an electronic signature DS (Device Certificate) indicating a license to the approved device. The devices A, B, and C store electronic signatures DS (a), DS (b), and DS (c) issued by the SRM issuing organization 115, respectively.

On the other hand, the SRM issuing organization 115 issues SRMs as needed. For example, an SRM is issued when a device inappropriate for copyright protection is discovered.
An example of the data content of the SRM data is shown in FIG.
As shown in FIG. 22, the SRM data is first provided with data of Type, Generation, and Version Number, and the type, generation, and version are indicated as the header of the SRM data.
Further, the CRL data length is recorded as the CRL length, and subsequently, the CRL is recorded as variable length data. The CRL is a “Certificate Revocation List”, that is, list information of electronic devices that have been revoked by the SRM issuing organization 115, that is, black list information.
In addition, an electronic signature (DTLA Signature) is recorded. This is an electronic signature in which the SRM issuing organization 115 proves the SRM data itself as valid data.

For example, it is assumed that there is no device currently listed as a CRL. That is, it is assumed that no SRM data has been issued. As shown in FIG. 21, it is assumed that the SRM issuing organization 115 approves licenses for the devices A, B, and C, respectively.
The SRM issuing organization 115 gives individual electronic signatures DS (a), DS (b), and DS (c) to the devices A, B, and C, respectively.
Each device A, B, C stores the assigned electronic signature DS (*) in the device.
In addition, since no SRM data has been issued, for example, in the SRM data format as shown in FIG.
This may be merely securing an area for SRM data, or only the header portion of the SRM data may be recorded.

  For convenience of explanation, it is assumed that the actual contents (CRL blacklist) do not exist, that is, the SRM data stored in each device at the time when effective SRM data has not yet been issued, This is referred to as 0.0 SRM data.

Thereafter, it is assumed that the device C is recognized as a device with insufficient copyright protection processing, and the SRM issuing organization 115 cancels the license for the device C. At this time, the SRM issuing organization 115 issues SRM data in which the electronic signature DS (c) assigned to the device C is listed in the CRL.
For the sake of explanation, this SRM data is assumed to be version 1.0 SRM data.
In this case, the devices A and B update the SRM data (version 0.0) stored by some method to the issued SRM data (version 1.0).
Of course, thereafter, the SRM issuing organization 115 issues SRM data such as versions 1.1, 1.2, 2.0... As necessary. Each of the electronic devices A, B,... Needs to update the SRM data each time.

In order to be able to perform updates and to achieve proper copyright protection with proper authentication, licensed equipment is required to:
1) After performing the authentication process between devices, when SRM data is received from the counterpart device, it is stored (updated) inside the device as necessary.
2) After performing the authentication process between the devices, the SRM data stored in the device is transmitted to the authentication counterpart device as necessary.
3) If it is determined that the authentication partner is described in the CRL of the SRM data inside the device during authentication, authentication is not performed thereafter (authentication processing is canceled and an authentication error occurs).

These are intended to provide a function to gently remove a product from the market when there is a product that is determined to have insufficient copyright protection in the future.
An example will be described with reference to FIG.
FIG. 23A shows the SRM issuance time and the device manufacturing time on the time axis.
In FIG. 23A, at a certain time, the SRM data is version 0.0, and this is a time when there is no device listed as a CRL. That is, it is a time when SRM data has not been issued yet.

  Thereafter, it is assumed that the device A is manufactured at a certain time, licensed by the SRM issuing organization 115, and the electronic signature DS (a) is given. In the device A, the electronic signature DS (a) is recorded as shown in FIG. 23B, and the held SRM data is version 0.0.

After that, it is assumed that the device C is manufactured at a certain time, licensed by the SRM issuing organization 115, and the electronic signature DS (c) is given. The electronic signature DS (c) is recorded in the device C as shown in FIG. The retained SRM data is version 0.0.
However, after that, the license of the device C is canceled, and the SRM issuing organization 115 issues version 1.0 SRM data in which the device C is listed in the CRL.

  If the device B is manufactured after the version 1.0 SRM data is issued and the version 1.0 SRM data has been transmitted to the manufacturer side by the time of manufacture, the device B receives the version 1.0 SRM data. It can be stored. For example, as shown in FIG. 23B, device B stores version 1.0 SRM data in which electronic signature DS (c) of device C is blacklisted as CRL.

  After such a situation, it is assumed that, as shown in FIG. 23B, the devices A and B are connected by the IEEE 1394 bus 116 and mutual authentication processing is performed when establishing communication. As described above, since the licensed device is obliged to transmit and receive authenticated SRM data, device B transmits version 1.0 SRM data to device A after authentication. The device A updates the stored SRM data because the transmitted version 1.0 SRM data is newer than the stored version 0.0 SRM data. As a result, the device A also stores the version 1.0 SRM data in which the electronic signature DS (c) of the device C is blacklisted as the CRL.

  Further, after that, at a certain point in time, as shown in FIG. 23C, it is assumed that the devices A and C are connected by the IEEE 1394 bus 116 to establish communication. However, since the device A is a device registered as CRL in the SRM data stored in the counterpart device C (DS (c)), the device A performs processing as an authentication error. That is, communication between the devices A and C is not established, and transmission of audio data or the like cannot be performed.

In this way, the device C for which the license has been revoked is regarded as an authentication error, thereby eliminating the device with insufficient copyright protection, thereby maintaining the copyright protection function.
In such a situation, it is understood that the SRM data needs to be updated (versioned up) as quickly as possible in each device in order to appropriately exclude inappropriate devices.
For this reason, as described above, SRM data is transmitted and received during authentication, and SRM data can be updated as necessary.

As a method for inputting a new version of SRM data in a user-side device, an electronic device and a personal computer are connected by an IEEE 1394 bus 116, an application is started on the personal computer side, and the SRM data is transmitted to the electronic device. There is a technique.
For example, if a personal computer can receive SRM data issued by network communication, or if the SRM data is provided by a CD-ROM or the like, the SRM data of the electronic device can be updated using the personal computer. Can do.

In a device that performs data transmission by IEEE 1394, such as the STR 60 and the STR compatible disk drive 30 in this example, authentication is performed in a connected state, and devices that are mutually valid (for example, devices that are licensed as having a correct copyright protection function). ). At this time, referring to the SRM data as described above, it is also confirmed whether or not the device is a valid license device.
In consideration of transmission of audio data from the STR compatible disk drive 30 to the STR 60, particularly, DSD data which is SACD reproduction data is encrypted and transmitted.
When transmitting the DSD data, the STR compatible disk drive 30 encrypts the DSD data, and transmits the packet data (isochronous packet) in which the encrypted data is distributed from the IEEE 1394 interface 39.
On the other hand, the STR 60 on the data receiving side receives the encryption key used by the STR compatible disk drive 30 when authentication with the STR compatible disk drive 30 is established.

4). NV-RAM Format Processing 4-1 Configuration of Initial Processing and Format Processing System In this example, in the STR compatible disk drive 30 and STR 60, the NV-RAM 43 and 74 are initialized each time the power is turned on. Processing is performed and necessary data update is performed.
On the other hand, when considering a process in a factory for manufacturing an electronic device, a program for initial processing is written in the device so that the device can perform initial processing. For example, the NV-RAM is activated when power is turned on. Execute initial processing for.
However, since NV-RAM at the time of manufacture is completely indefinite, there is no confirmation that the initial data can be in a correct data state.
Therefore, in this example, the NV-RAM data can be executed in the correct state and the process efficiency can be improved by enabling the NV-RAM format process to be executed as described later in the factory process.

Hereinafter, an example of the STR compatible disk drive 30 will be described.
FIG. 24 shows extracted blocks regarding the initial processing and formatting processing of the NV-RAM 43 in the STR compatible disk drive 30 shown in FIG.
That is, the system controller 50, the IEEE 1394 interface 39, the NV-RAM 43, the program memory 44, and the display unit 47 are shown.
A personal computer 250 shown in FIG. 24 is a personal computer as an apparatus in a factory, and functions as a program writing and format instruction apparatus here.
The personal computer 250 is an IEEE 1394 compatible device, and is connected to the STR compatible disk drive 30 via the IEEE 1394 bus 116.
It goes without saying that the NV-RAM 43 and the program memory 44 may be formed as storage areas inside the chip as the system controller 50.

4-2 Initial Processing In this example, the initial processing program and the format program are written in the program memory 44, so that the system controller 50 can perform initial processing and formatting processing on the NV-RAM 43. The initial process is, for example, a process performed every time the power is turned on, and particularly includes a process of updating predetermined data for the next power on. On the other hand, the formatting process is performed only once before shipment from the factory. In principle, the formatting process is not performed after shipment, for example, on the user side.

First, the initial process will be described.
FIG. 26 shows an initial process for the NV-RAM 43 in the STR compatible disk drive 30. For example, this is a process executed by the system controller 50 when the STR compatible disk drive 30 is turned on.
First, in step F <b> 101, the system controller 50 reads data from the NV-RAM 43. In this case, the read data is used for various processes executed in the current power-on state. For example, when authentication is performed with a connected device such as the STR 60 after the power is turned on, the SRM data read from the NV-RAM 43 is referred to.

In step F102 and subsequent steps, processing for writing data for use at the next power-on or reset to the NV-RAM 43 is performed.
First, the contents to be written in the NV-RAM 43 are determined in step F102.
In step F103, the writing of the determined data contents to the NV-RAM 43 is started.
This writing is performed in several times.
That is, waiting for a certain time in step F104 and writing of partial data in step F105 are repeated until it is determined in step F106 that all writing has been completed.
In the processes of steps F103 to F106, new data is written into the NV-RAM 43, whereby the initial process for the NV-RAM 43 is completed.

4-3 Format Trigger Corresponding Processing Next, processing performed before factory shipment will be described.
First, the flow of processing performed before factory shipment will be described with reference to FIG. 25A shows a case where a format trigger is not generated, and FIG. 25B shows a case where a format trigger is generated. In this example, a format trigger is generated as shown in FIG. Thus, appropriate initialization (format) for the NV-RAM 43 is performed efficiently.

As shown in FIG. 24, with the personal computer 250 connected via the IEEE 1394 bus 116, first, as shown in step ST1 in FIG. 25A, the personal computer 250 is connected to the STR compatible disk drive 30. The program is written.
That is, here, an initial processing program for the system controller 50 to execute the above-described initial processing, a format program for responding to the format trigger, and device-specific ID information are transferred from the personal computer 250 to the STR compatible disk drive 30. Entered. The system controller 50 of the STR compatible disk drive 30 stores the supplied initial processing program, format program, and ID information in the program memory 44, as shown in step ST2.

Thereafter, when the STR compatible disk drive 30 main body is reset and started (powered on) as shown in step ST3, the system controller 50 executes an operation based on a program stored in the program memory 44. Therefore, as the process when the power is turned on, the initial process for the NV-RAM 43 described above is executed (procedure ST4).
That is, as the processing described with reference to FIG. 26, data reading from the NV-RAM 43 and writing of next data to the NV-RAM 43 are performed.
This initial process requires a relatively long time, for example, about 10 to 20 seconds.

However, in the NV-RAM 43 at the stage of being incorporated at the factory as described above, the data contents are completely indefinite. For this reason, even if the initial processing is performed as the procedure ST4, there is no confirmation that the data state after the processing is appropriate.
Therefore, in this example, as shown in FIG. 25 (b), after program writing is performed in steps ST1 and ST2, device reset / startup is performed in step ST3, and the system controller 50 starts the initial step ST4. When the process is started, the personal computer 250 supplies a format trigger to the STR compatible disk drive 30 (procedure ST5).
When the format trigger is input, the system controller 50 interrupts the initial process and executes the format process as step ST6. This formatting process is a process for forcibly writing the initial value of the required data into the NV-RAM 43.

The format program as a program stored in the program memory 44 in the procedures ST1 and ST2 is a processing program for the system controller 50 to respond to the format trigger, and the initial value data to be written in the NV-RAM 43 is incorporated. ing.
By storing the format program in the program memory 44, the system controller 50 can perform format processing corresponding to the format trigger input.

FIG. 27 shows a format trigger handling process executed by the system controller 50.
When the system controller 50 recognizes the input of the format trigger as step F201, the system controller 50 proceeds to step F202.
The format trigger is encrypted and transmitted by the personal computer 250. For example, it is transmitted in a scrambled state. At this time, the personal computer 250 performs an encryption process using the ID information given to the STR compatible disk drive 30.
The STR compatible disk drive 30 decodes the format trigger input of the personal computer 250 using the assigned ID information, and recognizes that the format trigger is a format trigger correctly issued to itself. The process proceeds to step F202.
This is to prevent the format process from being executed on the user side, for example.

In steps F202 and F203, it is determined whether or not interrupting for the initial processing is possible while waiting for a predetermined time.
As shown in FIG. 25B, the STR compatible disk drive 30 starts the initial process in response to the power being turned on. Since the personal computer 250 transmits the format trigger after the STR compatible disk drive 30 is turned on, of course, the STR compatible disk drive 30 executes initial processing when the format trigger is input. Often in the middle. For this reason, in steps F202 and F203, a timing at which an interrupt can be performed with respect to the initial process is detected.
As described with reference to FIG. 26, in the initial processing, writing to the NV-RAM 43 is performed while waiting for a predetermined time in steps F104 and F105. Thus, in this format trigger handling process, the writing standby period in the initial process is detected as an interrupt timing.
Then, when it is time to interrupt, the process proceeds to step F204.

Of course, even when the format trigger is input after the initial processing as step ST4 in FIG. 25 is completed, the system controller 50 starts the processing in FIG. 27, and in this case, the initial processing is not being executed. The standby in steps F202 and F203 is substantially unnecessary. That is, the process can be immediately advanced to step F204.
However, considering efficiency and shortening of the manufacturing process, it is not appropriate to wait for the completion of the initial process of step ST14, and it is preferable to generate a format trigger as soon as possible when the STR compatible disk drive 30 is turned on. .
For this reason, as described above, the process by the format program can interrupt the initial process, thereby realizing process efficiency.

In step F204, the system controller 50 interrupts the initial process and loads information in the format program. In step F205, data contents to be written in the NV-RAM 43 are determined from the loaded format information.
Then, the process proceeds to step 103 in FIG. 26, and writing to the NV-RAM 43 is executed.

That is, when the format trigger is input, the system controller 50 interrupts the initial processing even if it is being executed, sets the initial value of information to be written in the NV-RAM 43, and then performs the initial processing step. By performing the processing from F103, initial values for the required data and the like are written in the NV-RAM 43.
Therefore, the initial value according to the format program is written in the NV-RAM 43. This is the format process in this example.
By performing such a formatting process, the data in the NV-RAM 43 in the initial state can be set to an appropriate value. In other words, if the initial processing is performed from the state in which the data content of the NV-RAM 43 is indefinite, it cannot be confirmed that the data content after the initial processing is appropriate, but the format processing must always make the information content appropriate. Therefore, the STR compatible disk drive 30 to be shipped can be suitable.

Of course, after that, whether it is before shipment or after passing over to the user side, initial processing at the first power-on is performed on the NV-RAM 43 in the formatted state, so that appropriate processing is executed. Is done.
Further, since the format trigger is input after being encrypted, it cannot be executed on the user side, and therefore, it is possible to prevent a situation where data necessary for malicious format processing is falsified.

  During the formatting process, the system controller 50 displays on the display unit 47 that formatting is in progress. Then, the worker can recognize that the device is being formatted, which is convenient for work.

4-4 Example of Format Trigger Input Path In the above description, the format trigger is input from the personal computer 250 via the IEEE 1394 bus 116.
In this case, the device that inputs the format trigger and instructs the format must be a device that can be connected to the IEEE 1394 bus 116 like the personal computer 250.
However, it may be preferable that the format trigger can be input by a device that is not compatible with IEEE 1394, depending on the circumstances in the factory, the equipment situation, the procedure of the formatting process, the number of devices to be formatted, and the like.

Therefore, for example, an example of the format trigger input path in the STR compatible disk drive 30 will be described.
FIG. 28 shows the configuration of the STR compatible disk drive 30 as shown in FIG. 24, further comprising four format trigger input paths.

  As shown in FIG. 5, the STR compatible disk drive 30 includes a receiving unit 45 that receives an operation command from the remote commander RM. For example, when this is an infrared receiver, the format trigger can be received and input from the format instructing device 94 that transmits and outputs the format trigger by infrared as shown in FIG. For example, when the format trigger is received by the receiving unit 45 as an infrared signal in the configuration of FIG. 5, this is supplied to the system controller 50, thereby realizing the format trigger input path by the infrared receiving unit 45 shown in FIG. 28.

In FIG. 28, an IC card reader 55 is shown. This is a device that reads information in a contact or non-contact manner with respect to a card medium such as an IC card or a memory card.
For example, information as a format trigger generated by the personal computer 250 is stored in the IC card 92, and the information on the IC card 92 is read by the IC card reader 55, whereby the format trigger can be input.

In FIG. 28, an antenna 57 and a tuner 56 are shown. For example, the tuner 56 receives and demodulates the format trigger transmitted from the format instruction device 93 and supplies it to the system controller 50.
As a result, an input path for inputting a format trigger as a radio signal by radio waves is realized.

FIG. 28 shows the USB interface 58 and shows a state in which the USB interface 58 is connected to an external device as the format instruction device 95.
As described above, it is also conceivable that a format trigger can be input from a device connected in another interface method such as USB other than IEEE1394.
Of course, connection by other methods such as MOST and control A1 is conceivable instead of USB.
As described above, if the format trigger can be input by another interface method, the format instruction device 95 can be realized by a device that does not support the IEEE1394 bus. For example, a device that does not support the IEEE 1394 bus as a personal computer or other electronic device can be used as the format instruction device 95.

  In FIG. 28, as described above, an infrared input path, an input path from a card medium, an input path by radio wave transmission, and an input path of an interface method other than the IEEE 1394 bus are illustrated. Of course, other input path examples are possible. In this way, the format instruction device can be diversified by providing various input paths other than the input path by the IEEE1394 bus. That is, the format instruction device can be prepared in accordance with the pre-shipment process for the product in the electronic device manufacturer or according to the factory equipment. This can promote manufacturing cost reduction and efficiency.

Although the format trigger input path has been described here, it is naturally possible to use the format trigger as a program or ID information writing path shown as step ST1 in FIG.
In other words, the format instruction device required in the process can be realized in various forms from writing a program or ID to a format trigger.

4-5 Format trigger transmission processing example By the way, after a program or ID is written in an electronic device such as the STR compatible disk drive 30, when the power is turned on, the format trigger is supplied immediately. As described above, it is suitable for improving the efficiency of the process because the initial processing is interrupted in the corresponding disk drive 30 and the like to execute the formatting process.
For example, immediately after the operator turns on the power of the STR compatible disk drive 30, the personal computer 250 is operated to supply the format trigger, thereby eliminating time for performing useless initial processing.

On the other hand, if the format instructing device monitors the power-on of the STR compatible disk drive 30, efficient format processing can be realized without any operator operation.
Here, for example, when the personal computer 250 is the format instruction device as shown in FIG. 24, the operation of automatically transmitting the format trigger will be described with reference to FIGS.

FIG. 30 is a processing example executed in the personal computer 250 which is a format instruction device.
In step F <b> 301, the personal computer 250 transmits an initial processing program, a format program, and a device ID to the STR compatible disk drive 30 and stores them in the program memory 44 of the STR compatible disk drive 30.

Thereafter, in step F302, a request for reading the device ID is made to the STR compatible disk drive 30, and it is monitored whether or not the reading is successful. This device ID read request is repeated until the read is successful.
When the power is turned on, the STR compatible disk drive 30 recognizes the device ID read request from the personal computer 250 and transmits the device ID as a response.
If the reading succeeds, the personal computer 250 proceeds to step F304 and transmits a format trigger.

When the personal computer 250 performs the processing of FIG. 30, the flow from program writing to formatting processing in the STR compatible disk drive 30 is as shown in FIG.
When the initial processing program, the format program, and the device ID are transmitted from the personal computer 250 in step ST11, the system controller 50 of the STR compatible disk drive 30 stores them in the program memory 44 as step ST12.
Thereafter, the main body of the STR compatible disk drive 30 is reset (ST13), and is activated (powered on) at a certain point (ST15).
After transmitting the program and ID, the personal computer 250 makes a device ID read request in step F302 in FIG. This is shown in FIG. 29 as device ID request procedures ST14-1, ST14-2,... ST14-n.

Since the response to the device ID is not performed during the period when the STR compatible disk drive 30 is reset, the device ID read request is repeatedly performed.
When the STR compatible disk drive 30 is turned on as step ST15, the system controller 50 starts the initial process based on the initial process program (ST16). At this time, in order to recognize the device ID read request (ST14-n), the device ID is transmitted to the personal computer 250 as a response.
The personal computer 250 transmits a format trigger when a device ID is transmitted as a response from the STR compatible disk drive 30 (ST18). The system controller 50 executes the process of FIG. 27 in response to the format trigger input. That is, the initial process is interrupted and the format process is performed (ST19).

  According to such an operation, the personal computer 250 monitors the power-on after the program is written to the STR compatible disk drive 30, so that the format trigger can be transmitted at the optimum timing. That is, on the STR-compatible disk drive 30 side, the formatting process can be executed without executing a wasteful initial process for a long time. Therefore, the said process can be performed efficiently.

Here, the personal computer 250 is described as an example of the format instruction device. However, even when another format instruction device such as the format instruction device 95 shown in FIG. 28 is used, the STR compatible disk drive 30 is turned on. By monitoring this, the format trigger can be transmitted at the optimum timing.
Of course, various power-on detection methods are possible.
In the processing of FIG. 30, the device that causes the STR-compatible disk drive 30 to write a program monitors the power-on of the STR-compatible disk drive 30 and transmits a format trigger. The device to be executed and the device that transmits the format trigger may be different devices. For example, after the program is written by the personal computer 250, the format trigger is transmitted by the format instruction devices 93, 94, 95, etc.
In this case, the device that transmits the format trigger may perform step F302 and subsequent steps in FIG.

As described above, the embodiments of the present invention have been described using the STR compatible disk drive 30 and the personal computer 250 as main examples. However, the present invention can be applied to other devices as well.
For example, the electronic device and the formatting method of the present invention can be similarly applied to STR60.
Furthermore, the present invention is also applicable to the devices 100 and 110 shown in FIG.

It is explanatory drawing of the structural example of the AV system in embodiment of this invention. It is a front view of the front panel of STR. It is a front view of the front panel of a STR disc drive. It is a block diagram which shows the internal structural example of STR. It is a block diagram which shows the example of an internal structure of a STR corresponding | compatible disk drive. It is explanatory drawing which shows the stack model of IEEE1394 corresponding to this Embodiment. It is explanatory drawing which shows the cable structure used for IEEE1394. It is explanatory drawing which shows the signal transmission form in IEEE1394. It is explanatory drawing for demonstrating the bus connection prescription | regulation in IEEE1394. It is explanatory drawing which shows the concept of the Node ID setting procedure on an IEEE1394 system. It is explanatory drawing which shows the outline | summary of Packet transmission in IEEE1394. It is a process transition diagram which shows the basic communication rule (transaction rule) in Asynchronous communication. It is explanatory drawing which shows the addressing structure of IEEE1394 bus | bath. It is a structural diagram of CIP. It is explanatory drawing which shows the example of a connection relationship prescribed | regulated with the plug. It is explanatory drawing which shows a plug control register. It is a process transition diagram which shows Write Transaction prescribed | regulated in Asynchronous communication. It is a structural diagram of Asynchronous Packet (AV / C command packet). It is explanatory drawing which shows the definition content of ctype / response in Asynchronous Packet. It is explanatory drawing which shows the definition content example of subunit_type and opcode in Asynchronous Packet. It is explanatory drawing of SRM issue. It is explanatory drawing of the data content of SRM. It is explanatory drawing of use of SRM at the time of an authentication process. It is a block diagram for explanation of initial processing and formatting processing of an embodiment. It is explanatory drawing of the format processing timing of embodiment. It is a flowchart of the initial process of embodiment. It is a flowchart of the format trigger corresponding | compatible process of embodiment. It is explanatory drawing of the various input path | routes of the format trigger of embodiment. It is explanatory drawing of the format processing timing by the starting detection of the electronic device of embodiment. It is a flowchart of the process for the format trigger output by the side of PC of embodiment.

Explanation of symbols

30 STR compatible disk drive 43 NV-RAM, 50, 70 System controller, 54 Flash memory, 60 STR, 39, 61 IEEE 1394 interface, 43, 74 NV-RAM, 44, 73 Program memory, 116 IEEE 1394 bus

Claims (1)

Non-volatile storage means at the time of device startup for an electronic device that is connected via a data bus in a predetermined communication format and establishes a communication state by performing authentication with another electronic device existing on the data bus An initial processing program for performing initial processing for the above, a format program for formatting information stored in the nonvolatile storage means, and ID information unique to the electronic device are transmitted and stored,
When the electronic device is activated, the format instruction encrypted using the ID information is transmitted to cause the electronic device to execute the format program.
After transmitting the initial processing program, the format program, and the ID information to the electronic device, transmission and reception of information for detecting activation of the electronic device is performed.
A format instruction method, comprising: transmitting the format instruction in response to detection of activation of the electronic device by the transmission / reception.

Images