JP4828139B2 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- JP4828139B2 JP4828139B2 JP2005079603A JP2005079603A JP4828139B2 JP 4828139 B2 JP4828139 B2 JP 4828139B2 JP 2005079603 A JP2005079603 A JP 2005079603A JP 2005079603 A JP2005079603 A JP 2005079603A JP 4828139 B2 JP4828139 B2 JP 4828139B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
Description
本発明は半導体装置に関し、特に外部接続用の端子をその下面に有し、マザーボード等に実装する表面実装型の半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a surface-mount type semiconductor device having a terminal for external connection on its lower surface and mounted on a mother board or the like.
インターポーザを使用したリードレス型のチップサイズパッケージ（Chip Size Package 以下、CSP）には、リフローソルダリングによりマザーボード等の実装基板に実装するための外部接続用端子として、インターポーザ下面にマトリクス状に配置されたランド電極に半田ボールを形成したボールグリッドアレイ（Ball Grid Array 以下、BGA）や、半田ボールを形成しないランドグリッドアレイ（Land Grid Array 以下、LGA）がある（例えば、特許文献１参照。）。 The leadless chip size package (CSP), which uses an interposer, is arranged in a matrix on the underside of the interposer as external connection terminals for mounting on a mounting board such as a motherboard by reflow soldering. There are ball grid arrays (hereinafter referred to as “BGA”) in which solder balls are formed on the land electrodes, and land grid arrays (hereinafter referred to as “LGA”) in which solder balls are not formed (see, for example, Patent Document 1).
特にLGAは実装基板との接続に半田ボールを使わないため、BGAに比べ実装したときの半導体パッケージの高さ（取り付け高さ）を低くすることができ、またコスト的に有利である。さらに、LGAの中でもインターポーザとしてプリント配線基板（Printed Circuit Board 以下、PCB）を用いたものは、セラミック製のものと比較して安価であり、かつ薄型化要求に対しても有利であるため広く用いられている。
一般にLGAでは、ランド電極はインターポーザ下面全面に配設したソルダーレジストの開口部に形成されており、ソルダーレジストにより、実装基板への実装時に、隣接するランド電極間での半田ブリッジ等の不具合を抑制している。 In general, in LGA, the land electrode is formed in the opening of the solder resist that is arranged on the entire lower surface of the interposer, and the solder resist suppresses problems such as solder bridges between adjacent land electrodes when mounted on the mounting board. is doing.
この場合、ランド電極端子面はソルダーレジスト面よりも深い位置となっている。 In this case, the land electrode terminal surface is deeper than the solder resist surface.
LGAやBGA等の表面実装型半導体パッケージを、リフローソルダリングにより実装基板に実装した際には、実装後に実装状態（半田接合部）の確認を行う検査工程においては、一般にX線検査により実装後の半田の形状を透過画像により確認する方法が行われている。 When a surface-mount semiconductor package such as LGA or BGA is mounted on a mounting board by reflow soldering, the mounting process (solder joint) is generally confirmed after mounting by X-ray inspection after mounting. A method of confirming the shape of the solder by a transmission image is performed.
しかし、この方法では半田接合部に生じた微細なクラックやランド電極との剥離等の不具合の検出が困難な場合があるため、半田接合部を直接目視により外観検査確認を行うことが要求される場合がある。 However, in this method, since it may be difficult to detect defects such as fine cracks generated in the solder joints and separation from the land electrodes, it is required to visually check the solder joints directly. There is a case.
しかし、LGAやBGAで、そのように半導体パッケージ側面方向から目視検査を行う場合には、一般にランド電極面がソルダーレジストよりも深い場所に位置しているため、ランド電極近傍に発生するクラックや剥離等の不具合を検出できない問題がある。 However, when visual inspection is performed from the side of the semiconductor package in such a manner with LGA or BGA, the land electrode surface is generally located deeper than the solder resist, so cracks and peeling that occur near the land electrode There is a problem that cannot detect such defects as.
これに対し、特許文献1では、ランド電極部をソルダーレジスト面より高くなるよう突出する構成としているため、実装後に外周側面から半田接合部の目視検査を行うことが可能である。 On the other hand, in Patent Document 1, since the land electrode portion protrudes to be higher than the solder resist surface, it is possible to perform a visual inspection of the solder joint portion from the outer peripheral side surface after mounting.
しかしこの例においては、突出電極端子を形成する際にめっきを厚く形成することで突出させるため、インターポーザの製造コストが上昇してしまう問題がある。 However, in this example, there is a problem that the manufacturing cost of the interposer increases because the protruding electrode terminal is formed by forming a thick plating so as to protrude.
また、ランド電極端子のピッチが微細になった場合、実装時に隣接する電極間での半田ブリッジが発生しやすい問題があり、端子ピッチの微細化に対応することが困難である。 Further, when the pitch of the land electrode terminals becomes fine, there is a problem that a solder bridge is easily generated between adjacent electrodes at the time of mounting, and it is difficult to cope with the miniaturization of the terminal pitch.
上記の課題を解決するために、本発明では、半導体素子と、前記半導体素子が搭載された基板とを有する半導体装置において、前記基板の前記半導体素子が搭載された第１の面とは反対の第２の面の前記基板の外周端部から離間する部位に、前記基板の外周に沿って配列された複数のランド型の外部接続端子を有し、前記第２の面には、前記基板の外周端面に延出すると共に、前記外部接続端子に接続されたパターンを有し、前記第２の面には、前記外部接続端子の上を除いて半田レジストが配設されており、前記半田レジストの前記外部接続端子部における半田レジスト開口部は前記基板外周端面に向かう方向に開口しており、前記配線パターンは、前記外部接続端子と接続される部位を除いて前記半田レジストにより被覆されていることを特徴とする。 In order to solve the above problems, in the present invention, in a semiconductor device having a semiconductor element and a substrate on which the semiconductor element is mounted, the first surface of the substrate on which the semiconductor element is mounted is opposite to the first surface. The second surface has a plurality of land-type external connection terminals arranged along the outer periphery of the substrate at a portion spaced from the outer peripheral edge of the substrate, and the second surface includes the substrate A pattern extending to the outer peripheral end surface and connected to the external connection terminal is provided, and a solder resist is disposed on the second surface except for the top of the external connection terminal. The solder resist opening in the external connection terminal portion is open in a direction toward the outer peripheral end surface of the substrate, and the wiring pattern is covered with the solder resist except for a portion connected to the external connection terminal . thing And features.
本発明によれば、リフローソルダリングにより実装基板に実装を行った際においても、側面方向より半田接合部の外観検査が容易なリードレス型のチップサイズパッケージを提供する。 According to the present invention, there is provided a leadless type chip size package in which the appearance inspection of a solder joint can be easily performed from the side surface direction even when mounted on a mounting substrate by reflow soldering.
次に、本発明を実施するための最良の形態について図面と共に説明する。 Next, the best mode for carrying out the present invention will be described with reference to the drawings.
本発明を実施するための形態について図面を用いて詳細に説明する。 Embodiments for carrying out the present invention will be described in detail with reference to the drawings.
図１は、第１参考例による半田接合部の外観検査が容易なリードレス型のCSP型半導体装置の構成を示す断面図を示す。図１に示した半導体装置１は、基材１２の上面に上面表面配線部２４とボンディングパッド２０を有し、基材１２の下面に下面表面配線部２６と外部接続端子２２を有する基板１０と、基板１０上にエポキシフィルム等の接着剤４０を介して配設される半導体素子２と、基板１０と半導体素子２を電気的に接続するワイヤ６と、半導体素子２及びワイヤ６を封止する封止樹脂４２とから構成される。 FIG. 1 is a cross-sectional view showing a configuration of a leadless CSP type semiconductor device in which the appearance inspection of the solder joint portion according to the first reference example is easy. The semiconductor device 1 shown in FIG. 1 has an upper surface wiring portion 24 and a bonding pad 20 on the upper surface of a base material 12, and a substrate 10 having a lower surface wiring portion 26 and an external connection terminal 22 on the lower surface of the base material 12. The semiconductor element 2 disposed on the substrate 10 via an adhesive 40 such as an epoxy film, the wire 6 that electrically connects the substrate 10 and the semiconductor element 2, and the semiconductor element 2 and the wire 6 are sealed. And a sealing resin 42.
絶縁物からなる基材１２上にＣｕ、Ｎｉ、Ａｕ等の金属層からなる上面表面配線部２４及びワイヤ６を接続するためのボンディングパッド２０が形成されており、ボンディングパッド２０を除く領域は、ポリイミド、エポキシ、アクリル等の樹脂からなるソルダーレジスト３０によって覆われている。 A bonding pad 20 for connecting the upper surface wiring portion 24 made of a metal layer such as Cu, Ni, Au and the wire 6 is formed on the base material 12 made of an insulator, and the region excluding the bonding pad 20 is It is covered with a solder resist 30 made of a resin such as polyimide, epoxy, or acrylic.
基材１２の下側にもＣｕ、Ｎｉ、Ａｕ等の金属層からなる下面表面配線部２６及び外部接続端子２２が形成されている。 A lower surface wiring portion 26 and an external connection terminal 22 made of a metal layer such as Cu, Ni, or Au are also formed on the lower side of the substrate 12.
図２は、基板１０を下面より見た平面図を示す。外部接続端子２２は基板１０の４辺に複数（図２の場合は４）個ずつ、基板１０の辺付近に配置されている。外部接続端子２２とその近傍を除く領域は、ポリイミド、エポキシ、アクリル等の樹脂からなるソルダーレジスト３２によって覆われている。ただし、基板１０の端部から各々の外部接続端子２２の間の領域にはソルダーレジスト３２は配設されず、基材１２が露出した開口部３４となっている。 FIG. 2 is a plan view of the substrate 10 as viewed from the lower surface. A plurality (four in the case of FIG. 2) of external connection terminals 22 are arranged in the vicinity of the side of the substrate 10 on four sides of the substrate 10. The region excluding the external connection terminal 22 and the vicinity thereof is covered with a solder resist 32 made of a resin such as polyimide, epoxy, or acrylic. However, the solder resist 32 is not disposed in the region between the end portion of the substrate 10 and each external connection terminal 22, and the opening portion 34 is exposed from the base material 12.
図１を参照して、基板１０の基材１２には、上面表面配線部２４と下面表面配線部２６とを電気的に接続する内部配線部（スルーホール配線）１４が形成され、これにより、半導体素子２の電極パッド４は、ワイヤ６、ボンディングパッド２０、上面表面配線部２４、内部配線部１４、下面表面配線部２６を介して外部接続端子２２へ電気的に接続されている。 Referring to FIG. 1, an internal wiring portion (through-hole wiring) 14 that electrically connects the upper surface wiring portion 24 and the lower surface wiring portion 26 is formed on the base 12 of the substrate 10, thereby The electrode pad 4 of the semiconductor element 2 is electrically connected to the external connection terminal 22 via the wire 6, the bonding pad 20, the upper surface wiring portion 24, the internal wiring portion 14, and the lower surface wiring portion 26.
第１参考例に係る半導体装置１においては、基板１０の下面における基板１０の端部から外部接続端子２２までの領域にはソルダーレジスト３２が形成されていないので、実装基板に本半導体装置を実装した後に、実装基板との接合状態を半導体装置の側面より観察することができる。 In the semiconductor device 1 according to the first reference example , since the solder resist 32 is not formed in the region from the edge of the substrate 10 to the external connection terminal 22 on the lower surface of the substrate 10, the semiconductor device is mounted on the mounting substrate. After that, the bonding state with the mounting substrate can be observed from the side surface of the semiconductor device.
図３は、第２の参考例である半導体装置を示す断面図である。 FIG. 3 is a cross-sectional view showing a semiconductor device as a second reference example .
図１の第１参考例による半導体装置においては、半導体素子２の電極パッド４は基板１０に対して反対側の面に形成されて、基板１０のボンディングパッド２０とはワイヤ６で接続されていたが、本参考例によれば、半導体素子２は、その電極パッド４の形成されている面が基板１０と向き合う様にフリップチップ実装され、基板１０のパッド２１とはバンプ８によって接続されている。 In the semiconductor device according to the first reference example of FIG. 1, the electrode pad 4 of the semiconductor element 2 is formed on the surface opposite to the substrate 10 and is connected to the bonding pad 20 of the substrate 10 by the wire 6. However, according to this reference example, the semiconductor element 2 is flip-chip mounted so that the surface on which the electrode pad 4 is formed faces the substrate 10, and is connected to the pad 21 of the substrate 10 by the bump 8. .
基板１０の基材１２上にはＣｕ、Ｎｉ、Ａｕ等の金属層からなる上面表面配線部２４とパッド２１が形成され、パッド２１を除く領域は、ポリイミド、エポキシ、アクリル等の樹脂からなるソルダーレジスト３０によって覆われている。 An upper surface wiring portion 24 made of a metal layer such as Cu, Ni, or Au and a pad 21 are formed on the base material 12 of the substrate 10, and a region excluding the pad 21 is a solder made of a resin such as polyimide, epoxy, or acrylic. It is covered with a resist 30.
半導体素子２の電極パッド４は、バンプ８を介して基板１０のパッド２１に接合され、半導体素子２と基板１０の間の接着剤４０により、半導体素子２と基板１０は固着されている。 The electrode pad 4 of the semiconductor element 2 is bonded to the pad 21 of the substrate 10 via the bump 8, and the semiconductor element 2 and the substrate 10 are fixed by an adhesive 40 between the semiconductor element 2 and the substrate 10.
電極パッド４はバンプ８、パッド２１、上面表面配線部２４、内部配線部１４、下面表面配線部２６を介して外部接続端子２２へ電気的に接続される。 The electrode pad 4 is electrically connected to the external connection terminal 22 via the bump 8, the pad 21, the upper surface wiring portion 24, the internal wiring portion 14, and the lower surface wiring portion 26.
本参考例では、半導体素子２と基板１０の接合方法が前記第１の参考例と異なるだけで、基板１０の下面は第１の参考例で示す図３と同じであり、本参考例においても、基板１０の下面における基板１０の端部から外部接続端子２２までの領域にはソルダーレジスト３２が形成されていないので、実装基板に本半導体装置を実装した後に、実装基板との接合状態を半導体装置の側面より観察することができる。 In the present embodiment, only the method of joining the semiconductor element 2 and the substrate 10 is different from the first reference example, the lower surface of the substrate 10 is the same as Figure 3 showing the first reference example, in the present reference example Since the solder resist 32 is not formed in the region from the edge of the substrate 10 to the external connection terminal 22 on the lower surface of the substrate 10, the semiconductor device is mounted on the mounting substrate, and the bonding state with the mounting substrate is changed to the semiconductor. It can be observed from the side of the device.
図４は、第３の参考例である半導体装置の構成を示す断面図である。 FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device as a third reference example .
第３の参考例の半導体装置は、前記第１の参考例の半導体装置１の外部接続端子２２にさらに外部接続端子となる半田ボール５０が形成されており、実装基板にはこの半田ボール５０によって接合される。半田ボール５０にて実装基板に接合することで、実装する際の応力の緩和効果があり、半導体装置を実装した際の実装信頼性が向上する。 In the semiconductor device of the third reference example, solder balls 50 serving as external connection terminals are further formed on the external connection terminals 22 of the semiconductor device 1 of the first reference example. Be joined. By bonding to the mounting substrate with the solder balls 50, there is a stress relaxation effect when mounting, and the mounting reliability when mounting the semiconductor device is improved.
本参考例においても、基板１０の下面における基板１０の端部から外部接続端子２２までの領域にはソルダーレジスト３２が形成されていないので、実装基板に本半導体装置を実装した後に、実装基板との接合状態を半導体装置の側面より観察することができる。 Also in this reference example, since the solder resist 32 is not formed in the region from the end of the substrate 10 to the external connection terminal 22 on the lower surface of the substrate 10, after mounting this semiconductor device on the mounting substrate, Can be observed from the side surface of the semiconductor device.
図５は、第４の参考例である半導体装置の基板の部分平面図である。 FIG. 5 is a partial plan view of a substrate of a semiconductor device as a fourth reference example .
外部接続端子２２は、基材１２上に形成され基板１２より突出した直方体構造となっているが、図５（Ａ）に示す参考例では、外部接続端子２２の面と面の境の角部は面取りされていて曲面状となっていることを特徴としている。 Although the external connection terminal 22 has a rectangular parallelepiped structure formed on the base material 12 and protruding from the substrate 12, in the reference example shown in FIG. 5A, the corner portion between the surface of the external connection terminal 22 and the surface. Is characterized by being chamfered and curved.
このように外部接続端子２２の角部を面取りすることで、実装基板に接合する際に面取りされた外部接続端子形状によって半田フィレットの形状が規定される事で、半田接合部での部分的な応力集中が分散され、接合信頼性を向上させる効果がある。 By chamfering the corners of the external connection terminals 22 in this way, the shape of the solder fillet is defined by the shape of the external connection terminals chamfered when bonded to the mounting substrate, so that a partial portion at the solder joint is obtained. The stress concentration is dispersed, and there is an effect of improving the bonding reliability.
図５（Ｂ）に示す参考例では、外部接続端子２２の側面から実装基板との接合面となる面にかかる部分までソルダーレジスト３２に覆われている。このように外部接続端子２２の上面にまでソルダーレジスト３２で覆うことにより、実装基板へ実装する際に外部接続端子２２に加わる応力により、外部接続端子２２が基材１２から剥がれてしまうのを防ぐ効果がある。 In the reference example shown in FIG. 5B, the solder resist 32 covers the part from the side surface of the external connection terminal 22 to the surface that becomes the bonding surface with the mounting substrate. By covering the upper surface of the external connection terminal 22 with the solder resist 32 in this way, the external connection terminal 22 is prevented from being peeled off from the base material 12 due to the stress applied to the external connection terminal 22 when mounted on the mounting board. effective.
本参考例においても、基板１０の下面における基板１０の端部から外部接続端子２２までの領域にはソルダーレジスト３２が形成されていないので、実装基板に本半導体装置を実装した後に、実装基板との接合状態を半導体装置の側面より観察することができる。 Also in this reference example, since the solder resist 32 is not formed in the region from the end of the substrate 10 to the external connection terminal 22 on the lower surface of the substrate 10, after mounting this semiconductor device on the mounting substrate, Can be observed from the side surface of the semiconductor device.
図６は、第５の参考例である半導体装置の基板の部分平面図である。 FIG. 6 is a partial plan view of a substrate of a semiconductor device as a fifth reference example .
図６（Ａ）に示す参考例では、基板１０の端面から外部接続端子２２との間のソルダーレジストの無い開口部３４の形状が、基板１０の端側で幅がやや広くなっていることを特徴としている。 In the reference example shown in FIG. 6A, the shape of the opening 34 without the solder resist between the end face of the substrate 10 and the external connection terminal 22 is slightly wider on the end side of the substrate 10. It is a feature.
このようにソルダーレジスト３２の開口を基板１０の端側で広げることで、ソルダーレジスト３２が基材１２から剥がれにくくすると共に、側面から接合部を観察しやすくする効果がある。 In this way, by widening the opening of the solder resist 32 on the end side of the substrate 10, the solder resist 32 is less likely to be peeled off from the base material 12, and the joint portion can be easily observed from the side surface.
図６（Ｂ）に示す参考例では、前記図６Ａに対しさらに基板１２の端側で広がったソルダーレジスト３２の側面を面取りして曲面状とすることを特徴としている。 The reference example shown in FIG. 6B is characterized in that the side surface of the solder resist 32 further spread on the end side of the substrate 12 is chamfered to form a curved surface with respect to FIG. 6A.
このようにソルダーレジスト３２の基板１０の端側の開口を広げ、さらにソルダーレジスト３２の側面を面取りして曲面状とすることで、ソルダーレジスト３２が基材１２から剥がれにくくすると共に、側面から接合部を観察しやすくする効果がある。 In this way, the opening on the end side of the substrate 10 of the solder resist 32 is widened, and the side surface of the solder resist 32 is further chamfered to form a curved surface. This makes it easier to observe the part.
本参考例においても、基板１０の下面における基板１０の端部から外部接続端子２２までの領域にはソルダーレジスト３２が形成されていないので、実装基板に本半導体装置を実装した後に、実装基板との接合状態を半導体装置の側面より観察することができる。 Also in this reference example, since the solder resist 32 is not formed in the region from the end of the substrate 10 to the external connection terminal 22 on the lower surface of the substrate 10, after mounting this semiconductor device on the mounting substrate, Can be observed from the side surface of the semiconductor device.
図７は、本発明の実施例である半導体装置、及び第６の参考例である半導体装置の基板の部分平面図である。 Figure 7 is a semiconductor device, and a partial plan view of a substrate of a semiconductor device according to a sixth reference example is a real施例of the present invention.
図７（Ａ）に示す参考例では、基板１０の下面の端部全辺にわたってソルダーレジストが無いことを特徴としている。つまり、基板１０の端部は基材１２が露出している。 The reference example shown in FIG. 7A is characterized in that there is no solder resist over the entire edge of the lower surface of the substrate 10. That is, the base material 12 is exposed at the end of the substrate 10.
このように、基板１０の外周端部にはソルダーレジスト３２が配設されていないため、半導体装置の製造時やハンドリング時においてソルダーレジストのクラック発生や剥離、脱落等の不具合を抑制できる。 As described above, since the solder resist 32 is not disposed on the outer peripheral end portion of the substrate 10, it is possible to suppress problems such as cracking, peeling, and dropping of the solder resist at the time of manufacturing or handling the semiconductor device.
図７（Ｂ）に示す実施例では、外部接続端子２２とソルダ−レジスト３２の間の基材１２が露出する部分に、ソルダーレジスト３２の下に形成されている下面表面配線部２６と接続する配線接続部２８が形成されている。さらに下面表面配線部２６は基板１０の端部に向かって配設され、下面表面配線部２６の断面が基板１０の側面に露出している。この基板１０の側面に露出した下面表面配線２６に給電することによって、外部接続端子２２に電解めっきによりＮｉ、Ａｕ等のめっきを形成することが容易になる。 In the embodiment shown in FIG. 7B, the lower surface wiring portion 26 formed under the solder resist 32 is connected to the portion where the base 12 between the external connection terminal 22 and the solder resist 32 is exposed. A wiring connection portion 28 is formed. Further, the lower surface wiring portion 26 is disposed toward the end portion of the substrate 10, and a cross section of the lower surface wiring portion 26 is exposed on the side surface of the substrate 10. By supplying power to the lower surface wiring 26 exposed on the side surface of the substrate 10, it becomes easy to form plating of Ni, Au or the like on the external connection terminals 22 by electrolytic plating.
本参考例及び実施例においても、基板１０の下面における基板１０の端部から外部接続端子２２までの領域にはソルダーレジスト３２が形成されていないので、実装基板に本半導体装置を実装した後に、実装基板との接合状態を半導体装置の側面より観察することができる。 Also in this reference example and example, since the solder resist 32 is not formed in the region from the end of the substrate 10 to the external connection terminal 22 on the lower surface of the substrate 10, after mounting the semiconductor device on the mounting substrate, The bonding state with the mounting substrate can be observed from the side surface of the semiconductor device.
図８は、第７の参考例である半導体装置の基板の部分平面図である。 FIG. 8 is a partial plan view of a substrate of a semiconductor device as a seventh reference example .
図８に示す参考例では、基板１０上のソルダーレジスト３２の側面が、図８（Ｂ）に示す様に傾斜していることを特徴としている。つまり、ソルダーレジスト３２の外部接続端子２２周辺の開口はテーパ状となっている。このようにソルダーレジスト３２の開口をテーパ状にすることで、ソルダーレジスト３２が基材１２から剥がれにくくする効果がある。 The reference example shown in FIG. 8 is characterized in that the side surface of the solder resist 32 on the substrate 10 is inclined as shown in FIG. 8B. That is, the opening around the external connection terminal 22 of the solder resist 32 is tapered. By making the opening of the solder resist 32 in a tapered shape in this way, there is an effect that the solder resist 32 is hardly peeled off from the base material 12.
本参考例においても、基板１０の下面における基板１０の端部から外部接続端子２２までの領域にはソルダーレジスト３２が形成されていないので、実装基板に本半導体装置を実装した後に、実装基板との接合状態を半導体装置の側面より観察することができる。 Also in this reference example, since the solder resist 32 is not formed in the region from the end of the substrate 10 to the external connection terminal 22 on the lower surface of the substrate 10, after mounting this semiconductor device on the mounting substrate, Can be observed from the side surface of the semiconductor device.
１…半導体装置
２…半導体素子
４…電極パッド
６…ワイヤ
８…バンプ
１０…基板
１２…基材
１４…内部配線部
２０…ボンディングパッド
２２…外部接続端子
２４…上面表面配線部
２６…下面表面配線部
２８…配線接続部
３０、３２…ソルダーレジスト
３４…開口部
４０…接着剤
４２…封止樹脂
５０…半田ボール
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Semiconductor element 4 ... Electrode pad 6 ... Wire 8 ... Bump 10 ... Substrate 12 ... Base material 14 ... Internal wiring part 20 ... Bonding pad 22 ... External connection terminal 24 ... Upper surface surface wiring part 26 ... Lower surface surface wiring Portion 28 ... Wiring connection portion 30, 32 ... Solder resist 34 ... Opening 40 ... Adhesive 42 ... Sealing resin 50 ... Solder ball
Claims (1)
前記半導体素子が搭載された基板とを有する半導体装置において、
前記基板の前記半導体素子が搭載された第１の面とは反対の第２の面の前記基板の外周端部から離間する部位に、前記基板の外周に沿って配列された複数のランド型の外部接続端子を有し，
前記第２の面には、前記基板の外周端面に延出すると共に、前記外部接続端子に接続された配線パターンを有し、
前記第２の面には、前記外部接続端子の上を除いて半田レジストが配設されており，
前記半田レジストの前記外部接続端子部における半田レジスト開口部は前記基板外周端面に向かう方向に開口しており、
前記配線パターンは、前記外部接続端子と接続される部位を除いて前記半田レジストにより被覆されていることを特徴とする半導体装置。 A semiconductor element;
In a semiconductor device having a substrate on which the semiconductor element is mounted,
A plurality of land-types arranged along the outer periphery of the substrate at a portion spaced from the outer peripheral end of the substrate on a second surface opposite to the first surface on which the semiconductor element is mounted. Have external connection terminals,
The second surface has a wiring pattern extending to the outer peripheral end surface of the substrate and connected to the external connection terminal,
Solder resist is disposed on the second surface except on the external connection terminals,
The solder resist opening in the external connection terminal portion of the solder resist is opened in a direction toward the outer peripheral end surface of the substrate ,
The semiconductor device, wherein the wiring pattern is covered with the solder resist except for a portion connected to the external connection terminal .
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