JP4825154B2 - Data processing device - Google Patents

Description

  The present invention relates to a data processing apparatus, and more particularly to a SIMD type microprocessor.

  In image processing, processing such as setting / changing a calculation formula for image processing using the maximum value or minimum value of all pixel data in a predetermined range as a feature amount may be necessary. In a SIMD type microprocessor whose feature of computing multiple data at once is suitable for image processing, the maximum value or the minimum value is selected from pixel data stored in each processor element (hereinafter referred to as PE). Several techniques have been disclosed in the past for realizing the selection.

  The techniques disclosed in Patent Document 1 and Patent Document 2 basically relate to sequential processing. The technology reads out the target pixel data from all PEs and obtains the maximum value or the minimum value of all target pixel data by leaving the larger one or the smaller one as a result of sequential size comparison. . This technique has a feature that the time required for detection increases as the number of target pixels increases, and it can be said that this technique is not appropriate for a processor having a large number of PEs.

  The technique disclosed in Patent Document 3 also basically relates to sequential processing. Unlike the techniques disclosed in Patent Literature 1 and Patent Literature 2, the data of each PE is sequentially supplied to all PEs, and the maximum value or the minimum value is obtained by collecting the comparison results. It can be said that the technology has the same advantages and disadvantages as those disclosed in Patent Document 1 and Patent Document 2.

  In Patent Document 4, a computing unit is provided in a tree shape between PEs, and the maximum value is detected and the sum is calculated while maintaining a small load on the computing unit by cutting the pipeline in each tree. The circuit configuration to be performed is disclosed. In this configuration, if the number of PEs increases, the number of computing units increases, leading to an increase in circuit scale, and an operation that spans half the distance of the total PE length is required at the end of the tree. There is concern in terms of speed. Patent Document 5 basically discloses the same technique.

  The techniques disclosed in Patent Document 6 and Patent Document 7 compare one bit at a time in order from the upper bits, and exclude flags that are out of the maximum value or minimum value candidates by using a flag. . In such a technique, the maximum value or the minimum value can be obtained by repeating the process for the number of bit widths of the target data. However, if the number of target data is large, there is a problem that the time required for one process increases. .

Patent Document 8 discloses a circuit configuration in which comparison target data is first decoded and a maximum value and a minimum value are detected by obtaining a logical sum of the decoding results. In this circuit configuration, when the bit width of the comparison target data is wide, the problem about the case where the number of target data is large is not solved.
JP 2001-265592 A Japanese Patent Laid-Open No. 08-030577 Patent No. 2969115 Japanese Patent Publication No. 8-14816 JP 2002-207706 A Japanese Patent Laid-Open No. 05-1000082 Japanese Patent Laid-Open No. 06-139048 Japanese Patent Laid-Open No. 11-85467

  An object of the present invention is to construct a data processing apparatus, particularly a microprocessor, which can select a maximum value or a minimum value in a short cycle while keeping a small circuit scale in consideration of the above-mentioned problems of the prior art. And That is, in the microprocessor, the maximum value or the minimum value can be obtained in a short cycle even when the number of binary data is large, and the maximum value or the minimum value can be obtained without increasing the circuit scale even when the bit width of the binary data is wide. It is an object to be able to obtain a value, and in particular, to obtain a maximum value or a minimum value from data processed by a parallel processor such as a SIMD type without increasing the circuit scale.

The present invention has been made to achieve the above object. The data processing device according to claim 1 according to the present invention is a data processing device for obtaining a maximum value or a minimum value from a plurality of binary data,
More than the same number of condition flags as binary data;
More than the same number of decoders as binary data for decoding each binary data;
More than the same number of comparators as binary data;
A decoding result from each decoder has a bit-by-bit bus that is output as a Wire-OR.
Each condition flag, each decoder, and each comparator are associated with the target binary data,
If the value of the related condition flag is true, the result of decoding by the decoder is Wired-ORed bit by bit and output to the bus, and if the related condition flag is false, it is not output to the bus.
Each comparator compares the decoded result value of the associated decoder with the value of the wired-OR bus, and if the decoded result is smaller than the wired-OR bus value, the related condition flag The value of is reset.

A data processing apparatus according to claim 2 of the present invention is
Furthermore, a bit shift circuit is installed in association with the related condition flag, decoder, and comparator,
Each bit shift circuit inputs each binary data, shifts the bit by a predetermined width, and outputs it to the associated decoder,
2. The data processing apparatus according to claim 1, wherein a maximum value or a minimum value is calculated with respect to data of a bit width of a specific portion among a plurality of binary data bit widths.

According to a third aspect of the present invention, there is provided a data processing device.
Each decoder
As a decoding result, from the LSB bit, the bit from which the input data is decoded to “1” is output as “1”, and the other bits are output as “0”.
The data processing apparatus according to claim 1, wherein the data processing apparatus is configured to output the negative logic.

According to a fourth aspect of the present invention, there is provided a data processing device.
A data processing device according to any one of claims 1 to 3,
The comparator is composed of an arithmetic operation unit (ALU) for processing a plurality of binary data.

  By utilizing the present invention, even when the number of target binary data is large in the data processing apparatus, it becomes possible to obtain the maximum value or the minimum value of the large number of binary data in a short cycle.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments according to the invention will be described with reference to the drawings.

[First Embodiment]

  FIG. 10 is a schematic configuration diagram of the microprocessor 2 according to the present invention. The microprocessor 2 shown in FIG. 10 includes a plurality (n in the figure) of processor elements (4- (1), 4- (2),... 4- (n)). Includes a register and an arithmetic unit (not shown). Each processor element 4 is appropriately connected, and its operation is controlled by a global processor (not shown). Such a parallel processor is usually referred to as a “SIMD type microprocessor”.

  FIG. 1 is a partially enlarged view of the microprocessor 2 according to the first embodiment of the present invention. In particular, a portion of each of the three processor elements is shown. Here, the case where the binary data to be compared is 4 bits and the binary data to be compared is three from the target data 1 to the target data 3 is illustrated. The target data 1 to the target data 3 are stored in, for example, registers (not shown), respectively, and are input to the decoders (decoder 1, decoder 2, decoder 3).

  The binary data and the value of each condition flag are input to the decoders (decoder 1, decoder 2, decoder 3). The configuration of each decoder is as shown in FIG. Each decoder outputs the result of decoding the binary data to the bus shown in the lower part of FIG. 1 via the 3-state buffer. As shown in FIG. 2, a condition flag is connected to the output enable signal of the 3-state buffer. That is, in the processor element in which the condition flag is true, the decoding result is output to the bus via the three-state buffer.

  It is obvious that the same operation can be performed even if a dynamic bus configuration or an open drain configuration is adopted instead of the 3-state buffer.

  The comparators (Comparator 1, Comparator 2, Comparator 3) receive the output from each decoder and the data on the bus, and the comparison result of the comparator is connected to the reset terminal of the condition flag. .

  FIG. 3 shows a configuration diagram (FIG. 3B) and functional contents (FIG. 3A) of a comparator included in the microprocessor according to the first embodiment of the present invention. FIG. 3A is a description showing the operation contents of two types of comparison elements constituting the comparator of FIG. 3B, that is, CMP1 and CMP2.

  The microprocessor having the configuration shown in FIGS. 1, 2, and 3 obtains the maximum value from the three target data as follows. Note that the target data 1, the target data 2, and the target data 3 are, for example, (1010b), (0111b), and (1001b).

(Step 1): All condition flags are set to “1”.

(Step 2-1): The output of the decoder and the data on the bus are as shown in Table 1 below.

(Step 2-2): The comparison results are shown in Table 2 below.

ここで、バス上のデータ“( 0000010000000000b )”をエンコードして“1010b”が得られる。 (Step 2-3); As a result, the condition flag 2 and the condition flag 3 are reset, and the output of the decoder and the data on the bus are as shown in Table 3 below, and the maximum value is obtained.

Here, “1010b” is obtained by encoding the data “(0000010000000000b)” on the bus.

  In the above, the description has been given of obtaining the maximum value in the three data, but the same may be applied to obtaining the maximum value in a larger number of data. Further, the minimum value can be obtained by inputting inversion of binary data to the decoder, and encoding by swapping (changing) the bit order of the data on the bus.

[Second Embodiment]
FIG. 4 is a partially enlarged view of the microprocessor 2 according to the second embodiment of the present invention. In particular, a portion of each of the three processor elements is shown. Since the microprocessor according to the second embodiment of the present invention is substantially the same as the microprocessor according to the first embodiment of the present invention, the difference between the two will be mainly described.

  Here, the binary data to be compared is 16 bits, and the binary data to be compared is three from target data 1 to target data 3. The target data 1 to 3 are stored in registers (not shown), for example, and are input to the barrel shifter, shifted by an arbitrary number of bits by the barrel shifter, and the resulting 4 bits are decoded (decoder 1). , Decoder 2 and decoder 3).

  For example, 16-bit data is right-shifted, and the lower 4 bits of the shift result are input to the decoder. According to this configuration, the maximum value can be obtained from the three 16-bit data as follows. Note that the target data 1, the target data 2, and the target data 3 are, for example, (32FFh), (3750h), and (289Ch).

(Step 1): All condition flags are set to “1”.

(Step 2-1): The lower 4 bits resulting from the right 12-bit shift by the barrel shifter are output to the decoder. The output of the decoder and the data on the bus are as shown in Table 4 below.

(Step 2-2): The comparison results in each comparator are as shown in Table 5 below.

  As a result, the condition flag 3 is reset, the decoder output and the data on the bus are as shown in Table 6 below, and the maximum value in bits 15 to 12 is obtained.

ここで、バス上のデータ“( 0000000000001000b )”をエンコードして“0011b (3h)”が得られる。

Here, “0011b (3h)” is obtained by encoding the data “(0000000000001000b)” on the bus.

(Step 3-1): The lower 4 bits of the result of the 8-bit right shift by the barrel shifter are output to the decoder. The decoder output and data on the bus are as shown in Table 7 below.

(Step 3-2): The comparison result in each comparator is as shown in Table 8 below.

  As a result, the condition flag 1 and the condition flag 3 are reset, and the output of the decoder and the data on the bus are as shown in Table 9 below, and the maximum value in the bits 11 to 8 is obtained.

ここで、バス上のデータ“( 0000000010000000b )”をエンコードして“0111b (7h)”が得られる。

Here, “0111b (7h)” is obtained by encoding the data “(0000000010000000b)” on the bus.

  In the above example, the maximum value is obtained here. If it is not yet determined at this point, as in the previous case, the lower 4 bits of the result of the right 4 bit shift by the barrel shifter are output to the decoder, and the maximum value in bits 7 to 4 is obtained to obtain the overall maximum value. Ask for. If it is not yet obtained at that time, the maximum 4 bits 0 to 3 are obtained by outputting the lower 4 bits of the result of the right 0 bit shift (ie, not shifted) by the barrel shifter to the decoder. Find the maximum value. That is, the target data in the processor element including the condition flag that is not reset to the end is the maximum value.

  In the above, the description has been given of obtaining the maximum value in the three data, but the same may be applied to obtaining the maximum value in a larger number of data.

[Third Embodiment]
FIG. 5 is a circuit configuration diagram of a decoder in the microprocessor according to the third embodiment of the present invention.

  In the microprocessor according to the first embodiment shown in FIG. 1 and the microprocessor according to the second embodiment shown in FIG. 4, when the decoder is changed from the one shown in FIG. 2 to the one shown in FIG. It is possible to use a normal comparator or subtractor.

  In the case of target data 1 (1010b), target data 2 (0111b), and target data 3 (1001b), the output of the decoder and the data on the bus are as shown in Table 10 below.

  Thus, it can be seen that the data on the bus is exactly the same as the decoder 1 having the maximum number. Therefore, a simple comparator as shown in FIG. 6 or a subtracter (not shown) can be used as the comparator.

[Fourth Embodiment]
FIG. 7 is a partially enlarged view of the microprocessor 2 according to the fourth embodiment of the present invention. In particular, a portion of each of the three processor elements is shown. Since the microprocessor according to the fourth embodiment of the present invention is substantially the same as the microprocessor according to the third embodiment of the present invention, the difference between the two will be mainly described.

  In the microprocessor according to the fourth embodiment shown in FIG. 7, a decoder is provided in the microprocessor according to the first embodiment shown in FIG. 1 and the microprocessor according to the second embodiment shown in FIG. 2 is replaced with the one shown in FIG. 5, and the comparators (Comparator 1, Comparator 2, Comparator 3) are replaced with ALUs (Arithmetic Logic Units) (ALU1, ALU2, ALU3). ). Furthermore, (not shown) ALU (ALU1, ALU2, ALU3) includes not only decoder output and bus data, but also accumulator data (not shown) and binary data from a register (not shown). And are input.

  Such a configuration can be realized by additionally setting a decoder, a condition flag, and a bus that outputs a Wired-OR result of a decoding result to a normal parallel microprocessor. By such additional setting, the maximum value or the minimum value in a large number of data can be obtained.

  FIG. 8 is a partially enlarged view of another example of the microprocessor 2 according to the fourth embodiment of the present invention. In this other example, the output of the decoder is not output to the bus, but is temporarily stored in the accumulator 12, and the output of the accumulator 12 is supplied to the bus according to the value of the condition flag. The accumulator 12 stores the calculation result in the ALU except when obtaining the maximum value or the minimum value in a large number of data. That is, it functions as a normal accumulator.

  In this configuration, a bus necessary for obtaining a maximum value or a minimum value in a large number of data and a bus used in other normal operations are shared. With this configuration, it can be said that the entire circuit can be made compact.

[Fifth Embodiment]
FIG. 9 is a partially enlarged view of the microprocessor 2 according to the fifth embodiment of the present invention. The microprocessor according to the fifth embodiment of the present invention is substantially the same as another example of the microprocessor according to the fourth embodiment of the present invention shown in FIG.

  In the microprocessor according to the fifth embodiment shown in FIG. 9, the value output from the accumulator to the bus is once stored in the external register 20, and the value of the register 20 is transferred to another ALU (ALU1, ALU2 via another bus). , ALU3).

  According to such a configuration, since the value of the wired-OR result is once stored in the register 20, the value of the wired-OR result and the value of each accumulator can be compared in the next cycle. With this configuration, even if the number of processor elements increases, the entire microprocessor can be operated at high speed.

1 is a partially enlarged view of a microprocessor according to a first embodiment of the present invention. 1 is a schematic configuration diagram of a decoder used in a microprocessor according to a first embodiment of the present invention. It is a block diagram (FIG.3 (b)) of a comparator contained in the microprocessor which concerns on the 1st Embodiment of this invention, and the function content (FIG.3 (a)). It is a partial enlarged view of the microprocessor which concerns on the 2nd Embodiment of this invention. It is a circuit block diagram of the decoder in the microprocessor which concerns on the 3rd Embodiment of this invention. It is a schematic block diagram of the comparator utilized with the microprocessor which concerns on the 3rd Embodiment of this invention. It is a partial enlarged view of the microprocessor which concerns on the 4th Embodiment of this invention. It is a partially expanded view of another example of the microprocessor according to the fourth embodiment of the present invention. It is a partial enlarged view of the microprocessor which concerns on the 5th Embodiment of this invention. 1 is a schematic configuration diagram of a microprocessor according to the present invention. FIG.

Explanation of symbols

2 ... microprocessor, 4 ... processor element, 10 ... barrel shifter, 12 ... accumulator, 20 ... external register.

Claims (4)

A data processing device for obtaining a maximum value or a minimum value from a plurality of binary data,
More than the same number of condition flags as binary data;
More than the same number of decoders as binary data for decoding each binary data;
More than the same number of comparators as binary data;
A decoding result from each decoder has a bit-by-bit bus that is output as a Wire-OR.
Each condition flag, each decoder, and each comparator are associated with the target binary data,
If the value of the related condition flag is true, the result of decoding by the decoder is Wired-ORed bit by bit and output to the bus. If the related condition flag is false, the result is not output to the bus.
Each comparator compares the decoded result value of the associated decoder with the value of the wired-OR bus, and if the decoded result is smaller than the wired-OR bus value, the related condition flag A data processing device characterized by resetting the value of. Furthermore, a bit shift circuit is installed in association with the related condition flag, decoder, and comparator,
Each bit shift circuit inputs each binary data, shifts the bit by a predetermined width, and outputs it to the associated decoder,
The data processing apparatus according to claim 1, wherein a maximum value or a minimum value is calculated with respect to data of a bit width of a specific portion among a plurality of binary data bit widths. Each decoder
As a decoding result, from the LSB bit, the bit from which the input data is decoded to “1” is output as “1”, and the other bits are output as “0”.
The data processing apparatus according to claim 1, wherein the data processing apparatus is configured to output the negative logic. A data processing device according to any one of claims 1 to 3,
A data processing apparatus, wherein the comparator comprises an arithmetic operation unit (ALU) for performing arithmetic processing on a plurality of binary data.

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