JP4823929B2 - Multiple bus interface module and multiple bus system - Google Patents

Description

  The present invention relates to a multiple bus interface module that relays data transmission on a multiple bus, and a multiple bus system including the multiple bus interface module.

  Conventionally, a bus is selected as means for connecting a plurality of functional blocks such as a processor device and a storage device to each other. A system configuration using a bus is called a bus system.

  In this bus system, when a plurality of functional blocks are connected to the bus, one functional block uses the bus to transmit data to other functional blocks, thereby exclusively exchanging one bus. Will be used. Accordingly, since a plurality of data communications between functional blocks cannot be used simultaneously on one bus, a bus arbiter is required to arbitrate and manage the right to use the bus in response to a bus usage request from the functional block.

  That is, the bus arbiter plays a role of arbitrating and managing the order in which the buses are used when each functional block requests use of the buses.

  Here, when the number of buses is one in the bus system, if a large number of functional blocks try to use the bus at the same time, the blocks other than the functional block with the highest priority cannot be used. Therefore, there is a problem that the efficiency of data communication between functional blocks is deteriorated.

  In order to solve the above problems, Patent Documents 1 and 2 report a multiple bus system using a plurality of buses.

  The basic configuration and control of the multiple bus system will be described below with reference to FIG.

  The module 103 includes a functional block 104, a bus interface module 105, and a bus interface module 106. When it is desired to use the bus 101 or the bus 102, the functional block 104 sends a bus request signal to the bus 101 or the bus 102 via the bus interface module 105 or the bus interface module 106. Further, the bus request signal sent to the bus 101 or the bus 102 is sent to the bus arbiter 107 via the bus request lines 108 and 109.

  Here, the bus arbiter 107 monitors the usage state of the bus 101 and the bus 102. When a bus request signal from the function block 104 is detected, the bus arbiter 107 is in an empty state according to the bus usage state at that time. A bus confirmation response signal is sent to the bus via the bus acknowledge line 110 or 111. When both the buses 101 and 102 are in use, it is monitored that either one of the buses becomes empty. When the bus becomes empty, a bus confirmation response signal is sent to the bus acknowledge signal. It is sent out through the die line 110 or 111.

  Next, the functional block 104 detects the bus confirmation response signal via the bus interface module 105 or 106. The function block 104 determines that the bus use permission has been received from the bus arbiter 107 by detecting the bus confirmation response signal, and then the function block 104 uses the bus to which the bus confirmation response signal is supplied. Data is transmitted to and received from other modules 103.

  The above configuration is a multiple bus system in which the number of buses is doubled, but the number of buses can be increased. At this time, it is necessary to add a bus interface module corresponding to the newly added bus to the module 103.

  In recent years, a bus system using a ring bus that transmits data in one direction has been used. An example of a bus system using a ring bus is reported in Patent Document 3.

  The basic structure and operation of a bus system using a ring bus will be described below with reference to FIGS. 25 (a) and 25 (b).

  FIG. 25A is a block diagram of a bus system using a ring bus, and FIG. 25B is a detailed block diagram of a bus interface module (described as a node in Patent Document 3) 121 and a function block 122. It is.

  As shown in FIG. 25A, a bus system using a ring bus includes a ring bus 124 that transmits data in one direction, a plurality of bus interface modules 121, a functional block 122, and a bus arbiter 123. The bus interface module 121 is connected to adjacent bus interface modules 121 by a ring bus 124. Each bus interface module 121 is connected to a corresponding functional block 122. Further, each bus interface module 121 and each functional block 122 and the bus arbiter 123 are connected by a route different from the ring bus 124. As shown in FIG. 25B, the bus interface module 121 includes a multiplexer 125. Note that the bus interface module 121, the functional block 122, and the bus arbiter 123 shown in FIG. 25A are connected through a different path from the ring bus 124. In FIG. Absent.

  Next, the operation of the bus system using the ring bus will be described. First, an operation in which the functional block 122 outputs data will be described.

  When the functional block 122 wants to use the ring bus 124, it sends a bus request signal to the bus arbiter 123. When the bus arbiter 123 detects the bus request signal, the bus arbiter 123 sends a bus confirmation response signal to the multiplexer 125 and the functional block 122 according to a predetermined algorithm.

  Here, the functional block 122 sends data to the multiplexer 125, assuming that the use of the ring bus 124 is permitted by detecting the bus confirmation response signal. In the multiplexer 125, the same bus confirmation response signal as the signal detected by the functional block 122 has already been detected, and the data from the corresponding functional block 122 is sent from the output terminal of the multiplexer 125 to the ring bus 124. .

  On the other hand, when the ring bus 124 is being used by another functional block 122, the bus arbiter 123 does not send a bus acknowledgment signal to the multiplexer 125 and the functional block 122 until the ring bus 124 becomes empty.

  Here, while the multiplexer 125 does not detect the bus confirmation response signal, if data from another functional block 122 is input to the input terminal connected to the ring bus 124, the input data is output to the output terminal. Let it pass.

  Next, control for receiving data input from the upstream ring bus 124 will be described.

  Each bus interface module 121 sends data input from the upstream ring bus 124 to the corresponding function block 122. The function block 122 to which the data has been sent confirms whether the data is addressed to itself, and if the data is addressed to itself, fetches the data into itself.

  In the above description, a bus system using a ring bus having a single layer is described as an explanation of a bus system using a ring bus. However, a bus system in which ring buses are multiplexed can be configured. In the case of a bus system using a multiplexed ring bus of multiple layers, a bus interface module corresponding to the number of layers of multiplexed ring buses is provided for one corresponding functional block. Multiplexing can be realized.

  Patent Document 4 reports a method for increasing the use efficiency of a ring bus in a ring bus system. Here, a plurality of functional blocks are connected to one bus interface module by providing a module interface circuit in the bus interface module that connects the ring bus and the functional blocks.

As described above, in the bus system including the conventional ring bus system, the bus arbiter monitors the use status of each bus and arbitrates and manages the bus use request from each function block, thereby data between each function block. Communication is possible.
JP 61-117649 A (released on June 5, 1986) Japanese Patent Laid-Open No. 5-314063 (published on November 26, 1993) JP 2003-218891 A (published July 31, 2003) JP 63-124160 A (published May 27, 1988)

  However, when bus multiplexing is advanced, or when the number and position of functional blocks are changed, the conventional bus system is provided with a bus arbiter, so that the design of the bus arbiter needs to be changed.

  Furthermore, in the conventional bus system, there is a problem that the use efficiency of the bus is poor because one data communication is exclusively used for one bus.

  Specifically, referring to FIG. 26, when the bus 101 is used for data transmission / reception between the module 103a and the module 103f, and the bus 102 is used for data transmission / reception between the module 103b and the module 103c, as shown in FIG. In this case, since there is no usable bus connecting between the modules 103d and 103e, data cannot be transmitted / received.

  Furthermore, a bus arbiter that controls data transfer on the bus is also required in a conventional multi-bus system using a multiplexed multiple layer ring bus. By providing a bus arbiter in a multiple bus system using a ring bus, there is a problem that the bus system becomes a large-scale multiple bus system and the design becomes complicated.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multiple bus interface module that does not require a bus arbiter and can easily design an efficient multiple bus system, and the multiple bus. An object of the present invention is to provide a multiple bus system system including an interface module.

In order to solve the above problems, a multiple bus interface module according to the present invention provides
Each of the above intermediate internal interface modules
Connecting an input link from the functional block side to an output link to a downstream multiple bus interface module or an output link to the opposite side of the functional block; and
Connecting an input link from an upstream multiple bus interface module to an output link to the functional block side, or an output link to a downstream multiple bus interface module, or an output link to the opposite side of the functional block; and
An input link from the opposite side of the functional block is connected to an output link to the functional block side.

  In the above configuration, each intermediate internal interface module (hereinafter abbreviated as “internal module”) included in the multiple bus interface module (hereinafter abbreviated as “this module”) of this configuration appropriately connects its own input link and output link to each other. Thus, communication of data input from the functional block or the upstream module is relayed.

  Furthermore, each internal module in this module can exchange data flexibly with each other. For example, suppose that this module includes three internal modules (abbreviated as M1, M2, and M3) connected in series. It is assumed that M1 is connected to the functional block.

  At this time, M1 connects the input link from the functional block to the output link to the downstream downstream module or the output link to M2. Thereby, the data inputted from the functional block is transmitted to the downstream module or the adjacent M2. Further, the input link from the upstream main module is connected to the output link to the functional block, the output link to the downstream main module, or the output link to M2. Thereby, the data input from the upstream main module is transmitted to the functional block, the downstream main module, or the adjacent M2. Furthermore, the input link from M2 is connected to the output link to the functional block. As a result, the data input from M2 is output to the functional block.

  On the other hand, M2 connects the input link from M1 to the output link to this downstream module or the output link to M3. Thereby, the data input from M1 is transmitted to this downstream module or the adjacent M3. Further, the input link from the upstream main module is connected to the output link to M1, the output link to the downstream main module, or the output link to M3. As a result, the data input from the upstream main module is transmitted to M1, the downstream main module, or the adjacent M3. In addition, the input link from M3 is connected to the output link to M1. As a result, the data input from M3 is output to M1.

  On the other hand, M3 connects the input link from M2 to the output link to this downstream module. This is because no more internal modules are connected in series to M3. Thereby, the data input from M2 is transmitted to this downstream module. Furthermore, the input link from the upstream module is connected to the output link to M2 or the output link to the downstream module. Thereby, the data input from the upstream main module is output to M2 or the downstream main module.

  As described above, M1 to M3 are connected to each M1 to M3 by flexibly rearranging the connection status of their own input link and output link, and for data transmission to the module downstream and upstream Each bus can be used flexibly. For example, as an example, it is possible to establish a bus connection for transmitting data input from the upstream module to M2 to the downstream module. Alternatively, as another example, a bus connection for transmitting data input to M1 from the upstream module through M1, M2, and M3 from M3 to the downstream module can be established.

  In addition, even if the internal modules in a certain hierarchy connect links to each other between two modules, the same hierarchy is used between the other two modules regardless of the link connection construction status. Other internal modules can independently establish link connections. Specifically, it is assumed that five modules each including M1 to M3 are connected in a ring shape. Here, it is assumed that M1 of the first main module and M1 of the second main module construct a link connection for transmitting the first data. At this time, for example, the third main module and M1 and the fourth main module M1 can construct another link connection for transmitting second data different from the first data. It is. Thus, this module can use multiple buses efficiently.

  As described above, this module determines and constructs a transmission path for transmitting data by itself. For this reason, the multi-bus system including this module operates normally without the bus arbiter that was necessary in the past.

  When it is desired to add a functional block connected to the system, this module connected to the functional block may be added to the system. Furthermore, when it is desired to change the multiplicity of the buses, the number of intermediate modules included in each module need only be set in accordance with the number of buses. For these reasons, the design of the multiple bus system can be easily changed.

  Therefore, according to the multiple bus interface module of this configuration, the bus arbiter is not required, and an efficient multiple bus system can be easily designed.

In the multiple bus interface module according to the present invention,
The intermediate internal interface module is
When the data input from the input link from the upstream multiple bus interface module is data addressed to the functional block connected to the multiple bus interface module,
The input link from the upstream multiple bus interface module is connected to the output link on the functional block side.

  According to the above configuration, each internal module receives the input when the data input from the input link from the upstream module is data addressed to the functional block connected to the module including the internal module. Connect the link to the output link on the function block side. For example, if data addressed to the function block is input from the upstream module to M3 of a module connected to a function block, the input data passes through M3, M2, and M1, It is transmitted to the function block.

  Therefore, there is an effect that data transmitted from a certain functional block can be reliably transmitted to the destination functional block.

In the multiple bus interface module according to the present invention,
The intermediate internal interface module is
Of the data input from the input link from the function block side and the data input from the input link from the upstream multiple bus interface module, determine which has the higher priority,
As a result of the determination, it is preferable to connect the input link to which high priority data is input to the output link to the downstream multiple bus interface module.

  As described above, priority is given to the data communication of high priority data by giving priority to the input link to which the high priority data is input and connecting to the idle output link. A route can be established, and an effect of realizing efficient data communication is achieved.

In the multiple bus interface module according to the present invention,
Among the plurality of intermediate internal interface modules, the intermediate internal interface module at the other end functions as a terminal internal interface module,
The termination internal interface module is
Connect the input link from the functional block side to the output link to the downstream multiple bus interface module, and
An input link from an upstream multiple bus interface module is connected to an output link to a downstream multiple bus interface module or an output link on the functional block side.

  With the above features, the termination internal interface module does not have an output link to the opposite side of the functional block. Furthermore, since this terminal internal interface module is arranged at one end on the opposite side of the functional block, the multiple bus interface module does not have an output link whose output destination is unknown. Therefore, there is an effect that data loss can be prevented in data communication between functional blocks.

In order to solve the above problems, a multiple bus system according to the present invention provides
A multiplex bus system including any of the multiplex bus interface modules described above, and performing data communication between the functional blocks via a predetermined number of multiplex buses,
Each of the multiple bus interface modules includes the number of intermediate internal interface modules equal to or greater than the number of the multiple buses.

  According to said structure, there exists an effect which can provide the multibus system which does not require a bus arbiter and can design a multibus easily.

  As described above, the multiple bus interface module and the multiple bus system according to the present invention include a plurality of intermediate internal interface modules in the multiple bus interface module, and the intermediate internal interface module has its own input link and output link. Can be flexibly rearranged at your own discretion. Therefore, the multi-bus system including the multi-bus interface module does not require a bus arbiter, has the effects of being easy to design and efficiently using the multi-bus.

  Embodiments according to the present invention will be described below with reference to the drawings.

(Configuration of multiple bus interface module)
1 to 3 are a block diagram and an explanatory diagram showing a configuration of a multiple bus system using the multiple bus interface module according to the present invention.

  FIG. 1 is a block diagram of a multiple bus interface module according to the present invention. As shown in the figure, a multiplex bus interface module RB_HB (corresponding to the multiplex bus interface module described in the claims. Hereinafter, abbreviated as RB_HB) 2 is one terminal internal interface module FMg (in the claims). Corresponding to the described termination internal interface module (hereinafter abbreviated as FMg) 4 and at least one or more intermediate internal interface module FMn (corresponding to the intermediate internal interface module described in the claims; hereinafter abbreviated as FMn) 3).

  Further, FMn3 and FMg4 are connected in series in RB_HB2, and FMg4 is located at a position farthest from function module FB (corresponding to the function block described in the claims, hereinafter abbreviated as FB) 1. Has been placed.

  As shown in the figure, FMg4 is connected to upstream RB_HB2 (not shown), one level upstream ring bus 5a, and downstream RB_HB2 (not shown) connected to the upstream ring bus. It is connected to the downstream ring bus 5b of the same level, and further connected to one FMn3 arranged on the FB1 side.

  Further, among a plurality of FMn3 connected in series, one FMn3 arranged at one end is connected to FMg4, and one FMn3 arranged at the other end is connected to the functional module FB1. . Each FMn3 is connected to the upstream ring bus 5a in one hierarchy connected to the upstream RB_HB2 and the downstream ring bus 5b in the hierarchy connected to the downstream RB_HB2.

  As shown in the figure, the FMn3 and FMg4 described above correspond to the ring buses 5a and 5b for each layer, and are connected in parallel to the ring buses 5a and 5b. Further, FMg4 is arranged at a position farthest from FB1, and FMn3 is arranged in series between FB1 and FMg4.

  Therefore, when the number of layers of the ring buses 5a and 5b in the multi-bus system is N-fold, RB_HB2 includes N-1 FMn3 and one FMg4.

  Note that FMn3 connected to FMg4 and FMn3 connected to FB1 may be the same. Specifically, when the configuration of the ring bus system is a dual-layer ring bus, RB_HB2 is configured by one FMn3 and one FMg4.

(Configuration of FB1)
Next, FIG. 2 is a block diagram of FB1 connected to RB_HB2. The FB1 includes an RB_CN6 that is a connector module with the RB_HB2 and an FB_CORE5 that is a core of the functional module FB1 and has functions such as calculation and storage.

(Configuration of multiple bus system)
Next, FIG. 3 is a schematic diagram of a multiple bus system using the multiple bus interface module of the present invention. As shown in the figure, each FB1 is connected to a corresponding RB_HB2, and RB_HB2 is connected to the upstream and downstream RB_HB2 via the ring bus 5.

  In the figure, the bus system is composed of a double-layer ring bus. However, it is of course possible to construct a bus system using a multi-layer ring bus in order to expand the bus bandwidth. At this time, the corresponding FMn3 and FMg4 are required for RB_HB2 by the number of layers of the multiplexed ring bus. In other words, in the case of a bus system using a ring bus multiplexed N times, one RB_HB2 is configured by N-1 FMn and one FMg.

(Configuration of FMn3 and FMg4)
Next, with reference to FIG. 4, the detailed structure of FMn3 and FMg4 which concerns on this invention is demonstrated.

  FIG. 4 is a schematic diagram showing input links and output links of FMn3 and FMg4. As shown in the figure, the terminal internal interface module FMg4 is connected to the upstream link bus WI40 connected to the upstream RB_HB2 (not shown) and the downstream RB_HB2 (not shown). WO41 which is an output link to the downstream ring bus, RI42 which is an input link from FMn3 (corresponding to the input link from the function block side described in the claims), and an output link to FMn3 RO43 (corresponding to the output link to the functional block side described in the claims).

  On the other hand, FMn3, which is an intermediate internal interface module, has WI30, which is an input link from an upstream ring bus connected to upstream RB_HB2, WO31, which is an output link to a downstream ring bus connected to downstream RB_HB2, and FB1. Alternatively, RI32 (corresponding to the input link from the functional block side described in the claims) that is an input link from FMn3 on the FB1 side, and RO33 (patent) that is an output link of data to FMn3 on the FB1 or FB1 side GI34 (corresponding to the output link to the functional block side described in the claims) and the input link from FMn3 on the FMg4 or FMg4 side (input link from the opposite side of the functional block described in the claims) And an output link to FMg4 or FMn3 on the FMg4 side 5 (corresponding to the output links described in the appended claims, to the opposite side of the functional blocks), and a.

(Flow of request signal and request response signal between FBs)
Next, the outline of the flow of data communication between the FBs 1 in the present invention will be described with reference to FIGS.

  FIG. 5 is an explanatory diagram illustrating a transmission path between a request signal for requesting writing or reading and a request response signal for permitting writing or reading for the request signal between the FB 1a and the FB 1c.

  In FIG. 5, the FB that is the request source for writing or reading is FB1a, and the FB that is the request destination is FB1c. In addition, the FB 1b transmits a data signal to and from another FB (not shown) via the transmission path 12 in which a link has already been established. Note that the data signal is a data signal including FB-specific information data, in other words, a data signal including data to be written or read.

  In the multi-bus system according to the present invention, since there is no bus arbiter, a request signal from the FB 1a is directly output to the requesting FB 1c via the bus interface modules RB_HG2a to 2c and the ring bus 5.

  At this time, each of the RB_HGs 1a to 1c that has received the request signal for the write request or the read request confirms the use state of the connected downstream ring bus 5, and sets the downstream ring bus 5 in which the use state becomes empty. Select and transmit the request signal to the FB 1c of the request destination. When the request destination FB 1 c receives the request signal from the request source FB 1 a, the request destination FB 1 c sends a request response signal permitting writing or reading to the request source FB 1 a via the transmission path 11 through which the request signal is transmitted. Put out.

  As described above, when the FB 1a receives the request response signal from the FB 1c, the data communication link is established between the FB 1a and the FB 1c.

The request / response signal is transmitted back to the unidirectional ring bus. This is because the transmission path including the ring bus is configured with a plurality of connections corresponding to the data structure of the transmission signal, and the connection corresponding to the request response signal is a connection that is opposite to the single direction of the ring bus. This is because. Connections constituting this ring bus will be described below with reference to FIG.
FIG. 6 is an explanatory diagram showing connection of transmission paths including a ring bus between FBs.

  As shown in the figure, the transmission path including the ring bus is configured by connection corresponding to each information constituting the data structure of the transmission signal. Specifically, it corresponds to four information constituting a request signal or a data signal, connection corresponding to REQ, VAL, ERR, and DATA, and two information constituting a request response signal, ACK and CHG. It consists of wiring.

  Here, as shown in the figure, the connection corresponding to the request signal or the data signal transmits the signal using the connection in the forward direction of the ring bus, while the request response signal is in the opposite direction to the ring bus. The signal is transmitted using the connection. Therefore, the request response signal can be transmitted back to the unidirectional ring bus for data communication.

  The data structure of the request response signal, data signal, and request response signal will be described later.

(Data signal flow between FBs)
Next, transmission of a data signal after the link is established will be described with reference to FIG.

  FIG. 7 is an explanatory diagram showing a transmission path for transmitting a data signal after the link is established between the FB 1a and the FB 1c.

  After the link between the request source FB 1a and the request destination FB 1c is established, the FB 1a performs burst transmission of the data signal through the transmission path 11 in which the link is established. 5 and 7, the solid line indicates a transmission path for establishing a link and transmitting a data signal, and the dotted line indicates a transmission path for transmitting a request signal and a request response signal for establishing the link. Is shown.

(Transmission path in FMn3 and FMg4)
Next, with reference to FIG. 8 and FIG. 9, transmission paths for the input request signal, request response signal, and data signal in FMn 3 and FMg 4 will be described. Hereinafter, the request signal, the request response signal, and the data signal are referred to as a transmission signal unless particularly distinguished.

  FIG. 8 is an explanatory diagram showing a transmission path of a transmission signal inside the FMg4.

  As shown in the figure, the WI 40 connected to the upstream ring bus has a transmission path between the RO 43 that is an output unit to FMn3 and the WO 41 connected to the downstream ring bus. Furthermore, the RI 42 as an input unit from FMn3 has a transmission path only in the WO 41 connected to the downstream ring bus.

  FIG. 9 is an explanatory diagram showing a transmission path of a transmission signal inside FMn3.

  As shown in the figure, the WI 30 connected to the upstream ring bus includes an RO 33 that is an output unit to the FB 1 or FB 1 side FMn 3, a WO 31 connected to the downstream ring bus, and an FMg 4 or FMg 4 side FMn 3. A transmission path is connected to the GO 35 which is an output unit. Furthermore, RI32, which is an input unit from FB1 or FB1 side FMn3, has a transmission path between WO31 connected to the downstream ring bus and GO35, which is an output unit to FMg4 or FMn3 on the FMg4 side. . Also, the GI 34 that is an input unit from the FMg4 or FMn3 on the FMg4 side has a transmission path only in the RO33 that is the output unit to the FMn3 on the FB1 or FB1 side.

  Next, operation algorithms in FMn3 and FMg4 shown in FIGS. 8 and 9 will be described.

(Operation algorithm of FMg4)
First, the operation algorithm of FMg4 will be described with reference to FIG. For the transmission signal inputted to the WI40 of FMg4, whether the transmission signal is a transmission signal addressed to FB1 corresponding to RB_HB2 including the FMg4 (hereinafter referred to as a signal addressed to the self module) Determine. Here, when the transmission signal input to the WI 40 is a signal addressed to the self module, the FMg4 establishes a transmission path between the WI 40 and the RO 43 and outputs the input transmission signal from the RO 43.

  On the other hand, if the transmission signal input to the WI 40 is not a signal addressed to the self module, the FMg4 establishes a transmission path between the W 140 and the WO 41, and connects the input data to the downstream ring connecting the WO 41. The data is transmitted to the downstream RB_HB2 via the bus.

  Note that, in order to determine whether the transmission signal input to the WIg 40 of the FMg4 is a signal addressed to the own module, the transmission signal is recorded with an ID for specifying the destination FB1. The FMg4 detects the ID recorded in the input transmission signal and performs the above determination. The detailed configuration of the transmission signal will be described later.

  For the transmission signal input to the RI 42, the FMg4 establishes a transmission path between the RI 42 and the WO 41, and transmits the input transmission signal via a downstream ring bus connected to the WO 41. To the downstream RB_HB2.

  When different transmission signals are input to RI42 and WI40, and these two transmission signals are transmission signals output from WO41, FMg4 is recorded in each of the priority levels recorded in the two transmission signals. A PRI value (corresponding to the priority described in the claims) is detected. Further, FMg4 compares the two detected PRI values and establishes a transmission path between the RI 42 or WI 40 to which a transmission signal having a high priority is input and the WO 41.

  On the other hand, a transmission signal determined to have a low priority in the comparison of PRI values is in a standby state at the input RI 42 or WI 40. Here, after the data communication of the transmission signal determined to have a high priority is completed, in other words, after the transmission path connected to the WO 41 becomes free, FMg4 is determined to have a low priority. A transmission path is established between the RI 42 or WI 40 to which the transmission signal is input and the WO 41, and the transmission signal is output from the WO 41.

  When a transmission signal determined to have a low priority is in a standby state and a transmission signal with a high priority is newly input to the RI 42 or WI 40, the transmission signal with a low priority is assigned a priority. There is a problem that data communication is not completed because the comparison continues to be lost. Here, FMg4 increases the PRI value of the transmission signal that is in the standby state at regular time intervals, thereby increasing the priority of the transmission signal that is in the standby state. Thereby, FMg4 prevents the problem that the data communication of the transmission signal with low priority is not completed.

  In addition, when one of the transmission signals is a data signal, in other words, when the link has already been established, FMg4 does not compare the PRI values and gives priority to the transmission path in which the link is established. To do.

(FMn3 operation algorithm)
Next, the operation algorithm of FMn3 will be described with reference to FIG. For a transmission signal input to the WI30 of FMn3, the FMn3 determines whether the transmission signal is a transmission signal addressed to FB1 corresponding to RB_HB2 including the FMn3 (hereinafter referred to as a signal addressed to the own module). . Here, when the transmission signal is a signal addressed to the self module, the FMn3 establishes a transmission path between the WI 30 and the RO 33, and the input transmission signal is connected to the RO 33 on the FB1 or FB1 side. Output to FMn3.

  On the other hand, when the transmission signal input to the WI 30 is not a signal addressed to the self module, the FMn 3 confirms whether the ring bus connected to the WO 31 is in an empty state. At this time, if the ring bus connected to the WO 31 is in an empty state, the FM n3 establishes a transmission path between the WI 30 and the WO 31, and transmits the transmission signal input to the WI 30 to the downstream connected to the WO 31. To the downstream RB_HB2 via the ring bus on the side. In addition, when the ring bus connected to the WO 31 is in use by other data communication, the FMn 3 establishes a transmission path between the WI 30 and the GO 35, and transmits the input transmission signal via the GO 35. Output to FMg4 or FMn3 on the FMg4 side. In order to determine whether the transmission signal input to the WI30 of FMn3 is a signal addressed to the own module, FMn3 detects and confirms the ID recorded in the transmission signal.

  Further, the FMn3 confirms whether the ring bus connected to the WO 31 is in an empty state with respect to the transmission signal input to the RI 32. At this time, if the ring bus connected to the WO 31 is empty, a transmission path is established between the RI 32 and the WO 31, and the input transmission signal is sent to the downstream ring bus connected to the WO 31. To the downstream RB_HB2. When the ring bus connected to WO 31 is in use by other data communication, a transmission path is established between RI 32 and GO 35, and the input transmission signal is transmitted from GO 35 to the FMg4 or FMg4 side. To FMn3.

  Further, for the transmission signal input to the GI 34, the FMn3 establishes a transmission path between the GI 34 and the RO 33, and outputs the input transmission signal from the RO 33. Here, it is confirmed that the transmission signal input to the GI 34 is a signal addressed to the self module in the FMn3 or FMg4 in the same RB_HB2, in other words, the FMn3 or FMg4 connected to the GI34. Therefore, the transmission path from the GI 34 is connected only to the RO 33.

  Note that when different transmission signals are input to the GI 34 and the WI 30 and these two transmission signals are transmission signals output from the RO 33, FMn3 indicates the respective priority levels recorded in the two transmission signals. Is detected. Further, FMn3 compares the two detected PRI values, and establishes a transmission path between GI 34 or WI 30 to which a transmission signal having a high priority is input and RO 33.

  On the other hand, a transmission signal determined to have a low priority in the PRI value comparison is in a standby state at the input GI 34 or WI 30. Here, after the data communication of the transmission signal determined to have a high priority is completed, in other words, after the transmission path connected to the RO 33 becomes empty, FMn3 is determined to have a low priority. A transmission path is established between the GI 34 or WI 30 to which the transmission signal is input and the RO 33, and the transmission signal is output from the RO 33.

  When a transmission signal determined to have a low priority is in a standby state and a transmission signal with a high priority is newly input to the GI 34 or WI 30, the transmission signal with a low priority is assigned a priority. There is a problem that data communication is not completed because the comparison continues to be lost. Here, FMn3 increases the PRI value of the transmission signal that is in the standby state at regular intervals, and increases the priority of the transmission signal that is in the standby state. Thereby, FMn3 prevents the problem that the data communication of the transmission signal with low priority is not completed.

  When one of the transmission signals is a data signal, in other words, when the link has already been established, the PRI value is not compared, and the transmission path with the established link is given priority.

  Next, when different transmission signals are input to the RI 32 and the WI 30, and these two transmission signals are transmission signals output from the WO 31, FMn3 is recorded in each of the two transmission signals. A PRI value indicating the degree is detected. Further, the FMn3 compares the two detected PRI values and establishes a transmission path between the RI 32 or the WI 30 to which a transmission signal having a high priority is input and the WO 31. On the other hand, a transmission path is established between the RI 32 or the WI 30 to which the transmission signal determined to have a low priority in the comparison of the PRI values is connected to the GO 35.

  Again, if one of the transmission signals is a data signal, in other words, if the link has already been established, FMn3 does not compare the PRI values and does not compare the transmission path with which the link is established. Never cut.

(Data communication flow at the time of write request)
Next, the operation of RB_HB2 from transmission of a write request signal to establishment of a link and transmission of a data signal between functional modules FB1 will be described with reference to FIGS.

  In FIG. 10 to FIG. 13, the FB that is the write request source is FB1a, and the FB that is the request destination is FB1c. In addition, the FB 1b transmits a data signal to and from another FB (not shown) via the transmission path 12 in which a link has already been established.

  FIG. 10 is an explanatory diagram showing a stage in which a request signal for a write request from the FB 1a is transmitted.

  As shown in the figure, the FB 1 a sends a write request signal to the FB 1 c using the transmission path 11. The request signal from the FB 1a is input to the RB_HB 2a corresponding to the FB 1a. Here, as shown in the figure, the RB_HB 2a establishes the transmission path 11 via the idle downstream ring bus and transmits the request signal to the next RB_HB 2b.

  Next, FIG. 11 is an explanatory diagram showing a stage where the request signal of the write request from the FB 1a has reached the FB 1c as the request destination.

  As shown in the figure, the RB_HB 2b confirms that the input request signal is not a signal addressed to its own module, and outputs the request signal to the downstream ring bus. However, in the RB_HB 2b that has received the request signal from the RB_HB 2a, the downstream ring bus in the same hierarchy as the upstream ring bus that has received the request signal is already used by the transmission path 12 by the FB 1b. Accordingly, the RB_HB 2b selects a free downstream ring bus in a different hierarchy from the upstream ring bus that has received the request signal, and establishes the transmission path 11. Using the established transmission path 11, the RB_HB 2b outputs the request signal to the RB_HB 2c.

  Further, the RB_HB 2c confirms that the input request signal is a signal addressed to its own module, and outputs the request signal to the FB 1c.

  Next, FIG. 12 is an explanatory diagram illustrating a stage where the request response signal from the FB 1c has reached the FB 1a that is the write request source.

  As shown in the figure, after receiving the write request signal from the FB 1a, the FB 1c outputs a request response signal to the request signal to the FB 1a via the transmission path 11 through which the request signal is transmitted. Here, when the FB 1a receives the request response signal from the FB 1c in response to the write request signal, a link from the FB 1a to the FB 1c is established.

  Next, FIG. 13 is an explanatory diagram showing a stage in which data communication after link establishment is performed between the FB 1a and the FB 1c.

  After the link from FB1a to FB1c described with reference to FIG. 12 is established, as shown in FIG. 13, FB1a sends a data signal as write data to FB1c via transmission path 11 with the link established. To transmit.

(Flow of data communication at the time of read request)
Next, the operation of RB_HB2 from the transmission of the read request signal to the establishment of the link and the transmission of the data signal between the functional modules FB will be described with reference to FIGS.

  14 to 18, the read request source FB is FB1a and the request destination FB is FB1c. In addition, the FB 1b transmits a data signal to the other FB (not shown) through the transmission path 12 in which a link has already been established.

  FIG. 14 is an explanatory diagram showing the stage at which the read request signal from the FB 1a to the FB 1c has arrived.

  As shown in the figure, the FB 1 a sends a read request signal to the FB 1 c using the transmission path 11. The request signal from the FB 1a is input to the RB_HB 2a corresponding to the FB 1a. Here, as shown in the figure, the RB_HB 2a establishes the transmission path 11 via the idle downstream ring bus and transmits the request signal to the next RB_HB 2b.

  The RB_HB 2b confirms that the input request signal is not a signal addressed to its own module, and outputs the request signal to the downstream ring bus. However, in the RB_HB 2b that has received the request signal from the RB_HB 2a, the downstream ring bus in the same hierarchy as the upstream ring bus that has received the request signal is already used by the transmission path 12 by the FB 1b. Accordingly, the RB_HB 2b selects a free downstream ring bus in a different hierarchy from the upstream ring bus that has received the request signal, and establishes the transmission path 11. Using the established transmission path 11, the RB_HB 2b outputs the request signal to the RB_HB 2c.

  Further, the RB_HB 2c confirms that the input request signal is a signal addressed to its own module, and outputs the request signal to the FB 1c.

  Next, FIG. 15 is an explanatory diagram showing a stage where a request response signal from the FB 1c reaches the FB 1a in response to a read request signal from the FB 1a.

  Upon receiving the read request signal from the FB 1a, the FB 1c outputs a request response signal for the request signal to the FB 1a via the transmission path 11 through which the request signal is transmitted, as shown in FIG. Simultaneously with outputting the request response signal, the FB 1 c outputs a write request signal to the FB 1 a via a transmission path different from the transmission path 11 for the read request signal.

  Next, FIG. 16 is an explanatory diagram showing a stage where the write request signal from the FB 1c has reached the FB 1a.

  As shown in the figure, the RB_HB 2c that has received the write request signal from the FB 1c selects a downstream ring bus that becomes free, and outputs the write request signal to the RB_HB 2b. Next, the RB_HB 2b confirms that the input request signal is not a signal addressed to its own module, and outputs the request signal to the RB_HB 2a through the idle downstream ring bus. The RB_HB 2a confirms that the input write request signal is a signal addressed to its own module, and outputs the write request signal to the FB 1a.

  Next, FIG. 17 is an explanatory diagram showing a stage where a request response signal from FB 1a reaches FB 1c in response to a write request signal from FB 1c.

  As shown in the figure, after receiving the write request signal from the FB 1c, the FB 1a outputs a request response signal to the write request signal to the FB 1c via the transmission path 13 through which the write request signal is transmitted. Here, when the FB 1c receives the request response signal from the FB 1a in response to the write request signal, the link from the FB 1c to the FB 1a is established.

  Next, FIG. 18 is an explanatory diagram illustrating a stage in which data communication after link establishment is performed between the FB 1c and the FB 1a.

  After the link from FB1c to FB1a described with reference to FIG. 17 is established, as shown in FIG. 18, FB1c sends a data signal as read data to FB1a via the transmission path 13 with which the link is established. To transmit.

(Write sequence between FBs)
FIGS. 19A and 19B show the data write and read sequences between the functional modules FB described above.

  FIG. 19A is a sequence diagram showing transmission / reception of transmission signals between the write request source FB and the write request destination FB at the time of data writing.

  In the figure, FB (SRC) indicates a write request source FB, and FB (DST) indicates a write request destination FB. Write REQ indicates a write request signal, Write ACK indicates a write request response signal with respect to the write request signal, and Burst Write indicates a data signal by burst transmission.

  Furthermore, Link Search indicates the transmission time from FB (SRC) to FB (DST) in the transmission of Write REQ. Fixed Link is the time from the output of FB (DST) to the arrival of FB (SRC) in the transmission of Write ACK, that is, the time from the output of FB (DST) to the establishment of the link. Is shown. Burst transmission indicates the time required for burst transmission of the data signal.

  As shown in the figure, the Write REQ output from the FB (SRC) is received by the FB (DST), and then the FB (DST) outputs the Write ACK, and the FB (SRC) receives the Write ACK. At this time, a link between FB (SRC) and FB (DST) is established. Next, since the link from FB (SRC) to FB (DST) is established, FB (SRC) performs burst transmission of Burst Write to FB (DST).

(Read sequence between FBs)
FIG. 19B is a sequence diagram illustrating delivery of transmission signals between the read request source FB and the read request destination FB when reading data.

  In the figure, FB (SRC) indicates the read request source FB, and FB (DST) indicates the read request destination FB. Read REQ indicates a read request signal, Read ACK indicates a read request response signal for the read request signal, and Write REQ indicates a write request signal output from the read request destination FB (DST). , Write ACK indicates a write request response signal to the write request signal from the FB (DST), and Burst Write indicates a data signal by burst transmission.

  Further, Read Link Search indicates a transmission time from FB (SRC) to FB (DST) in transmission of Read REQ. Acknowledge indicates the transmission time of Read ACK with respect to Read REQ from FB (SRC). Write Link Search indicates the transmission time from FB (DST) to FB (SRC) in transmission of Write REQ. Fixed Link is the time from the output of FB (SRC) to the arrival of FB (DST) in the transmission of Write ACK, that is, the time from the output of FB (SRC) to the establishment of the link. Is shown. Burst transmission indicates the time required for burst transmission of the data signal.

  As shown in the figure, Read REQ output from FB (SRC) is received by FB (DST), and then FB (DST) outputs Read ACK and FB (SRC) receives Read ACK. Here, the FB (DST) outputs a Write REQ to the FB (SRC) at the same time as the Read ACK is output. The FB (SRC) that has received the Write REQ outputs a Write ACK to the FB (DST), and the FB (DST) receives the Write ACK. At this time, the link between FB (SRC) and FB (DST) is established. Next, since the link from FB (SRC) to FB (DST) is established, FB (DST) performs burst transmission of the burst write to FB (SRC).

(Data structure of transmission signal)
Next, a data structure of a transmission signal for transmitting data between FBs in the embodiment of the present invention will be described with reference to FIGS.

  FIG. 20A is an explanatory diagram showing a data structure of a write or read request signal and a data signal by burst transmission, and FIG. 20B is an explanation showing a data structure of a request response signal for the request signal. FIG.

  As shown in FIG. 20A, the data structure of the request signal and the data signal includes a REQ flag indicating whether the transmission signal is a request signal, a VAL flag indicating whether the transmission signal is data transmitted in a burst, and a link. It has an ERR flag for notifying the data output destination that disconnection or the like has occurred. In the DATA shown in the figure, different information is recorded for each type of transmission signal, and details will be described later. The REQ flag, VAL flag, and ERR flag are expressed by 1-bit information. DATA is expressed by a variable bit length of 8 to 256 bits.

  Further, as shown in FIG. 20B, the data structure of the request response signal for the request signal indicates that the ACK flag indicating whether the transmission signal is the request response signal and the transmission path of the request signal have been changed. And a CHG flag shown. The ACK flag and the CHG flag are expressed by 1-bit information.

(Data structure of transmission signal at the time of writing)
An example of the data structure of the request signal at the time of a write request will be described below with reference to FIG.

  FIG. 21A is an explanatory diagram showing the data structure of a write request signal at the time of a write request.

  As shown in the figure, since the REQ flag indicates that this transmission signal is a request signal, 1 information is recorded. Since the request signal is not transmitted in bursts, 0 information is recorded in the VAL flag. In the example in the figure, it is assumed that an error such as link disconnection has not occurred, and information of 0 is recorded in the ERR flag.

  Here, DATA is 64 bits, and the data structure in DATA as a request signal at the time of a write request is as follows.

  As shown in the figure, the data structure in DATA includes an SRC_ID which is an ID for identifying each FB corresponding to the requesting FB, a DST_ID which is an ID corresponding to the requesting FB, and the transmission signal is written. RW, which is information indicating whether it is a request signal, DIR, which is information indicating the direction of data flow, PRI, which is information indicating the priority of the transmission signal, and a flag when performing single-word transmission of half the size It is composed of a certain SHW, LEN that is information indicating the transmission length of data during burst transmission, and OPT that is FB-specific information data.

  The SRC_ID and DST_ID are represented by 8-bit information, RW, DIR, and SHW are represented by 1-bit information, PRI is represented by 5-bit information, LEN is represented by 8-bit information, and OPT is 32-bit information. Expressed by information.

  In the figure, SRC_ID records 00 information, which is the ID of the transmission source FB, and DST_ID records information 02, which is the ID of the transmission destination FB, in the RW. Records 1 information indicating a write request signal, DIR records 0 information indicating the data traveling direction, and PRI stores the priority of the transmission signal. 10 is recorded, SHW is recorded with 0 information indicating that single word transmission is not being performed, and LEN is a target of a write request during burst transmission. 03 information indicating the transmission length of the data is recorded. Since the transmission signal is a write request signal, no information is recorded in OPT.

  Next, an example of the data structure of the request response signal at the time of a write request will be described with reference to FIG.

  FIG. 21B is an explanatory diagram showing the data structure of the request response signal with respect to the write request signal.

  As shown in the figure, the ACK flag records 1 information indicating that it is a request response signal, and the CHG flag indicates that there is no change from the transmission path of the request signal. 0 information is recorded.

(Data structure of transmission signal at the time of reading)
Hereinafter, an example of the data structure of the request signal at the time of a read request will be described with reference to FIG.

  FIG. 22 is an explanatory diagram showing the data structure of a read request signal at the time of a read request.

  As shown in the figure, the REQ flag records 1 information to indicate that this transmission signal is a request signal. Since the request signal is not transmitted in bursts, 0 information is recorded in the VAL flag. In the example in the figure, it is assumed that an error such as link disconnection has not occurred, and information of 0 is recorded in the ERR flag.

  Here, DATA is 64 bits, and the data structure in DATA is as follows as a request signal at the time of a write request.

  As shown in the figure, the data structure in DATA includes an SRC_ID that is an ID for identifying each FB corresponding to the requesting FB, a DST_ID that is an ID corresponding to the requesting FB, and the transmission signal is read out. RW, which is information indicating whether it is a request signal, DIR, which is information indicating the direction of data flow, PRI, which is information indicating the priority of the transmission signal, and a flag when performing single-word transmission of half the size It is composed of a certain SHW, LEN that is information indicating the transmission length of data during burst transmission, and OPT that is FB-specific information data.

  The SRC_ID and DST_ID are represented by 8-bit information, RW, DIR, and SHW are represented by 1-bit information, PRI is represented by 5-bit information, LEN is represented by 8-bit information, and OPT is 32-bit information. Expressed by information.

  In the figure, SRC_ID records 00 information, which is the ID of the transmission source FB, and DST_ID records information 02, which is the ID of the transmission destination FB, in the RW. Records 0 information indicating a read request signal, DIR records 0 information indicating the data traveling direction, and PRI stores the priority of the transmission signal. 10 is recorded, SHW is recorded with 0 information indicating that single word transmission is not being performed, and LEN is a target of a write request during burst transmission. 03 information indicating the transmission length of the data is recorded. Since the transmission signal is a write request signal, no information is recorded in OPT.

  The data structure of the request response signal for the read request signal has the same configuration as the request response signal for the write request signal shown in FIG. Is omitted.

(Data signal data structure)
Next, with reference to FIG. 23, a data structure of a data signal transmitted in burst will be described. As shown at the same time, as for the data structure of the data signal, a REQ flag indicating whether the transmission signal is a request signal or a data signal, a VAL flag indicating whether the transmission signal is data to be transmitted in burst, a link disconnection, or the like has occurred. And an ERR flag for informing the data output destination. In the figure, the REQ flag records 0 information indicating a data signal, and the VAL flag records 1 information indicating burst transmission data. In the ERR flag, 0 information indicating that no link disconnection or the like has occurred is recorded. Further, FB-specific information data is recorded in DATA. Here, the bit length of DATA is determined in accordance with the system architecture to be used, and in the example in the figure, the bit length of DATA is 64 bits. Therefore, when the information data written in the request destination FB exceeds 64 bits, the information data is transmitted by multiple burst transmissions.

  Note that the number of bits of each information constituting the data structure of the transmission signal is not limited to the number of bits, and can be changed as appropriate depending on the number of FBs connected to the bus system.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The present invention provides a multiplex bus interface that can efficiently use a multiplex bus without requiring a bus arbiter in a multiplex bus system that performs data communication using a multiplex bus. It can be used in a multiprocessor system in which a plurality of processor devices and storage devices are interconnected.

It is a block diagram which shows the structure of multiple bus | bath interface module RB_HB in embodiment of this invention. It is a block diagram which shows the structure of the functional module FB connected to the multiplex bus interface module RB_HB in embodiment of this invention. It is a schematic diagram which shows the multiple bus system using the ring bus | bath which becomes a double hierarchy in embodiment of this invention. It is a schematic diagram which shows the structure of internal interface module FMn and FMg in multi-bus interface module RB_HB in embodiment of this invention. It is explanatory drawing which shows the step in which the link is established between the functional modules FB in embodiment of this invention. It is explanatory drawing which shows the connection of the transmission path between FB in embodiment of this invention. It is explanatory drawing which shows the step which is carrying out the burst transmission of the data signal between the functional modules FB in embodiment of this invention. It is a schematic diagram which shows the transmission path | route in the internal interface module FMg in embodiment of this invention. It is a schematic diagram which shows the transmission path | route in the internal interface module FMn in embodiment of this invention. It is explanatory drawing which shows the step which is transmitting the request signal at the time of the write request in embodiment of this invention. It is explanatory drawing which shows the step in which the request signal at the time of a write request | requirement reached | attained the functional module FB of a request destination in embodiment of this invention. It is explanatory drawing which shows the step in which the request response signal at the time of a write request | requirement reaches | attains the request source functional module FB, and the link is established in embodiment of this invention. It is explanatory drawing which shows the step in which the burst transmission of the data signal is performed between the functional modules FB via the transmission path | route in which the link was established in FIG. It is explanatory drawing which shows the step in which the request signal at the time of a read request | requirement reached | attained the functional module FB of a request destination in embodiment of this invention. It is explanatory drawing which shows the step which the request response signal at the time of the read request | requirement in embodiment of this invention arrived at the function module FB of a request origin. FIG. 10 is an explanatory diagram showing a stage at which a write request signal from a read request destination reaches a read request source functional module FB at the time of a read request in the embodiment of the present invention. FIG. 17 is an explanatory diagram showing a stage where a request response signal for the write request signal of FIG. 16 reaches the functional module FB and a read request link is established in the embodiment of the present invention. It is explanatory drawing which shows the step in which the burst transmission of the data signal is performed between the functional modules FB via the transmission path | route in which the link was established in FIG. (A) is a sequence diagram showing a flow of a transmission signal at the time of a write request in the embodiment of the present invention, and (b) shows a flow of the transmission signal at the time of a read request in the embodiment of the present invention. FIG. (A) And (b) is explanatory drawing which shows the data structure of the transmission signal in embodiment of this invention. (A) is explanatory drawing which shows the data structure of the request signal at the time of writing in embodiment of this invention, (b) is description which shows the data structure of the request response signal in embodiment of this invention. FIG. It is explanatory drawing which shows the data structure of the read request signal in embodiment of this invention. It is explanatory drawing which shows the data structure of the data signal in embodiment of this invention. It is a block diagram which shows the multiplex bus system using the multiplex bus in a prior art example. (A) And (b) is a block diagram which shows the bus system using the ring bus in a prior art example. It is explanatory drawing which shows the transmission path which can be used in a multibus system in a prior art example.

Explanation of symbols

1 Function module FB (Function block)
1a Function module FB (Function block)
1b Function module FB (Function block)
1c Function module FB (Function block)
2 Multiple bus interface module RB_HB (Multiple bus interface module)
2a Multiple bus interface module RB_HB (Multiple bus interface module)
2b Multiple bus interface module RB_HB (Multiple bus interface module)
2c Multiple bus interface module RB_HB (Multiple bus interface module)
3 Intermediate internal interface module FMn (Intermediate internal interface module)
4 Termination internal interface module FMg (Termination internal interface module)
5 ring bus 5a upstream ring bus 5b downstream ring bus 101 bus 102 bus 103 module 103a module 103b module 103c module 103d module 103e module 103f module 104 functional block 105 bus interface module 106 bus interface module 106 bus arbiter 121 bus interface module 122 function Block 123 Bus Arbiter 124 Ring Bus 124a Ring Bus 124b Ring Bus 126a Module 126b Module 126c Module 126d Module 126d Module 126e Module 126f Module

Claims (5)

A multi-bus interface module that is individually connected to the functional block and connected to the upstream and downstream multi-bus interface modules, and relays data communication between the functional blocks,
A plurality of intermediate internal interface modules connected in series with each other;
Of the plurality of intermediate internal interface modules, one at one end is connected to the functional block,
Each of the above intermediate internal interface modules
Connecting an input link from the functional block side to an output link to a downstream multiple bus interface module or an output link to the opposite side of the functional block; and
Connecting an input link from an upstream multiple bus interface module to an output link to the functional block side, or an output link to a downstream multiple bus interface module, or an output link to the opposite side of the functional block; and
A multi-bus interface module, wherein an input link from the opposite side of the functional block is connected to an output link to the functional block side. The intermediate internal interface module is
When the data input from the input link from the upstream multiple bus interface module is data addressed to the functional block connected to the multiple bus interface module,
2. The multiple bus interface module according to claim 1, wherein an input link from an upstream multiple bus interface module is connected to an output link on the functional block side. The intermediate internal interface module is
Of the data input from the input link from the function block side and the data input from the input link from the upstream multiple bus interface module, determine which has the higher priority,
2. The multi-bus interface module according to claim 1, wherein an input link to which high priority data is input as a result of the determination is connected to an output link to a downstream multi-bus interface module. Among the plurality of intermediate internal interface modules, the intermediate internal interface module at the other end functions as a terminal internal interface module,
The termination internal interface module is
Connect the input link from the functional block side to the output link to the downstream multiple bus interface module, and
2. The multiple bus interface according to claim 1, wherein an input link from an upstream multiple bus interface module is connected to an output link to a downstream multiple bus interface module or an output link on the function block side. module. A multiplex bus interface module according to any one of claims 1 to 4, wherein the multiplex bus system performs data communication between the functional blocks via a predetermined number of multiplex buses.
Each of the multiple bus interface modules includes the number of intermediate internal interface modules equal to or greater than the number of the multiple buses.

Images