JP4819407B2 - Semiconductor device having trimming circuit, trimming method and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a trimming circuit, a trimming method thereof, and a manufacturing method thereof, and more particularly, to a trimming circuit capable of performing trimming related to a plurality of circuits having mutually related characteristics in one step. The present invention relates to a semiconductor device having the same, a trimming method thereof, and a manufacturing method thereof.

Conventionally, when there are multiple portions where trimming is performed to adjust circuit characteristics, and when these circuit characteristics are related to each other, trimming is first performed to determine the characteristics of the most reference circuit, Trimming was performed to determine the characteristics of the next circuit in response to the trimming result.
FIG. 5 is a circuit diagram showing an example of a conventional constant voltage circuit, and a conventional trimming method will be described with reference to FIG.
The constant voltage circuit 100 of FIG. 5 forms a series regulator, generates a reference voltage generation circuit 101 that generates and outputs a predetermined reference voltage Vr, and generates and outputs a divided voltage Vo1 by dividing the output voltage Vo. An output voltage detection circuit 102, an output transistor M15 composed of a PMOS transistor for controlling a current output to the output terminal OUT in accordance with a signal input to the gate, and an output transistor so that the divided voltage Vo1 becomes the reference voltage Vr. And an error amplifier circuit 103 for controlling the operation of M15.

The reference voltage generation circuit 101 includes two depletion type NMOS transistors M1 and M3, two enhancement type NMOS transistors (hereinafter referred to as NMOS transistors) M2 and M4, and two fuses F5 and F6 as trimming means. Has been.
In a state where the fuses F5 and F6 are not cut, that is, in an initial state where trimming is not performed, the depletion type NMOS transistors M1 and M3 are each biased to 0. Therefore, specific drain currents id1 and id3 flow correspondingly to the respective drains of the depletion type NMOS transistors M1 and M3. The sum of the drain currents id2 and id4 of the NMOS transistors M2 and M4 is the same as the sum of the drain currents id1 and id3, the gates of the NMOS transistors M2 and M4 are connected, and the connection is connected to the drain of the NMOS transistor M2. It is connected. Thus, the gate voltages of the NMOS transistors M2 and M4 are set to voltages determined by the drain currents id2 and id4, and the voltages become the reference voltage Vr.

  On the other hand, the temperature characteristics of the reference voltage Vr change due to the influence of manufacturing process variations. FIG. 6 is a diagram illustrating an example of temperature characteristics of the reference voltage Vr, where the vertical axis is the reference voltage Vr and the horizontal axis is the temperature. In FIG. 6, a temperature characteristic S1 indicated by a solid line is a target temperature characteristic. The reference voltage Vr becomes maximum near 25 ° C., and gradually increases as the temperature rises or falls from around 25 ° C. However, the fluctuation of the reference voltage Vr can be kept small over a wide temperature range. In FIG. 6, a temperature characteristic S2 indicated by a one-dot chain line and a temperature characteristic S3 indicated by a broken line are characteristic diagrams when the temperature characteristic changes due to a variation in the manufacturing process. In the temperature characteristic S2, the reference voltage Vr increases as the temperature increases, and in the temperature characteristic S3, the reference voltage Vr decreases as the temperature increases. In the temperature characteristics S2 and S3, the change of the reference voltage Vr due to temperature fluctuation is large, and when used as it is as the reference voltage source of the constant voltage circuit, the specification of the constant voltage circuit cannot be satisfied.

The temperature characteristics of the reference voltage Vr can be controlled by changing the ratio W / L of the gate width W and the gate length L of the MOS transistor used in the reference voltage generation circuit 101. In the case of the temperature characteristic S2, the W / L of the depletion type NMOS transistors M1 and M3 can be reduced, or the W / L of the NMOS transistors M2 and M4 can be increased to approximate the temperature characteristic S1.
Further, when the temperature characteristic is S3, the W / L of the depletion type NMOS transistors M1 and M3 can be increased, or the W / L of the NMOS transistors M2 and M4 can be reduced to approximate the temperature characteristic S1.

However, since the completed semiconductor device cannot reduce or increase the element area of the MOS transistor, each of the depletion type NMOS transistor M1 and the NMOS transistor M2 is connected to the depletion type NMOS transistor M1 and the NMOS transistor M2 via the fuses F5 and F6 as shown in the circuit of FIG. The depletion type NMOS transistor M3 and NMOS transistor M4 connected in parallel are provided, and by cutting the fuse, the same effect as changing the W / L value of the MOS transistor can be obtained.
For example, when the temperature characteristic is S2, the temperature characteristic can be brought close to S1 by cutting the fuse F5, but the drain current id3 of the depletion type NMOS transistor M3 is lost. For this reason, the drain currents of the NMOS transistors M2 and M4 decrease, and the reference voltage Vr decreases from the temperature characteristic S2 to the temperature characteristic S1, as shown in FIG.

In the case of the temperature characteristic S3, the temperature characteristic can be brought close to S1 by cutting the fuse F6, but the drain current id4 of the NMOS transistor M4 is lost. Therefore, since the drain currents id1 and id3 of the depletion type NMOS transistors M1 and M3 all become the drain current id2 of the NMOS transistor M2, the reference voltage Vr increases from the temperature characteristic S3 to the temperature characteristic S1 as shown in FIG. To do.
As described above, when the trimming is performed by the reference voltage generation circuit 101, the temperature characteristic of the reference voltage Vr is improved. However, since the reference voltage Vr varies, the output voltage Vo of the constant voltage circuit 100 also varies. . Therefore, it is necessary to adjust the output voltage Vo after trimming the reference voltage generation circuit 101. The output voltage Vo of the constant voltage circuit 100 can be adjusted by a combination of cutting the fuses F10 and F11. After adjusting the temperature characteristics of the reference voltage Vr, the output voltage detection circuit 102 performs trimming to obtain a desired voltage. The output voltage Vo can be adjusted.

Thus, in order to perform adjustment by trimming of the constant voltage circuit 100, the temperature characteristics of the reference voltage generation circuit 101 are measured in the first step to determine the trimming contents of the reference voltage generation circuit 2, and the second step. The trimming of the reference voltage generating circuit 2 is performed in step 3, the output voltage Vo of the constant voltage circuit 100 is measured in the third step, the trimming contents of the output voltage detecting circuit 102 are determined, and the output voltage detecting circuit in the fourth step. It was necessary to perform the trimming of 102, and the number of processes was increased.
In the above example, the number of circuits to be trimmed is two, but when a plurality of circuit characteristics are related to each other and trimming is performed in each circuit, a pre-process for measuring and determining trimming contents In addition, the subsequent two steps of the actual trimming must be repeated many times, which increases the number of manufacturing steps, which increases the cost of the semiconductor device.

Therefore, in order to reduce the number of trimming steps, a MOS transistor M is connected in series to the trimming fuse F as shown in FIG. 8, and the gate of the MOS transistor M is controlled by a test mode signal to cut the fuse F. It was made possible to achieve the same state as that (see, for example, Patent Document 1). For this reason, since the trimmed state is created and other circuits can be adjusted before actually cutting the fuse, the trimming process can be performed all at once.
JP-A-7-144101

  However, when the MOS transistor M is connected in series to the trimming fuse F as in the circuit of FIG. 8, it is often difficult to dispose the fuse F near the MOS transistor. Since the wiring of F becomes long, the circuit layout of the semiconductor device becomes complicated due to the routing of the wiring, etc., and it is easy to be affected by characteristic deterioration and noise, so there is a problem that it is not suitable for applications requiring high precision characteristics. It was.

  The present invention has been made to solve the above-described problems, and a semiconductor device having a trimming circuit in which wiring of a trimming fuse is simple and is not easily affected by characteristic deterioration or noise, a trimming method thereof, and its manufacture The purpose is to obtain a method.

A semiconductor device according to the present invention includes a semiconductor device having one or more trimming circuits that perform trimming by cutting a fuse.
The trimming circuit includes:
A semiconductor switch that performs switching according to a control signal input to the control electrode;
Having the fuse, turning on or off the semiconductor switch in response to cutting of the fuse, and turning on / off the semiconductor switch in response to a test signal input from the outside in an initial state where the fuse is not cut A control circuit for controlling,
With
The control circuit includes:
A first fuse that turns on the semiconductor switch when disconnected;
A second fuse that turns off the semiconductor switch when disconnected;
With
To the initial state in which the first and second of each fuse is not cut, respectively, and performs on / off control of the semiconductor switch in response to the test signal inputted from the outside.

The semiconductor device according to the present invention includes an output transistor for outputting a current corresponding to the input signal to the control electrode to the input terminal or RaIzuru output terminal,
An output voltage controller that generates a predetermined reference voltage and generates a proportional voltage proportional to the voltage of the output terminal, amplifies a difference between the reference voltage and the proportional voltage, and outputs the amplified voltage to the control electrode of the output transistor;
In a semiconductor device having a constant voltage circuit comprising:
The output voltage controller is
A reference voltage generating circuit for generating the reference voltage using a work function difference between gate electrodes of two field effect transistors;
The reference voltage generation circuit includes:
Switching according to a control signal input to the control electrode, each semiconductor switch for performing parallel connection control of the same type of field effect transistor with respect to each field effect transistor,
A control circuit which has each fuse selectively cut by trimming and changes the temperature characteristic of the reference voltage by turning on or off each semiconductor switch according to the cutting of the selected fuse;
A trimming circuit consisting of
The control circuit performs on / off control of each semiconductor switch in accordance with a test signal input from the outside in an initial state where the fuse is not cut.

Specifically, the control circuit includes:
Each first fuse that turns on the corresponding semiconductor switch when disconnected,
Each second fuse that turns off the corresponding semiconductor switch when disconnected;
With
In the initial state in which each of the first and second fuses is not cut, on / off control of each semiconductor switch is performed according to a test signal input from the outside.

The output voltage controller is
An output voltage detection circuit that divides the voltage of the output terminal to generate the proportional voltage;
The output voltage detection circuit includes:
A resistor circuit comprising a plurality of resistors for dividing the voltage of the output terminal;
One or more third fuses provided corresponding to a predetermined resistance of the resistor circuit and selectively cut by trimming;
With
The third fuse is selectively cut to change the voltage dividing ratio when generating the proportional voltage.

  The reference voltage generation circuit selectively turns on the semiconductor switches according to the test signal to adjust the temperature characteristics of the reference voltage. The reference voltage generation circuit and the output voltage detection circuit The fuses are selectively trimmed collectively so that the temperature characteristic of the reference voltage can be obtained and the voltage of the output terminal becomes a desired voltage.

According to the semiconductor device trimming method of the present invention, when the semiconductor switch that performs switching according to the control signal input to the control electrode and the first fuse that turns on the semiconductor switch when disconnected are disconnected. by the a second fuse turning off the semiconductor switch, and a control circuit that turns on or off the semiconductor switch in accordance with the cutting of the first and second respective fuses to cut the respective fuse In a trimming method of a semiconductor device to be trimmed,
In an initial state where each of the first and second fuses is not cut, on / off control of the semiconductor switch is performed in accordance with a test signal input from the outside,
Determining the state of the semiconductor switch;
Regardless the test signal, and to perform the execution selection of cutting of the fuse as the state of the semiconductor switch with the determined is maintained.

Also, the trimming method of a semiconductor device according to the present invention includes an output transistor for outputting a current corresponding to the input signal to the control electrode to the input terminal or RaIzuru output terminal,
A reference voltage generating circuit for generating a predetermined reference voltage using a work function difference between the gate electrodes of two field effect transistors, and an output voltage detecting circuit for generating a proportional voltage proportional to the voltage of the output terminal. An output voltage control unit that amplifies the difference between the proportional voltage and the output voltage to the control electrode of the output transistor;
A constant voltage circuit having
The reference voltage generation circuit includes:
Switching according to a control signal input to the control electrode, each semiconductor switch for performing parallel connection control of the same type of field effect transistor with respect to each field effect transistor,
In a trimming method of a semiconductor device having a trimming circuit including a control circuit that changes the temperature characteristics of the reference voltage by turning on or off each semiconductor switch according to the cutting of each fuse selectively cut by trimming,
Each semiconductor switch is turned on or off according to a test signal input from the outside in an initial state where each of the fuses is not cut,
Determining the state of each semiconductor switch that provides the desired temperature characteristics of the reference voltage;
Each fuse is selected to be cut so that the determined state of each semiconductor switch is maintained regardless of the test signal.

  Also, each fuse of the trimming circuit and one or more fuses of the output voltage detection circuit provided corresponding to a predetermined resistance of a resistance circuit composed of a plurality of resistors for dividing the voltage of the output terminal. The temperature characteristics of the reference voltage are obtained, and the output terminal voltage is selectively trimmed in a batch so that the voltage becomes a desired voltage.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a semiconductor switch that performs switching according to a control signal input to a control electrode; and a first fuse that turns on the semiconductor switch when disconnected. by the a second fuse turning off the semiconductor switch, and a control circuit that turns on or off the semiconductor switch in accordance with the cutting of the first and second respective fuses to cut the respective fuse In the manufacturing method of the semiconductor device to be trimmed,
In an initial state where each of the first and second fuses is not cut, on / off control of the semiconductor switch is performed in accordance with a test signal input from the outside,
Determining the state of the semiconductor switch;
Regardless the test signal, and to perform the execution selection of cutting of the fuse as the state of the semiconductor switch with the determined is maintained.

A method of manufacturing a semiconductor device according to the present invention, an output transistor for outputting a current corresponding to the input signal to the control electrode to the input terminal or RaIzuru output terminal,
A reference voltage generating circuit for generating a predetermined reference voltage using a work function difference between the gate electrodes of two field effect transistors, and an output voltage detecting circuit for generating a proportional voltage proportional to the voltage of the output terminal. An output voltage control unit that amplifies the difference between the proportional voltage and the output voltage to the control electrode of the output transistor;
A constant voltage circuit having
The reference voltage generation circuit includes:
Switching according to a control signal input to the control electrode, each semiconductor switch for performing parallel connection control of the same type of field effect transistor with respect to each field effect transistor,
In a method of manufacturing a semiconductor device having a trimming circuit including a control circuit that changes a temperature characteristic of the reference voltage by turning on or off each semiconductor switch according to cutting of each fuse selectively cut by trimming,
Each semiconductor switch is turned on or off according to a test signal input from the outside in an initial state where each of the fuses is not cut,
Determining the state of each semiconductor switch that provides the desired temperature characteristics of the reference voltage;
Each fuse is selected to be cut so that the determined state of each semiconductor switch is maintained regardless of the test signal.

  Also, each fuse of the trimming circuit and one or more fuses of the output voltage detection circuit provided corresponding to a predetermined resistance of a resistance circuit composed of a plurality of resistors for dividing the voltage of the output terminal. The temperature characteristics of the reference voltage are obtained, and the output terminal voltage is selectively trimmed in a batch so that the voltage becomes a desired voltage.

  According to the semiconductor device having the trimming circuit, the trimming method, and the manufacturing method thereof according to the present invention, trimming related to a plurality of circuits having mutually related characteristics can be performed in one process. Since the process can be shortened and the fuse and the semiconductor switch are not connected in series as in the prior art, the fuse is provided on the control circuit side for turning on / off the semiconductor switch. Wiring relating to the switch and the circuit can be shortened, the circuit layout in the semiconductor device can be simplified, and characteristic deterioration due to complicated layout can be prevented.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a configuration example of a trimming circuit of a semiconductor device according to a first embodiment of the present invention. FIG. 1 shows a constant voltage circuit as a series regulator as an example.
The constant voltage circuit 1 of FIG. 1 forms a series regulator, converts the power supply voltage Vdd into a predetermined constant voltage, and outputs it from the output terminal OUT.
The constant voltage circuit 1 includes a reference voltage generation circuit 2 that generates and outputs a predetermined reference voltage Vr, an output voltage detection circuit 3 that generates and outputs a divided voltage Vo1 by dividing the output voltage Vo, and inputs to the gate The output transistor M15, which is a PMOS transistor that controls the current output to the output terminal OUT according to the received signal, and the error amplifier circuit 4 that controls the operation of the output transistor M15 so that the divided voltage Vo1 becomes the reference voltage Vr. It consists of and.

The reference voltage generation circuit 2 includes two depletion type NMOS transistors M1 and M3, two NMOS transistors M2 and M4, a first trimming circuit 11, and a second trimming circuit 12. The first trimming circuit 11 includes an enhancement type PMOS transistor (hereinafter referred to as a PMOS transistor) M5, an OR circuit OR1, resistors R1 and R2, and fuses F1 and F2. The second trimming circuit 12 includes a PMOS transistor M6 and an OR circuit. It consists of OR2, resistors R3 and R4, and fuses F3 and F4.
The output voltage detection circuit 3 includes resistors R10 to R13 and fuses F10 and F11, and the error amplifier circuit 4 includes PMOS transistors M10 and M11 and NMOS transistors M12 to M14.

An output transistor M15 is connected between the power supply voltage Vdd and the output terminal OUT, and resistors R10 to R13 are connected in series between the output terminal OUT and the ground voltage Vss. A fuse F10 is connected in parallel to the resistor R11, a fuse F11 is connected in parallel to the resistor R12, and a divided voltage Vo1 is output from a connection portion between the resistors R11 and R12.
In the reference voltage generation circuit 2, a depletion type NMOS transistor M1 and an NMOS transistor M2 are connected in series between the power supply voltage Vdd and the ground voltage, and a connection portion between the depletion type NMOS transistor M1 and the NMOS transistor M2 The gates of the depletion type NMOS transistor M1 and the NMOS transistor M2 are connected to each other, and the reference voltage Vr is output from the connection portion.

Further, a PMOS transistor M5, a depletion type NMOS transistor M3, a PMOS transistor M6, and an NMOS transistor M4 are connected in series between the power supply voltage Vdd and the ground voltage Vss. The gates of the depletion type NMOS transistor M3 and the NMOS transistor M4 are connected to the connection part between the depletion type NMOS transistor M3 and the PMOS transistor M6, and the connection part is connected to the connection part between the depletion type NMOS transistor M1 and the NMOS transistor M2. It is connected.
The first trimming circuit 11 and the second trimming circuit 12 operate using the power supply voltage Vdd2 as a power supply, and the power supply voltage Vdd2 is separated from the power supply voltage Vdd. This is because the power supply voltage Vdd is a power supply for analog circuits, and the power supply voltage Vdd2 is a power supply for digital circuits.

A resistor R1 and fuses F1 and F2 are connected in series between the power supply voltage Vdd2 and the ground voltage Vss, and a connection portion A between the fuses F1 and F2 is connected to one input terminal of the OR circuit OR1. The other input terminal of the OR circuit OR1 is pulled down to the ground voltage Vss by the resistor R2, the test signal TEST1 is input from the outside, and the output terminal of the OR circuit OR1 is connected to the gate of the PMOS transistor M5. A connection portion between the input terminal of the OR circuit OR1 and the resistor R2 is B.
Similarly, a resistor R3 and fuses F3 and F4 are connected in series between the power supply voltage Vdd2 and the ground voltage Vss, and a connection C between the fuses F3 and F4 is connected to one input terminal of the OR circuit OR2. ing. The other input terminal of the OR circuit OR2 is pulled down to the ground voltage Vss by the resistor R4, the test signal TEST2 is input from the outside, and the output terminal of the OR circuit OR2 is connected to the gate of the PMOS transistor M6. A connection portion between the input terminal of the OR circuit OR2 and the resistor R2 is D.

Next, in the error amplifying circuit 4, the NMOS transistors M12 and M13 form a differential pair, and the PMOS transistors M10 and M11 form a current mirror circuit to load the differential pair. The sources of the PMOS transistors M10 and M11 are connected to the power supply voltage Vdd, the gates of the PMOS transistors M10 and M11 are connected, and the connection is connected to the drain of the PMOS transistor M11. The drain of the PMOS transistor M10 is connected to the drain of the NMOS transistor M12, and the drain of the PMOS transistor M11 is connected to the drain of the NMOS transistor M13.
The sources of the NMOS transistors M12 and M13 are connected, and an NMOS transistor M14 is connected between the connection portion and the ground voltage. A reference voltage Vr is input to each gate of the NMOS transistors M12 and M14, and a divided voltage Vo1 is input to the gate of the NMOS transistor M13. The NMOS transistor M14 forms a constant current source.

In such a configuration, the PMOS transistor M5 that forms a semiconductor switch is switching-controlled by a control circuit including an OR circuit OR1, resistors R1 and R2, and fuses F1 and F2. Similarly, the PMOS transistor M6 that forms a semiconductor switch is switching-controlled by a control circuit including an OR circuit OR2, resistors R3 and R4, and fuses F3 and F4.
In the first trimming circuit 11, in the initial state where the fuses F1 and F2 are not cut, the connection portion A is fixed at a low level, so that the signal level of the output signal from the OR circuit OR1 is input to the connection portion B. Is determined by the signal level of the test signal TEST1. That is, when the test signal TEST1 is at a high level, the output terminal of the OR circuit OR1 is at a high level, and when the test signal TEST1 is at a low level, the output terminal of the OR circuit OR1 is at a low level. Note that when the test signal TEST1 is not input, the connection B is set to the low level by the pull-down resistor R2, and therefore the output terminal of the OR circuit OR1 is set to the low level.

  The PMOS transistor M5 is turned off when the output terminal of the OR circuit OR1 is at a high level, and turned on when the output terminal is at a low level. That is, since the PMOS transistor M5 can be turned on / off according to the level of the test signal TEST1, an operation equivalent to cutting or connecting the fuse F5 in FIG. 5 can be performed by the test signal TEST1. When the operation state of the PMOS transistor M5 is determined, the fuse F1 or F2 is cut by trimming so that the operation state of the PMOS transistor M5 can be maintained even if the test signal TEST1 is not input. That is, when setting the PMOS transistor M5 to be turned on, the output terminal of the OR circuit OR1 may be set to a low level, and thus the fuse F1 is cut. Conversely, when setting the PMOS transistor M5 to be turned off, the fuse F2 is cut because the output terminal of the OR circuit OR1 only needs to be set to the high level. When the trimming state is determined, the test signal TEST1 is set to a low level or a high impedance state.

  Similarly, in the second trimming circuit 12, in the initial state where the fuses F3 and F4 are not cut, the connection portion C is fixed at a low level, so that the signal level of the output signal from the OR circuit OR2 is It is determined by the signal level of the test signal TEST2 input to D. That is, when the test signal TEST2 is at a high level, the output terminal of the OR circuit OR2 is at a high level, and when the test signal TEST2 is at a low level, the output terminal of the OR circuit OR2 is at a low level. Note that when the test signal TEST2 is not input, the connection portion D is set to the low level by the pull-down resistor R4, so that the output terminal of the OR circuit OR2 is set to the low level.

  The PMOS transistor M6 is turned off when the output terminal of the OR circuit OR2 is at a high level, and turned on when the output terminal is at a low level. That is, since the PMOS transistor M6 can be controlled to be turned on / off according to the level of the test signal TEST2, an operation equivalent to cutting or connecting the fuse F6 in FIG. 5 can be performed by the test signal TEST2. When the operation state of the PMOS transistor M6 is determined, the fuse F3 or F4 is cut by trimming so that the operation state of the PMOS transistor M6 can be maintained even if the test signal TEST2 is not input. That is, when the PMOS transistor M6 is set to be turned on, the output terminal of the OR circuit OR2 only needs to be set to a low level, so the fuse F3 is cut. Conversely, when setting the PMOS transistor M5 to be turned off, the fuse F4 is disconnected because the output terminal of the OR circuit OR2 only needs to be set to the high level. When the trimming state is confirmed, the test signal TEST2 is set to a low level or a high impedance state.

  In the state where the PMOS transistors M5 and M6 are turned on, the depletion type NMOS transistors M1 and M3 are each biased to 0. Therefore, specific drain currents id1 and id3 flow correspondingly to the respective drains of the depletion type NMOS transistors M1 and M3. The sum of the drain currents id2 and id4 of the NMOS transistors M2 and M4 is the same as the sum of the drain currents id1 and id3. Further, the gates of the NMOS transistors M2 and M4 are connected, and the connection portion is connected to the drain of the NMOS transistor M2. Accordingly, the gate voltages of the NMOS transistors M2 and M4 are set to voltages determined by the drain currents id2 and id4, and the voltages become the reference voltage Vr.

The temperature characteristics of the reference voltage Vr can be controlled by changing the ratio W / L of the gate width W and the gate length L of the MOS transistor used in the reference voltage generation circuit 2. In the case of the temperature characteristic S2 in FIG. 6, the W / L of the depletion type NMOS transistors M1 and M3 is reduced, or the W / L of the NMOS transistors M2 and M4 is increased to increase the target temperature characteristic S1 in FIG. Can be approached.
When the temperature characteristic is S3 in FIG. 6, the W / L of the depletion type NMOS transistors M1 and M3 is increased, or the W / L of the NMOS transistors M2 and M4 is decreased to reduce the temperature characteristic S1 in FIG. Can be approached.

However, since the completed semiconductor device cannot reduce or increase the element area of the MOS transistor, a PMOS transistor that forms a semiconductor switch in each of the depletion type NMOS transistor M1 and the NMOS transistor M2 as in the circuit of FIG. A depletion type NMOS transistor M3 and an NMOS transistor M4 connected in parallel via M5 and M6 are provided, and by turning off the PMOS transistor M5 or M6, the same effect as changing the W / L value of the MOS transistor is provided. be able to.
For example, when the temperature characteristic of the reference voltage Vr is S2 in FIG. 6, the temperature characteristic can be brought close to S1 in FIG. 6 by turning off the PMOS transistor M5, but the drain current id3 of the depletion type NMOS transistor M3. Will disappear. For this reason, the drain currents of the NMOS transistors M2 and M4 decrease, and the reference voltage Vr decreases from the temperature characteristic S2 to the temperature characteristic S1, as shown in FIG.

When the reference voltage Vr has the temperature characteristic S3, the temperature characteristic can be brought close to S1 by turning off the PMOS transistor M6, but the drain current id4 of the NMOS transistor M4 is lost. Therefore, since the drain currents id1 and id3 of the depletion type NMOS transistors M1 and M3 all become the drain current id2 of the NMOS transistor M2, the reference voltage Vr increases from the temperature characteristic S3 to the temperature characteristic S1 as shown in FIG. To do.
As described above, when the trimming is performed by the reference voltage generation circuit 2, the temperature characteristics of the reference voltage Vr are improved, but the reference voltage Vr varies, so that the output voltage Vo of the constant voltage circuit 1 also varies. . Therefore, it is necessary to adjust the output voltage Vo after trimming the reference voltage generation circuit 2.

  The error amplifier circuit 4 amplifies the difference voltage between the reference voltage Vr and the divided voltage Vo1 and outputs the amplified voltage to the gate of the output transistor M15. The output voltage detection circuit 3 includes four resistors R10 to R13 connected in series between the drain of the output transistor M15 and the ground voltage Vss. The output voltage Vo of the constant voltage circuit 1 can be adjusted by a combination of cutting the fuses F10 and F11 as shown by the following equations (a) to (d), and after adjusting the temperature characteristics of the reference voltage Vr, Trimming by the output voltage detection circuit 3 can be adjusted to a desired output voltage Vo.

When the fuses F10 and F11 are not cut, the output voltage Vo is expressed by the following equation (a).
Vo = Vr × {(r10 + r13) / r13} (a)
When only the fuse F10 is cut, the output voltage Vo is expressed by the following equation (b).
Vo = Vr × {(r10 + r11 + r13) / r13} (b)
When only the fuse F11 is cut, the output voltage Vo is expressed by the following equation (c).
Vo = Vr × {(r10 + r12 + r13) / (r12 + r13)} (c)
When the fuses F10 and F11 are both cut, the output voltage Vo is expressed by the following equation (d).
Vo = Vr × {(r10 + r11 + r12 + r13) / (r12 + r13)} (d)
In the equations (a) to (d), r10 to r13 indicate resistance values of the resistors R10 to R13.

For this reason, the adjustment procedure of the constant voltage circuit 1 is as follows.
In the first step,
(1) Energize the constant voltage circuit 1 and measure the voltage value of the reference voltage Vr and the current consumption of the constant voltage circuit 1. When measuring the consumption current, the zero bias current of the depletion type NMOS transistor M3 can be indirectly measured from the difference between the consumption currents when the test signal TEST1 is at the high level and at the low level.
(2) The temperature characteristics of the reference voltage generation circuit 2 can be predicted by comparing these measured values with past manufacturing data. The trimming method of the first trimming circuit 11 and the second trimming circuit 12 of the reference voltage generation circuit 2 is determined from the predicted value of the temperature characteristic.
(3) The signal levels of the test signals TEST1 and TEST2 are set so as to be in the trimming state determined in (2), and are input to the first trimming circuit 11 and the second trimming circuit 12, respectively.
(4) The output voltage Vo of the constant voltage circuit 1 is measured.
(5) The trimming contents of the fuses F10 and F11 of the output voltage detection circuit 3 are determined based on the measured output voltage Vo.

Next, in the second step,
(1) The fuses F1 to F4 of the reference voltage generation circuit 2 are selectively cut based on the contents determined in (2) of the first step.
(2) The fuses F10 and F11 of the output voltage detection circuit 3 are selectively cut based on the contents determined in (5) of the first step.
In this manner, trimming related to a plurality of circuits having mutually related characteristics can be performed in one process as in the second process, and the process can be shortened. Further, since the fuse and the MOS transistor forming the semiconductor switch are not connected in series as in the prior art, the fuse is provided on the control circuit side for turning on / off the MOS transistor forming the semiconductor switch. The wiring between the terminals can be shortened, the circuit layout in the semiconductor device can be simplified, and the characteristic deterioration due to the complicated layout can be prevented.

  In the above description, a case where PMOS transistors are used as the semiconductor switches M5 and M6 is shown as an example. However, depending on the potential of the circuit in which the semiconductor switches are used, an NMOS transistor or a depletion type MOS transistor may be used. Good. Further, as the semiconductor switches M5 and M6, a switch circuit composed of an analog switch and an inverter combining a PMOS transistor and an NMOS transistor as shown in FIG. 2 may be used.

FIG. 3 is a diagram showing another configuration example of the trimming circuit of the semiconductor device according to the first embodiment of the present invention. In FIG. 3, the same or similar parts as those in FIG. The description is omitted here, and only the differences from FIG. 1 are described.
3 differs from FIG. 1 in that the circuit configurations of the first trimming circuit 11 and the second trimming circuit 12 are changed.
In FIG. 3, the first trimming circuit 11 includes a PMOS transistor M5, an inverter INV31, resistors R31 and R32, and fuses F31 to F33, and the second trimming circuit 12 includes a PMOS transistor M6, an inverter INV35, resistors R35 and R36, and a fuse. It consists of F35-F37.

  A fuse F31, resistors R31 and R32, and a fuse F32 are connected in series between the power supply voltage Vdd2 and the ground voltage Vss, and a connection portion between the resistors R31 and R32 is connected to the gate of the PMOS transistor M5. Further, the signal level of the test signal TEST1 is inverted by the inverter INV31, and then input to the connection portion of the resistor R31 and the resistor R32 via the fuse F33. Similarly, a fuse F35, resistors R35 and R36, and a fuse F36 are connected in series between the power supply voltage Vdd2 and the ground voltage Vss, and a connection portion between the resistors R35 and R36 is connected to the gate of the PMOS transistor M6. Yes. Further, the signal level of the test signal TEST2 is inverted by the inverter INV35, and then input to the connection portion of the resistors R35 and R36 via the fuse F37.

  In such a configuration, the test signal TEST1 is input to the gate of the PMOS transistor M5 via the inverter INV31 before the fuses F31 to F33 are cut. By trimming, when the fuse F31 is cut, the PMOS transistor M5 can be turned on, and when the fuse F32 is cut, the PMOS transistor M5 can be turned off. After the fuse F31 or F32 is cut, the fuse F33 is cut so that the PMOS transistor M5 is not affected by the test signal TEST1. Similarly, before the fuses F35 to F37 are cut, the test signal TEST2 is input to the gate of the PMOS transistor M6 via the inverter INV35. By trimming, when the fuse F35 is cut, the PMOS transistor M6 can be turned on, and when the fuse F36 is cut, the PMOS transistor M6 can be turned off. After the fuse F35 or F36 is cut, the fuse F37 is cut so that the PMOS transistor M6 is not affected by the test signal TEST2. By doing in this way, the effect similar to FIG. 1 can be acquired.

FIG. 4 is a diagram showing another configuration example of the trimming circuit of the semiconductor device according to the first embodiment of the present invention. In FIG. 4, the same or similar parts as those in FIG. The description is omitted here, and only the differences from FIG. 1 are described.
4 differs from FIG. 1 in that the circuit configurations of the first trimming circuit 11 and the second trimming circuit 12 are changed.
4, the first trimming circuit 11 includes a PMOS transistor M5, an inverter INV41, resistors R41 and R42, and fuses F41 and F42. The second trimming circuit 12 includes a PMOS transistor M6, an inverter INV45, resistors R45 and R46, and a fuse. It consists of F45 and F46.

  A resistor R41, fuses F41 and F42, and a resistor R42 are connected in series between the power supply voltage Vdd2 and the ground voltage Vss, and a connection portion between the fuses F41 and F42 is connected to the gate of the PMOS transistor M5. The test signal TEST1 is input to the connection portion between the fuse F42 and the resistor R42 after the signal level is inverted by the inverter INV41. Similarly, a resistor R45, fuses F45 and F46, and a resistor R46 are connected in series between the power supply voltage Vdd2 and the ground voltage Vss, and the connection portion between the fuses F45 and F46 is connected to the gate of the PMOS transistor M6. Yes. The test signal TEST2 is input to the connection portion between the fuse F46 and the resistor R46 after the signal level is inverted by the inverter INV45.

  In such a configuration, the test signal TEST1 is input to the gate of the PMOS transistor M5 via the inverter INV41 before the fuses F41 and F42 are cut. By trimming, when only the fuse F41 is cut, the PMOS transistor M5 can be turned on, and when only the fuse F42 is cut, the PMOS transistor M5 can be turned off. After the fuse F41 or F42 is cut, the test signal TEST1 is fixed at a high level. For this reason, since the output terminal of the inverter INV41 is at a low level, an increase in current consumption can be prevented without supplying current to the resistor R42, and the operation of the PMOS transistor M5 set by cutting the fuse by trimming is affected. Never give.

  Similarly, before the fuses F45 and F46 are cut, the test signal TEST2 is input to the gate of the PMOS transistor M6 via the inverter INV45. By trimming, if only the fuse F45 is cut, the PMOS transistor M6 can be turned on, and if only the fuse F46 is cut, the PMOS transistor M6 can be turned off. After the fuse F45 or F46 is cut, the test signal TEST2 is fixed at a high level. For this reason, since the output terminal of the inverter INV45 is at a low level, an increase in current consumption can be prevented without supplying current to the resistor R46, and the operation of the PMOS transistor M6 set by cutting the fuse by trimming is affected. Never give. By doing in this way, the effect similar to FIG. 1 can be acquired.

  In the above description, in order to simplify the description, the case where each of the trimming depletion type NMOS transistor M3 and the NMOS transistor M4 included in the reference voltage generating circuit 2 is described as an example. The number of MOS transistors that can be trimmed may be increased according to the specifications required by 1. Also, the output voltage Vo may be increased by the necessary number of resistors that can be trimmed in the output voltage detection circuit 3 in accordance with the required specifications.

It is the figure which showed the structural example of the trimming circuit of the semiconductor device in the 1st Embodiment of this invention. It is the figure which showed the other circuit structural example of the semiconductor switches M5 and M6 of FIG. It is the figure which showed the other structural example of the trimming circuit of the semiconductor device in the 1st Embodiment of this invention. It is the figure which showed the other structural example of the trimming circuit of the semiconductor device in the 1st Embodiment of this invention. It is the circuit diagram which showed the example of the conventional constant voltage circuit. It is the figure which showed the temperature characteristic example of the reference voltage Vr. It is the figure which showed the example of a change of the temperature characteristic of the reference voltage Vr. It is a circuit diagram showing an example of a conventional trimming circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Constant voltage circuit 2 Reference voltage generation circuit 3 Output voltage detection circuit 4 Error amplifier circuit 11 1st trimming circuit 12 2nd trimming circuit M5, M6 PMOS transistor M15 Output transistor OR1, OR2 OR circuit F1-F4, F10, F11, F31 F33, F35 to F37, F41, F42, F45, F46 Fuses R1 to R4, R31, R32, R35, R36, R41, R42, R45, R46 Resistors INV31, INV35, INV41, INV45 Inverter

Claims (11)

In a semiconductor device having one or more trimming circuits that perform trimming by cutting a fuse,
The trimming circuit includes:
A semiconductor switch that performs switching according to a control signal input to the control electrode;
Having the fuse, turning on or off the semiconductor switch in response to cutting of the fuse, and turning on / off the semiconductor switch in response to a test signal input from the outside in an initial state where the fuse is not cut A control circuit for controlling,
With
The control circuit includes:
A first fuse that turns on the semiconductor switch when disconnected;
A second fuse that turns off the semiconductor switch when disconnected;
With
Wherein the initial state in which the first and second of each fuse is not cut, respectively, wherein a performing on / off control of the semiconductor switch in response to the test signal inputted from the outside. An output transistor for outputting a current corresponding to a signal input to the control electrode from the input terminal to the output terminal;
An output voltage controller that generates a predetermined reference voltage and generates a proportional voltage proportional to the voltage of the output terminal, amplifies a difference between the reference voltage and the proportional voltage, and outputs the amplified voltage to the control electrode of the output transistor;
In a semiconductor device having a constant voltage circuit comprising:
The output voltage controller is
A reference voltage generating circuit for generating the reference voltage using a work function difference between gate electrodes of two field effect transistors;
The reference voltage generation circuit includes:
Each semiconductor switch that performs switching in accordance with a control signal input to the control electrode, and performs parallel connection control of the same type of field effect transistor with respect to each field effect transistor,
A control circuit which has each fuse selectively cut by trimming and changes the temperature characteristic of the reference voltage by turning on or off each semiconductor switch according to the cutting of the selected fuse;
A trimming circuit consisting of
Wherein the control circuit, the fuses are disconnected which do such have Initial state, semi-conductor devices you and performs on / off control of the respective semiconductor switches in response to the test signal inputted from the outside. The control circuit includes:
Each first fuse that turns on the corresponding semiconductor switch when disconnected,
Each second fuse that turns off the corresponding semiconductor switch when disconnected;
With
To the initial state in which the first and second of each fuse is not cut, respectively, according to claim 2, wherein the performing on / off control of the respective semiconductor switches in response to the test signal input from the outside semiconductor device. The output voltage controller is
An output voltage detection circuit that divides the voltage of the output terminal to generate the proportional voltage;
The output voltage detection circuit includes:
A resistor circuit comprising a plurality of resistors for dividing the voltage of the output terminal;
One or more third fuses provided corresponding to a predetermined resistance of the resistor circuit and selectively cut by trimming;
With
4. The semiconductor device according to claim 2 , wherein the voltage dividing ratio when the proportional voltage is generated is changed by selectively cutting the third fuse . The reference voltage generation circuit selectively turns on the semiconductor switches according to the test signal to adjust the temperature characteristics of the reference voltage, and the reference voltage generation circuit and the output voltage detection circuit 5. The semiconductor device according to claim 4 , wherein the fuses are selectively trimmed collectively so that a temperature characteristic of a reference voltage can be obtained and a voltage of the output terminal becomes a desired voltage . A semiconductor switch that performs switching in response to a control signal input to the control electrode; a first fuse that turns on the semiconductor switch when disconnected; and a second fuse that turns off the semiconductor switch when disconnected. A control circuit for turning on or off the semiconductor switch in response to cutting of each of the first and second fuses, and a trimming method for a semiconductor device in which trimming is performed by cutting each of the fuses.
In an initial state where each of the first and second fuses is not cut, on / off control of the semiconductor switch is performed in accordance with a test signal input from the outside,
Determining the state of the semiconductor switch;
It said test signal regardless of the trimming method of the semi-conductor device you characterized in that the execution selection of cutting of the fuse as the state of the semiconductor switch is maintained in which the determined. An output transistor for outputting a current corresponding to a signal input to the control electrode from the input terminal to the output terminal;
A reference voltage generating circuit for generating a predetermined reference voltage using a work function difference between the gate electrodes of two field effect transistors, and an output voltage detecting circuit for generating a proportional voltage proportional to the voltage of the output terminal. An output voltage control unit that amplifies the difference between the proportional voltage and the output voltage to the control electrode of the output transistor;
A constant voltage circuit having
The reference voltage generation circuit includes:
There line switching according to a control signal input to a control electrode, wherein the row Cormorant respective semiconductor switches connected in parallel control of the same type of field effect transistor for each of the field effect transistor,
It turns on or off the respective semiconductor switch in response to the disconnection of the fuses are selectively cleaved by trimming, in trimming method of a semiconductor device having a trimming circuit comprising a control circuit for Ru changing the temperature characteristic of the reference voltage ,
Each semiconductor switch is turned on or off according to a test signal input from the outside in an initial state where each of the fuses is not cut,
Determining the desired of the condition of each semiconductor switch temperature characteristics are obtained in the reference voltage,
A trimming method for a semiconductor device, wherein execution selection of cutting of each fuse is performed so that the determined state of each semiconductor switch is maintained regardless of the test signal. Each fuse of the trimming circuit, and one or more fuses of the output voltage detection circuit provided corresponding to a predetermined resistance of a resistance circuit composed of a plurality of resistors for dividing the voltage of the output terminal, 8. The method of trimming a semiconductor device according to claim 7, wherein the trimming is selectively performed collectively so that the temperature characteristic of the reference voltage is obtained and the voltage of the output terminal becomes a desired voltage . A semiconductor switch that performs switching in response to a control signal input to the control electrode; a first fuse that turns on the semiconductor switch when disconnected; and a second fuse that turns off the semiconductor switch when disconnected. And a control circuit for turning on or off the semiconductor switch in response to cutting of each of the first and second fuses, and a method of manufacturing a semiconductor device in which trimming is performed by cutting each of the fuses.
In an initial state where each of the first and second fuses is not cut, on / off control of the semiconductor switch is performed in accordance with a test signal input from the outside,
Determining the state of the semiconductor switch;
It said test signal regardless of the method of manufacturing a semi-conductor device you characterized in that the execution selection of cutting of the fuse as the state of the semiconductor switch is maintained in which the determined. An output transistor for outputting a current corresponding to a signal input to the control electrode from the input terminal to the output terminal;
A reference voltage generating circuit for generating a predetermined reference voltage using a work function difference between the gate electrodes of two field effect transistors, and an output voltage detecting circuit for generating a proportional voltage proportional to the voltage of the output terminal. An output voltage control unit that amplifies the difference between the proportional voltage and the output voltage to the control electrode of the output transistor;
A constant voltage circuit having
The reference voltage generation circuit includes:
There line switching according to a control signal input to a control electrode, wherein the row Cormorant respective semiconductor switches connected in parallel control of the same type of field effect transistor for each of the field effect transistor,
It turns on or off the respective semiconductor switch in response to the disconnection of the fuses are selectively cleaved by trimming, in the manufacturing method of a semiconductor device having a trimming circuit comprising a control circuit for Ru changing the temperature characteristic of the reference voltage ,
Each semiconductor switch is turned on or off according to a test signal input from the outside in an initial state where each of the fuses is not cut,
Determining the desired the state of each semiconductor switch temperature characteristics are obtained in the reference voltage,
A method of manufacturing a semiconductor device, comprising: performing cutting selection of each fuse so that the determined state of each semiconductor switch is maintained regardless of the test signal. Each fuse of the trimming circuit, and one or more fuses of the output voltage detection circuit provided corresponding to a predetermined resistance of a resistance circuit composed of a plurality of resistors for dividing the voltage of the output terminal, 11. The method of manufacturing a semiconductor device according to claim 10 , wherein temperature characteristics of a reference voltage are obtained and trimming is selectively performed collectively so that a voltage of the output terminal becomes a desired voltage .

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