JP4817443B2 - Plasma mask CVD equipment - Google Patents

Plasma mask CVD equipment Download PDF

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JP4817443B2
JP4817443B2 JP2006211714A JP2006211714A JP4817443B2 JP 4817443 B2 JP4817443 B2 JP 4817443B2 JP 2006211714 A JP2006211714 A JP 2006211714A JP 2006211714 A JP2006211714 A JP 2006211714A JP 4817443 B2 JP4817443 B2 JP 4817443B2
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mask
substrate
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秀一 宮本
幹夫 浅田
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Canon Tokki Corp
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Description

本発明は、プラズマ方式マスクCVD装置に関する。   The present invention relates to a plasma type mask CVD apparatus.

有機EL(エレクトロルミネッセンス)素子は、基板上に電極膜やRGBの有機発光層を形成して製造されるが、大気中の湿分(水分)及び酸素によって劣化して素子の寿命を損ない易い。そこで、通常、電極と有機物層の露出部分を保護膜で封止することが行われている。このような保護膜としては、各種無機膜(窒化シリコン膜)をプラズマCVD法により成膜したものが一般に用いられている。プラズマCVD法は、対向するカソード電極とアノード電極間の放電空間に電圧を印加し、原料ガスをプラズマ化させて基板上に成膜する方法であり、熱CVD法より低温での成膜が可能であるという利点がある。   An organic EL (electroluminescence) element is manufactured by forming an electrode film or an RGB organic light emitting layer on a substrate. Therefore, usually, the exposed portions of the electrode and the organic layer are sealed with a protective film. As such a protective film, a film in which various inorganic films (silicon nitride films) are formed by a plasma CVD method is generally used. The plasma CVD method is a method in which a voltage is applied to the discharge space between the cathode electrode and the anode electrode facing each other, and the source gas is turned into a plasma to form a film on the substrate. There is an advantage of being.

プラズマCVD装置としては、基板を装置の下側電極上に配置したデポダウン(又はフェースアップ)方式が一般に知られている(特許文献1、2参照)。一方、本発明者らは、基板を装置の上側電極の下面に配置したデポアップ方式のCVD装置を提案している(特許文献3参照)。
又、保護膜は、有機EL層の所定部分に成膜される必要があるため、通常、マスクを用いてCVD成膜が行われる。
As a plasma CVD apparatus, a deposition down (or face up) system in which a substrate is disposed on a lower electrode of the apparatus is generally known (see Patent Documents 1 and 2). On the other hand, the present inventors have proposed a deposition-up type CVD apparatus in which a substrate is disposed on the lower surface of the upper electrode of the apparatus (see Patent Document 3).
Further, since the protective film needs to be formed on a predetermined portion of the organic EL layer, the CVD film formation is usually performed using a mask.

特開2005-339828号公報(図4、図6)JP 2005-339828 A (FIGS. 4 and 6) 特開2006-164543号公報(図2)JP 2006-164543 A (FIG. 2) 特開2006-45583号公報(図2)JP 2006-45583 A (FIG. 2)

しかしながら、上記したデポダウン方式のプラズマCVD装置の場合、基板上に配置されるマスクが成膜時に熱膨張し、基板との間で密着不良を起こしたり、マスク精度を損なうことがある。又、デポダウン方式の場合、パーティクル(ごみ粒子)が落下して成膜面(デバイス面)に付着するという問題もある。
一方、デポアップ方式のプラズマCVD装置の場合、パーティクルの問題は生じず、成膜品質を向上させることができる。しかし、上記特許文献3記載の技術の場合、マスクフレーム(マスクの周縁を保持する枠体)が電極面(基板)より下側に突出しているため、上下電極間近傍のプラズマ放電空間の形状が均一でない(上下電極の対向領域からマスクフレームへ離れるにつれてプラズマ放電空間が湾曲する)場合があり、成膜の均一性の点でさらなる改善の可能性がある。
However, in the case of the above-described deposition down type plasma CVD apparatus, the mask disposed on the substrate may thermally expand during film formation, which may cause poor adhesion with the substrate or impair mask accuracy. In the case of the deposition down method, there is also a problem that particles (dust particles) fall and adhere to the film formation surface (device surface).
On the other hand, in the case of a deposition CVD plasma CVD apparatus, the problem of particles does not occur, and the film formation quality can be improved. However, in the case of the technique described in Patent Document 3, since the mask frame (frame body that holds the periphery of the mask) protrudes below the electrode surface (substrate), the shape of the plasma discharge space in the vicinity between the upper and lower electrodes is There is a case where the plasma discharge space is not uniform (the plasma discharge space is curved as the distance from the opposed region of the upper and lower electrodes to the mask frame).

本発明は上記の課題を解決するためになされたものであり、成膜の均一性が高く、パーティクルによる影響を防止することができるプラズマ方式マスクCVD装置の提供を目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a plasma type mask CVD apparatus that has high uniformity of film formation and can prevent the influence of particles.

上記の目的を達成するために、本発明のプラズマ方式マスクCVD装置は、真空槽と、該真空槽内にそれぞれ平行に配置された下側カソード電極及び上側アノード電極と、前記上側アノード電極の下面に基板を介して配置されるマスクの周縁を支持するマスクフレームとを有し、前記下側カソード電極と前記上側アノード電極との間の放電空間に電圧を印加して該放電空間内の原料ガスをプラズマ化させて前記基板上に成膜するプラズマ方式マスクCVD装置であって、前記放電空間近傍において前記マスクフレームの下面は前記マスクの下面と面一であり、かつ該マスクフレームの内側に前記上側アノード電極及び前記基板を収容する空間を有し、この状態で前記マスク、前記基板、及び前記上側アノード電極を重ね合わせ可能である。
このような構成とすると、マスクフレーム下面が上側アノード電極下面(マスク下面)と同一面となり、各電極間近傍の放電空間が均一な形状になる(上下電極の対向領域からマスクフレームへ離れた場合でもプラズマ放電空間は上下電極の面と平行に延びて一様となり、空間が湾曲等しない)ので、基板近傍のプラズマ状態が安定化し、基板の位置によらずに膜厚分布が均一になる。


In order to achieve the above object, a plasma type mask CVD apparatus of the present invention comprises a vacuum chamber, a lower cathode electrode and an upper anode electrode arranged in parallel in the vacuum chamber, and a lower surface of the upper anode electrode, respectively. And a mask frame for supporting a peripheral edge of the mask disposed through the substrate, and applying a voltage to the discharge space between the lower cathode electrode and the upper anode electrode to supply a source gas in the discharge space The plasma mask CVD apparatus for forming a film on the substrate by converting the plasma into a plasma, wherein a lower surface of the mask frame is flush with a lower surface of the mask in the vicinity of the discharge space, and the inner surface of the mask frame There is a space for accommodating the upper anode electrode and the substrate, and the mask, the substrate, and the upper anode electrode can be overlaid in this state.
With this configuration, the lower surface of the mask frame is flush with the lower surface of the upper anode electrode (the lower surface of the mask), and the discharge space in the vicinity of each electrode has a uniform shape (when separated from the opposing area of the upper and lower electrodes to the mask frame) However, the plasma discharge space extends in parallel with the surfaces of the upper and lower electrodes and is uniform, and the space is not curved. Therefore, the plasma state in the vicinity of the substrate is stabilized, and the film thickness distribution is uniform regardless of the position of the substrate.


前記マスクがテンションマスクであって、成膜時の熱膨張とマスク自体の重さによる撓み(以下、自重撓みと称す)が基板の成膜時の自重撓みよりも小さいことが好ましい。
このような構成とすると、マスクのテンションを所定の強さ以上に調節することで、成膜時のマスクの自重撓みを抑制できる。これに加えて、成膜時のマスクの自重撓みを基板の成膜時の自重撓みよりも小さいマスクとすることで、マスクと基板を重合した際の撓みにおいてマスクの撓みが支配的に働くことにより、基板の自重撓みを利用して基板とマスクの密着状態を良好に維持できることとなる。従って、重合したマスクが変形するのを抑制すると共にマスクと基板の密着性も向上でき基板上の成膜レートの均一性や、マスク精度が向上する。
Preferably, the mask is a tension mask, and the deflection due to the thermal expansion during film formation and the weight of the mask itself (hereinafter referred to as self-weight deflection) is smaller than the self-weight deflection during film formation of the substrate.
With such a configuration, the self-weight deflection of the mask during film formation can be suppressed by adjusting the tension of the mask to a predetermined strength or more. In addition, by making the self-weight deflection of the mask at the time of film formation smaller than the self-weight deflection at the time of film formation of the substrate, the mask deflection acts dominantly in the deflection when the mask and the substrate are superposed. Thus, the close contact state between the substrate and the mask can be satisfactorily maintained by utilizing the self-weight bending of the substrate. Accordingly, deformation of the superposed mask can be suppressed and the adhesion between the mask and the substrate can be improved, and the uniformity of the film formation rate on the substrate and the mask accuracy can be improved.

本発明によれば、マスクを用いたプラズマCVDの際、基板への成膜の均一性が高く、パーティクルによる影響を防止することができる。   According to the present invention, when performing plasma CVD using a mask, the uniformity of film formation on a substrate is high, and the influence of particles can be prevented.

以下、本発明の実施形態について、図面を参照して説明する。なお、本発明の実施形態に係るプラズマ方式マスクCVD装置としては、本発明に特有な構成を除いては特開2006-45583号公報記載の装置と同様とすることができるので、この公報と同一の部分は同一の符号を付して説明を適宜引用(又は省略)する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. The plasma-type mask CVD apparatus according to the embodiment of the present invention can be the same as the apparatus described in Japanese Patent Application Laid-Open No. 2006-45583 except for the configuration peculiar to the present invention. These parts are denoted by the same reference numerals, and the description is appropriately cited (or omitted).

図1は、本発明の実施形態に係るプラズマ方式マスクCVD装置の全体構成図である。この図において、プラズマ方式マスクCVD装置は、真空槽1と、該真空槽内にそれぞれ平行に配置された下側カソード電極3及び上側アノード電極2と、上側アノード電極2の下面に基板5を介して配置されるマスク4の周縁と結合する矩形枠状のマスクフレーム50とを有する。マスクフレーム50はマスク4の形状を保持し、補強する機能を有する。   FIG. 1 is an overall configuration diagram of a plasma type mask CVD apparatus according to an embodiment of the present invention. In this figure, a plasma mask CVD apparatus includes a vacuum chamber 1, a lower cathode electrode 3 and an upper anode electrode 2 arranged in parallel in the vacuum chamber, and a substrate 5 on the lower surface of the upper anode electrode 2. And a mask frame 50 having a rectangular frame shape that is coupled to the periphery of the mask 4. The mask frame 50 has a function of maintaining the shape of the mask 4 and reinforcing it.

真空槽1外上部には回転機構24(回転駆動源と回転軸等から成る)、アライメント機構7、カメラ部13、補正駆動機構26が設けられている。これらの機構の作用については特開2006-45583号公報に記載されているものと同様である。
そして、マスクフレーム50に結合し上方に向かって2本のアーム状の連設部23が延び、連設部23はその上方で横方向の棒状部で接続されている。連設部23の横方向棒状部の中心から上方へ向かって1本の中心軸が延び、中心軸が回転機構24中心に接続され、マスクフレーム50が真空槽1内に吊り下げられる。
同様に、上側アノード電極2の上面から上方に向かって2本のアーム状の連設部29が延び、連設部29はその上方で横方向の棒状部で接続されている。連設部29の横方向棒状部の中心から上方へ向かって1本の中心軸が延び、中心軸が回転機構24中心に接続され、上側アノード電極2が真空槽1内に吊り下げられる。
A rotation mechanism 24 (consisting of a rotation drive source and a rotation shaft), an alignment mechanism 7, a camera unit 13, and a correction drive mechanism 26 are provided on the outer top of the vacuum chamber 1. The operation of these mechanisms is the same as that described in JP-A-2006-45583.
Then, two arm-like connecting portions 23 are connected to the mask frame 50 and extend upward, and the connecting portions 23 are connected to each other by a horizontal rod-like portion. One central axis extends upward from the center of the lateral bar-shaped portion of the continuous portion 23, the central axis is connected to the center of the rotating mechanism 24, and the mask frame 50 is suspended in the vacuum chamber 1.
Similarly, two arm-like connecting portions 29 extend upward from the upper surface of the upper anode electrode 2, and the connecting portions 29 are connected to each other by a horizontal bar-like portion. One central axis extends upward from the center of the lateral bar-shaped portion of the continuous portion 29, the central axis is connected to the center of the rotating mechanism 24, and the upper anode electrode 2 is suspended in the vacuum chamber 1.

そして、アライメント機構7及び補正駆動機構26を適宜用い、まず、マスクフレーム50に取付けられたマスク4上にガラス基板5を位置調整してこれらを重合した後、上側アノード電極2を基板5側に押圧(又は近接)させた状態で上側アノード電極2とマスクフレーム50とを図示しないクランプによって固定する。これにより、マスク、基板、及び上側アノード電極が重合され、成膜が可能となる。
なお、基板とマスクのアライメントは、成膜室とは別室として設けられたアライメント室にて行うことも可能である。この場合は、基板とマスクが重合した状態で、前記成膜室のマスクフレームの固定位置に重合物を配設することで、前記と同様に成膜が可能となる。
一方、下側カソード電極3の下面から下方に向かって支持管19が延び、下側カソード電極3を真空槽1に保持する。支持管19内には、図示しない成膜材料ガス(放電ガス)導入管が配置され、下側カソード電極3と上側アノード電極2との間の放電空間に成膜材料ガス(必要に応じてさらに放電ガス)を導入可能になっている。又、真空槽1の下側には、真空ポンプ等から成る真空排気系と接続される排気口22が配置されている。
なお、上側アノード電極2の上部には後述するオイル循環路(加熱機構)が配置され、オイル循環部18から導入された加熱オイルにより上側アノード電極2(及び基板5)の温度を制御する。
Then, using the alignment mechanism 7 and the correction drive mechanism 26 as appropriate, first, the glass substrate 5 is positioned on the mask 4 attached to the mask frame 50 to superpose them, and then the upper anode electrode 2 is placed on the substrate 5 side. The upper anode electrode 2 and the mask frame 50 are fixed by a clamp (not shown) in a pressed (or close) state. As a result, the mask, the substrate, and the upper anode electrode are polymerized to enable film formation.
Note that the alignment of the substrate and the mask can also be performed in an alignment chamber provided as a separate chamber from the film formation chamber. In this case, the film can be formed in the same manner as described above by disposing the polymer at the fixed position of the mask frame in the film forming chamber in a state where the substrate and the mask are polymerized.
On the other hand, the support tube 19 extends downward from the lower surface of the lower cathode electrode 3 to hold the lower cathode electrode 3 in the vacuum chamber 1. A film-forming material gas (discharge gas) introduction tube (not shown) is arranged in the support tube 19, and a film-forming material gas (if necessary, further in the discharge space between the lower cathode electrode 3 and the upper anode electrode 2). Discharge gas) can be introduced. An exhaust port 22 connected to an evacuation system composed of a vacuum pump or the like is disposed below the vacuum chamber 1.
An oil circulation path (heating mechanism), which will be described later, is disposed above the upper anode electrode 2, and the temperature of the upper anode electrode 2 (and the substrate 5) is controlled by the heating oil introduced from the oil circulation unit 18.

上側アノード電極2は接地されてグランド電極をなし、下側カソード電極3には高周波電圧を供給するための電源60がインピーダンスマッチング回路を介して容量接続され、RF電極をなす。そして、基板5を上側アノード電極2の下面に配置して各電極2、3間に高周波電圧を印加し、各電極2、3間の放電空間に導入される成膜材料ガスをプラズマ化させ、CVD成膜を行う。
成膜材料は、マスクフレーム50下面に露出するマスク4の開口部を介して基板5上に堆積し、マスクパターンに沿った成膜が進行する。
The upper anode electrode 2 is grounded to form a ground electrode, and a power source 60 for supplying a high frequency voltage is capacitively connected to the lower cathode electrode 3 through an impedance matching circuit to form an RF electrode. Then, the substrate 5 is disposed on the lower surface of the upper anode electrode 2, a high frequency voltage is applied between the electrodes 2 and 3, and the film forming material gas introduced into the discharge space between the electrodes 2 and 3 is turned into plasma, CVD film formation is performed.
The film forming material is deposited on the substrate 5 through the opening of the mask 4 exposed on the lower surface of the mask frame 50, and the film formation along the mask pattern proceeds.

次に、拡大図2を参照して、各電極2、3周辺の構成について説明する。上側アノード電極2は、それぞれ矩形の下部部材2aと上部部材2bからなり、下部部材2aが下面に露出して実質的な電極として作用する。上部部材2bの内部には等間隔でオイル循環路(加熱機構)12が配置され、上側アノード電極2全体が適宜加熱される。
ここで、下部部材2aの周縁は上部部材2bの周縁より内側に位置し、下部部材2aの側端と上部部材2bの周縁下面との間に段部が形成されている。一方、マスクフレーム50は断面が矩形をなし、マスクフレーム50の内径は下部部材2aの外径より若干大きく、マスクフレーム50の厚みは下部部材2aの厚みより若干薄くなっている。そして、マスク4はマスクフレーム50の下面とほぼ面一(同一面上)になるように、YAG等のレーザービームを用いたポイント溶接により結合されて取付けられている。
なお、マスクフレーム50は正確には、連設部23より内側に位置しマスクを保持するマスクフレーム本体51と、連設部23より外側に位置するマスクフレーム辺部52とからなり、マスクフレームとして実質的に機能する部分はマスクフレーム本体51であるが、便宜上、これらを総称してマスクフレーム50とする。
Next, a configuration around each electrode 2 and 3 will be described with reference to an enlarged view 2. The upper anode electrode 2 is composed of a rectangular lower member 2a and an upper member 2b, respectively, and the lower member 2a is exposed on the lower surface and functions as a substantial electrode. Inside the upper member 2b, oil circulation paths (heating mechanisms) 12 are arranged at equal intervals, and the entire upper anode electrode 2 is appropriately heated.
Here, the periphery of the lower member 2a is located inside the periphery of the upper member 2b, and a step is formed between the side end of the lower member 2a and the lower surface of the periphery of the upper member 2b. On the other hand, the mask frame 50 has a rectangular cross section, the inner diameter of the mask frame 50 is slightly larger than the outer diameter of the lower member 2a, and the thickness of the mask frame 50 is slightly smaller than the thickness of the lower member 2a. The mask 4 is coupled and attached by point welding using a laser beam such as YAG so that it is substantially flush with the lower surface of the mask frame 50 (on the same plane).
The mask frame 50 includes a mask frame main body 51 that is located on the inner side of the connecting portion 23 and holds the mask, and a mask frame side portion 52 that is located on the outer side of the connecting portion 23. The substantially functioning part is the mask frame main body 51, but these are collectively referred to as the mask frame 50 for convenience.

一方、下側カソード電極3の上面には多数の孔11aが格子状に配列したガス吹き付け機構11を備え、各孔11aは下側カソード電極3の内部空間に連通し、この内部空間は支持管19内の成膜材料ガス(放電ガス)導入管15に接続されている。このようにして、基板5上に均一に成膜材料ガスを供給することができる。
なお、下側カソード電極3の下側内部には上側アノード電極2の場合と同様のオイル循環路(加熱機構)12が配置され、オイル循環部16,17により加熱オイルを流入及び流出させて下側カソード電極3の温度を制御する。
On the other hand, the upper surface of the lower cathode electrode 3 is provided with a gas blowing mechanism 11 in which a large number of holes 11a are arranged in a lattice pattern. Each hole 11a communicates with the inner space of the lower cathode electrode 3, and this inner space is supported by a support tube. 19 is connected to a film forming material gas (discharge gas) introduction pipe 15. In this way, the film forming material gas can be uniformly supplied onto the substrate 5.
An oil circulation path (heating mechanism) 12 similar to that in the case of the upper anode electrode 2 is disposed inside the lower cathode electrode 3, and heated oil flows in and out by the oil circulation portions 16 and 17. The temperature of the side cathode electrode 3 is controlled.

図3は、マスクフレーム50、上側アノード電極2、基板5の位置関係を示す。この図において、マスクフレーム50の内側には下部部材2a及び基板5を収容する空間を有し、この状態でマスク、基板、及び上側アノード電極を重合して成膜することが可能となる。なお、この際、マスクフレーム50の上部は図2で説明した段部に収容される。
このようにすると、マスクフレーム50下面が電極2下面(正確にはマスク4下面)と平行になり、各電極2、3間近傍の放電空間6が均一な形状になる(上下電極からマスクフレーム側へ向かって上下電極の面と平行なプラズマ放電空間が一様に形成され、プラズマ放電空間が上下に湾曲することがない)ので、基板近傍のプラズマ状態が安定化し、基板の位置によらずに膜厚分布が均一になる。
FIG. 3 shows the positional relationship between the mask frame 50, the upper anode electrode 2, and the substrate 5. In this figure, there is a space for accommodating the lower member 2a and the substrate 5 inside the mask frame 50. In this state, the mask, the substrate, and the upper anode electrode can be polymerized to form a film. At this time, the upper portion of the mask frame 50 is accommodated in the step portion described with reference to FIG.
In this way, the lower surface of the mask frame 50 is parallel to the lower surface of the electrode 2 (more precisely, the lower surface of the mask 4), and the discharge space 6 between the electrodes 2 and 3 becomes a uniform shape (from the upper and lower electrodes to the mask frame side). The plasma discharge space parallel to the surface of the upper and lower electrodes is uniformly formed and the plasma discharge space is not curved up and down), so that the plasma state in the vicinity of the substrate is stabilized, regardless of the position of the substrate. The film thickness distribution becomes uniform.

図2に戻り、本発明においても、特開2006-45583号公報に記載されているものと同様なプラズマ漏出阻止機構8を備えていることが好ましい。プラズマ漏出阻止機構8は、各電極2、3の対向面にそれぞれ平行な2つの絶縁領域形成体9からなる。
上側アノード電極2側の絶縁領域形成体9は連設部23より外側のマスクフレーム辺部52下面に取付けられ、マスクフレーム本体51を囲む枠体をなす。同様に、下側カソード電極3側の絶縁領域形成体9は下側カソード電極3を囲む枠体をなす。
Returning to FIG. 2, it is preferable that the present invention also includes a plasma leakage prevention mechanism 8 similar to that described in Japanese Patent Laid-Open No. 2006-45583. The plasma leakage prevention mechanism 8 includes two insulating region forming bodies 9 that are parallel to the opposing surfaces of the electrodes 2 and 3, respectively.
The insulating region forming body 9 on the upper anode electrode 2 side is attached to the lower surface of the mask frame side portion 52 outside the connecting portion 23 and forms a frame surrounding the mask frame main body 51. Similarly, the insulating region forming body 9 on the lower cathode electrode 3 side forms a frame surrounding the lower cathode electrode 3.

従って、各電極2、3の対向面にそれぞれ平行に、かつ放電空間6の外側に絶縁領域形成体9が対向近接し、放電空間6の外周位置に空間部6を囲って絶縁領域が形成される。
従って、各電極2・3に電圧を印加しても、この絶縁領域では成膜材料ガスがプラズマ化せず、空間6からのプラズマの漏出を阻止できる。また、放電空間6内のプラズマ化した成膜材料ガスは、空間6と連通する絶縁領域形成体9の対向空間10を介してアライメント機構7側に排出されるが、この際に成膜材料ガスのプラズマが消失する。従って、真空槽1のアライメント機構7等をプラズマガスが汚染することがない。
なお、絶縁領域形成体9として使用できる材料としては、特開2006-45583号公報に記載されているものが例示できる。
Accordingly, the insulating region forming body 9 is opposed to and close to the opposing surfaces of the electrodes 2 and 3 and outside the discharge space 6, and an insulating region is formed at the outer peripheral position of the discharge space 6 so as to surround the space 6. The
Therefore, even if a voltage is applied to each of the electrodes 2 and 3, the film forming material gas is not converted into plasma in this insulating region, and leakage of plasma from the space 6 can be prevented. Further, the film forming material gas converted into plasma in the discharge space 6 is discharged to the alignment mechanism 7 side through the facing space 10 of the insulating region forming body 9 communicating with the space 6. At this time, the film forming material gas is discharged. The plasma disappears. Therefore, the plasma gas does not contaminate the alignment mechanism 7 or the like of the vacuum chamber 1.
Examples of materials that can be used for the insulating region forming body 9 include those described in JP-A-2006-45583.

<テンションマスク>
マスク4としてはテンションマスクを用いることが好ましく、成膜時のマスクの自重撓みが基板の成膜時の自重撓みよりも小さいものであることがより好ましい。マスクの張力としては、基板の自重撓みによってマスクが変形するのを抑制できるレベルであればよく、好ましくは、基板5面と下側カソード電極3上面との距離の差が周縁部と中心部(最も基板撓みの大きい部分)とで5%以下、より好ましくは3〜2%とする。上記距離差が5%を超える場合、成膜した材料の膜厚が基板の位置によって変化する。ここで、膜厚の差異は膜質にも影響するため、得られた素子の局所的な封止性能が低下したり、最低膜厚部を基準として膜厚の制御を行う場合には、成膜時間を延長する必要がありスループットの低下が顕著になるなどの問題が生じる。
上記距離差が5%以下であれば、基板上の成膜レート並びに膜質の均一性、ひいては膜質の均一性やマスク精度が向上する。特に、本発明においてはマスクフレーム50の下側にマスク4を通常は結合させて取り付けるため、マスクの下側からマスクフレームで支持する場合に比べてマスクが撓みやすく、この点でもテンションマスクが有効である。マスクに与える張力は、マスクの材質に対する線熱膨張係数、使用時の温度及びマスクの大きさ(厚さ、重さ、面積)を考慮して成膜時の撓みをコンピューターによるシミュレーション等により決定可能である。
本発明においては、成膜時のマスク及び基板の自重撓みを、上記したコンピューターシミュレーションにより決定した値とすることができる。コンピューターによるシミュレーション方法としては、例えば、公知のCAE(Computer Aided Engineering:コンピュータによる数値解析、シミュレーション)解析プログラム等により材料のキャラクターを入力して計算することができる。
<Tension mask>
It is preferable to use a tension mask as the mask 4, and it is more preferable that the self-weight deflection at the time of film formation is smaller than the self-weight deflection at the time of film formation of the substrate. The tension of the mask is not particularly limited as long as the mask can be prevented from being deformed by its own weight deflection. Preferably, the difference in distance between the surface of the substrate 5 and the upper surface of the lower cathode electrode 3 is a peripheral portion and a central portion ( 5% or less, and more preferably 3 to 2%. When the distance difference exceeds 5%, the film thickness of the deposited material varies depending on the position of the substrate. Here, since the difference in film thickness also affects the film quality, when the local sealing performance of the obtained element deteriorates or the film thickness is controlled based on the minimum film thickness portion, the film is formed. There is a problem that it is necessary to extend the time and the decrease in throughput becomes remarkable.
When the distance difference is 5% or less, the film formation rate on the substrate and the film quality uniformity, and hence the film quality uniformity and mask accuracy are improved. In particular, in the present invention, since the mask 4 is usually bonded and attached to the lower side of the mask frame 50, the mask is easily bent as compared with the case where the mask frame is supported from the lower side of the mask. It is. The tension applied to the mask can be determined by computer simulation, etc., taking into account the linear thermal expansion coefficient for the mask material, temperature during use, and mask size (thickness, weight, area). It is.
In the present invention, the self-weight deflection of the mask and the substrate during film formation can be a value determined by the above-described computer simulation. As a computer simulation method, for example, a material character can be input and calculated by a known CAE (Computer Aided Engineering: computer numerical analysis, simulation) analysis program or the like.

なお、通常、プラズマCVDの前工程でマスクに基板を載置した後、マスクと基板とを反転させてプラズマCVDの処理に供するが、デポアップ方式を採用する本発明によれば、このような反転が不要となる。   Normally, after placing the substrate on the mask in the previous step of plasma CVD, the mask and the substrate are inverted and used for plasma CVD processing. According to the present invention employing the deposition method, such inversion is performed. Is no longer necessary.

本発明の実施形態に係るプラズマ方式マスクCVD装置の全体構成図である。1 is an overall configuration diagram of a plasma type mask CVD apparatus according to an embodiment of the present invention. 図1の部分拡大図である。It is the elements on larger scale of FIG. マスクフレーム50、上側アノード電極2、基板5の位置関係を示す図である。FIG. 4 is a diagram showing a positional relationship among a mask frame 50, an upper anode electrode 2, and a substrate 5.

符号の説明Explanation of symbols

1 真空槽
2 上側アノード電極
3 下側カソード電極
4 マスク
5 基板
50 マスクフレーム
DESCRIPTION OF SYMBOLS 1 Vacuum chamber 2 Upper anode electrode 3 Lower cathode electrode 4 Mask 5 Substrate 50 Mask frame

Claims (2)

真空槽と、該真空槽内にそれぞれ平行に配置された下側カソード電極及び上側アノード電極と、前記上側アノード電極の下面に基板を介して配置されるマスクの周縁を支持するマスクフレームとを有し、前記下側カソード電極と前記上側アノード電極との間の放電空間に電圧を印加して該放電空間内の原料ガスをプラズマ化させて前記基板上に成膜するプラズマ方式マスクCVD装置であって、
前記放電空間近傍において前記マスクフレームの下面は前記マスクの下面と面一であり、かつ該マスクフレームの内側に前記上側アノード電極及び前記基板を収容する空間を有し、この状態で前記マスク、前記基板、及び前記上側アノード電極を重ね合わせ可能であるプラズマ方式マスクCVD装置。
A vacuum chamber; a lower cathode electrode and an upper anode electrode arranged in parallel in the vacuum chamber; and a mask frame for supporting a peripheral edge of a mask arranged on a lower surface of the upper anode electrode through a substrate. And a plasma type mask CVD apparatus for forming a film on the substrate by applying a voltage to the discharge space between the lower cathode electrode and the upper anode electrode to convert the source gas in the discharge space into plasma. And
In the vicinity of the discharge space, the lower surface of the mask frame is flush with the lower surface of the mask and has a space for accommodating the upper anode electrode and the substrate inside the mask frame. A plasma-type mask CVD apparatus capable of overlaying a substrate and the upper anode electrode.
前記マスクがテンションマスクであって、成膜時の自重撓みが成膜時の基板の自重撓みよりも小さいことを特徴とする請求項1記載のプラズマ方式マスクCVD装置。
2. The plasma type mask CVD apparatus according to claim 1, wherein the mask is a tension mask, and the self-weight deflection at the time of film formation is smaller than the self-weight deflection of the substrate at the time of film formation.
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