JP4810832B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a so-called composite type semiconductor device in which a plurality of types of switching structures are formed in the same semiconductor layer. In particular, the present invention relates to a method of manufacturing a composite semiconductor device having at least a first switching structure using a first dopant region and a second switching structure using a second dopant region. The present invention is also useful for manufacturing a semiconductor device having third and fourth switching structures.
The dopant region in this specification refers to a region in which p-type or n-type impurity atoms are added to a semiconductor. Different types of switching structures include switching structures with different structural elements themselves, switching structures with different structural element shapes, switching structures with different conductivity types, and the like.

Composite semiconductor devices are being developed. The switching structure is configured using a dopant region in which p-type or n-type impurity atoms are added to a semiconductor. Therefore, the composite semiconductor device having the first switching structure and the second switching structure of different types includes the first dopant region for the first switching structure and the second dopant region for the second switching structure. . In order to manufacture a composite type semiconductor device, it is necessary to form a first dopant region and a second dopant region.
In the prior art, a first dopant region is formed by doping through a mask having an opening corresponding to the first dopant region, and a second dopant region is formed by doping through a mask having an opening corresponding to the second dopant region. Was. According to this technique, two or more masks are required, the number of manufacturing steps is large, and the yield is also reduced. According to the conventional technique in which two or more masks are selectively used, the time required for the production becomes longer and the production cost increases.
In order to solve this problem, Patent Document 1 proposes a technique of simultaneously forming a first dopant region and a second dopant region using a single common mask. In Patent Document 1, a single common mask is used to simultaneously form an n-type drain region (an example of a first dopant region) of a lateral MOSFET and an n-type well region (an example of a second dopant region) of a CMOS. Propose the technology to form. In the technique of Patent Document 1, an n-type drain region and an n-type drain region are introduced by introducing an n-type dopant through a mask having openings corresponding to both the n-type drain region and the n-type well region on the surface of the semiconductor layer. A mold well region is formed simultaneously.
A related technique is also proposed in Patent Document 2 and the like.
JP-A-7-307401 JP-A-8-107151 JP 2000-183181 A

When the technique of Patent Document 1 is used, the first dopant region and the second dopant region can be formed simultaneously. However, in order to form simultaneously, the dopant concentration of a 1st dopant area | region and a 2nd dopant area | region cannot be changed. However, the required dopant concentration is often different between the first dopant region for the first switching structure and the second dopant region for the second switching structure. In the technique of Patent Document 1, when doping is performed according to the conditions required for the first dopant region, a preferable dopant concentration cannot be obtained in the second dopant region, and when doping is performed according to the conditions required for the second dopant region. A preferable dopant concentration cannot be obtained in the first dopant region. In the technique of Patent Document 1, since the first dopant region and the second dopant region are formed at the same time, the doping condition required for the first region and the doping condition required for the second region cannot be accommodated. . In the technique of Patent Document 1, it is accepted that the second dopant region deviates from the optimum condition by optimizing the first dopant region, or the first dopant region is removed from the optimum condition by optimizing the second dopant region. It may be necessary to compromise or to compromise by choosing doping conditions that are both appropriate but not optimal.
The present invention has been developed to solve the above-described problems. The first dopant region is optimally doped in the first region, the second dopant region is optimally doped in the second region, and A technique capable of simultaneously doping a first region and a second region is provided.

As described above, the required dopant concentration is often different between the first dopant region for the first switching structure and the second dopant region for the second switching structure. If this phenomenon is well studied, there is rarely a need to have different doping concentrations in the first region and the second region at the same depth of the semiconductor layer. And the depth of the important doping concentration in the second region is often different. For example, in the first region, it is important to adjust the dopant concentration in the shallow portion to a desired concentration and the dopant concentration in the deep portion is not important, whereas in the second region, the dopant concentration in the deep portion is adjusted to the desired concentration. Is important, and the dopant concentration in the shallow part is often unimportant.
If the depth of the important dopant concentration in the first region is different from the depth of the important dopant concentration in the second region, the first region and the second region are simultaneously formed using one common mask, In the region, the dopant concentration having an important depth in the first region can be adjusted to a necessary concentration, and in the second region, the dopant concentration having an important depth can be adjusted to the necessary concentration in the second region. The present invention has succeeded in this, and by performing a plurality of doping processes using different doping conditions while using one common mask, the first region has an important depth in the first region. In the second region, the doping concentration at an important depth in the second region was successfully adjusted to the necessary concentration.

The manufacturing method of the present invention includes a composite type semiconductor device having a lateral first MOSFET that uses a body region and a lateral second MOSFET that uses an offset drain region in which a current flows in a deep portion and has a conductivity type opposite to that of the first MOSFET . Suitable for manufacturing.
In this manufacturing method , the dopant is introduced into the shallow part of the body region and the offset drain region through the mask having openings corresponding to both the body region and the offset drain region on the surface of the semiconductor layer under the first condition. A first doping step is provided. Furthermore, a second doping step is provided in which the surface of the semiconductor layer is doped through the mask under a second condition and a dopant is introduced into the deep portions of the body region and the offset drain region . Furthermore, a step of forming a field oxide film on a part of the surface of the semiconductor layer forming the offset drain region is provided.
There is no restriction on the order of performing the first doping step, the second doping step, and the step of forming the field oxide film. The doping conditions may change discontinuously between the first doping process and the second doping process, but the doping conditions may change continuously.
In the doping step, an ion implantation method, a laser doping method, a plasma doping method, or the like can be used, or a combination of these methods can be used.
The doping conditions include (1) energy introduced during doping (eV), (2) type of dopant used during doping, (3) introduction angle during doping, (4) ambient temperature during doping, (5) The doping technique can be changed. The case where the doping condition is changed includes the case where any one of the above conditions is changed or the combination of the above conditions is changed.
According to this manufacturing method, by using a single common mask, the doping concentration of the depth important in the body region is adjusted in the body region to a necessary concentration in the body region, and important in the offset drain region in the offset drain region. It is possible to adjust the doping concentration at a proper depth to a concentration necessary for the offset drain region.
As the first condition, a condition for introducing a dopant into the shallow portion of the body region is selected based on a desired gate voltage threshold. As the second condition, a condition for introducing a dopant into the deep portion of the offset drain region is selected based on a desired on-resistance. Specifically, the implantation energy under the first condition is lower than the implantation energy under the second condition. Furthermore, the peak concentration of the dopant introduced under the first condition is thinner than the peak concentration of the dopant introduced under the second condition. Here, the terms “shallow part” and “deep part” refer to the relative positional relationship in the semiconductor layer, the side closer to the surface is called “shallow part”, and the side far from the surface is called “deep part”. . Macroscopically, both may exist near the surface in the semiconductor layer.
The dopant concentration in the shallow part of the body region is closely related to the threshold value of the gate voltage. On the other hand, the dopant concentration in the deep portion of the offset drain region is closely related to the on-resistance. Therefore, the gate voltage threshold can be adjusted to a desired value by performing the first doping step under the condition that the dopant concentration that sets the gate voltage threshold to a desired value is introduced into the shallow portion of the body region. . On the other hand, the on-resistance can be adjusted to a desired value by performing the second doping step under the condition that the dopant concentration that sets the on-resistance to a desired value is introduced deep in the offset drain.
If the condition for introducing the dopant into the shallow portion of the body region is selected, the dopant is also introduced into the shallow portion of the offset drain region. However, since the latter is not technically important, the condition for introducing the dopant into the shallow portion is referred to as the condition for introducing the dopant into the shallow portion of the body region. Similarly, if the condition for introducing the dopant into the deep portion of the offset drain region is selected, the dopant is also introduced into the deep portion of the body region. However, since the latter is not technically important, the condition for introducing the dopant into the deep part is referred to as the condition for introducing the dopant into the shallow part of the offset drain region.
Further, by forming a field oxide film on the surface of the semiconductor layer, a current flowing in the offset drain region flows in a deep portion of the offset drain region. Therefore, the dopant concentration in the deep portion of the offset drain region becomes more important for the on-resistance characteristics of the second switching structure. According to the manufacturing method of the present invention, the dopant concentration distribution in the depth direction of the semiconductor layer can be variously adjusted. The dopant concentration in the deep portion of the offset drain region can be optimized. Therefore, the manufacturing method of the present invention is particularly useful for a semiconductor device in which a current flows in the deep part of the offset drain region by forming a field oxide film on the surface of the semiconductor layer.

It is preferable that the dopant introduced in the first doping step and the dopant introduced in the second doping step are the same type.
When the same dopant is used for the doping process, the first doping process and the second doping process can be performed by changing the operating conditions of the doping apparatus, thereby simplifying the manufacturing process.

It is preferable to implant ions with low energy in the first doping step and implant ions with high energy in the second doping step.
When an ion implantation apparatus is used in the doping process, the dopant implantation depth can be changed by changing the implantation energy. Relatively simply, in the first dopant region, an important depth doping concentration in the first dopant region is adjusted to a required concentration, and in the second dopant region an important depth doping concentration is required in the second dopant region. It becomes possible to adjust the density.

According to the present invention, by using a single mask, when forming the first dopant region of the first MOSFET and the second dopant region of the second MOSFET simultaneously, the first dopant region depth important first dopant region The doping concentration can be adjusted to a necessary concentration. In the second dopant region, a doping concentration at a depth important in the second dopant region can be adjusted to a necessary concentration.
The manufacturing process of the semiconductor device can be simplified without impairing the characteristics of the semiconductor device.

The main features of the examples are listed.
(First Embodiment) In the doping process, an ion implantation apparatus using a high acceleration voltage is used.
(2nd form) When the dopant concentration distribution of the depth direction of a semiconductor is observed, ion implantation is carried out on condition that a peak is observed in the intermediate depth.
(3rd form) Ion implantation conditions are changed discontinuously.

  With reference to FIGS. 1-7, the manufacturing method of the semiconductor device of a present Example is demonstrated. In this embodiment, a lateral n-MOSFET (an example of a first switching structure) using a p-type body region 42 (an example of a first dopant region: hereinafter referred to as an n-MOS body region) shown in FIG. A lateral p-MOSFET (an example of a second switching structure) using a p-type offset drain region 44 (an example of a second dopant region: hereinafter referred to as a p-MOS offset drain region) is formed in the same semiconductor layer. The combined semiconductor device is manufactured. In FIG. 7, another switching structure such as a CMOS, a diode, or an IGBT may be formed in another region of the semiconductor layer (not shown). In addition, a resistor structure, a capacitor structure, or the like may be formed in another region of the semiconductor layer (not shown). In this embodiment, only a cross-sectional view of the main part of the n-MOSFET and p-MOSFET regions in which the manufacturing method of this embodiment is utilized will be described. A feature of this manufacturing method is that an n-MOS body region 42 which is a component of an n-MOSFET and a p-MOS offset drain region 44 which is a component of a p-MOSFET are simultaneously formed using a single mask. It is characterized in that Further, the p-MOS body region 54 that is a component of the p-MOSFET and the n-MOS offset drain region 52 that is a component of the n-MOSFET are formed using another mask. Has characteristics.

First, as shown in FIG. 1, a semiconductor layer 26 is prepared. The semiconductor layer 26 includes a p-type semiconductor substrate 22 made of silicon single crystal and an n-type epitaxial layer 24 made of silicon single crystal covering the surface of the semiconductor substrate 22. The epitaxial layer 24 can be obtained by epitaxially growing, for example, an n-type silicon single crystal on the surface of the semiconductor substrate 22.
Next, as shown in FIG. 2, a p ⁺ -type sinker region 32 is selectively formed in the epitaxial layer 24 by using, for example, a solid phase diffusion technique using a boron-doped oxide film (BSG). The sinker region 32 penetrates through the epitaxial layer 24 and reaches the semiconductor substrate 22. The sinker region 32 is formed so as to divide the epitaxial layer 24 into a plurality of regions when the semiconductor layer 26 is viewed in plan. The epitaxial layer 24 is partitioned into a plurality of island regions by the sinker region 32. As shown in FIG. 2, FIG. 27 is a cross section of one island-like region, and an n-MOSFET is formed in this island-like region 27. Note that the left island region 27 where the n-MOSFET is formed is referred to as the left island region 27. On the other hand, a p-MOSFET is formed in the island-shaped region shown in FIG. This right island region 28 is referred to as a right island region 28. Both the left island region 27 and the right island region 28 are n type semiconductor regions surrounded by a p type sinker region 32 and a p type semiconductor substrate 22. Both the n-type left island region 27 and the n-type right island region 28 are insulated from the surrounding semiconductor region by a pn junction.

  Next, as shown in FIG. 3, field oxide films 34, 36, and 38 are selectively formed on the surface of the epitaxial layer 24 by using the LOCOS method. The LOCOS method includes the following steps. First, after an oxide film and a nitride film are sequentially formed on the surface of the epitaxial layer 24, an oxide film and a nitride film corresponding to a region in which the field oxide films 34, 36, and 38 are to be formed using a photolithography technique and an etching technique. And the surface of the epitaxial layer 24 is exposed. Next, for example, heat treatment at 1100 ° C. is performed in an oxygen atmosphere. As a result, the exposed region is selectively oxidized to form field oxide films 34, 36, and 38 having a layer thickness of about 500 nm. Part of the field oxide films 34, 36 and 38 are formed in a state of entering the epitaxial layer 24. Here, the field oxide film 36 formed in the left island region 27 is referred to as a left field oxide film 36, and the field oxide film 38 formed in the right island region 28 is referred to as a right field oxide film 38.

Next, referring to FIG. 4, an n-MOS body region 42 that is a component of the n-MOSFET and a p-MOS offset drain region 44 that is a component of the p-MOSFET are combined into one mask 82. The process of forming simultaneously using will be described.
First, a sacrificial oxide film having a thickness of about 20 nm is uniformly formed on the surface of the epitaxial layer 24 (not shown in FIG. 4 because it is too thin). After the sacrificial oxide film is formed uniformly, as shown in FIG. 4A, an opening 82a corresponding to the n-MOS body region 42, which is a component of the n-MOSFET, and a component of the p-MOSFET are used. A mask 82 having an opening 82b corresponding to a certain p-MOS offset drain region 44 is formed on the surface of the epitaxial layer 24 (specifically, the surface of the sacrificial oxide film). For example, a resist material is used for the mask 82. The openings 82a and 82b can be formed in a desired positional relationship using a photolithography technique and an etching technique.

Next, as shown in FIG. 4A, ionized boron is implanted through the mask 82 into the surface of the epitaxial layer 24. Ionized boron is introduced from the surface of the epitaxial layer 24 through the openings 82a and 82b. In this ion implantation process, an ion implantation apparatus that can use a high acceleration voltage is used.
In this embodiment, the injection process is repeated four times while switching from an injection condition with a high injection energy to a low injection condition.
First, implantation is performed with the highest implantation energy (about 400 keV). When implanted with high energy, boron passes through the shallow portion of the epitaxial layer 24 and is implanted exclusively into a deep portion. When the boron concentration distribution in the depth direction of the epitaxial layer 24 is observed, the highest concentration is observed in the deep part (see 42a and 44a in FIG. 4A). Implanting under the condition that the highest concentration is observed in the deep part is usually called the retrograde method or the reverse gradient ion implantation method.
Next, implantation is performed at a slightly lower implantation energy (about 280 keV). In the second implantation, implantation is performed so that the highest boron concentration is obtained in 42b and 44b in FIG.
Next, implantation is performed at a lower implantation energy (about 130 keV). In the third implantation, implantation is performed so that the highest boron concentration is obtained in 42c and 44c in FIG.
Finally, implantation is performed with the lowest implantation energy (about 30 keV). In the fourth implantation, as shown by 42d and 44d in FIG. 4D, implantation is performed so that the highest boron concentration is obtained in the shallow portion.
In this embodiment, a total of four ion implantation steps are performed on the surface of the epitaxial layer 24 through the mask 82 while changing the implantation energy. In the ion implantation of this embodiment, since the high acceleration voltage ion implantation apparatus is used, the ion implantation amount can be increased. Therefore, the heat treatment step necessary for diffusing the implanted ions can be completed at a low temperature and / or in a short time. For this reason, a dedicated heat treatment step for diffusing the implanted ions can be omitted, and the heat treatment step can also be used.
By performing the ion implantation process through the mask 82, both the n-MOS body region 42 and the p-MOS offset drain region 44 are formed in the epitaxial layer 24 as shown in FIG. be able to. In addition, when it is desired to form a wide dopant region, a heat treatment step may be performed as necessary.

  FIG. 8 shows a dopant concentration distribution corresponding to the line VIII-VIII shown in FIG. 4E, that is, a dopant concentration distribution in the depth direction of the n-MOS body region 42. The dopant concentration distribution in the depth direction of the p-MOS offset drain region 44 is also formed in the same manner as the n-MOS body region 42. As shown by the broken line in FIG. 8, the dopant concentration distribution in the n-MOS body region 42 and the p-MOS offset drain region 44 is adjusted with respect to the depth direction by performing ion implantation multiple times. ing. By performing ion implantation a plurality of times, a dopant concentration distribution that cannot be obtained by a single ion implantation step can be obtained. The dopant concentration in the shallow portion of the n-MOS body region 42 is closely related to the threshold value of the gate voltage. For this reason, it is necessary to adjust the dopant concentration in the shallow portion of the n-MOS body region 42 to a desired value. On the other hand, the dopant concentration in the deep portion of the p-MOS offset drain region 44 is closely related to the on-resistance of the p-MOSFET. For this reason, it is necessary to adjust the dopant concentration in the deep portion of the p-MOS offset drain region 44 to a desired value. In particular, in the present embodiment, since the right field oxide film 38 is formed on the surface of the p-MOS offset drain region 44, the current flowing through the p-MOS offset drain region 44 is The existence restricts the flow on the shallow portion side, and flows in the deep portion of the p-MOS offset drain region 44. Therefore, the dopant concentration in the deep portion of the p-MOS offset drain region 44 is more important for the on-resistance of the p-MOSFET. In this embodiment, the peak of the ion implantation amount suitable for the on-resistance is formed in the deep portion of the epitaxial layer 24 by the first and second ion implantation steps. Therefore, the dopant concentration in the deep portion of the p-MOS offset drain region 44 can be increased, and a low on-resistance p-MOSFET can be obtained. In this embodiment, the ion implantation amount peak suitable for optimization of the gate voltage threshold, suppression of the short channel effect or the snapback phenomenon is formed in the shallow portion of the epitaxial layer 24 by the third and fourth ion implantations. is doing. Therefore, the dopant concentration in the shallow portion of the n-MOS body region 42 is optimized, and an n-MOSFET operating at a necessary threshold value can be obtained. In this way, a desired dopant concentration can be obtained in the depth direction of the epitaxial layer 24 by performing ion implantation multiple times with different implantation energies. The dopant concentration at a depth important for the characteristics of the n-MOS body region 42 can be adjusted to a desired concentration, and the dopant concentration at a depth important for the characteristics of the p-MOS offset drain region 44 can be adjusted to a desired value. The concentration can be adjusted.

Next, with reference to FIG. 5, a process of forming the body region 54 constituting the p-MOSFET structure and the offset drain region 52 constituting the n-MOSFET structure will be described. This process also uses the technical idea described with reference to FIG.
First, as shown in FIG. 5A, an opening 84a corresponding to the n-MOS offset drain region 52 constituting the n-MOSFET and an opening corresponding to the p-MOS body region 54 constituting the p-MOSFET. A mask 84 having 84b is formed on the surface of the epitaxial layer 24 (specifically, the surface of the sacrificial oxide film). Next, ionized phosphorus is implanted into the surface of the epitaxial layer 24 through the mask 84. Ionized phosphorus is introduced from the surface of the epitaxial layer 24 through the openings 84a and 84b. In this embodiment, the injection process is repeated four times while switching from an injection condition with a high injection energy to a low injection condition.
First, implantation is performed with the highest implantation energy (about 1 MeV). When implanted with high energy, phosphorus passes through the shallow portion of the epitaxial layer 24 and is implanted exclusively into the deep portion. When the phosphorus concentration distribution in the depth direction of the epitaxial layer 24 is observed, the highest concentration is observed in the deep part (see 52a and 54a in FIG. 5A).
Next, implantation is performed at a slightly lower implantation energy (about 700 keV). In the second injection, injection is performed so that the highest phosphorus concentration is obtained in 52b and 54b of FIG.
Next, implantation is performed at a lower implantation energy (about 400 keV). In the third injection, injection is performed so that the highest phosphorus concentration is obtained at 52c and 54c in FIG.
Finally, the implantation is performed with the lowest implantation energy (about 150 keV). In the fourth implantation, as shown by 52d and 54d in FIG. 5D, the implantation is performed so that the highest phosphorus concentration is obtained in the shallow portion. By performing ion implantation a total of four times while changing the implantation energy, the dopant concentration distributions in the n-MOS offset drain region 52 and the p-MOS body region 54 can be adjusted in the depth direction. .
By the first and second ion implantations, the ion implantation amount in the deep portion of the epitaxial layer 24 can be adjusted to an implantation amount that realizes a desired on-resistance. By the third and fourth ion implantations, the ion implantation amount in the shallow portion of the epitaxial layer 24 can be adjusted to an implantation amount that realizes a desired gate voltage threshold, short channel effect, or suppression of the snapback phenomenon. By performing ion implantation a plurality of times while changing the implantation energy, the dopant concentration in the shallow portion of the p-MOS body region 54 can be set to a concentration that realizes a desired gate voltage, and the offset drain region 52 for the n-MOS. The dopant concentration in the deep part can be a concentration that realizes a desired on-resistance.

  After proceeding to the step of FIG. 5E, the sacrificial oxide film covering the surface of the epitaxial layer 24 is removed by wet etching. By this wet etching, defects on the surface of the epitaxial layer 24 are removed. Next, an oxide film to be a gate oxide film later is formed on the surface of the epitaxial layer 24. The thickness of the oxide film is, for example, 15 nm. A polycrystalline silicon film is formed on the surface of the oxide film by a CVD method. Next, phosphorus is introduced into the polycrystalline silicon film at a high concentration to reduce the resistance. Next, by using a photolithography technique and an etching technique, the oxide film and the polycrystalline silicon film are patterned at predetermined positions as shown in FIG. In the left island region 27, the oxide film 62 and the polycrystalline silicon film 64 are patterned so that the center side of the n-MOS body region 42 and the peripheral side of the n-MOS offset drain region 52 are exposed. . A portion of oxide film 62 and polycrystalline silicon film 64 extends on the surface of left field oxide film 36. This is called a field plate or the like, and this structure helps alleviate electric field concentration in the n-MOS offset drain region 52. In the right island region 28, the oxide film 66 and the polycrystalline silicon film 68 are patterned so that the center side of the p-MOS offset drain region 44 and the peripheral side of the p-MOS body region 54 are exposed. . Similarly, a field plate structure is formed in the right island region 28.

  Next, as shown in FIG. 7, ion implantation is selectively performed on the exposed surface of the semiconductor layer 26 by using a photolithography technique and an etching technique. Thus, in the left island region 27, an n-MOS body contact region 73 and an n-MOS source region 72 are formed on the center side of the n-MOS body region 42, and the n-MOS offset drain region 52 is formed. An n-MOS drain region 71 is formed on the peripheral side. Further, in the right island region 28, a p-MOS drain region 75 is formed on the center side of the p-MOS offset drain region 44, and a p-MOS body contact region is formed on the peripheral side of the p-MOS body region 54. 77 and a p-MOS source region 76 are formed. Through these steps, a composite semiconductor device in which an n-MOSFET structure and a p-MOSFET structure are formed in the same semiconductor layer 26 can be obtained.

The above manufacturing method can be the following modification.
In the above example, the case where the implantation energy in the ion implantation step is changed discontinuously is illustrated, but the implantation energy may be continuously reduced. Also in this case, a dopant region having a required dopant concentration can be formed at a predetermined depth. Alternatively, the ion implantation process can be simultaneously performed by selecting a different implantation energy using a plurality of ion implantation apparatuses. Also in this case, a dopant region having a required dopant concentration can be formed at a predetermined depth.

In the above manufacturing method, the combination of the body region constituting the n-MOSFET structure and the offset drain region constituting the p-MOSFET structure, the body region constituting the p-MOSFET structure, and the offset drain region constituting the n-MOSFET structure A method of forming a combination of the above by one mask and a plurality of ion implantations is illustrated. This method can be applied to the following combinations of dopant regions, for example.
(1) A combination of an n-type (or p-type) well region of one switching structure and an n-type (or p-type) body region of the other switching structure.
(2) A combination of an n-type (or p-type) well region of one switching structure and an n-type (or p-type) offset drain region of the other switching structure.
(3) A combination of the base region of one NPN transistor structure and the p-type body region of the other switching structure.
(4) A combination of the base region of one NPN transistor structure and the p-type offset drain region of the other switching structure.

Moreover, in said manufacturing method, the method of adjusting the dopant density | concentration of a depth direction was illustrated by changing the introduction energy at the time of doping. The following method can be used as another method for adjusting the dopant concentration.
(1) You may change the kind of dopant used when doping. The dopant concentration in the depth direction of the semiconductor layer can be adjusted by utilizing the difference in introduction characteristics of the respective dopants. Further, the dopant concentration may be adjusted by combining dopants having different conductivity types.
(2) The introduction angle for doping may be changed. That is, an oblique doping technique may be used. The dopant concentration in the depth direction of the semiconductor layer and / or in a plane parallel to the surface of the semiconductor layer can be adjusted. By adjusting the introduction angle of the oblique doping and the thickness of the mask, a shielding region where the dopant cannot reach the surface of the semiconductor layer can be formed. Thereby, the dopant concentration in a plane parallel to the surface of the semiconductor layer can be adjusted.
(3) You may change the atmospheric temperature at the time of doping. By changing the ambient temperature, the amount of dopant introduced, the density of lattice defects generated in the semiconductor layer, and the like can be changed. By utilizing this phenomenon, the dopant concentration in the depth direction of the semiconductor layer and / or in the plane parallel to the surface of the semiconductor layer can be adjusted.
(4) You may use together the method of utilizing physical phenomena, such as a laser. For example, a laser or the like may be irradiated simultaneously when introducing the dopant. In this case, the amount of dopant introduced, the density of lattice defects generated in the semiconductor layer, and the like can be changed by changing the presence or absence of laser irradiation or the output of laser irradiation. The dopant concentration in the depth direction of the semiconductor layer and / or in a plane parallel to the surface of the semiconductor layer can be adjusted.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The process of the manufacturing method of a composite type semiconductor device is shown (1). The process of the manufacturing method of a composite type semiconductor device is shown (2). The process of the manufacturing method of a composite type semiconductor device is shown (3). The process of the manufacturing method of a composite type semiconductor device is shown (4). The process of the manufacturing method of a composite type semiconductor device is shown (5). The process of the manufacturing method of a composite type semiconductor device is shown (6). The process of the manufacturing method of a composite type semiconductor device is shown (7). The dopant concentration distribution of the depth direction of the body region for n-MOS is shown.

Explanation of symbols

22: Semiconductor substrate 24: Epitaxial layer 26: Semiconductor layer 27: Left island region 28: Right island region 32: Linker regions 34, 36, 38: Field oxide film 42: n-MOS body region 44: p-MOS Offset drain region 52: n-MOS offset drain region 54: p-MOS body region 71: n-MOS drain region 72: n-MOS source region 73: n-MOS body contact region 75: p- MOS drain region 76: p-MOS source region 77: p-MOS body contact region 82, 84: masks 82a, 82b, 84a, 84b: openings

Claims (2)

A method of manufacturing a semiconductor device having a lateral first MOSFET that uses a body region and a lateral second MOSFET that uses an offset drain region in which a current flows in a deep portion and has a conductivity type opposite to that of the first MOSFET .
The surface of the semiconductor layer, through the mask having an opening corresponding to both of the offset drain region and the body region, doped with the first condition, a dopant in the shallow portion of the body region and the offset drain region first 1 doping process;
A second doping step of doping the surface of the semiconductor layer through the mask under a second condition and introducing a dopant into a deep portion of the body region and the offset drain region ;
A part of the surface of the semiconductor layer forming the offset drain region comprises forming a field oxide film, a
The implantation energy of the first condition is lower than the implantation energy of the second condition,
The peak concentration of the dopant introduced under the first condition is a manufacturing method thinner than the peak concentration of the dopant introduced under the second condition . The process according to claim 1, the dopant to be introduced in the dopant and the second doping step of introducing in the first doping process is characterized in that the same type.

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