JP4810387B2 - Circuit operation analysis apparatus, circuit operation analysis method, and program - Google Patents

Description

  The present invention relates to a circuit operation analysis technique for an electronic circuit, and more particularly, to a circuit operation analysis technique that can analyze a DC operation point of a circuit to be analyzed reliably and in a short time with a few computer hardware resources.

  Due to advances in semiconductor technology, the dependence on computers is increasing in the design of semiconductor integrated circuits. Along with this, various circuit simulators for analyzing a design circuit have been developed.

  When performing a circuit simulation by a computer, first, a direct current analysis for obtaining a direct current operating point (DC point) of the circuit is performed. In circuit simulation, the DC operating point is extremely basic and important because it is the starting point for performing AC analysis and transient analysis.

  Currently, in many circuit simulators, the Newton-Raphson (NR) iterative algorithm is used for DC analysis. However, it is well known that the NR method cannot converge to one solution unless the initial values of the voltage and current at each node in the analysis target circuit are sufficiently close to the final solution. (See Non-Patent Document 1).

  In order to overcome this non-convergence problem, various methods are currently proposed. In the homotopy method, global convergence is strictly guaranteed in principle, and many studies have been made (for example, see Non-Patent Documents 2 and 3). However, when mounted on an actual circuit simulator, there are problems such as that the mounting method is not easy, the calculation time is long, and the required computer hardware resources are large. Absent.

Meanwhile, in the commercial EDA software, G _min stepping (G _min stepping), the source stepping (source stepping), as in such pseudo transient analysis (pseudo-transient analysis (PTA) ), a number of other practical methods Has been developed. These practical methods are basically based on continuous NR methods.

  Among these, the pseudo-transient analysis method (PTA method) is summarized as follows. First, when executing the algorithm, first, a specific pseudo-element is inserted into the original circuit to be analyzed to create a new pseudo-circuit. Then, a transient analysis is performed on the new pseudo circuit with a designated initial value. When the pseudo circuit finally reaches a steady state through the transient analysis, the steady state solution is regarded as a DC solution of the original circuit.

  The outline of the PTA method will be briefly described below.

  In DC analysis, first, all the energy-storage elements are removed by opening each capacitor in the original circuit and shorting each inductor. In this way, capacitors and inductors are eliminated from the original circuit. As described above, the circuit equation is described by the modified nodal analysis method (see Non-Patent Document 4) with respect to the analysis target circuit in which only the resistance portion is left as follows.

Here, f _G is a nodal equation. The nodal equation is a circuit equation derived by selecting the nodal potential of each node in the circuit as a variable and applying Kirchhoff's current law so that the sum of the currents flowing out from each node is zero. f _E is an equation relating to a branch characteristic of a voltage defining branch (generally a non-linear voltage source) such as an independent voltage source.

  In the PTA method, correction is made by inserting a pseudo element into the original analysis target circuit.

Various pseudo elements have been considered so far. For example, in the PTA algorithm introduced into the ASTAP simulator by W. Weeks et al., The pseudo capacitor C and the pseudo inductor L shown in FIGS. 1A and 1B are used as the pseudo elements (Non-Patent Document 5). reference). The pseudo inductor L is inserted in series with the voltage source in the circuit, and the pseudo capacitor C is inserted in parallel with the current source in the circuit. For example, for a bipolar transistor, a pseudo capacitor C is inserted as shown in FIG. The value of each pseudo element is kept constant (see Non-Patent Document 6). Further, for example, in the PTA algorithm proposed by R. Wilton and L. Goldgeisser et al., A time-varying pseudo capacitor C _V shown in FIG. 2A is used as a pseudo element (Non-patent Document 7). , 8). The time-varying pseudo-capacitor C _V decreases during the transient analysis as shown in FIG. 2B, and finally becomes 0 at t = ∞. Further, as shown in FIG. 2C, the time-varying pseudo capacitor C _V is inserted between each node of the original analysis target circuit and the ground.

  Whatever the pseudo-element, the general mathematical expression of the changed analysis target circuit is as follows.

  Where x is an unknown variable vector,

はxの時間tによる導関数、t₀は過渡解析の出発時刻、x₀は時刻t=t₀のときのxの初期値、t_SETTLEは、擬似回路が定常状態となるときの時刻を表す。

Is the derivative of x by time t, t ₀ is the departure time of the transient analysis, x ₀ is the initial value of x when time t = t ₀ , and t _SETTLE is the time when the pseudo circuit is in a steady state .

When you start a PTA simulation from the time t = t _0, to start the transient analysis of the initial value as x = x _0. And through the transient analysis, finally at time t = t _SETTLE

となって定常化することができる限り、そのときの式（２ａ）の解は、オリジナルの解析対象回路の直流解、即ち、式（１）の解とみなされる。一般に、PTA法は安定した動作点に収束する。即ち、回路に複数の動作点がある場合、安定した動作点に収束する。従って、回路に動作点が複数ある場合であっても、PTA法を用いることによって、安定した動作点を１つ見つけることができる。

Thus, the solution of equation (2a) at that time is regarded as the direct current solution of the original circuit to be analyzed, that is, the solution of equation (1). In general, the PTA method converges to a stable operating point. That is, when a circuit has a plurality of operating points, it converges to a stable operating point. Therefore, even when the circuit has a plurality of operating points, one stable operating point can be found by using the PTA method.

  To summarize the above, in the PTA method, a pseudo element and a time t that is a continuous variable parameter are introduced into the original analysis target circuit, and the equation (2a) is configured. Then, transient analysis is performed by giving an equation (2b) as an initial condition. The stop condition for the transient analysis is expressed by equation (2c). Thereby, the solution x for the circuit equation (1) of the original analysis target circuit is expressed as follows.

  By the way, in the PTA method, generally, the pseudo element is configured by a capacitor or an inductor (see FIGS. 1 and 2). Therefore, by inserting a pseudo element, the pseudo circuit can oscillate during transient analysis. This may cause the PTA method to become non-convergent. In order to succeed in DC analysis by the PTA method, it is necessary to solve this non-convergence problem.

  In order to solve the non-convergence problem of the PTA method, the present inventors have devised a composite pseudo branch including a time-varying resistance or a time-varying conductance as a pseudo element used in the PTA method (see Patent Document 1).

FIG. 3 shows a compound pseudo-element used in the PTA method. FIG. 3A shows a composite pseudo branch in which a capacitor C ₀ and a time-varying resistor R _v are connected in series, and this is called an RVC branch (branch RVC). FIG. 3B shows a composite pseudo branch in which an inductor L ₀ and a time-varying conductor G _V are connected in parallel, and this is called a GVL branch (branch GVL). The values of R _v and G _v are set in advance so as to increase according to a predetermined curve with time, as shown in FIG.

  FIG. 4 is a diagram showing the insertion position of the composite pseudo branch used in the PTA method of Patent Document 1. A GVL branch is added in series to each nonlinear voltage source and independent voltage source. The RVC branch is added in parallel to each nonlinear current source and each independent current source.

In this way, by using a composite pseudo branch including a time-varying pseudo-resistance or a time-varying pseudo-conductor, it is possible to suppress oscillation due to capacitors and inductors included in the pseudo element and to speed up the convergence time of transient analysis ( Patent Document 1).
Japanese Patent Application No. 2006-83860 Ron M. Kielkowski, "Inside SPICE (Second Edition)", McGraw-Hill, 1998. CB Garcia and WI Zangwill, "Pathways to Solutions, Fixed Points, and Equilibria", Prentice-Hall, 1981. Y. Inoue, S. Kusanobu, K. Yamamura, and M. Ando, "An initial solution algorithm for globally convergent homotopy methods," IEICE Trans. Fundamentals, vol.E87-A, no.4, pp.780-786, April 2004. Akio Ushida, Mamoru Tanaka, “Electronic Circuit Simulation”, Corona Co., Ltd., June 2002, pp.37-47, 148-158. LW Nagel, "Spice2: A computer program to simulate semiconductor circuits," Univ. Of California, Berkeley, CA, ERL-M520, May 1975. W. Weeks, A. Jimenez, G. Mahoney, D. Mehta, H. Qassemzadeh, and T. Scott, "Algorithms for ASTAP-A network-analysis program," IEEE Trans. Circuits and Systems, vol. 20, no. 6, pp.628-634, Nov. 1973. R. Wilton, "Supplementary algorithms for DC convergence," IEE Colloquium, SPICE: Surviving Problems in Circuit Evaluation, pp. 3/1 -3/19, June 1993. L. Goldgeisser, E. Christen, M. Vlach, and J. Langenwalter, "Open ended dynamic ramping simulation of multi-discipline systems," Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Sydney, Australia, vol. 5, pp.307-3 10, May 2001.

The circuit equation shown in Equation (2a) is generally a nonlinear simultaneous ordinary differential equation. Therefore, in the PTA method, the numerical integration formula is applied to the equation (2a) at each time point (generally t = t ^{(m + 1)} , n = 0, 1, 2,...) This is linearly approximated by Newton's method (see Non-Patent Document 4), resulting in simultaneous algebraic equations such as

Here, the matrix A ^(m) is a Jacobian matrix of the circuit equation F at x = x ^(m ), and the vector b ^(m) is a right-hand vector (right-hand-side at x = x ^(m)) . vector: RHS vector). Further, the vector variable x is a voltage at each node in the analysis target circuit and a current flowing through the voltage definition branch. In the present specification, the superscript enclosed in parentheses () represents the number of iteration steps.

In the Newton method, the initial estimated value of the variable x at m = 0 is set to x ⁽⁰⁾ , and the operation of finding the variable x ^{(m + 1)} by solving equation (4) is expressed as m = 0,1, Repeat until it converges as 2, ...

The Jacobian matrix A ^(m) is generally obtained by replacing each element of the original circuit to be analyzed with a Newton equivalent circuit and applying the modified nodal method to this equivalent circuit (see Non-Patent Document 4). .

  Assuming that the number of nodes in the circuit is N and the number of voltage sources is M, Equation (4) is expressed by a matrix equation such as the following equation.

Where Y ^(m) is the admittance matrix of x = x ^(m) , B ^(m) , C ^(m) and D ^(m) are the matrix representing the element characteristics, and V ^{(m + 1)} is x = x ^(m) nodal voltage vector, I ^{(m + 1)} is the current flowing in the voltage definition branch at x = x ^(m) , J ^(m) is the nodal current, E ^(m) is the voltage of the independent voltage source Represents.

  Consider a case in which the composite pseudo branch shown in FIGS. 3A and 3B is mounted on the circuit equation of the circuit to be analyzed.

First, consider a case where the RVC branch of FIG. For convenience of explanation, the reference numerals, voltages and currents of the RVC branches in FIG. 3A are set as shown in FIG. In FIG. 5A, C ₀ is a pseudo capacitor, R (t) is a time-varying pseudo resistance, i, j are nodes at both ends of the RVC branch, and k is a node between C ₀ and R (t). is there.

The current flowing through the pseudo capacitor C ₀ is I _C (t), the voltage across the pseudo capacitor is V _C (t), the current flowing through the time varying pseudo resistance R (t) is I _R (t), and the time varying pseudo resistance R ( Let the voltage across t) be V _R (t). At this time, there is the following relationship between these variables.

Here, V _i (t), V _j (t), and V _k (t) are voltages at nodes i, j, and k, respectively. From the equation (8a), the time-varying pseudo resistance R (t) can be equivalently regarded as a current-controlled voltage source (CCVS). In addition, when implemented in the circuit equation, the derivative of the equation (7a) is generally expressed by the following Euler Method (BE method) at the n + 1th time point t = t _{n + 1} as follows: Approximate as follows.

ここで，h_n+1は時間刻み幅，V_Cn+1はt=t_n+1におけるV_Cの値を表す。なお、t=t_n+1の時間点においてニュートン反復（m=0,1,2,...）が行われるので、それを考慮すると、このV_C,n+1はm+1における値は、正確にはV_C,n+1 ^(m+1)と記述される。しかし、本明細書においては煩雑を防ぐために、これを単にV_C,n+1と表記する。

Here, h _{n + 1} represents the time step size, and V _{Cn + 1} represents the value of V _C at t = t _{n + 1} . Since Newton iteration (m = 0,1,2, ...) is performed at time point t = t _{n + 1} , considering this, V _{C, n + 1} is the value at m + 1. Is accurately described as V _{C, n + 1} ^{(m + 1)} . However, in this specification, in order to prevent complication, this is simply expressed as V _{C, n + 1} .

  Substituting equation (9) into equation (7a) yields the following equation:

From this, it can be seen that the pseudo capacitor C ₀ can be replaced by the equivalent pseudo conductor G _eq and the equivalent pseudo current source J _eq as shown in FIG. On the other hand, the voltage across the time-varying pseudo-resistance R (t) is expressed by the following equation.

  From equations (10a), (11), (7b), and (8b), the matrix components and vector components that are added to the circuit equations related to the RVC branch modeled by this equivalent circuit are as follows.

Comparing equation (12) with the original circuit equation, a variable V _{k, n + 1} and a variable I _{R, n + 1} are newly added. Therefore, by implementing this modeled RVC branch, the Jacobian matrix of the circuit equation is increased by adding 2 rows and 2 columns.

  By the way, the equation (8a) can be rewritten as the following equation.

  Equation (13) means that the time-varying pseudo-resistance R (t) can also be regarded as a voltage-controlled current source (VCCS). Therefore, the RVC branch is modeled with reference to FIG. When BE method is applied to this model, it can be approximated as follows.

  Therefore, the matrix components and vector components added to the circuit equation relating to the RVC branch modeled by this equivalent circuit are as follows.

When the equation (15) is compared with the original circuit equation, one variable V _{k, n + 1} is added. Therefore, the increase in the size of the Jacobian matrix by implementing this modeled RVC branch can be suppressed to 1 row and 1 column.

Next, consider a case where the GVL branch of FIG. Also here, for convenience of explanation, the symbols, voltages and currents of the respective parts of the GVL branch in FIG. 3B are set as shown in FIG. FIG. 6A also shows a voltage source E connected in series to the GVL branch. In FIG. 6A, L ₀ is a pseudo inductor, G (t) is a time-varying pseudo conductor, and i and j are series connection circuits of a GVL branch and a voltage source E (hereinafter referred to as “GVL branch voltage source”). The nodes at both ends, k, is the node between the GVL branch and the voltage source E.

The current flowing through the pseudo inductor L ₀ is I _L (t), the voltage across the pseudo inductor L ₀ is V _L (t), the current flowing through the time-varying pseudo conductor G (t) is I _G (t), and the voltage source E The voltage between both ends is set to V _E (t) = E. At this time, there is the following relationship between these variables.

Here, V _i (t), V _j (t), and V _k (t) are voltages at nodes i, j, and k, respectively. In this case, from the equation (16a), the time-varying pseudoconductor G (t) can be regarded as a voltage-controlled current source. Similarly to the case of the RVC branch, the expression (16b) can be approximated as the following expression by applying the BE method at t = t _{n + 1} .

Here, h _{n + 1} = t _{n + 1} -t _n . Further, the equivalent pseudo resistance R _eq and the equivalent pseudo voltage source E _eq are defined by the following equations.

  From the equation (17a), the GVL-branched voltage source in FIG. 6 (a) can be replaced with the equivalent circuit in FIG. 6 (b). Further, from the equations (16a), (16b), (16c), and (16d), the matrix component and the vector component added to the circuit equation regarding the GVL-branched voltage source modeled by the equivalent circuit of FIG. become that way.

Comparing equation (19) with the original circuit equation, a variable V _{k, n + 1} and a variable I _{L, n + 1} are newly added. Therefore, by implementing the GVL branch modeled in FIG. 6B, the Jacobian matrix of the circuit equation is increased by adding 2 rows and 2 columns.

Also in this case, assuming that (17b) is V _L (t) = G (t) ⁻¹ I _G (t) and the time-varying pseudo-conductor G (t) is regarded as a current control voltage source, the Jacobian matrix The size increment can be reduced to 1 row and 1 column.

  When analyzing a small circuit, this increase in the size of the Jacobian matrix is not a problem. However, when the analysis target circuit is large, a large number of composite pseudo branches are inserted into the original analysis target circuit. Accordingly, when the Jacobian matrix of the circuit equation is increased by one row and one column per one complex pseudo branch, the size of the modified Jacobian matrix becomes very large. Therefore, in the calculation of the circuit equation, a large memory capacity is required and the calculation time becomes long.

  Therefore, an object of the present invention is to prevent the size of the Jacobian matrix of the circuit equation from changing due to the insertion of the composite pseudo branch when the composite pseudo branch is implemented for the circuit equation of the circuit to be analyzed, and to reduce the computer hardware An object of the present invention is to provide a circuit operation analysis technique capable of analyzing a DC operating point of a circuit to be analyzed reliably and in a short time with resources.

[1] Principle of the Invention As described above, when an RVC branch or a GVL branch is simply inserted in parallel with a current source or in series with a voltage source, one new node associated with the insertion of a composite pseudo branch is added. The addition of this node increases the variable and increases the size of the Jacobian matrix.

  Therefore, in the present invention, first, it is considered that the RVC branch and the GVL branch voltage source are regarded as an integrated composite pseudo branch from the beginning and are modeled so as not to generate an extra node.

[1-1] Implementation of RVC branch First, consider the case of mounting an RVC branch. The current flowing through the RVC branch (hereinafter referred to as “RVC branch current”) is I _CB , and the voltage at both ends (hereinafter referred to as “RVC branch voltage”) is V _CB . Put it in. At this time, the RVC branch current I _CB and the RVC branch voltage V _CB are expressed by the following equations.

Accordingly, the RVC branch current I _CB flowing through this RVC branch is expressed by the following equation.

  When the BE method is applied to Equation (21) and the difference is approximated, Equation (21) becomes as follows.

This, solving for RVC branch current I _CB, RVC branch current I _CB is expressed by the following equation.

Here, G _eq and G _CDeq are equivalent conductances, J _eq and J _CBeq are equivalent current sources, and are expressed by the following equations.

  From equation (23), it can be seen that the RVC branch can be modeled by the equivalent circuit of FIG. From equation (37), the matrix component and vector component added to the circuit equation for the RVC branch modeled by the equivalent circuit of FIG.

  Comparing equation (40) with the Jacobian matrix of the original circuit equation, it can be seen that there is no variable newly introduced with the addition of the RV branch, and the size of the Jacobian matrix of the circuit equation does not change.

[1-2] Implementation of GVL branch
Assuming that the current flowing through the GVL branching voltage source is I _CB and the voltage at both ends is V _CB , the current and voltage of each part are set as shown in FIG. At this time, the GVL branch current I _CB and the GVL branch voltage V _CB are each expressed by the following equations.

Here, the voltage V _L across the inductance L ₀ and the current I _G flowing through the conductance G (t) are expressed by the following equations.

  Therefore, when the equations (27a) and (27b) are substituted into the equation (26a), the following equation is obtained.

  When the BE method is applied to the equation (28) and the difference approximation is performed, an equation such as the following equation is obtained.

Solving this equation for V _{CB, n + 1} , the GVL branch voltage can be expressed as:

Here, R _eq and R _CBeq are equivalent resistances, and E _eq and E _CBeq are equivalent voltage sources, which are expressed as follows.

  From equation (30), the GVL branch can be modeled by the equivalent circuit of FIG. Matrix components and vector components added to the circuit equation for the GVL branch modeled by the equivalent circuit of FIG. 8B are as follows.

  From the above results, the RVC branch is modeled by the equivalent circuit of FIG. 7B, and the GVL branch voltage source is modeled by the equivalent circuit of FIG. It can be seen that the increase in the size of the Jacobian matrix of the circuit equation accompanying the addition of can be eliminated.

[2] Configuration and Operation of the Present Invention A first configuration of the circuit operation analysis apparatus according to the present invention is a circuit analysis apparatus that calculates a DC operating point of a circuit to be analyzed by a pseudo transient analysis method,
Circuit storage means for storing circuit configuration data representing the analysis target circuit;
Initial value setting means for setting an initial estimated value of a node voltage and a current of a voltage definition branch for each node of the analysis target circuit;
Newton equivalent circuit generation means for generating circuit configuration data of Newton's equivalent circuit for DC analysis of the analysis target circuit based on each node voltage, current of each voltage definition branch, and the circuit configuration data;
For each current source in the circuit to be analyzed, an RVC branch circuit in which a pseudo capacitor and a time-varying pseudo resistance whose resistance value increases with time is connected in series is converted into an equivalent circuit in which a conductor and a current source are connected in parallel. Equivalent RVC circuit generation means for calculating parameter values of the conductor and the current source of the RVC branch circuit;
RVC branch adding means for replacing each current source in the Newton equivalent circuit with the corresponding equivalent RVC branch circuit;
For each voltage source in the circuit to be analyzed, a pseudo-inductor and a GVL branch circuit in which a time-varying pseudo-conductor whose conductance value increases with time are connected in parallel and a circuit in which the voltage source is connected in series (hereinafter referred to as “GVL branching”). Equivalent GVL circuit generation means for calculating parameter values of the resistor and voltage source of an equivalent GVL branch circuit obtained by converting a resistor and voltage source into an equivalent circuit in which a resistor and a voltage source are connected in series.
GVL branch addition means for replacing each voltage source in the Newton equivalent circuit with the corresponding equivalent GVL branch circuit;
The circuit equation of the Newton equivalent circuit modified by the RVC branch adding means and the GVL branch adding means is calculated, and the node voltages and the currents of the voltage defining branches of the analysis target circuit in the next calculation step are calculated. Nodal parameter calculation means ;
Convergence determining means for determining whether or not the current of each node voltage and each voltage definition branch has converged, and when it converges,
It is provided with.

  According to this configuration, first, after the initial value setting means sets the initial value of the current of each node voltage / voltage definition branch, the pseudo-transient analysis is executed by repeatedly performing the following processing. .

First, a Newton equivalent circuit is generated by the Newton equivalent circuit generation means. Next, the equivalent RVC circuit generation means calculates the conductor and current source parameter values of the equivalent RVC branch circuit, and the RVC branch addition means incorporates it into the Newton equivalent circuit. The equivalent GVL circuit generation means calculates the conductor and current source parameter values of the equivalent GVL branch circuit, and the GVL branch addition means incorporates it into the Newton equivalent circuit. Next, the node parameter calculation means calculates the circuit equation of the Newton equivalent circuit corrected by the RVC branch addition means and the GVL branch addition means, and calculates the node voltages and the currents of the voltage definition branches in the next calculation step. To do. Finally, the convergence determination unit performs convergence determination. If the convergence has not been achieved, the iterative process is continued, and if it has converged, the iterative process is terminated.

  Here, the “equivalent RVC branch circuit” means a circuit obtained by converting the RVC branch circuit into an equivalent circuit in which a conductor and a current source are connected in parallel, and is specifically represented by FIG. Circuit. The “equivalent GVL branch circuit” refers to a circuit obtained by converting a GVL-branched voltage source into an equivalent circuit in which a resistor and a voltage source are connected in series, and is specifically shown in FIG. Circuit.

The equivalent RVC branch circuit generated by the equivalent RVC circuit generating means is equivalent to an RVC branch circuit in which a time-varying pseudo-resistance and a pseudo-capacitor are connected in series. Oscillation due to is prevented. Also, as described above, converting the RVC branch circuit to the equivalent RVC branch circuit does not increase the size of the Jacobian matrix of the circuit equation of the Newton equivalent circuit.

Similarly, an equivalent GVL branch circuit generated by the equivalent GVL circuit generation means includes a circuit (GVL branch voltage source) in which a GVL branch circuit in which a time-varying pseudo conductor and a pseudo inductor are connected in parallel and a DC power source are connected. Since the time-varying pseudo-conductor increases with time, oscillation by this equivalent GVL branch is prevented. Further, as described above, the size of the Jacobian matrix of the circuit equation of the Newton equivalent circuit is not increased by converting the GVL branching voltage source into the equivalent GVL branch circuit.

Therefore, the node parameter calculation means can calculate each node voltage and the current flowing through each voltage definition branch in the next calculation step in a short time with a small number of computer hardware resources.

  The “analysis target circuit” refers to a circuit that is a target of DC analysis. “Pseudo-transient analysis (PTA method)” is one of the techniques to analyze the DC operating point of a circuit. A pseudo-element is inserted between predetermined nodes of the original analysis target circuit. A transient analysis is performed, and when a steady state is reached through the transient analysis, the solution at that time is used as the DC solution of the original analysis target circuit. “DC operating-point” refers to the operating point of each element in the circuit against a DC bias. “Circuit configuration data” refers to data of parameter values such as voltage, current, resistance, capacitor, inductor, etc., of the connection relation of each element of the circuit, and is expressed in a data format such as a net list. “Nodal voltage” refers to the voltage of a node in a circuit relative to a predetermined reference node (eg, ground). The “initial value of the node voltage and the current of the voltage definition branch” can be appropriately set according to the analysis target circuit.

  “Newton's equivalent circuit” refers to an equivalent circuit obtained by performing linear approximation at each step by Newton's method for basic nonlinear elements in the circuit (see Non-Patent Document 4). "Newton's equivalent circuit configuration data for DC analysis of the analysis target circuit" means that each nonlinear element is replaced with a Newton equivalent circuit for the analysis target circuit and the capacitor in the circuit is opened. The circuit configuration data of the circuit corrected for DC analysis with the inductor shorted.

  “Pseudo-capacitor” is a capacitor that is artificially inserted for transient analysis in the pseudo-transient analysis method, and “time-varying pseudo-resistance” is pseudo-inserted for transient analysis in the pseudo-transient analysis method. A resistor whose resistance value changes with time, an inductor that is artificially inserted for transient analysis in the “pseudo-inductor” pseudo-transient analysis method, and a “time-varying pseudo-conductor” is a pseudo-transient analysis method The conductor inserted in a pseudo manner for transient analysis in FIG. 2 and whose conductance changes with time.

  The “circuit equation” refers to a simultaneous equation representing circuit characteristics obtained by applying Kirchhoff's current law or voltage law to each node of the circuit.

According to a second configuration of the circuit operation analysis apparatus of the present invention, in the first configuration, the circuit equation of the equivalent circuit of the Newton is calculated by the modified nodal method based on the circuit configuration data generated by the Newton equivalent circuit generation means. Circuit equation generation means for calculating the value of each element of the Jacobian matrix and the right-hand side vector of
The equivalent RVC circuit generation means applies a backward Euler method to the RVC branch circuit to calculate a parameter value of a conductor and a current source of the equivalent RVC branch circuit,
The RVC branch adding means replaces each element of the Jacobian matrix and the right-hand vector corresponding to a node of each current source based on a conductor value of the equivalent RVC branch circuit corresponding to the current source and a parameter value of the current source. Is what
The equivalent GVL circuit generating means applies a backward Euler method to the GVL branch voltage source, calculates a resistance value of the equivalent GVL branch circuit and a parameter value of the voltage source,
The GVL branch adding means replaces each element of the Jacobian matrix and the right-hand vector corresponding to the node of each voltage source based on a resistance of the equivalent GVL branch circuit corresponding to the voltage source and a parameter value of the voltage source. Is what
The transient analysis execution means performs a transient analysis calculation based on the Jacobian matrix and the right-hand side vector of the circuit equation modified by the RVC branch addition means and the GVL branch addition means, thereby determining the DC operating point of the analysis target circuit. It is characterized by calculating.

According to a third configuration of the circuit operation analysis apparatus according to the present invention, in the first configuration, the equivalent RVC circuit generation unit applies a backward Euler method to the RVC branch circuit, thereby providing a conductor of the equivalent RVC branch circuit. And the parameter value of the current source
The RVC branch adding means replaces each current source in the Newton equivalent circuit with the equivalent RVC branch circuit based on the circuit configuration data generated by the Newton equivalent circuit generation means,
The equivalent GVL circuit generating means applies a backward Euler method to the GVL branch voltage source, calculates a resistance value of the equivalent GVL branch circuit and a parameter value of the voltage source,
The GVL branch addition means replaces each voltage source in the Newton equivalent circuit with the equivalent GVL branch circuit based on the circuit configuration data generated by the Newton equivalent circuit generation means,
Based on the circuit configuration data of the Newton equivalent circuit modified by the RVC branch addition means and the GVL branch addition means, the value of each element of the Jacobian matrix and the right-hand side vector of the circuit equation of the Newton equivalent circuit by the modified nodal method Circuit equation generation means for calculating
The transient analysis execution means calculates a DC operating point of the analysis target circuit by performing a transient analysis calculation based on a Jacobian matrix and a right side vector of the circuit equation calculated by the circuit equation generation means. To do.

The first configuration of the circuit operation analysis method according to the present invention includes circuit storage means, initial value setting means, Newton equivalent circuit generation means, equivalent RVC circuit generation means, RVC branch addition means, equivalent GVL circuit generation means, and GVL branch addition. A circuit analysis method for calculating a DC operating point of a circuit to be analyzed by a pseudo transient analysis method using a computer comprising means, a nodal parameter calculation means, and a convergence determination means ,
a. An initial value setting step in which the initial value setting means sets an initial value of a node voltage and a current of a voltage definition branch for each node of the analysis target circuit stored in the circuit storage means ;
b. The Newton equivalent circuit generation means, the equivalent RVC circuit generation means, the RVC branch addition means, the equivalent GVL circuit generation means, the GVL branch addition means, the node parameter calculation means, and the convergence determination means cooperate, Generate circuit configuration data of Newton's equivalent circuit for DC analysis of the circuit to be analyzed from circuit configuration data representing the circuit to be analyzed ,
For each current source in the Newton equivalent circuit, an RVC branch circuit in which a pseudo capacitor and a time-varying pseudo resistance whose resistance value increases with time is connected in series is added in parallel, and each voltage in the Newton equivalent circuit is added. By adding in series a GVL branch circuit connected in parallel with a pseudo-inductor and a time-varying pseudo-conductor whose conductance value increases with time , a modified Newton equivalent circuit is generated.
By performing the transient analysis calculated for an equivalent circuit of the modified Newton, we have a, and transient analysis step of calculating the dc operating point of the analysis target circuit,
In the transient analysis step,
(1) The Newton equivalent circuit generation means is configured to determine the circuit of the analysis target circuit based on the circuit configuration data of the analysis target circuit, the node voltage set for each node in the analysis target circuit, and the current of the voltage definition branch. Newton's equivalent circuit generation step for generating circuit configuration data of Newton's equivalent circuit;
(2) The conductor of the equivalent RVC branch circuit in which the equivalent RVC circuit generation means converts the RVC branch circuit into an equivalent circuit in which a conductor and a current source are connected in parallel for each current source in the analysis target circuit. And an equivalent RVC branch generation step for calculating a parameter value of the current source,
(3) the RVC branch additional means, each current source in the equivalent circuit of the Newton, and RVC branch additional step of replacing at the equivalent RVC branch circuit corresponding thereto,
(4) The equivalent GVL circuit generation means , for each voltage source in the circuit to be analyzed, a circuit in which the GVL branch circuit and the voltage source are connected in series (hereinafter referred to as “GVL branch voltage source”). An equivalent GVL branch generation step of calculating a parameter value of the resistance and voltage source of the equivalent GVL branch circuit converted into an equivalent circuit in which a resistor and a voltage source are connected in series;
(5) the GVL branch additional means, each voltage source in the equivalent circuit of the Newton, and GVL branch additional step of replacing at the equivalent GVL branch circuit corresponding thereto,
(6) The node parameter calculation means calculates the node voltage of each node and the current of the voltage definition branch in the next calculation step based on the Newton equivalent circuit modified by the RVC branch addition step and the GVL branch addition step. A nodal value calculating step,
(7) A convergence determination step for determining whether or not the convergence determination means has converged each of the node voltages and the current of each voltage definition branch;
The convergence determination unit repeatedly executes the series of processes until it is determined that the node voltage of each node and the current value of the voltage definition branch have converged.

According to a second configuration of the circuit operation analysis method of the present invention, in the first configuration, the computer further includes circuit equation generation means, and the circuit equation generation means includes the Newton equivalent circuit generation step. A circuit equation generation step for calculating the value of each element of the Jacobian matrix and the right-hand side vector of the circuit equation of the Newton equivalent circuit based on the circuit configuration data generated in
In the equivalent RVC branch generation step, the equivalent RVC circuit generation means applies a backward Euler method to the RVC branch circuit to calculate parameter values of the conductor and current source of the equivalent RVC branch circuit,
In the RVC branch adding step, the RVC branch adding means converts each element of the Jacobian matrix and the right-hand vector corresponding to the node of each current source into the conductor and current of the equivalent RVC branch circuit corresponding to the current source. Replace based on source parameter values,
In the equivalent GVL branch generation step, the equivalent GVL circuit generation means applies a backward Euler method to the GVL branch voltage source to calculate the resistance of the equivalent GVL branch circuit and the parameter value of the voltage source,
In the GVL branch adding step, the GVL branch adding means converts each element of the Jacobian matrix and the right-hand vector corresponding to the node of each voltage source into the resistance and voltage of the equivalent GVL branch circuit corresponding to the voltage source. Replace based on source parameter values,
In the nodal value calculating step, the nodal parameter calculating means is based on the Jacobian matrix and the right side vector of the circuit equation modified in the RVC branch adding step and the GVL branch adding step, and the node of each node in the next calculating step The voltage and the current of the voltage definition branch are calculated.

According to a third configuration of the circuit operation analysis method of the present invention, in the first configuration, the computer further includes circuit equation generation means. In the equivalent RVC branch generation step, the equivalent RVC circuit generation is performed. Means applies a backward Euler method to the RVC branch circuit to calculate parameter values of the conductor and current source of the equivalent RVC branch circuit;
In the RVC branch addition step, the RVC branch addition means replaces each current source in the Newton equivalent circuit with the equivalent RVC branch circuit based on the circuit configuration data generated in the Newton equivalent circuit generation step. And
In the equivalent GVL branch generation step, the equivalent GVL circuit generation means applies a backward Euler method to the GVL branch voltage source to calculate the resistance of the equivalent GVL branch circuit and the parameter value of the voltage source,
In the GVL branch addition step, the GVL branch addition means replaces each voltage source in the Newton equivalent circuit with the equivalent GVL branch circuit based on the circuit configuration data generated in the Newton equivalent circuit generation step. And
Based on the circuit configuration data of the Newton equivalent circuit modified in the RVC branch addition step and the GVL branch addition step, the circuit equation generation means constructs a circuit equation of the Newton equivalent circuit by a modified nodal method. A circuit equation generation step for calculating values of each element of the matrix and the right-hand side vector;
In the node value calculation step, the node parameter calculation means calculates the node voltage and voltage definition branch of each node in the next calculation step based on the Jacobian matrix and the right side vector of the circuit equation calculated in the circuit equation generation step. The current is calculated.

  The program according to the present invention, when executed by a computer, causes the computer to function as the circuit operation analysis device having any one of the first to third configurations.

As described above, according to the present invention, for the pseudo element used in the transient analysis, the RVC branch circuit in which the time-varying pseudo resistance and the pseudo capacitor whose resistance value increases with time is connected in series, and the conductance value with time. Using a GVL branch circuit in which time-varying pseudoconductors and pseudoinductors with increasing connections are connected, an RVC branch circuit is inserted in parallel with each current source in the circuit to be analyzed, and a GVL branch circuit is connected in series with each voltage source Insert. As a result, the RVC branch circuit closes to the open state and the GVL branch circuit approaches the short circuit state with time, and the influence of the pseudo capacitor and the pseudo inductor decreases with time, thereby suppressing the oscillation in the transient analysis.
In addition, when the RVC branch circuit and the GVL branch circuit are incorporated in the circuit equation, the size of the Jacobian matrix of the circuit equation of the Newton equivalent circuit is increased by modeling with the equivalent RVC circuit generation means and the equivalent GVL branch circuit. There is no. Therefore, the calculation of the node voltages and the currents of the voltage definition branches by the node parameter calculation means can be performed in a short time with a small number of computer hardware resources.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 9 is a diagram illustrating the configuration of the circuit operation analysis apparatus 1 according to the first embodiment of the invention. The circuit operation analysis apparatus 1 includes circuit data storage means 2, time-varying resistance function storage means 3, time-varying conductance function storage means 4, circuit equation storage means 5, nodal parameter storage means 6, initial value setting means 7, Newton equivalent circuit Generation means 8, circuit equation generation means 9, insertion node extraction means 10, equivalent RVC circuit generation means 11, equivalent GVL circuit generation means 12, RVC branch addition means 13, GVL branch addition means 14, node parameter calculation means 15, convergence determination Means 16, a step counter 17, and output means 18 are provided. The circuit operation analysis apparatus 1 according to the present embodiment may be configured in hardware, but may be realized by configuring each functional part as a program module, reading the program into a computer, and executing the program. Good.

  The circuit data storage means 2 stores circuit configuration data input by the user using the circuit diagram editor 20. Here, a net list is used as the circuit configuration data.

  The time-varying resistance function storage means 3 uses the time-varying function and the derivative of the time-varying pseudo resistance R (t) in the RVC branch of FIG. 6A used when applying the pseudo-transient analysis method as a lookup table. Remember. The time-varying function of the time-varying pseudo-resistance R (t) can be anything as long as it is a monotonically increasing function in which R (∞) = ∞ at time t = ∞. Function is used.

  The time-varying conductance function storage means 4 uses the time-varying function and its derivative of the time-varying pseudoconductor G (t) in the GVL branch of FIG. 7A used when applying the pseudo-transient analysis method as a lookup table. Remember. The time-varying function of the time-varying pseudo-conductor G (t) may be any monotonically increasing function that generally satisfies G (∞) = ∞ at time t = ∞. Function is used.

  The circuit equation storage means 5 stores each coefficient value (value of each element of the Jacobian matrix and the right side vector) of the circuit equation to be analyzed.

  The node parameter storage means 6 stores the node voltage and the current value of the voltage definition branch at each node of the analysis target circuit.

  The initial value setting means 7 sets the current of the voltage definition branch at each node of the analysis target circuit and the initial value of the node voltage at each node, and stores them in the node parameter storage means 6.

  The Newton equivalent circuit generation means 8 is based on the circuit configuration data stored in the circuit data storage means 2 and the node voltages stored in the node parameter storage means 6 and the currents of the voltage definition branches. Generate data.

  The circuit equation generation means 9 generates a circuit equation in the form of equations (4) and (6) for the Newton equivalent circuit generated by the Newton equivalent circuit generation means 8 by the modified nodal method.

  The insertion node extraction means 10 extracts the node pair connected to the nonlinear current source or the independent current source as the RVC branch insertion node pair for the Newton equivalent circuit generated by the Newton equivalent circuit generation means 8, and extracts the nonlinear voltage source or the independent node. The node to which the + side of the voltage source is connected is extracted as a GVL branch insertion node.

Equivalent RVC circuit generating means 11, inserted for each RVC branch inserted node pair extracted by the node extraction means 10, the resistance value of the variable pseudo resistance when the node voltages and voltage defined branch of the current and the calculation step t _n Based on R (t _n ), the parameter values of the conductor G _CBeq and the current source J _CBeq of the equivalent RVC branch circuit are calculated according to the equations (24a) and (24b). The RVC branch adding means 13 implements an equivalent RVC branch circuit by adding the parameter values of the conductor G _CBeq and current source J _CBeq of the equivalent RVC branch circuit calculated by the equivalent RVC circuit generating means 11 to the circuit equation. .

The equivalent GVL circuit generation means 12 is connected to the GVL branch insertion node extracted by the insertion node extraction means 10, the node voltage, the current of the voltage definition branch, the voltage source to be connected, and the time-varying pseudoconductor at each calculation step t _n. Based on the conductance G (t _n ), the parameter values of the resistance R _CBeq and the voltage source E _CBeq of the equivalent GVL branch circuit are calculated according to the equations (31a) and (31b). The GVL branch adding means 14 implements the equivalent GVL branch circuit by adding the parameter values of the resistance R _CBeq and the voltage source E _CBeq of the equivalent GVL branch circuit calculated by the equivalent GVL circuit generating means 12 to the circuit equation. .

  The node parameter calculation means 15 solves the circuit equations of the formulas (4) and (6) by matrix operation such as LU decomposition method, and calculates the node voltage of each node and the current (node parameter) of the voltage definition branch.

  The convergence determination unit 16 compares the node parameter of each node calculated by the node parameter calculation unit 15 with the node parameter of each node calculated in the previous calculation step, and determines whether or not the node parameter has converged. To do.

  The step counter 17 is a counter that counts the calculation step of the transient analysis, and counts up by one each time the node parameter calculation means 15 calculates the node parameter of each node once.

  When the convergence determining unit 16 determines that the convergence has been completed, the output unit 18 outputs the node parameters of each node to an external storage device, a display, or the like.

  The operation of the circuit operation analyzing apparatus 1 according to this embodiment configured as described above will be described below.

  FIG. 10 is a flowchart illustrating a circuit operation analysis method according to the present embodiment.

  In step S1, the initial value setting means 7 first reads out the circuit configuration data stored in the circuit data storage means 2 and extracts all nodes. Then, according to a predetermined rule, initial values of node parameters (current of the voltage definition branch and node voltage) are set for each node. The node parameter for which the initial value is set is stored in the node parameter storage means 6.

  Here, for example, the initial value is set as follows. First, one reference node is selected, and the node voltage at that node is set to 0 (ground). The reference node is usually the node with the most connections. The node voltage of the node connected to the reference node via an independent voltage source sets the value of the voltage source. For other nodes, the node voltage is set to zero. However, when nodes other than the reference node are connected via an independent voltage source, the value of one of the node voltages is adjusted according to the value of the voltage source. For the node to which the independent current source is connected, the current of the voltage definition branch is set according to the value of the current source. For other nodes, the current in the voltage definition branch is set to zero.

  Next, in step S 2, the Newton equivalent circuit generation means 8 generates the circuit configuration data (net list) of the original analysis target circuit stored in the circuit data storage means 2 and the node data stored in the node parameter storage means 6. Is read. Then, the circuit configuration data of the Newton equivalent circuit of the original analysis target circuit is configured. A method for constructing a Newton equivalent circuit is known, and is described in Non-Patent Document 4, for example.

  At this time, all capacitors in the circuit are opened and all inductors are removed by short-circuiting.

  Next, in step S3, the circuit equation generation means 9 calculates a Jacobian matrix and a right-hand side vector of the circuit equations of the formulas (4) and (6) by applying the modified nodal method to the Newton equivalent circuit. . A method for calculating the Jacobian matrix and the right-hand vector is also known, and is described in Non-Patent Document 4, for example.

  Next, in step S4, the insertion node extracting means 10 inserts an RVC branch insertion node pair (a node pair to which a nonlinear current source or an independent current source is connected) and a GVL branch insertion based on the circuit configuration data of Newton's equivalent circuit. A node (a node to which the non-linear voltage source or the independent voltage source is connected to the + side) is extracted.

Next, in step S5, the equivalent RVC circuit generation means 11 _sets the parameter values of the conductor G _CBeq and the current source J _CBeq of the equivalent RVC branch circuit according to the equations (24a) and (24b) for each RVC branch insertion node pair. Is calculated. Then, the RVC branch adding unit 13 _adds the parameter values of the conductor G _CBeq and the current source J _CBeq of the equivalent RVC branch circuit calculated by the equivalent RVC circuit generating unit 11 to the circuit equation. The parameter values of the conductor G _CBeq and the current source J _CBeq are added to the circuit equation by adding the matrix on the left side of Equation (25) to the Jacobian matrix of the circuit equation and the vector on the right side of Equation (25) to the right side of the circuit equation. This is done by adding to the vector. That is, the Jacobian matrix A ^(m) and the right-hand side vector b ^(m) in Expression (4) are updated by addition as follows.

Next, in step S6, the equivalent GVL circuit generating means 12 _applies the resistance R _CBeq and voltage of the equivalent GVL branch circuit to the voltage source connected to each GVL branch insertion node according to the equations (31a) and (31b). _Calculate the parameter value of source E _CBeq . The GVL branch adding means 14 _adds the parameter values of the resistance R _CBeq and voltage source E _CBeq of this equivalent GVL branch circuit to the circuit equation. The parameter values of the resistance R _CBeq and the voltage source E _CBeq to the circuit equation are added to the element of the Jacobian matrix of the circuit equation corresponding to the element of the matrix on the left side of Equation (32), and the matrix of the left side of Equation (32). In addition to adding the elements, the element of the original voltage source E is subtracted by adding the element of the right-hand side vector of Expression (32) to the element of the right-hand side matrix of the circuit equation corresponding to the element of the right-hand side vector of Expression (32). By doing. That is, the Jacobian matrix A ^(m) and the right-side vector b ^(m) in Expression (4) are updated by the following addition / subtraction, respectively.

  Next, in step S7, the nodal parameter calculating means 15 calculates the nodal parameters by solving the circuit equations corrected in steps S5 and S6 by matrix operation such as LU decomposition method.

  Next, in step S8, the convergence determination unit 16 determines the node parameters of each node calculated by the node parameter calculation unit 15 and the node parameters of each node in the previous calculation step (nodes stored in the node parameter storage unit 6). Parameter) to determine whether the node parameter has converged. In this case, for example, the convergence determination is performed by calculating the sum of the absolute values of the differences in the values of the respective calculation steps for each node parameter and determining whether the value is equal to or less than the threshold value.

  If it is determined that it has not converged, the node parameters stored in the node parameter storage means 6 are updated with the newly calculated node parameters, and the process returns to step S2.

  If it is determined that the nodes have converged, the node parameters of each node are output to an external storage device, a display, or the like in step S9.

  As described above, according to the circuit operation analysis apparatus 1 of the present embodiment, the Jacobian matrix of the circuit equation by this addition is obtained by converting the time-varying pseudo branch into an equivalent RVC branch or an equivalent GVL branch and adding it to the circuit equation. There is no change in size. Therefore, it is possible to easily implement a time-varying pseudo-branch by an operation of only addition or replacement of matrix elements or vector elements. Further, since there is no change in the size of the Jacobian matrix, the amount of memory for storing the Jacobian matrix can be reduced, and an increase in the calculation time of the matrix calculation by the node parameter calculation means 15 can be suppressed.

  FIG. 11 is a diagram illustrating the configuration of the circuit operation analysis apparatus 1 according to the second embodiment of the present invention. In the present embodiment, the circuit operation analysis apparatus 1 basically has the same configuration as that of the first embodiment, but only the position of the circuit equation generation means 9 is different.

  That is, in the first embodiment, after the circuit equation is created from the Newton equivalent circuit, the equivalent RVC branch and the equivalent GVL branch are added. However, in this embodiment, the equivalent RVC branch is directly added to the circuit configuration data of the Newton equivalent circuit. The circuit equation is created after adding the equivalent GVL branch.

  Even with such a configuration, it is possible to eliminate the size change of the Jacobian matrix as in the first embodiment.

It is the pseudo element (a) (b) used in the PTA algorithm introduced into the ASTAP simulator, and its insertion example (c). The time-varying pseudocapacitor (a) used in the PTA algorithm proposed by R. Wilton and L. Goldgeisser et al., Its value change (b), and its insertion example (c). It is a figure which shows the time change of the composite pseudo branch used with the PTA method of patent document 1, and its parameter value. It is a figure showing the insertion position of the composite pseudo branch used by the PTA method of patent document 1. FIG. It is a figure showing an RVC branch and its equivalent circuit. It is a figure showing a GVL branch and its equivalent circuit. It is a figure showing modeling by the equivalent circuit of the RVC branch in this invention. It is a figure showing modeling by the equivalent circuit of the GVL branch in this invention. It is a figure showing the structure of the circuit operation | movement analysis apparatus which concerns on Example 1 of this invention. It is a flowchart showing the circuit operation | movement analysis method based on a present Example. It is a figure showing the structure of the circuit operation | movement analysis apparatus which concerns on Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit operation | movement analysis apparatus 2 Circuit data storage means 3 Time-varying resistance function storage means 4 Time-varying conductance function storage means 5 Circuit equation storage means 6 Node parameter storage means 7 Initial value setting means 8 Newton equivalent circuit generation means 9 Circuit equation generation means DESCRIPTION OF SYMBOLS 10 Insertion node extraction means 11 Equivalent RVC circuit generation means 12 Equivalent GVL circuit generation means 13 RVC branch addition means 14 GVL branch addition means 15 Node parameter calculation means 16 Convergence determination means 17 Step counter 18 Output means 20 Circuit diagram editor

Claims (7)

A circuit analysis device for calculating a DC operating point of a circuit to be analyzed by a pseudo transient analysis method,
Circuit storage means for storing circuit configuration data representing the analysis target circuit;
Initial value setting means for setting an initial estimated value of a node voltage and a current of a voltage definition branch for each node of the analysis target circuit;
Newton equivalent circuit generation means for generating circuit configuration data of Newton's equivalent circuit for DC analysis of the analysis target circuit based on each node voltage, current of each voltage definition branch, and the circuit configuration data;
For each current source in the circuit to be analyzed, an equivalent of an RVC branch circuit in which a pseudo capacitor and a time-varying pseudo resistance whose resistance value increases with time is connected in series is converted into an equivalent circuit in which a conductor and a current source are connected in parallel. Equivalent RVC circuit generation means for calculating parameter values of the conductor and current source of the RVC branch circuit;
RVC branch adding means for replacing each current source in the Newton equivalent circuit with the corresponding equivalent RVC branch circuit;
For each voltage source in the circuit to be analyzed, a pseudo-inductor and a GVL branch circuit in which a time-varying pseudo-conductor whose conductance value increases with time are connected in parallel and a circuit in which the voltage source is connected in series (hereinafter referred to as “GVL branching”). An equivalent GVL circuit generating means for calculating parameter values of the resistor and the voltage source of an equivalent GVL branch circuit obtained by converting a resistor and a voltage source into an equivalent circuit connected in series;
GVL branch adding means for replacing each voltage source in the Newton equivalent circuit with the corresponding equivalent GVL branch circuit;
The circuit equation of the Newton equivalent circuit modified by the RVC branch adding means and the GVL branch adding means is calculated, and the node voltages of the circuit to be analyzed and the currents of the voltage definition branches in the next calculation step are calculated. Nodal parameter calculation means ;
Convergence determining means for determining whether or not each node voltage and current of each voltage definition branch has converged,
A circuit operation analysis apparatus comprising: Based on the circuit configuration data generated by the Newton equivalent circuit generation means, circuit equation generation means for calculating the value of each element of the Jacobian matrix and the right-hand side vector of the circuit equation of the Newton equivalent circuit by a modified nodal method,
The equivalent RVC circuit generation means applies a backward Euler method to the RVC branch circuit to calculate a parameter value of a conductor and a current source of the equivalent RVC branch circuit,
The RVC branch adding means replaces each element of the Jacobian matrix and the right-hand vector corresponding to a node of each current source based on a conductor value of the equivalent RVC branch circuit corresponding to the current source and a parameter value of the current source. Is what
The equivalent GVL circuit generation means applies a backward Euler method to the GVL branch voltage source to calculate a resistance value of the equivalent GVL branch circuit and a parameter value of the voltage source,
The GVL branch adding means replaces each element of the Jacobian matrix and the right-hand vector corresponding to the node of each voltage source based on a resistance of the equivalent GVL branch circuit corresponding to the voltage source and a parameter value of the voltage source. Is what
The node parameter calculation means calculates the node voltages and currents of the voltage definition branches of the circuit to be analyzed based on the Jacobian matrix and the right-hand side vector of the circuit equation modified by the RVC branch addition means and the GVL branch addition means. The circuit operation analysis apparatus according to claim 1, wherein: The equivalent RVC circuit generation means applies a backward Euler method to the RVC branch circuit to calculate a parameter value of a conductor and a current source of the equivalent RVC branch circuit,
The RVC branch adding means replaces each current source in the Newton equivalent circuit with the equivalent RVC branch circuit based on the circuit configuration data generated by the Newton equivalent circuit generation means,
The equivalent GVL circuit generation means applies a backward Euler method to the GVL branch voltage source to calculate a resistance value of the equivalent GVL branch circuit and a parameter value of the voltage source,
The GVL branch addition means replaces each voltage source in the equivalent circuit of the Newton with the equivalent GVL branch circuit based on the circuit configuration data generated by the Newton equivalent circuit generation means.
Based on the circuit configuration data of the Newton equivalent circuit modified by the RVC branch addition means and the GVL branch addition means, the value of each element of the Jacobian matrix and the right-hand side vector of the circuit equation of the Newton equivalent circuit is obtained by the modified nodal method. Circuit equation generation means for calculating
The node parameter calculation unit calculates each node voltage and current of each voltage definition branch of the circuit to be analyzed based on a Jacobian matrix and a right side vector of the circuit equation calculated by the circuit equation generation unit. The circuit operation analysis apparatus according to claim 1. A computer comprising circuit storage means, initial value setting means, Newton equivalent circuit generation means, equivalent RVC circuit generation means, RVC branch addition means, equivalent GVL circuit generation means, GVL branch addition means, node parameter calculation means, and convergence determination means Is a circuit analysis method for calculating a DC operating point of a circuit to be analyzed by a pseudo transient analysis method,
a. An initial value setting step in which the initial value setting means sets an initial estimated value of a node voltage and a current of a voltage definition branch for each node of the analysis target circuit stored in the circuit storage means ;
b. The Newton equivalent circuit generation means, the equivalent RVC circuit generation means, the RVC branch addition means, the equivalent GVL circuit generation means, the GVL branch addition means, the node parameter calculation means, and the convergence determination means cooperate, From the circuit configuration data representing the analysis target circuit, generate circuit configuration data of Newton's equivalent circuit for DC analysis of the analysis target circuit,
For each current source in the Newton equivalent circuit, an RVC branch circuit in which a pseudo capacitor and a time-varying pseudo resistance whose resistance value increases with time is connected in series is added in parallel, and each voltage in the Newton equivalent circuit is added. By adding, in series, a pseudo-inductor and a GVL branch connected in parallel with a pseudo-inductor and a time-varying pseudo-conductor whose conductance value increases with time , a modified Newton equivalent circuit is generated,
By performing the transient analysis calculated for an equivalent circuit of the modified Newton, we have a, and transient analysis step of calculating the dc operating point of the analysis target circuit,
In the transient analysis step,
(1) The Newton equivalent circuit generation means is configured to determine the circuit of the analysis target circuit based on the circuit configuration data of the analysis target circuit, the node voltage set for each node in the analysis target circuit, and the current of the voltage definition branch. Newton's equivalent circuit generation step for generating circuit configuration data of Newton's equivalent circuit;
(2) The conductor of the equivalent RVC branch circuit in which the equivalent RVC circuit generation means converts the RVC branch circuit into an equivalent circuit in which a conductor and a current source are connected in parallel for each current source in the analysis target circuit. And an equivalent RVC branch generation step for calculating a parameter value of the current source;
(3) the RVC branch additional means, each current source in the equivalent circuit of the Newton, and RVC branch additional step of replacing at the equivalent RVC branch circuit corresponding thereto,
(4) The equivalent GVL circuit generation means , for each voltage source in the analysis target circuit, a circuit in which the GVL branch circuit and the voltage source are connected in series (hereinafter referred to as “GVL branch voltage source”). An equivalent GVL branch generation step of calculating parameter values of the resistance and voltage source of the equivalent GVL branch circuit converted into an equivalent circuit in which a resistor and a voltage source are connected in series;
(5) the GVL branch additional means, each voltage source in the equivalent circuit of the Newton, and GVL branch additional step of replacing at the equivalent GVL branch circuit corresponding thereto,
(6) The node parameter calculation means calculates the node voltage of each node and the current of the voltage definition branch in the next calculation step based on the Newton equivalent circuit corrected by the RVC branch addition step and the GVL branch addition step. A nodal value calculating step,
(7) A convergence determination step for determining whether or not the convergence determination means has converged each of the node voltages and the current of each voltage definition branch;
A series of processes, circuit operation analyzing method, wherein the convergence determination unit is repeatedly executed until determined that the value of the current of the node voltages and voltage defined branch of each node has converged consisting. The computer further includes circuit equation generation means,
Based on the circuit configuration data generated in the Newton equivalent circuit generation step, the circuit equation generation means calculates a value of each element of the Jacobian matrix and the right-hand side vector of the circuit equation of the Newton equivalent circuit based on the modified nodal method. A circuit equation generation step to
In the equivalent RVC branch generation step, the equivalent RVC circuit generation means applies a backward Euler method to the RVC branch circuit to calculate a parameter value of a conductor and a current source of the equivalent RVC branch circuit,
In the RVC branch adding step, the RVC branch adding means converts the elements of the Jacobian matrix and the right-hand vector corresponding to the nodes of each current source into the conductor and current of the equivalent RVC branch circuit corresponding to the current source. Replace based on source parameter values,
In the equivalent GVL branch generation step, the equivalent GVL circuit generation means applies a backward Euler method to the GVL branch voltage source to calculate the resistance of the equivalent GVL branch circuit and the parameter value of the voltage source,
In the GVL branch adding step, the GVL branch adding means converts the elements of the Jacobian matrix and the right-hand vector corresponding to the node of each voltage source into the resistance and voltage of the equivalent GVL branch circuit corresponding to the voltage source. Replace based on source parameter values,
In the node value calculating step, the node parameter calculating means is configured to determine the node of each node in the next calculating step based on the Jacobian matrix and the right side vector of the circuit equation modified in the RVC branch adding step and the GVL branch adding step. 5. The circuit operation analysis method according to claim 4, wherein the voltage and the current of the voltage definition branch are calculated. The computer further includes circuit equation generation means,
In the equivalent RVC branch generation step, the equivalent RVC circuit generation means applies a backward Euler method to the RVC branch circuit to calculate a parameter value of a conductor and a current source of the equivalent RVC branch circuit,
In the RVC branch addition step, the RVC branch addition means replaces each current source in the Newton equivalent circuit with the equivalent RVC branch circuit based on the circuit configuration data generated in the Newton equivalent circuit generation step. And
In the equivalent GVL branch generation step, the equivalent GVL circuit generation means applies a backward Euler method to the GVL branch voltage source to calculate the resistance of the equivalent GVL branch circuit and the parameter value of the voltage source,
In the GVL branch addition step, the GVL branch addition means replaces each voltage source in the Newton equivalent circuit with the equivalent GVL branch circuit based on the circuit configuration data generated in the Newton equivalent circuit generation step. And
Based on the circuit configuration data of the Newton equivalent circuit modified in the RVC branch addition step and the GVL branch addition step, the circuit equation generation means constructs a circuit equation of the Newton equivalent circuit by a modified nodal method. A circuit equation generation step for calculating values of each element of the matrix and the right-hand side vector;
In the node value calculation step, the node parameter calculation means calculates the node voltage and voltage definition branch of each node in the next calculation step based on the Jacobian matrix and the right side vector of the circuit equation calculated in the circuit equation generation step. 5. The circuit operation analysis method according to claim 4, wherein a current is calculated.   A program that, when executed by a computer, causes the computer to function as the circuit operation analysis device according to any one of claims 1 to 3.

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