JP4662162B2 - Circuit operation analysis apparatus and circuit operation analysis method - Google Patents

Description

  The present invention relates to a circuit operation analysis technique for an electronic circuit, and more particularly, to a circuit operation analysis technique capable of reliably and quickly analyzing a DC operating point of a circuit to be analyzed.

  Circuit simulation is obtained by calculating the behavior of an electronic circuit such as an LSI by a numerical method, and is generally classified into DC analysis, AC analysis, and transient analysis. Among these, DC analysis is a starting point for all analysis, and it is extremely important to perform this analysis reliably. This is because if the DC analysis fails, all other analysis is impossible. Many practical circuits include nonlinear elements, and their circuit equations are nonlinear equations. In direct current analysis, a method is used in which a numerical solution is applied to a nonlinear algebraic equation describing a circuit to be analyzed to find a solution of the equation. However, in general, it is a very difficult problem to reliably obtain a solution of a nonlinear equation.

  In recent years, SPICE-like circuit simulators used as one of the most common EDA tools use the Newton-Raphson (NR) method to calculate the DC operating point of a nonlinear circuit. However, it is known that the NR method converges only when a given initial value is sufficiently close to a true solution, and the solution does not converge if the initial value is set incorrectly (see Non-Patent Document 1). Therefore, there are many examples in which analysis fails in practical circuits such as LSI. In particular, when the circuit becomes large, convergence fails in most cases.

  In order to solve this non-convergence problem, many methods such as a Gmin stepping method, a source stepping method, and a pseudo transient analysis (PTA) method have been proposed (see Non-Patent Documents 2 to 4). These methods are often used in commercial SPICE type simulators.

  Among these, the PTA method is considered to be a method with good convergence compared to the Gmin stepping method and the source stepping method (see Non-Patent Document 2). The PTA method is a technique in which a pseudo-reactance is inserted into an analysis target circuit, a transient analysis is executed, and when the solution is stabilized, it is used as a DC solution of the original analysis target circuit. In the following, the conventional pseudo-transient analysis method used conventionally will be outlined.

  In the pseudo transient analysis method, a predetermined pseudo element (pseudo element) whose initial value is determined is inserted into the analysis target circuit. For example, a pseudo capacitor or a pseudo inductor is used as the pseudo element.

  Pseudo-active devices were first introduced in the DC analysis of the ASTAP simulator by W. Weeks et al. This is regarded as a modification of the source stepping algorithm (see Non-Patent Document 5). In the ASTAP algorithm, a pseudo capacitor is inserted in parallel with each nonlinear current source. A pseudo inductor is inserted in series with each nonlinear voltage source. The characteristic values (capacitance and inductance) of these pseudo elements are held at constant values (see Non-Patent Document 6).

  Thereafter, this PTA method was introduced in the SPICE simulator according to the following rules. As shown in FIG. 1A, a 1 F capacitor is added in parallel to each independent current source. Further, as shown in FIG. 1B, a 1H inductor is added in parallel to each independent voltage source. Further, as shown in FIG. 1C, a built-in capacitor of the BJT model is used as a pseudo capacitor for the nonlinear branch. The initial condition of each pseudo element is selected by creating a zero initial solution (see Non-Patent Document 5).

  Since then, this method has been developed by using time-varying pseudo capacitors (capacitors whose capacitance changes with time, the same applies hereinafter). These have been reported by R. Wilton and L. Goldgeisser et al. (See Non-Patent Documents 3 and 7).

The main feature points of the PTA algorithm in Non-Patent Document 3 are as follows.
(1) Only pseudo capacitors are used and their values change as shown in FIG. 2 (b).
(2) The pseudo capacitor is inserted between each node of the original circuit to be analyzed and the ground.
(3) When performing transient analysis, the voltage value and current value of the independent current source and the independent voltage source are set to specific values. All other nodes in the circuit are initially set to zero voltage and current values.
(4) All inductances and capacitances (including parasitic elements) in the original circuit to be analyzed are validated through the PTA.

  Further, as discussed in Non-Patent Document 7, the SABER simulator which is a part of HSPICE has also developed a pseudo element having a constant characteristic value into a time-varying pseudo element whose characteristic value changes with time. Here, the PTA algorithm is controlled by two simulation parameters dr_rise and dr_settle.

The major advantages of the PTA method are how much time step should be taken during the transient analysis, how much the solution changes during the analysis, how much the numerical truncation error should be, It is not necessary to consider so much. As long as the final circuit state in the transient analysis reaches a steady state, the DC operating point of the original circuit to be analyzed can be found.
Japanese Unexamined Patent Publication No. 63-4345 JP-A-6-231202 JP-A-7-141416 Japanese Patent Laid-Open No. 10-260999 JP-A-10-320444 Y. Inoue, Y. Imai, and K. Yamamura, "A homotopy method using a nonlinear auxiliary function for solving transistor circuits," IEICE Trans. INF. & SYST., Vol.E88-D, no.7, pp.1401 -1408, Jan. 2005. TL Quarles, "Analysis of performance and convergence issues for circuit simulation," Univ. Of California, Berkeley, CA, ERL-M89 / 42, Apr. 1989. R. Wilton, "Supplementary algorithms for DC convergence," IEE Colloquium, SPICE: Surviving Problems in Circuit Evaluation, pp. 3 / 1-3 / 19, Jun. 1993. E. Yilmaz, and MM Green, "Some standard SPICE dc algorithms revisited: why does SPICE still not converge?" Proc. IEEE Int. Symp. Circuits and Systems (ISCAS) vol.6, pp.286-289, May 1999, Orlando, Floride. LW Nagel, "Spice2: A computer program to simulate semiconductor circuits," Univ. Of California, Berkeley, CA, ERL-M520, May 1975. W. Weeks, A. Jimenez, G. Mahoney, D. Mehta, H. Qassemzadeh, and T. Scott, "Algorithms for ASTAP-A network-analysis program," IEEE Trans. Circuits and Systems, vol. 20, no. 6, pp.628-634, Nov. 1973. L. Goldgeisser, E. Christen, M. Vlach, and J. Langenwalter, "Open ended dynamic ramping simulation of multi-discipline systems," Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol.5, pp. 307-310, May 2001, Sydney, Australia. Y. Inoue, S. Kusanobu, and K. Yamamura, "A practical approach for the fixed-point homotopy method using a solution-tracing circuit," IEICE Trans. Fundamentals, vol.E88-D, no.7, pp.1401 -1408, Jun. 2005.

  However, the conventional PTA method has a problem that the circuit may oscillate due to the insertion of the pseudo element, and when the circuit oscillates, a steady solution cannot be obtained and the DC analysis fails. In addition, depending on the analysis target circuit, there is a problem that it may take a relatively long time to converge to a steady solution.

  Therefore, an object of the present invention is to provide a circuit operation analysis technique capable of preventing oscillation in transient analysis and improving calculation efficiency when performing DC operation analysis of a circuit using a pseudo transient analysis method. .

A first configuration of a circuit operation analysis apparatus according to the present invention is a circuit operation analysis apparatus that calculates a DC operating point of a circuit to be analyzed by a pseudo transient analysis method,
Circuit storage means for storing circuit configuration data of the analysis target circuit;
Pseudo element insertion means for generating correction circuit configuration data of the DC analysis circuit by inserting a time-varying pseudo element for the analysis target circuit represented by the circuit configuration data;
Transient analysis execution means for calculating a DC operating point of the analysis target circuit by performing a transient analysis calculation of the DC analysis circuit based on the corrected circuit configuration data while changing the parameter value of each time-varying pseudo-element over time When,
With
The pseudo-element inserting means includes a first time-varying pseudo-element in which a pseudo-inductor and a time-varying pseudo-conductor whose conductance changes with time are connected in parallel, or a pseudo-capacitor and a time-varying pseudo-resistance whose resistance value changes with time. A second time-varying pseudo-element connected in series in the circuit to be analyzed,
The transient analysis execution means increases the conductance of the time-varying pseudo-conductor of the first time-varying pseudo-element with time and increases the resistance value of the time-varying pseudo-resistance of the second time-varying pseudo-element with time. And performing transient analysis calculation.

  With this configuration, in the initial stage of transient analysis, the time-varying pseudoconductor connected in parallel with the pseudoinductor attenuates the oscillation of the circuit state caused by the pseudoinductor. it can. Further, at the stage where the time has advanced in the transient analysis, the conductance of the time-varying pseudo-conductor becomes infinite, and the pseudo-inductor does not affect the circuit characteristics. In addition, since the resistance value of the time-varying pseudo-resistance connected directly to the pseudo-capacitor becomes infinite, the circuit is disconnected and the pseudo-capacitor does not affect the circuit characteristics. Therefore, oscillation due to pseudo-reactance does not occur in the later stage of transient analysis. As a result, it is possible to prevent oscillation in transient analysis.

  Further, by increasing the conductance of the time-varying pseudo-conductor and the resistance value of the time-varying pseudo-resistance exponentially at an appropriate speed, circuit convergence can be accelerated and calculation efficiency can be improved.

  Here, the time-varying pseudo-resistance and the time-varying pseudo-conductor are not necessarily actual resistances or conductors, and may be circuit elements equivalent to them. For example, an equivalent control voltage source as shown in FIG. 6A may be used as the time-varying pseudo resistance, and an equivalent control current source as shown in FIG. 6B may be used as the time-varying pseudo conductor.

  Here, the insertion position of the first time-varying pseudo element or the second time-varying pseudo element is not particularly limited. For example, the first time-varying pseudo-element is inserted in series with the voltage source, the second time-varying pseudo-element is inserted in parallel with the current source, and the second time-varying pseudo-element is connected to each node in the analysis target circuit. For example, it can be inserted between the grounds.

According to a second configuration of the circuit operation analysis apparatus of the present invention, in the first configuration, the pseudo element insertion unit includes:
A voltage source in the circuit to be analyzed is extracted, and a first time-varying pseudo element in which a pseudo inductor and a time-varying pseudo conductor whose conductance changes with time is connected in parallel to each voltage source in the circuit to be analyzed. First time-varying pseudo-element inserting means for inserting in series with
A current source in the analysis target circuit is extracted, and a second time-varying pseudo-element in which a pseudo capacitor and a time-varying pseudo resistance whose resistance value changes with time is connected in series to each current source in the analysis target circuit. And a second time-varying pseudo-element inserting means for inserting in parallel.

  As a result, it is possible to alleviate the oscillation of the rise of the voltage source and current source in the transient analysis and suppress the oscillation.

  Here, the “current source” also includes a non-linear current source in a model expression representing a non-linear element (such as a bipolar transistor or a field effect transistor). That is, when the analysis target circuit includes a nonlinear element, the second time-varying pseudo element is inserted in parallel between nodes connected by the nonlinear current source in the model formula of each nonlinear element.

According to a third configuration of the circuit operation analysis apparatus of the present invention, in the second configuration, the analysis target circuit is a circuit including a bipolar transistor,
The second time-varying pseudo-element inserting means further extracts a bipolar transistor in the analysis target circuit, and the second time-variant pseudo element insertion means extracts the second transistor between the base and emitter and between the base and collector of each bipolar transistor in the analysis target circuit. The time-varying pseudo-element is inserted.

  With this configuration, oscillation in transient analysis can be effectively prevented even when the analysis target circuit includes a bipolar transistor.

According to a fourth configuration of the circuit operation analysis apparatus according to the present invention, in the second or third configuration, the circuit to be analyzed is a circuit including a field effect transistor,
The second time-varying pseudo-element inserting means further extracts a field effect transistor in the circuit to be analyzed, and the second time-variant pseudo element insertion means between the gate and source and between the gate and drain of each field effect transistor in the circuit to be analyzed. The time-varying pseudo-element is inserted.

  With this configuration, oscillation in transient analysis can be effectively prevented even when the analysis target circuit includes a field effect transistor.

  According to a fifth configuration of the circuit operation analysis apparatus of the present invention, in the first configuration, the pseudo-element insertion unit is configured such that the second time-variant is inserted between each node in the analysis target circuit and the ground. A pseudo element is inserted.

  With this configuration, it is possible to reduce the oscillation of the voltage and current rise of each node in the transient analysis and suppress the oscillation.

A first configuration of a circuit operation analysis method according to the present invention is a circuit operation analysis method for calculating a DC operating point of a circuit to be analyzed by a pseudo transient analysis method,
Correction of the DC analysis circuit by reading the circuit configuration data of the analysis target circuit stored in the circuit storage means and inserting a time-varying pseudo-element into the analysis target circuit represented by the circuit configuration data A pseudo-element insertion step for generating circuit configuration data;
A transient analysis execution step of calculating a DC operating point of the analysis target circuit by performing a transient analysis calculation of the DC analysis circuit based on the correction circuit configuration data while changing a parameter value of each time-varying pseudo-element over time When,
Have
In the pseudo-element insertion step, a first time-varying pseudo-element in which a pseudo-inductor and a time-varying pseudo-conductor whose conductance changes with time are connected in parallel, or a pseudo-capacitor and a time-varying pseudo-resistance whose resistance value changes with time And a second time-varying pseudo-element connected in series with each other in the circuit to be analyzed,
In the transient analysis execution step, the conductance of the time-varying pseudo-conductor of the first time-varying pseudo-element is increased with time, and the resistance value of the time-varying pseudo-resistance of the second time-varying pseudo-element is increased with time. However, it is characterized by performing transient analysis calculation.

In a second configuration of the circuit operation analysis method according to the present invention, in the first configuration, in the pseudo element insertion step,
A voltage source in the circuit to be analyzed is extracted, and a first time-varying pseudo element in which a pseudo inductor and a time-varying pseudo conductor whose conductance changes with time is connected in parallel to each voltage source in the circuit to be analyzed. A first time-varying pseudo-element insertion step for inserting in series with respect to,
A current source in the analysis target circuit is extracted, and a second time-varying pseudo-element in which a pseudo capacitor and a time-varying pseudo resistance whose resistance value changes with time is connected in series to each current source in the analysis target circuit. And a second time-varying pseudo-element insertion step for inserting in parallel.

According to a third configuration of the circuit operation analysis method of the present invention, in the second configuration, the analysis target circuit is a circuit including a bipolar transistor,
In the second time-varying pseudo-element insertion step, a bipolar transistor in the circuit to be analyzed is further extracted, and the second transistor between the base-emitter and the base-collector of each bipolar transistor in the circuit to be analyzed is extracted. 2 time-varying pseudo-elements are inserted.

According to a fourth configuration of the circuit operation analysis method of the present invention, in the second or third configuration, the circuit to be analyzed is a circuit including a field effect transistor,
In the second time-varying pseudo-element insertion step, a field effect transistor in the circuit to be analyzed is further extracted, and the field effect transistor in the circuit to be analyzed is connected between the gate and source and between the gate and drain. 2 time-varying pseudo-elements are inserted.

  According to a fifth configuration of the circuit operation analysis method of the present invention, in the first configuration, in the pseudo element insertion step, the sixth time is set between each node in the analysis target circuit and the ground. A variable pseudo element is inserted.

  A circuit operation analysis program according to the present invention is read and executed by a computer, thereby causing the computer to function as the circuit operation analysis apparatus having any one of the first to fifth configurations.

  As described above, according to the present invention, the time-varying pseudo-conductor and the time-varying pseudo-resistance are caused to act as a damping resistor that suppresses oscillation at the initial stage of the transient analysis, and in the later stage of the transient analysis, these conductance and resistance value are By eliminating the influence of the pseudo inductor and the pseudo capacitor as infinite, oscillation in the pseudo transient analysis can be effectively prevented. Further, by increasing the conductance of the time-varying pseudo-conductor and the resistance value of the time-varying pseudo-resistance exponentially at an appropriate speed, it is possible to accelerate circuit convergence and improve calculation efficiency. Therefore, it is possible to solve the problems of the conventional PTA method described above, and to provide a circuit operation analysis technique capable of efficiently performing DC analysis of a circuit in a short time.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

[1] Configuration and Operation FIG. 3 is a diagram illustrating the configuration of the circuit operation analysis apparatus 1 according to the first embodiment of the present invention. The circuit operation analysis device 1 performs DC analysis calculation of the analysis target circuit based on the circuit configuration data of the analysis target circuit input from the circuit data input device 2 and outputs the result to the output device 3.

  As the circuit data input device 2, a normal net list input circuit diagram editor or the like is used. The output device 3 can use a display, a hard disk, a CD-ROM, or the like.

  Each of these devices is configured using a computer, an auxiliary storage device, an external storage device, and the like in hardware. The circuit operation analysis apparatus 1 can be configured as a circuit using an FPGA or the like. However, the circuit operation analysis apparatus 1 is configured as a program module and executed by the computer so that the computer operates as the circuit operation analysis apparatus 1. You may comprise as follows.

  In FIG. 3, the circuit operation analysis apparatus 1 includes an analysis target circuit storage unit 11, a pseudo element insertion unit 12, a correction circuit storage unit 13, and a transient analysis execution unit 14.

  The analysis target circuit storage unit 11 stores circuit configuration data of the analysis target circuit. The pseudo element insertion unit 12 generates and outputs corrected circuit configuration data of the DC analysis circuit by inserting a time-varying pseudo element into the analysis target circuit represented by the circuit configuration data. The correction circuit storage unit 13 stores correction circuit configuration data of the DC analysis circuit output from the pseudo element insertion unit 12. The transient analysis execution means 14 calculates the DC operating point of the analysis target circuit by performing transient analysis calculation of the DC analysis circuit based on the corrected circuit configuration data while changing the parameter value of each time-varying pseudo-element with time. The DC operating point data obtained by the calculation is output to the output device 3.

  The operation of the circuit operation analyzing apparatus 1 according to this embodiment configured as described above will be described below.

  First, the user creates a net list of the analysis target circuit using the circuit data input device 2, and the net list is stored in the analysis target circuit storage unit 11 as circuit configuration data of the analysis target circuit.

  Next, the pseudo element insertion unit 12 reads circuit configuration data from the analysis target circuit storage unit 11. Then, a voltage source in the analysis target circuit is extracted, and a time-varying pseudo element (hereinafter referred to as “GVL branch”) as shown in FIG. 4B is inserted in series with the voltage source. FIG. 5A shows a state where the GVL branch is inserted.

The GVL branch of FIG. 4B has a configuration in which a pseudo inductor having an inductance L ₀ that does not change with time and a time-varying pseudo conductor whose conductance G _v changes with time are connected in parallel.

  Further, the pseudo element insertion unit 12 extracts a current source in the analysis target circuit, and for each current source, a time-varying pseudo element (hereinafter referred to as “RVC branch”) as shown in FIG. Insert in parallel to the source. FIG. 5B shows a state in which this RVC branch is inserted.

The RVC branch of FIG. 4 (a) has a configuration in which a pseudo capacitor having a capacitance C ₀ that does not change with time and a time-varying pseudo resistor whose resistance R _v changes with time are connected in parallel.

  Further, the pseudo element insertion means 12 extracts the bipolar transistor in the analysis target circuit, and the RVC branch of FIG. 4A between the base-emitter and the base-collector of each bipolar transistor in the analysis target circuit. Insert. FIG. 5C shows a state in which this RVC branch is inserted.

  Furthermore, the pseudo element insertion unit 12 extracts the field effect transistor in the analysis target circuit, and the RVC branch of FIG. 4A between the gate and source and between the gate and drain of each field effect transistor in the analysis target circuit. Insert. FIG. 5D shows a state in which this RVC branch is inserted.

  The pseudo element insertion unit 12 stores the circuit configuration data of the analysis target circuit into which each time-varying pseudo element is inserted in the correction circuit storage unit 13 as correction circuit configuration data.

  Next, the transient analysis execution means 14 performs a transient analysis based on the correction circuit configuration data stored in the correction circuit storage means 13.

  The initial values of the voltage value and current value of each node in the transient analysis are set in the same manner as in the conventional PTA method. In other words, the voltage value and current value of the independent current source and the independent voltage source are set to the specific values. For all other nodes, the voltage value and current value are set to zero as the initial state.

Furthermore, the conductance G _v and the resistance value R _v of varying pseudo resistance when the RVC branches of varying pseudo conductor when the GVL branch, respectively, is set to an initial value G _v0, R _v0.

Next, in the calculation of transient analysis, conductance G _v and the resistance value R _v of the time-varying pseudo-resistance of each time-varying pseudo-conductor, as shown in FIG. 4 (c), increasing exponentially with time . And finally, it is infinite at time t _settle .

  By introducing the time-varying pseudo-resistance and the time-varying pseudo-conductor, the correction circuit becomes a circuit that does not easily oscillate in the transient analysis performed by the transient analysis executing means 14.

The Q value at the angular frequency ω ₀ of the RVC branch and the GLV branch shown in FIGS. 4A and 4B is expressed as the following equation.

The Q value represents the order of oscillation of the circuit. That is, the greater the Q value, the easier it is for oscillation to occur. In this embodiment, since R _v and G _v appearing in the denominator of Q value to increase indefinitely with time, the Q value decreases with time. Therefore, oscillation can be mitigated. According to equation (1), the Q value approaches zero at t = t _settle . In this way, the oscillation can be theoretically evaluated.

From another point of view, if R _v and G _v are considered infinite, the RVC branch is considered to be removed. Also, the GLV branch is considered short-circuit removed. Therefore, the influence of the constants C ₀ and L ₀ is eliminated.

As a result of the transient analysis executing means 14 performing the transient analysis as described above, the voltage / current value of each node of the analysis target circuit reaches a steady state at t = t _settle . This value state is the DC operating point. The transient analysis execution means 14 outputs the DC operating point data to the output device 3 and ends the DC analysis processing.

[2] Experimental Examples in Some Circuits In the conventional PTA algorithm, there is a possibility of oscillation by a pseudo element when the analysis target circuit includes a specific partial circuit as shown in the following example. In this case, DC analysis fails if the conventional PTA algorithm is used. On the other hand, when the processing method of the circuit operation analysis apparatus 1 of the present embodiment is used, oscillation can be avoided and at the same time the convergence time is accelerated.

According to Non-Patent Document 8, as the models of the time-varying pseudo resistance R _v and the time-varying pseudo conductor G _v , the control voltage source ERV and the control current source GGV as shown in FIGS. 6A and 6B are used. Is often used. The current-voltage relationship of ERV and GGV is as follows.

In equation (2), V _ERV is the voltage across ERV. I (C ₀ ) is a current flowing through the capacitor C ₀ . I (GGV) is a current flowing through GGV. V (L ₀ ) is a current flowing through the inductor L ₀ . V _CTRL is a control voltage whose value changes with time, as shown in FIG. R _v0 and G _v0 are initial values of R _v and G _v .

  According to this model, the equivalent resistance and equivalent conductance of the time-varying composite pseudo element shown in FIGS. 6A and 6B have the same characteristics as the curve shown in FIG.

[Example 1] Inverter chain circuit As a test circuit, consider an inverter chain circuit composed of five CMOSs as shown in FIG.

  The inverter chain circuit is one of the typical examples that cause the oscillation problem in the pseudo transient analysis method. If the analysis target circuit includes a partial circuit of this structure, oscillation occurs in all the circuits in the pseudo transient analysis. However, this type of oscillation problem does not occur in the analysis method performed by the circuit operation analysis apparatus 1 of this embodiment.

  FIG. 8 is a diagram showing a comparison of pseudo transient analysis between the conventional methods (a), (b), and (c) and the method (d) of the present invention for the inverter chain circuit of FIG.

FIGS. 8A and 8B show the results of a transient analysis of the inverter chain circuit of FIG. 7 by the PTA algorithm using a pseudo capacitor having a constant capacitance as shown in FIG. 1 (hereinafter, this PTA). The algorithm is referred to as “algorithm A1” or “algorithm A2”). Due to advances in semiconductor technology, smaller values are used for capacitance C ₀ and inductance L ₀ .

  In the algorithm A1, the pseudo capacitor is 1F, and in the algorithm A2, the pseudo capacitor is 0.0001F.

  Two types of oscillation are seen in the curves of FIGS. One is an oscillation that attenuates in the early part of the transient analysis, and the other is a steady oscillation that appears after that. The oscillation that decays in the early part is caused by a pseudo inductor L inserted in series with the voltage source. Further, the steady oscillation that appears thereafter is due to the influence of the inserted pseudo capacitor.

  FIG. 8C shows the result of the transient analysis of the inverter chain circuit of FIG. 7 by the PTA algorithm using the time-varying pseudo-capacitor whose capacitance decays with time as shown in FIG. This PTA algorithm is referred to as “algorithm B”).

  In this case, since the inductor is not inserted into the original circuit to be analyzed, the initial damped oscillation does not appear. However, there is oscillation that increases in frequency over time. This oscillation becomes serious with time, and the voltage / current value of each node does not reach a steady state.

FIG. 8D shows the result of the transient analysis of the inverter chain circuit of FIG. 7 by the PTA algorithm performed by the circuit operation analysis apparatus 1 of the first embodiment (hereinafter, this PTA algorithm is referred to as “algorithm C”. Called). Despite adding inductance in series with the voltage source, there is only a slight variation between t = 4 and t = 6. Also, the final steady state is clearly obtained by the inserted time-varying pseudo-elements R _v and G _v .

  From the above results, it can be seen that the oscillation problem in the PTA method is solved by the PTA algorithm performed by the circuit operation analysis apparatus 1 of the present embodiment.

[Example 2] Practical regulator circuit As a second example, consider a practical regulator circuit that causes a non-convergence problem in DC analysis of the HSPICE simulator. The circuit is composed of 45 elements including 25BJT (Bipolar Junction Transistor). The same four algorithms as in Example 1 were applied to the DC analysis of this circuit for experiments.
In algorithm A1, oscillation was seen in the transient analysis. The oscillation vibration attenuated with time, but the oscillation was still observed at t = 1000, and a steady state was not obtained.
In the algorithm A2, when the value of the capacitor C was decreased, the oscillation attenuated relatively quickly and a steady state was obtained.
Algorithm B also oscillated over time due to the positive feedback of the regulator circuit in the transient analysis.
On the other hand, it was confirmed that algorithm C easily reaches a steady state.

[Example 3] Hybrid voltage reference circuit As a third example, a hybrid voltage reference circuit as shown in FIG. 9 is considered. A detailed description of the operation of this circuit is described in Non-Patent Document 1. The same four algorithms as in Example 1 were applied to the DC analysis of this circuit for experiments.

  As a result of performing the transient analysis for the direct current analysis, the result similar to [Example 2] was obtained for the algorithm A1. That is, oscillation occurred at the start of analysis, and the vibration attenuated with time, but did not reach a steady state even at t = 1000.

Since the value of the pseudocapacitor was reduced, the other three algorithms could finally reach a steady state. The simulation result of algorithm A2 is equivalent to the result of algorithm C. This is because in the algorithm A2, the parameter values of the pseudo elements C and L are set to C ₀ and L ₀ which are the same as those in the algorithm C.

  In algorithm B, the node voltage waveform changed greatly, and some period fluctuations were observed before the steady state was reached. On the other hand, in the algorithm C, the fluctuation of the node voltage was small.

  Table 1 shows the simulation efficiencies of these four algorithms. Table 1 also shows the simulation efficiency of [Example 1] and [Example 2].

The data marked with * is the data obtained at t = t _settle . Data without * is data obtained at the end of the transient analysis as shown in FIGS.

When comparing algorithm C with other algorithms A and B, #tot. (Total number of iterations) is reduced by about 10% in [Example 1]. The time t _settle (time until the solution reaches a steady state) is extremely short in [Example 3]. In any case. CPU time T _CPU (CPU consumption time) is suppressed.

  The configuration of the circuit operation analysis apparatus 1 according to the second embodiment of the present invention is the same as that shown in FIG. The second embodiment is different from the first embodiment in that the pseudo element inserting means 2 inserts a time-varying pseudo element into the analysis target circuit.

FIG. 10 is a diagram for explaining a time-varying pseudo element in Embodiment 2 of the present invention. In this embodiment, when as the varying pseudo element is used an element of the circuit structure variables and a pseudo resistor R _v are connected in series when a pseudo-capacitor C _0, as shown in Figure 10 (a). As shown in FIG. 10B, the resistance value of the time-varying pseudo-resistance increases exponentially with time.

  As shown in FIG. 10C, the time-varying pseudo element is inserted between each node of the analysis target circuit and the ground.

  Even in this case, it is possible to prevent oscillation in the transient analysis in the DC analysis and obtain the DC operating point in a short time.

It is a figure which shows the state which inserted the pseudo inductance and pseudo capacitance in SPICE. It is a figure explaining the time-varying pseudocapacitance in Non-Patent Document 3. It is a figure showing the structure of the circuit operation | movement analysis apparatus 1 which concerns on Example 1 of this invention. It is a figure explaining the time-varying pseudo element used in Example 1 of this invention. It is a figure explaining the method of inserting the time-varying pseudo element used in Example 1 of this invention in a circuit. It is a figure which shows the simulation model of the time-varying pseudo element used in Example 1 of this invention. It is a figure which shows an example of an inverter chain circuit. It is a figure which shows the comparison of the pseudo transient analysis of the conventional method (a) (b) and the method (c) of this invention about the inverter chain circuit of FIG. It is a figure which shows a hybrid voltage reference circuit. It is a figure explaining the time-varying pseudo element in Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit operation | movement analyzer 2 Circuit data input device 3 Output device 11 Analysis object circuit storage means 12 Pseudo element insertion means 13 Correction circuit storage means 14 Transient analysis execution means

Claims (6)

A circuit operation analysis device for calculating a DC operating point of a circuit to be analyzed by a pseudo transient analysis method,
Circuit storage means for storing circuit configuration data of the analysis target circuit;
Pseudo element insertion means for generating correction circuit configuration data of the DC analysis circuit by inserting a time-varying pseudo element for the analysis target circuit represented by the circuit configuration data;
Transient analysis execution means for calculating a DC operating point of the analysis target circuit by performing a transient analysis calculation of the DC analysis circuit based on the corrected circuit configuration data while changing the parameter value of each time-varying pseudo-element over time When,
With
The pseudo-element inserting means includes a first time-varying pseudo-element in which a pseudo-inductor and a time-varying pseudo-conductor whose conductance changes with time are connected in parallel, or a pseudo-capacitor and a time-varying pseudo-resistance whose resistance value changes with time. A second time-varying pseudo-element connected in series in the circuit to be analyzed,
The transient analysis execution means increases the conductance of the time-varying pseudo-conductor of the first time-varying pseudo-element with time and increases the resistance value of the time-varying pseudo-resistance of the second time-varying pseudo-element with time. A circuit operation analysis device characterized by performing transient analysis calculation. The pseudo element insertion means includes:
A voltage source in the circuit to be analyzed is extracted, and a first time-varying pseudo element in which a pseudo inductor and a time-varying pseudo conductor whose conductance changes with time is connected in parallel to each voltage source in the circuit to be analyzed. First time-varying pseudo-element inserting means for inserting in series with
A current source in the analysis target circuit is extracted, and a second time-varying pseudo-element in which a pseudo capacitor and a time-varying pseudo resistance whose resistance value changes with time is connected in series to each current source in the analysis target circuit. 2. The circuit operation analyzing apparatus according to claim 1, further comprising second time-varying pseudo-element inserting means that is inserted in parallel. The analysis target circuit is a circuit including a bipolar transistor,
The second time-varying pseudo-element inserting means further extracts a bipolar transistor in the analysis target circuit, and the second time-variant pseudo element insertion means extracts the second transistor between the base and emitter and between the base and collector of each bipolar transistor in the analysis target circuit. 3. The circuit operation analyzing apparatus according to claim 2, wherein a time-varying pseudo-element is inserted. The circuit to be analyzed is a circuit including a field effect transistor,
The second time-varying pseudo-element inserting means further extracts a field effect transistor in the circuit to be analyzed, and the second time-variant pseudo element insertion means between the gate and source and between the gate and drain of each field effect transistor in the circuit to be analyzed. 4. The circuit operation analysis device according to claim 2, wherein the time-varying pseudo-element is inserted. 5.   2. The circuit operation analyzing apparatus according to claim 1, wherein the pseudo element inserting means inserts the second time-varying pseudo element between each node in the analysis target circuit and the ground.   A program that causes a computer to function as the circuit operation analysis device according to any one of claims 1 to 5 by being read and executed by a computer.

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