JP4809166B2 - リモートｉ／ｏを構成する計算機システム及びｉ／ｏデータ転送方法 - Google Patents

リモートｉ／ｏを構成する計算機システム及びｉ／ｏデータ転送方法 Download PDF

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Publication number
JP4809166B2
JP4809166B2 JP2006241238A JP2006241238A JP4809166B2 JP 4809166 B2 JP4809166 B2 JP 4809166B2 JP 2006241238 A JP2006241238 A JP 2006241238A JP 2006241238 A JP2006241238 A JP 2006241238A JP 4809166 B2 JP4809166 B2 JP 4809166B2
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Japan
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data
address
memory
host
bridge
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Expired - Fee Related
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JP2006241238A
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Japanese (ja)
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JP2008065515A5 (enExample
JP2008065515A (ja
Inventor
潤 沖津
淑子 保田
貴成 馬場
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Hitachi Ltd
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Hitachi Ltd
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Priority to JP2006241238A priority Critical patent/JP4809166B2/ja
Priority to US11/896,757 priority patent/US7930445B2/en
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Publication of JP2008065515A5 publication Critical patent/JP2008065515A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
JP2006241238A 2006-09-06 2006-09-06 リモートｉ／ｏを構成する計算機システム及びｉ／ｏデータ転送方法 Expired - Fee Related JP4809166B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006241238A JP4809166B2 (ja) 2006-09-06 2006-09-06 リモートｉ／ｏを構成する計算機システム及びｉ／ｏデータ転送方法
US11/896,757 US7930445B2 (en) 2006-09-06 2007-09-05 Computer system using remote I/O and I/O data transfer method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006241238A JP4809166B2 (ja) 2006-09-06 2006-09-06 リモートｉ／ｏを構成する計算機システム及びｉ／ｏデータ転送方法

Publications (3)

Publication Number Publication Date
JP2008065515A JP2008065515A (ja) 2008-03-21
JP2008065515A5 JP2008065515A5 (enExample) 2009-04-09
JP4809166B2 true JP4809166B2 (ja) 2011-11-09

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JP2006241238A Expired - Fee Related JP4809166B2 (ja) 2006-09-06 2006-09-06 リモートｉ／ｏを構成する計算機システム及びｉ／ｏデータ転送方法

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US (1) US7930445B2 (enExample)
JP (1) JP4809166B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010054366A2 (en) * 2008-11-10 2010-05-14 Brian Joseph Niedermeyer Transaction notification system and method
WO2013011565A1 (ja) 2011-07-19 2013-01-24 トヨタ自動車株式会社 ブレーキ制御装置
ES2866156T3 (es) 2013-05-02 2021-10-19 Huawei Tech Co Ltd Sistema informático, método para acceder a un terminal de interconexión de componentes periféricos exprés, y equipo
US9952979B1 (en) * 2015-01-14 2018-04-24 Cavium, Inc. Methods and systems for direct memory access operations

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3454294B2 (ja) * 1994-06-20 2003-10-06 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプル・バス情報処理システム及びブリッジ回路
JP2570187B2 (ja) 1994-07-15 1997-01-08 日本電気株式会社 Ｄｍａ転送装置および方法
JPH0895899A (ja) 1994-09-22 1996-04-12 Hitachi Ltd Ｄｍａ転送制御装置
US5850571A (en) * 1996-04-22 1998-12-15 National Instruments Corporation System and method for converting read cycles into write cycles for improved system performance
JPH10187541A (ja) * 1996-12-24 1998-07-21 Toshiba Corp データ記憶システム及び同システムに適用するキャッシュ制御方法
US5864876A (en) * 1997-01-06 1999-01-26 Creative Technology Ltd. DMA device with local page table
US5983303A (en) * 1997-05-27 1999-11-09 Fusion Micromedia Corporation Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method
US6128674A (en) * 1997-08-08 2000-10-03 International Business Machines Corporation Method of minimizing host CPU utilization in driving an adapter by residing in system memory a command/status block a soft interrupt block and a status block queue
US6081851A (en) * 1997-12-15 2000-06-27 Intel Corporation Method and apparatus for programming a remote DMA engine residing on a first bus from a destination residing on a second bus
JP2000112835A (ja) * 1998-10-01 2000-04-21 Sony Corp メモリ装置、データ記録再生装置及びコンピュータシステム
JP2000235542A (ja) * 1999-02-16 2000-08-29 Sony Corp データ処理装置及び記録媒体
JP2002215563A (ja) 2001-01-19 2002-08-02 Fuji Xerox Co Ltd Ｄｍａ制御装置
US6988160B2 (en) * 2001-02-12 2006-01-17 P-Cube Ltd. Method and apparatus for efficient messaging between memories across a PCI bus
JP2004087867A (ja) * 2002-08-28 2004-03-18 Renesas Technology Corp 半導体集積回路装置
JP3944449B2 (ja) * 2002-12-19 2007-07-11 株式会社日立製作所 計算機システム、磁気ディスク装置、および、ディスクキャッシュ制御方法
US7398337B2 (en) * 2005-02-25 2008-07-08 International Business Machines Corporation Association of host translations that are associated to an access control level on a PCI bridge that supports virtualization
JP4394624B2 (ja) * 2005-09-21 2010-01-06 株式会社日立製作所 計算機システム及びｉ／ｏブリッジ

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Publication number Publication date
US20080256266A1 (en) 2008-10-16
JP2008065515A (ja) 2008-03-21
US7930445B2 (en) 2011-04-19

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