JP4805302B2 - Method for controlling operation of DC / DC converter device - Google Patents

Description

  The present invention relates to an operation control method for a DC / DC converter device that drives a switching element by a drive signal generated using pulse frequency modulation (PFM).

  There is known a DC / DC converter that can be used by switching between two modulation methods of pulse width modulation (PWM) and pulse frequency modulation (PFM) (Patent Documents 1 and 2). There is also a DC / DC converter that uses only PFM (Patent Document 3). Furthermore, what uses feedback control as operation control of a DC / DC converter is known (patent document 4).

Japanese Patent Laid-Open No. 06-311736 JP 2003-219637 A JP 2004-194484 A JP 2006-042536 A

  In the PFM, by changing the switching frequency, in other words, the driving time of the switching element for each switching period is made constant, and the duty of the driving signal is changed by changing the switching period. For this reason, when the calculation processing cycle for performing the calculation processing related to driving of the switching element such as calculation of the target duty is associated with the switching cycle, the calculation processing cycle changes according to the change of the switching cycle. As a result, for example, since the interval for acquiring the deviation (error) in the feedback control is not constant, there arises a problem that the weight of the acquired deviation changes, and the feedback control may not function sufficiently. In this regard, in any of Patent Documents 1 to 4, control that focuses on the change in the arithmetic processing period accompanying the change in the switching period is not performed.

  The present invention has been made in consideration of such problems, and the operation of the DC / DC converter device capable of suitably controlling the DC / DC converter device that generates the drive signal for the switching element using the PFM. An object is to provide a control method.

  An operation control method for a DC / DC converter apparatus according to the present invention is an operation control method for a DC / DC converter apparatus for driving a switching element by a drive signal generated using pulse frequency modulation (PFM), wherein the switching element The coefficient used in the arithmetic processing related to the driving is weighted according to the arithmetic processing cycle that is a cycle in which the arithmetic processing is performed and changes corresponding to the switching cycle.

  In the present invention, the coefficient used in the arithmetic processing related to the driving of the switching element is weighted according to the arithmetic processing cycle which is a cycle for performing the arithmetic processing and changes corresponding to the switching cycle. As a result, even if the calculation processing cycle changes with the change of the switching cycle, it is possible to equalize the influence, and even when the PFM is used as the modulation method, the DC / DC converter can be suitably controlled. it can.

  The coefficient is the coefficient of the integral term (I term) used in the integral control process used to calculate the duty of the drive signal. The higher the switching frequency, the smaller the I term coefficient, and the lower the switching frequency, the I The coefficient of the term may be increased. Alternatively, the coefficient is a coefficient of a differential term (D term) used in the differential control process used for calculating the duty of the drive signal, and the lower the switching frequency, the smaller the D term coefficient and the higher the switching frequency. The coefficient of the D term can be increased. Alternatively, the coefficient is a first-order lag correction coefficient used in a first-order lag process for an output value of a sensor that detects a state of a power system equipped with the DC / DC converter device, and the first-order lag correction coefficient is increased as the switching frequency is lower. The higher the switching frequency, the smaller the first order lag correction coefficient may be. Alternatively, the coefficient is set as an allowable change amount setting coefficient for a change amount limiting process for a target voltage or target current used in a power system equipped with the DC / DC converter device, and the allowable change amount setting coefficient decreases as the switching frequency increases. The allowable variation setting coefficient can be increased as the switching frequency is lower.

  In the present invention, the coefficient used in the arithmetic processing related to the driving of the switching element is weighted according to the arithmetic processing cycle which is a cycle for performing the arithmetic processing and changes corresponding to the switching cycle. As a result, even if the calculation processing cycle changes with the change of the switching cycle, it is possible to equalize the influence, and even when the PFM is used as the modulation method, the DC / DC converter can be suitably controlled. it can.

A. EMBODIMENT OF THE INVENTION Hereinafter, the vehicle electric power system 20 which can implement one Embodiment of the operation control method of the DC / DC converter device which concerns on this invention is demonstrated with reference to drawings.

1. Configuration of Vehicle Power System 20 (1) Overall Configuration FIG. 1 is a circuit diagram of a vehicle power system 20 capable of executing the operation control method of the DC / DC converter device according to this embodiment. The vehicle power system 20 can be mounted on a vehicle such as a fuel cell vehicle, and is basically a hybrid power device including a fuel cell 22 and a power storage device (referred to as a battery) 24 that is an energy storage. A traveling motor 26 to which current (electric power) is supplied from the hybrid power device through the inverter 34, the primary side 1S to which the battery 24 is connected, the fuel cell 22 and the motor 26 (inverter 34), DC / DC converter apparatus {VCU (Voltage Control Unit) which performs voltage conversion with the secondary side 2S to which is connected. } 23. The rotation of the motor 26 is transmitted to the wheel 16 through the speed reducer 12 and the shaft 14.

(2) Fuel cell 22
The fuel cell 22 has, for example, a stack structure in which cells formed by sandwiching a solid polymer electrolyte membrane between an anode electrode and a cathode electrode from both sides are stacked. A hydrogen tank 28 and an air compressor 30 are connected to the fuel cell 22 by piping. Pressurized hydrogen in the hydrogen tank 28 is supplied to the anode of the fuel cell 22. Further, air is supplied to the cathode of the fuel cell 22 by the air compressor 30. A power generation current If is generated by an electrochemical reaction between hydrogen (fuel gas), which is a reaction gas, and air (oxidant gas) in the fuel cell 22. The generated current If is supplied to the inverter 34 and / or the DC / DC converter 36 of the VCU 23 via a current sensor 32 and a diode (also referred to as a disconnect diode) 33.

(3) Battery 24
As the battery 24 connected to the primary side 1S, for example, a lithium ion secondary battery, a nickel hydride secondary battery, or a capacitor can be used. In this embodiment, a lithium ion secondary battery is used. The battery 24 supplies the motor current Im to the inverter 34 through the DC / DC converter 36 of the VCU 23.

(4) Inverter 34
The inverter 34 performs DC / AC conversion and supplies the motor current Im to the motor 26, while the motor current Im after AC / DC conversion accompanying the regenerative operation is transferred from the secondary side 2 </ b> S to the primary side through the DC / DC converter 36. Supply to 1S.

  In this case, the primary voltage V1 obtained by converting the regenerative voltage or the secondary voltage V2 that is the power generation voltage Vf of the fuel cell 22 into a low voltage by the DC / DC converter 36 charges the battery 24 as the battery current Ibat.

(5) VCU23
The VCU 23 includes a DC / DC converter 36 and a converter control unit 54 that drives and controls the DC / DC converter 36.

  The DC / DC converter 36 includes an upper arm composed of a switching element such as an IGBT between the battery 24 (first power device) and the second power device {the fuel cell 22 or the regenerative power source (inverter 34 and motor 26)}. Three phase arms {U-phase arm UA (81u, 82u) consisting of element 81 {81u, 81v, 81w (81u to 81w)} and lower arm element 82 {82u, 82v, 82w (82u to 82w)}, The V-phase arm VA (81v, 82v) and the W-phase arm WA (81w, 82w)} are configured as a three-phase arm connected in parallel.

  Diodes 83u, 83v, 83w, 84u, 84v, and 84w are connected in the reverse direction to the arm elements 81u, 81v, 81w, 82u, 82v, and 82w, respectively.

  In consideration of convenience of understanding and the like, in the present invention, it is assumed that the upper arm element 81 and the lower arm element 82 do not include the antiparallel diodes 83 and 84.

  When the voltage is converted between the primary voltage V1 and the secondary voltage V2 by the DC / DC converter 36, one reactor 90 for releasing and storing energy is provided for each phase arm (U phase). Arm UA, V-phase arm VA, W-phase arm WA) are inserted between the common connection point at the midpoint and battery 24.

  The upper arm elements 81 (81u to 81w) are respectively driven by gate drive signals (drive voltages) UH, VH, and WH (high levels thereof) output from the converter control unit 54, and the lower arm elements 82 (82u to 82w). ) Are driven by gate drive signals (drive voltages) UL, VL, WL (high levels thereof), respectively.

  The converter control unit 54 includes a microcomputer 72, a memory 74, and a timer 76, and controls the operation of the DC / DC converter 36. The control method will be described later.

(6) Capacitors 38 and 39
Smoothing capacitors 38 and 39 are provided on the primary side 1S and the secondary side 2S, respectively.

(7) Various control units (FC control unit 50, motor control unit 52, converter control unit 54, overall control unit 56)
The system including the fuel cell 22, the hydrogen tank 28 and the air compressor 30 is controlled by the FC control unit 50. The system including the inverter 34 and the motor 26 is controlled by a motor control unit 52 including an inverter driving unit (not shown). As described above, the system including the DC / DC converter 36 is controlled by the converter control unit 54.

  The FC control unit 50, the motor control unit 52, and the converter control unit 54 are higher-level control units, and are controlled by the overall control unit 56 that determines values such as the total load amount Lt of the fuel cell 22.

  The overall control unit 56 determines the total load request of the vehicle power system 20 determined based on inputs (load requests) from various switches and various sensors in addition to the state of the fuel cell 22, the state of the battery 24, and the state of the motor 26. From the amount Lt, the fuel cell shared load amount (required output) Lf that the fuel cell 22 should bear, the battery shared load amount (required output) Lb that the battery 24 should bear, and the regenerative power source shared load that the regenerative power source should bear The distribution (sharing) of the amount Lr is determined while arbitrating, and a command is sent to the FC control unit 50, the motor control unit 52, and the converter control unit 54.

  The overall control unit 56, the FC control unit 50, the motor control unit 52, and the converter control unit 54 are respectively an input / output interface such as an A / D converter and a D / A converter in addition to a CPU, a ROM, a RAM, and a timer. In addition, a DSP (Digital Signal Processor) or the like is included as necessary.

  The overall control unit 56, the FC control unit 50, the motor control unit 52, and the converter control unit 54 are connected to each other through a communication line 70 such as a CAN (Controller Area Network) that is an in-vehicle LAN, and are connected to various switches and sensors. Input / output information is shared, and input / output information from these various switches and various sensors is input, and each CPU executes a program stored in each ROM to realize various functions.

(8) Various switches and various sensors As various switches and various sensors for detecting the vehicle state, the primary voltage V1 (which is basically equal to the battery voltage Vbat) is detected in addition to the current sensor 32 for detecting the generated current If. A voltage sensor 61 for detecting a primary current I1 and a voltage sensor 63 for detecting a secondary voltage V2 (approximately equal to the generated voltage Vf of the fuel cell 22 when the disconnect diode 33 is conductive). There are a current sensor 64 for detecting the secondary current I2, an ignition switch 65 connected to the communication line 70, an accelerator sensor 66, a brake sensor 67, a vehicle speed sensor 68, and the like.

2. Various Controls / Processing (1) Basic Voltage Control in VCU 23 FIG. 2 shows a flowchart of the basic operation of the DC / DC converter 36 that is driven and controlled by the converter control unit 54.

  In step S1, when the overall control unit 56 determines (calculates) the total load request amount Lt from the electric power request of the motor 26, the electric power request of the air compressor 30, and the electric power request of other auxiliary machines, each of which is a load request. In step S2, the overall control unit 56 determines the distribution of the fuel cell shared load amount Lf, the battery shared load amount Lb, and the regenerative power source shared load amount Lr for outputting the determined total load request amount Lt. The command sent from the overall control unit 56 to the converter control unit 54 usually takes the form of a command value of the secondary voltage V2 (secondary voltage command value V2com).

  Next, in step S3, the converter control unit 54 determines the power generation voltage Vf of the fuel cell 22, based on the secondary voltage command value V2com, here, the target value of the secondary voltage V2 (secondary voltage target value V2tar). The

  When the secondary voltage target value V2tar is determined, in step S4, the converter control unit 54 drives and controls the DC / DC converter 36 so as to be the determined secondary voltage target value V2tar. The DC / DC converter 36 performs a step-up operation, a step-down operation, and the like (details will be described later).

  The secondary voltage V <b> 2 and the primary voltage V <b> 1 are controlled by the converter control unit 54 by PID control in which the DC / DC converter 36 is combined with feedforward control and feedback control.

(2) Output Control of Fuel Cell 22 Next, output control of the fuel cell 22 by the VCU 23 will be described.

  During power generation in which fuel gas from the hydrogen tank 28 and compressed air from the air compressor 30 are supplied, the power generation current If of the fuel cell 22 is referred to as the characteristic 91 {function F (Vf) shown in FIG. } Is determined by setting the secondary voltage V2, that is, the generated voltage Vf, through the DC / DC converter 36 by the converter control unit 54. That is, the generated current If is determined as a function F (Vf) value of the generated voltage Vf. If If = F (Vf) and the generated voltage Vf is set to Vf = Vfa = V2, for example, the generated current Ifa as a function value of the generated voltage Vfa (V2) is determined. {Ifa = F (Vfa) = F (V2)}.

  As described above, since the fuel cell 22 determines the generated current If by determining the secondary voltage V2 (generated voltage Vf), the secondary voltage V2 (generated voltage) is controlled when driving the vehicle power system 20. Vf) is set to the target voltage (target value).

  In a system including the fuel cell 22 such as the vehicular power system 20, basically, the VCU 23 is set so that the secondary voltage V2 on the secondary side 2S of the DC / DC converter 36 becomes the target voltage (secondary voltage target value V2tar). The VCU 23 controls the output (generated current If) of the fuel cell 22.

(3) Exceptional Control in VCU 23 As described above, in the VCU 23, in the V2 control mode (the secondary voltage target value V2tar and the secondary voltage V detected by the voltage sensor 63 are matched with each other) Is basically used. In addition to this V2 control mode, the following modes are also used.

(A) I1 control mode For example, when an overcurrent occurs on the primary side 1S, that is, the primary current I1 detected by the current sensor 62 is a threshold value indicating the occurrence of an overcurrent (overcurrent threshold THoc [A] ), The DC / DC converter 36 can be controlled so that the primary current I1 becomes equal to or less than the overcurrent threshold THoc. In this way, the target value (target primary current I1tar) of the primary current I1 is set, and the DC / DC converter 36 is configured to limit the primary current I1 detected by the current sensor 62 to the target primary current I1tar or less. The operation mode for controlling is referred to as “I1 control mode”.

(B) V1 control mode For example, for the purpose of controlling the battery current Ibat flowing into or out of the battery 24, the DC / DC converter 36 is controlled so that the secondary voltage V2 becomes equal to the primary voltage V1. Is possible. In this way, the target value of the primary voltage V1 (target primary voltage V1tar) is set, and the DC / DC converter 36 is set so that the primary voltage V1 detected by the voltage sensor 61 matches the target primary voltage V1tar. The operation mode to be controlled is referred to as “V1 control mode”.

(4) Switching Control of DC / DC Converter 36 (a) Outline As switching control of the DC / DC converter 36 in this embodiment, (i) the upper arm element 81 is driven in a part of each switching cycle Tsw [μs]. Step-down chopper control, (ii) step-up chopper control for driving the lower arm element 82 in a part of each switching cycle Tsw, and (iii) DC / DC converter 36 without performing either step-down chopper processing or step-up chopper processing. And (iv) stop control in which no current is supplied to the DC / DC converter 36.

(B) Synchronous switching processing As shown in FIGS. 4 and 5, the step-down chopper control and the step-up chopper control described above are used in combination in each switching cycle Tsw. That is, in each switching cycle Tsw, the driving time of the upper arm elements 81u to 81w (hereinafter also referred to as “upper arm element driving time T1”) and the driving time of the lower arm elements 82u to 82w (hereinafter referred to as “lower arm element driving time T1”). Both of them appear, and the upper arm elements 81u to 81w and the lower arm elements 82u to 82w are driven alternately. In this manner, the process of alternately driving the upper arm elements 81u to 81w and the lower arm elements 82u to 82w every switching cycle Tsw is referred to as “synchronous switching process”.

  Further, between the upper arm element driving time T1 and the lower arm element driving time T2, the upper arm elements 81u to 81w and the lower arm elements 82u to 82w are simultaneously driven to prevent the secondary voltage V2 from being short-circuited. A dead time dt is arranged for this purpose. Hereinafter, of the dead time dt, the one arranged after the previous lower arm element driving time T2 and before the current upper arm element driving time T1 is referred to as a first dead time dt1, and this time the upper arm element driving is performed. What is arranged after the time T1 and before the current lower arm element driving time T2 is referred to as a second dead time dt2.

  In the synchronous switching process, the upper arm elements 81u to 81w and the lower arm elements 82u to 82w are alternately driven every switching cycle Tsw. However, because of the potential difference between the primary side 1S and the secondary side 2S, , Only one of them is turned on (not flowing).

(C) Step-down Chopper Control FIG. 4 shows a state in which the upper arm elements 81u to 81w are turned on and the lower arm elements 82u to 82w are not turned on by the step-down chopper control. In FIG. 4, in the waveforms of the drive signals UH, UL, VH, VL, WH, WL, the hatched period is an arm element to which the drive signals UH, UL, VH, VL, WH, WL are supplied (for example, , The arm element corresponding to the drive signal UH indicates a period during which the upper arm element 81u) is ON (a period during which current actually flows).

  When the upper arm elements 81u to 81w are turned on, the secondary current I2 is supplied from the secondary side 2S to the primary side 1S {sinking. }, The step-down operation is executed by so-called step-down chopper control. For example, when the upper arm element 81u is turned on between time points t1 and t2 in FIG. 4, energy is stored in the reactor 90 by the secondary current I2 output from the capacitor 39, and the primary current I1 is transferred from the capacitor 38 to the battery 24. Supplied. Next, the diodes 84 u to 84 w are turned on as flywheel diodes, energy is released from the reactor 90, energy is stored in the capacitor 38, and the primary current I 1 is supplied to the battery 24. Next, between the time points t5 and t6, the upper arm element 81v is turned on, and the secondary current I2 is sunk to the battery 24 side as described above. Thus, in the present embodiment, the three upper arm elements 81u to 81w are turned on while rotating (such an operation is also referred to as “rotation switching”).

  When there is a regenerative voltage, the regenerative power source shared load Lr is added to the sunk secondary current I2 during this step-down operation. The driving time of the upper arm elements 81u to 81w and the lower arm elements 82u to 82w in the step-down operation is also determined so that the secondary voltage V2 is maintained.

  A time chart of the primary current I1 during the step-down control of the VCU 23 is shown on the lower side of FIG.

  In FIG. 4, the sign of the primary current I1 flowing through the reactor 90 is a step-up current flowing from the primary side 1S to the secondary side 2S (source current flowing out from the secondary side 2S of the DC / DC converter 23 to the inverter 34). Positive (+), a step-down current flowing from the secondary side 2S to the primary side 1S (a sink current flowing from the fuel cell 22 or the inverter 34 to the secondary side 2S) is negative (−). This also applies to FIG.

(D) Boost Chopper Control FIG. 5 shows a state in which the lower arm elements 82u to 82w are turned on and the upper arm elements 81u to 81w are not turned on by the boost chopper control. The meaning of the hatched period is the same as that in FIG.

  When the lower arm elements 82u to 82w are turned on, a current flows from the primary side 1S to the secondary side 2S, and the boosting operation is executed by so-called boosting chopper control. For example, when the lower arm element 82u is turned on between time points t13 and t14 in FIG. 5, energy is stored in the reactor 90 by the primary current I1 as the battery current Ibat, and at the same time, the secondary current I2 is transferred from the capacitor 39 to the inverter 34 side. To supply {to say source. }. Next, the diodes 83u to 83w functioning as rectifier diodes are turned on, energy is discharged from the reactor 90, energy is stored in the capacitor 39, and it is sourced to the inverter 34 as the secondary current I2. Next, between time points t17 and t18, the lower arm element 82v is turned on, and the secondary current I2 is sourced to the inverter 34 side as described above. Similar to the three upper arm elements 81u to 81w, the three lower arm elements 82u to 82w also perform rotation switching.

  The upper arm element driving time T1 (time for driving the upper arm elements 81u to 81w) and the lower arm element driving time T2 (time for driving the lower arm elements 82u to 82w) are such that the secondary voltage V2 is maintained. To be determined. In general, since the proportion of the dead time dt in the switching cycle Tsw is small, the proportion of the lower arm element driving time T2 in one switching cycle Tsw is “1-DUT” and “1- (V1 / V2tar). ) ". Alternatively, the duty voltage DUT can be defined as “DUT = (T1−dt) / Tsw” by calculating the secondary voltage command value V2com in consideration of the dead time dt by the overall control unit 56.

(E) Modulation method In the present embodiment, pulse width modulation (PWM) and pulse frequency modulation are used as modulation methods for the drive signals UH, UL, VH, VL, WH, and WL generated by the converter control unit 54. (PFM: Pulse Frequency Modulation) can be used selectively.

  The PWM fixes the switching frequency Fsw [Hz] (1 / switching cycle Tsw [μs]), the upper arm element driving time T1, the lower arm element driving time T2, and the first dead time dt1 and the second second as necessary. By controlling the drive of the upper arm elements 81u to 81w and the lower arm elements 82u to 82w by changing the length of the dead time dt2, the step-up / step-down operation of the DC / DC converter 36 is controlled.

  The PFM fixes either the length of the upper arm element driving time T1 or the lower arm element driving time T2, and changes the switching cycle Tsw to turn on / off the upper arm elements 81u to 81w and the lower arm elements 82u to 82w. By controlling the off operation, the step-up / step-down operation of the DC / DC converter 36 is controlled.

(F) Generation of Drive Signals UH, UL, VH, VL, WH, WL FIG. 6 and FIG. 7 show each process in converter control unit 54 and generation of drive signals UH, UL, VH, VL, WH, WL. The relationship is simply shown. The converter control unit 54 determines a waveform of each drive signal UH, UL, VH, VL, WH, WL (calculates a timer set value TMR for setting each drive signal to a high level), a timer set value calculation process, and a calculation The timer set value TMR thus set is set in the timer 76, and drive signal output processing for outputting drive signals UH, UL, VH, VL, WH, WL corresponding to the timer set value TMR is performed. The timer set value calculation process and the drive signal output process are controlled by the microcomputer 72.

  In the present embodiment, the time Pcal required for one timer set value calculation process is, for example, 120 μs, and the time Pout required for one drive signal output process is, for example, 15 μs. When using PWM, the control cycle Tc (one of the calculation processing cycles in the microcomputer 72) is, for example, 60 μs, and when using PFM, the control cycle Tc is variable. The control cycle Tc indicates the cycle of the drive signal output process (the interval from the start of a certain drive signal output process to the start of the next drive signal output process). The control cycle Tc has the same length as the corresponding switching cycle Tsw (Tc = Tsw), and starts earlier by the time Pout related to the drive signal output process than the corresponding switching cycle Tsw.

  As shown in FIGS. 6 and 7, the drive signal output process is performed for a time Pout from the start of the control cycle Tc [μs]. In the present embodiment, the timer set value calculation process is performed with the remaining time Pr obtained by subtracting the drive signal output process time Pout from the control cycle Tc (Pr = Tc−Pout). For this reason, when PWM is used, the remaining time Pr is 45 μs (45 = 60−15), for example, and is shorter than the time Pcal (eg, 120 μs) required for the timer set value calculation process (Pr <Pcal). . For this reason, one timer set value calculation process is performed during a plurality of control cycles Tc (specifically, three control cycles Tc).

  On the other hand, when the PFM is used, the remaining time Pr changes according to the length of the control cycle Tc (Pr∝Tc). As a result, it is possible to perform a single timer set value calculation process with a control cycle Tc that is smaller than that in PWM. For example, if the remaining time Pr is 60 μs or more, the timer setting value calculation process can be performed once every two control cycles Tc. If the remaining time Pr is 120 μs or more, one timer setting value calculation process can be performed for each control cycle Tc. In this embodiment, paying attention to this point, as shown in FIGS. 6 and 7, the use of PFM increases the switching cycle Tsw, and the control cycle Tc increases accordingly, and the smaller the number. The timer setting value calculation process is performed once corresponding to the switching period Tsw (control period Tc). Thereby, the timer setting value calculation processing cycle Tcal indicating the interval from the start of a certain timer setting value calculation processing to the start of the next timer setting value calculation processing is not as long as the switching cycle Tsw or the control cycle Tc. It may be shorter.

  Switching between PWM and PFM is performed according to the duty DUT. The duty DUT indicates the ratio of the upper arm element driving time T1 to the switching cycle Tsw without considering the first dead time dt1 and the second dead time dt2 (DUT = T1 / Tsw). Therefore, if the first dead time dt1 and the second dead time dt2 are not taken into consideration, the ratio of the lower arm element driving time T2 to the switching cycle Tsw is obtained by 1-DUT (T2 / Tsw = 1−DUT). The first dead time dt1 and the second dead time dt2 are added according to the duty DUT in the signal modulation processing unit 136 (FIG. 8) described later. As the first dead time dt1 and the second dead time dt2, fixed values (for example, 5 μs) are usually used. Therefore, by mapping the correspondence relationship between the duty DUT and the upper arm element driving time T1 and the lower arm element driving time T2 in advance, the upper arm element driving time T1 and the lower arm element driving are based on the duty DUT. Time T2 can be selected.

  In the present embodiment, PWM is normally used as the modulation method, and PFM is used when the duty DUT approaches 1 (100%) or 0 (0%). Specifically, PFM is used when the duty DUT approaches 100% and the lower arm element drive time T2 is less than the minimum on-time T2on_min of the lower arm elements 82u to 82w. Further, when the duty approaches 0% and the upper arm element driving time T1 is less than the minimum on-time T1on_min of the upper arm elements 81u to 81w, PFM is used. In the present embodiment, the minimum on-time T1on_min of the upper arm elements 81u to 81w and the minimum on-time T2on_min of the lower arm elements 82u to 82w are the same length.

  In the present embodiment, the PWM switching frequency Fsw is a frequency that exceeds the audible frequency band (for example, 20 kHz), and the PFM switching frequency Fsw includes from the audible frequency band to the frequency band that exceeds the audible frequency band ( For example, 1 to 20 kHz).

(5) Calculation of Duty DUT (a) V2 Control Mode FIG. 8 shows a functional block diagram of the converter control unit 54 for calculating the duty DUT in the V2 control mode described above.

  The secondary voltage command value V2com calculated by the overall control unit 56 is supplied to the change amount limiting unit 110 through the port 101. In the change amount limiting unit 110, a change amount limiting process is performed on the secondary voltage command value V2com, and a secondary voltage target value V2tar is calculated. In the change amount limiting process, the previous secondary voltage target value V2tar {secondary voltage target value V2tar (previous)} and the current secondary voltage target value V2tar {secondary voltage target value V2tar (current)} are different. This is a process of limiting the amount of change in the secondary voltage target value V2tar so that it does not pass.

  FIG. 9 shows a flowchart of the change amount limiting process in the V2 control mode. In step S11, the converter control unit 54 compares the current secondary voltage command value V2com {secondary voltage command value V2com (current)} notified from the overall control unit 56 and the secondary voltage target value V2tar (previous). The difference Dt_V2 is calculated {Dt_V2 = V2com (current) −V2tar (previous)}. In subsequent step S12, it is determined whether or not the difference Dt_V2 is equal to or greater than the upper limit value Cmax_V2 (positive number) of the allowable change amount of the secondary voltage target value V2tar. When the difference Dt_V2 is greater than or equal to the upper limit value Cmax_V2 (S12: Yes), in step S13, the converter control unit 54 calculates the sum of the secondary voltage target value V2tar (previous) and the upper limit value Cmax_V2 as the secondary voltage target value V2tar (current time). ) {V2tar (current) ← V2tar (previous) + Cmax_V2}.

  When the difference Dt_V2 is less than the upper limit value Cmax_V2 (S12: No), in step S14, the converter control unit 54 determines that the difference Dt_V2 is the lower limit value Cmin_V2 (negative number) of the allowable change amount of the secondary voltage target value V2tar. Determine if: When the difference Dt_V2 is equal to or smaller than the lower limit value Cmin_V2 of the allowable change amount (S14: Yes), in step S15, the converter control unit 54 calculates the sum of the secondary voltage target value V2tar (previous) and the lower limit value Cmin_V2 as the secondary voltage. Set to target value V2tar (current). When the difference Dt_V2 is larger than the lower limit value Cmin_V2 of the allowable change amount (S14: No), in step S16, the converter control unit 54 changes the secondary voltage command value V2com (current) to the secondary voltage target value V2tar (current). Set.

Here, in the present embodiment, the upper limit value Cmax_V2 and the lower limit value Cmin_V2 of the allowable change amount are changed according to the switching frequency Fsw calculated this time. That is, the upper limit value Cmax_V2 and the lower limit value Cmin_V2 are calculated using the following formulas (1) and (2).
Cmax_V2 = Cmaxr_V2 × (Fswr / Fsw) (1)
Cmin_V2 = Cminr_V2 × (Fswr / Fsw) (2)

  In the above formulas (1) and (2), Cmaxr_V2 is the reference value of the upper limit value Cmax_V2, Cminr_V2 is the reference value of the lower limit value Cmin_V2, Fsw is the current switching frequency, and Fswr is the switching frequency. This is a reference value of Fsw (reference switching frequency Fswr).

  In the above formula (1), the higher the switching frequency Fsw (the shorter the switching cycle Tsw), the smaller the upper limit value Cmax_V2, and the lower the switching frequency Fsw (the longer the switching cycle Tsw), the higher the upper limit value Cmax_V2. Take a large value. Therefore, the higher the switching frequency Fsw, the smaller the rate of change of the secondary voltage target value V2tar (current) with respect to the secondary voltage target value V2tar (previous), and the larger the rate of change as the switching frequency Fsw is lower. Can do.

  Similarly, in the above formula (2), the lower limit value Cmin_V2 is smaller as the switching frequency Fsw is higher, and the lower limit value Cmin_V2 is larger as the switching frequency Fsw is lower. Therefore, the higher the switching frequency Fsw, the smaller the rate of change of the secondary voltage target value V2tar (current) with respect to the secondary voltage target value V2tar (previous), and the larger the rate of change as the switching frequency Fsw is lower. Can do.

  Since the switching cycle Tsw is the reciprocal of the switching frequency Fsw, “Tsw / Tswr” can be used instead of “Fswr / Fsw” in the above formulas (1) and (2). Tswr is a reference value of the switching period Tsw. Further, since the switching cycle Tsw and the control cycle Tc corresponding thereto are equal, “Tc / Tcr” or “Fcr / Fc” can be used instead of “Tsw / Tswr”. Tcr is a reference value of the control cycle Tc, Fc is a control frequency as the reciprocal (1 / Tc) of the control cycle Tc, and Fcr is a reference value of the control frequency Fc. Regardless of which is used, weighting corresponding to the control cycle Tc is performed in the equations (1) and (2).

  Returning to FIG. 8, the secondary voltage target value V2tar calculated by the variation limiter 110 is supplied as a division signal (divisor signal) to the calculation point 144 (ratio generator) and also to the calculation point 142 (subtractor). It is supplied as an addition signal (subtracted signal).

The analog value (analog secondary voltage V2ana) of the secondary voltage V2 detected by the voltage sensor 63 is supplied to the A / D converter 122 via the port 102, and the digital value of the secondary voltage V2 (digital secondary voltage V2dig). ). The digital secondary voltage V2dig is supplied to the primary delay correction unit 112, and the secondary voltage V2 is calculated by performing the primary delay correction process. The first-order lag correction process in the V2 control mode of the present embodiment is a process for correcting a so-called first-order lag (response delay of sensor output), and is performed using the following equation (3).
V2 (current) = V2 (previous) + Kf_V2 × {V2dig (current) −V2 (previous)} (3)

In the above equation (3), V2 (current) is the current secondary voltage V2, V2 (previous) is the previous secondary voltage V2, and Kf_V2 is a coefficient (primary for correcting the primary delay). Delay correction coefficient), and V2dig (current) is the current digital secondary voltage V2dig. In the present embodiment, the first-order lag correction coefficient Kf_V2 is defined by the following equation (4).
Kf_V2 = Kf_V2r × (Fswr / Fsw) (4)

  In the above equation (4), Kf_V2r is a reference value of the first-order lag correction coefficient Kf_V2, and takes a value of 0 to 1. Fsw is the current switching frequency, and Fswr is a reference value for the switching frequency Fsw.

  In equation (4), the higher the switching frequency Fsw (the shorter the switching period Tsw), the smaller the first order lag correction coefficient Kf_V2, and the lower the switching frequency Fsw (the longer the switching period Tsw), the first order lag correction. The coefficient Kf_V2 takes a large value. For this reason, the effect of the first-order lag can be made constant (constant time constant) regardless of the switching frequency Fsw.

  Similarly to the above, “Tsw / Tsw”, “Tc / Tcr”, or “Fcr / Fc” may be used instead of “Fswr / Fsw” in Formula (4).

  Returning to FIG. 8, the secondary voltage V <b> 2 calculated by the primary delay correction unit 112 is supplied to the calculation point 142 (subtractor) as a subtraction signal (decrement signal).

The deviation e = V2tar−V2 output from the calculation point 142 is supplied to the PID processing unit 135. The PID processing unit 135 converts the deviation e into a correction duty ΔDUT that is a correction value of the duty DUT, using PID processing including proportional (P) control processing, integration (I) control processing, and differentiation (D) control processing. The correction duty ΔDUT is a feedback term (FB term) for obtaining the duty DUT and can be expressed by the following equation (5).
ΔDUT = P term + I term + D term (5)

  In the above equation (5), the P term, the I term, and the D term are a proportional term, an integral term, and a differential term of so-called PID processing, respectively.

The P term, I term, and D term of the formula (5) are represented by the following formulas (6) to (8) as general formulas.
P term (current) = Kp × e (current) (6)
I term (current) = I term (previous) + Ki × e (current) (7)
D term (current) = Kd × {e (current) −e (previous)} (8)

  Here, Kp is a P-term coefficient (positive value), Ki is a I-term coefficient (positive value), and Kd is a D-term coefficient (positive value). The I term (previous) is the previous value (correction value) of the I term. As described above, e (current) is a deviation between V2tar (current) and V2 (current). e (previous) is a deviation between V2tar (previous) and V2 (current). The sum of the P term, the I term, and the D term indicates the correction duty ΔDUT.

In the present embodiment, the coefficients Ki and Kd are defined by the following expressions (9) and (10).
Ki = Kir × (Fswr / Fsw) (9)
Kd = Kdr × (Fsw / Fswr) (10)

  Kir is a reference value of the coefficient Ki, and Kdr is a reference value of the coefficient Kd. As shown in Expression (9), the coefficient Ki is calculated by multiplying the reference value Kir by a value obtained by dividing the reference switching frequency Fswr by the switching frequency Fsw. Therefore, as the switching frequency Fsw increases, in other words, as the switching period Tsw decreases, the value of the coefficient Ki decreases, and as a result, the absolute value of the I term also decreases.

  Further, as shown in the equation (10), the coefficient Kd is calculated by multiplying the reference value Kdr by dividing the switching frequency Fsw by the reference switching frequency Fswr. Therefore, as the switching frequency Fsw increases, in other words, as the switching period Tsw decreases, the coefficient Ki increases in value, and as a result, the absolute value of the D term also increases.

  Returning to FIG. 8 again, the calculated correction duty ΔDUT is supplied as an addition signal to one input of the calculation point 146 (adder).

The analog value of the primary voltage V1 detected by the voltage sensor 61 (analog primary voltage Vana) is supplied to the A / D converter 121 via the port 104, and the digital value (digital 1) of the primary voltage V1. Next voltage V1dig). The digital primary voltage V1dig is supplied to the primary delay correction unit 114 and subjected to the same primary delay correction processing as that of the primary delay correction unit 112, and then calculated as the primary voltage V1. That is, the primary voltage V1 is calculated using the following equation (11).
V1 (current) = V1 (previous) + Kf_V1 × {V1dig (current) −V1 (previous)} (11)

In the above equation (11), V1 (current) is the current primary voltage V1, V1 (previous) is the previous primary voltage V1, and Kf_V1 is a coefficient (primary for correcting the primary delay). Delay correction coefficient), and V1dig (current) is the current digital primary voltage V1dig. The first-order lag correction coefficient Kf_V1 is defined by the following equation (12).
Kf_V1 = Kf_V1r × (Fswr / Fsw) (12)

  In the above equation (12), Kf_V1r is a reference value of the first-order lag correction coefficient Kf_V1, and takes a value of 0 to 1.

  Returning to FIG. 8, the primary voltage V <b> 1 calculated by the primary delay correction unit 114 is supplied to the calculation point 144 (ratio generator) as a multiplication signal (dividend signal).

  The reference duty DUTs (DUTs = V1 / V2tar) that is the output of the calculation point 144 is supplied to the other input of the calculation point 146 as an addition signal, and the duty DUT (DUT = DUTs + ΔDUT = V1 / V2tar + ΔDUT) that is the output of the calculation point is The signal is supplied to the signal modulation processing unit 136.

  The signal modulation processing unit 136 includes the timer 76 described above, and supplies the drive signals UH, VH, and WH having the duty DUT (DUT = V1 / V2tar + ΔDUT) to the upper arm elements 81u to 81w through the ports 138 to 143. The arm element 82 is supplied with drive signals UL, VL, WL having a duty of 1-DUT, that is, 1- (V1 / V2tar + ΔDUT). At this time, the PWM method or the PFM method is used according to the duty DUT.

(B) V1 Control Mode FIG. 10 is a functional block diagram of the converter control unit 54 for calculating the duty DUT in the V1 control mode described above.

  The primary voltage command value V1com calculated by the overall control unit 56 is supplied to the change amount limiting unit 116 through the port 201. The change amount restriction unit 116 performs the same change amount restriction process as described above. That is, based on the difference Dt_V1 between the current primary voltage command value V1com {primary voltage target value V1com (current)} and the previous primary voltage target value V1tar {primary voltage target value (previous)}. Primary voltage target value V1tar {Primary voltage target value V1tar (current)} is calculated. At this time, the upper limit value Cmax_V1 and the lower limit value Cmin_V1 of the allowable change amount of the primary voltage target value V1tar are set, and the upper limit value Cmax_V1 and the lower limit value Cmin_V1 are weighted according to the current switching frequency Fsw (control cycle Tc). To do. The primary voltage target value V1tar (current) is supplied as an addition signal (subtracted signal) to the calculation point 242 (subtracter).

  Similarly to the case of the V2 control mode, the analog primary voltage Vana detected by the voltage sensor 61 is supplied to the A / D converter 121 via the port 104 and converted to the digital primary voltage V1dig. The digital primary voltage V1dig is supplied to the primary delay correction unit 114, and after the primary delay correction process is performed, the digital primary voltage V1dig is calculated as the primary voltage V1. The primary voltage V1 is supplied to the calculation point 242 (subtracter) as a subtraction signal (decrement signal).

  The deviation e = V1tar−V1 output from the calculation point 242 is supplied to the PID processing unit 235. The PID processing unit 235 converts the deviation e into a correction duty ΔDUT that is a correction value of the duty DUT using PID processing including proportional (P) control processing, integration (I) control processing, and differentiation (D) control processing. The correction duty ΔDUT is supplied to the signal modulation processing unit 136 as a duty DUT (DUT = ΔDUT).

  The signal modulation processing unit 136 supplies the drive signals UH, VH, and WH having the duty DUT (DUT = ΔDUT) to the upper arm elements 81u to 81w through the ports 138 to 143, and the duty 1-DUT to the lower arm elements 82u to 82w. That is, the drive signals UL, VL, WL of 1-ΔDUT are supplied.

3. As described above, in the present embodiment, coefficients used in the change amount limiting process, the primary delay correction process, and the PID process (upper limit values Cmax_V2, Cmax_V1, lower limit values Cmin_V2, Cmin_V1, primary delay in the change amount limiting process). The first-order lag correction coefficients Kf_V2 and Kf_V1 in the correction process, and the P-term coefficient Kp and the I-term coefficient Ki) in the PID process are weighted according to the control period Tc that changes corresponding to the switching period Tsw. As a result, even if the control cycle Tc changes with the change of the switching cycle Tsw, the influence can be equalized, and the DC / DC converter 36 is suitably controlled even when the PFM is used as the modulation method. be able to.

  In the present embodiment, the higher the switching frequency Fsw, the smaller the coefficient Ki of the I term, and the lower the switching frequency Fsw, the larger the coefficient Ki. In the integral control process, the product of the deviation e acquired this time and the coefficient Ki of the I term is added to the I term (previous) to obtain the current value, but the cycle of the integral control process (control cycle Tc) is set to the switching cycle Tsw. When the switching frequency Fsw is increased (the switching period Tsw is shortened), the interval for acquiring the deviation e is shortened, and the current value may be excessive. On the other hand, when the switching frequency Fsw is decreased (the switching period Tsw is increased), the interval for acquiring the deviation e is increased, so that the current value may be too small. According to the present embodiment, the higher the switching frequency Fsw, the smaller the coefficient Ki of the I term, and the lower the switching frequency Fsw, the larger the coefficient Ki. Therefore, the influence of changing the acquisition interval of the deviation e is equalized. It is possible to reduce the influence of changing the switching frequency Fsw.

  In this embodiment, the lower the switching frequency Fsw, the smaller the coefficient Kd of the D term, and the higher the switching frequency Fsw, the larger the coefficient Kd. In the differential control process, the difference between the currently acquired deviation e and the previously acquired deviation e (previous) multiplied by the coefficient Kd is used as the current value. The differential control process cycle (control cycle Tc) is used as the switching cycle. When changing according to Tsw, when the switching frequency Fsw is lowered (the switching cycle Tsw is lengthened), the difference {e (current) -e (previous)} is likely to increase, while the switching frequency Fsw is increased. When the switching period Tsw is shortened, the difference tends to be small. According to the present embodiment, the coefficient Kd is reduced as the switching frequency Fsw is lower, and the coefficient Kd is increased as the switching frequency Fsw is higher. Therefore, it is possible to equalize the influence caused by the change in the difference. , The influence of changing the switching frequency Fsw can be reduced.

  In the present embodiment, the first order lag correction coefficients Kf_V2 and Kf_V1 are increased as the switching frequency Fsw is lower, and the first order lag correction coefficients Kf_V2 and Kf_V1 are decreased as the switching frequency Fsw is higher. In general first-order lag processing, the previous measured value is added to the difference between the current sensor output value and the previous measured value (the value after correcting the sensor output value) multiplied by the first-order lag correction coefficient. The sum is taken as the current measurement value. Also in the present embodiment, in the V2 control mode, the difference between the digital secondary voltage V2dig (current) and the secondary voltage V2 (current) is multiplied by the primary delay correction coefficient Kf_V2, and the secondary voltage V2 (current) is applied. The added sum is the secondary voltage V2 (current). The same applies to the V1 control mode. When the period of the primary delay processing (control period Tc) is changed according to the switching period Tsw, the lower the switching frequency Fsw (the longer the switching period Tsw), the longer the addition period and the larger the time constant. The effect of the delay is greater. On the other hand, the higher the switching frequency Fsw (the shorter the switching period Tsw), the shorter the period of addition and the smaller the time constant, so the influence of the first-order lag becomes smaller. According to the present embodiment, the higher the switching frequency Fsw, the smaller the first order lag correction coefficients Kf_V2 and Kf_V1, and the lower the switching frequency Fsw, the larger the first order lag correction coefficients Kf_V2 and Kf_V1. It is possible to reduce the influence of changing the switching frequency Fsw.

  In the present embodiment, the higher the switching frequency Fsw, the lower the upper limit values Cmax_V2, Cmax_V1 and the lower limit values Cmin_V2, Cmin_V1 used in the change amount limiting process. Increase In the change amount limiting process for the target voltage and target current, at least one of the upper limit value and the lower limit value of the allowable change amount is set, and when the change amount of the control command value from the host system exceeds the upper limit value or the lower limit value, The upper limit value or the lower limit value is set as the maximum change width used in the actual calculation.

  For example, also in the change amount limiting process in the V2 control mode of the present embodiment, the upper limit value Cmax_V2 and the lower limit value Cmin_V2 of the allowable change amount are set, and the secondary voltage command value V2com (current) and the secondary value from the overall control unit 56 are set. When the difference Dt_V2 between the voltage target value V2tar (previous) exceeds the upper limit value Cmax_V2 and the lower limit value Cmin_V2, the upper limit value Cmax_V2 and the lower limit value Cmin_V2 are set as the maximum change width used in the actual calculation. In the case where the change amount limiting process cycle (control cycle Tc) is changed in accordance with the switching cycle Tsw, if the upper limit value Cmax_V2 and the lower limit value Cmin_V2 of the change amount are constant, the higher the switching frequency Fsw (the shorter the switching cycle Tsw). ) It is possible to increase the change rate of the change amount of the secondary voltage target value V2tar. On the other hand, the lower the switching frequency Fsw (the longer the switching period Tsw), the lower the change rate of the change amount of the secondary voltage target value V2tar. According to the present embodiment, as the switching frequency Fsw is higher, the upper limit value Cmax_V2 and the lower limit value Cmin_V2 are reduced, and the range in which the allowable change amount can be reduced. Therefore, the possible change rate of the change amount of the secondary voltage target value V2tar is set small. On the other hand, as the switching frequency Fsw is lower, the upper limit value Cmax_V2 and the lower limit value Cmin_V2 are increased, and the range in which the allowable change amount can be increased. For this reason, the possible change rate of the change amount of the secondary voltage target value V2tar is set large. As a result, it is possible to equalize the possible change rate of the change amount of the secondary voltage target value V2tar, and to reduce the influence caused by the change of the switching frequency Fsw. The same can be said for the V1 control mode.

B. Modifications It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various configurations can be adopted based on the contents described in this specification. For example, the following configurations 1 to 5 can be employed.

1. In the above embodiment, the vehicle power system 20 is mounted on the fuel cell vehicle, but the present invention is not limited to this. For example, it can be applied to a battery-driven vehicle (electric vehicle). Of course, the present invention can also be applied to a so-called parallel or series-parallel hybrid vehicle equipped with an engine, a battery, and a motor.

2. Phase arm UA, VA, WA
In the above-described embodiment, the three-phase phase arms UA, VA, and WA are used, but a single-phase, two-phase, or four-phase or more may be used.

3. Switching Control In the above embodiment, synchronous switching is used in which each switching cycle Tsw includes both switching of the upper arm elements 81u to 81w (step-down chopper control) and switching of the lower arm elements 82u to 82w (step-up chopper control). However, the present invention is not limited to this, and the present invention can be applied to only one of the step-down chopper control and the step-up chopper control.

  In the above embodiment, the configuration using the PWM method and the PFM method by switching is adopted, but the present invention can also be applied to a configuration using only the PFM method.

4). Weighting according to switching frequency Fsw In the above formula (1), formula (2), formula (4), formula (9), formula (10) and formula (12), the relationship between the switching frequency Fsw and the reference switching frequency Fswr , And the relationship between the switching cycle Tsw and the reference switching cycle Tswr (reference value of the switching cycle Tsw), the relationship between the control cycle Tc and the reference control cycle Tcr (reference value of the control cycle Tc), Weighting can also be performed using the relationship between the control frequency Fc (the number of control processes per second) and the reference control frequency Fcr (reference value of the control frequency Fc).

  In the above-described embodiment, the change amount limiting process, the first-order lag correction process, and the PID process are given as the weighting process. However, in the calculation process performed in the switching cycle Tsw (the calculation processing cycle that changes according to the switching frequency Fsw). If there is, it is not limited to this.

  In the above embodiment, the change amount limiting process is performed on the command value (secondary voltage command value V2com, primary voltage command value V1com) from the overall control unit 56, but is not limited thereto. For example, another change limiting unit may be provided between the calculation point 146 and the signal modulation processing unit 136 in FIG. 8, and the change amount limiting process may be performed on the duty DUT.

5. Others In the above embodiment, the configuration using the V2 control mode and the V1 control mode has been described with reference to FIGS. 8 to 10. However, the present invention is not limited to this, and for example, the same processing can be used in the I1 control mode. .

  In the above embodiment, 1 to 3 control cycles Tc correspond to the timer set value calculation processing cycle Tcal, but the present invention is not limited to this. For example, one timer set value calculation processing cycle Tcal can always be associated with one control cycle Tc.

1 is a circuit diagram of a vehicle power system capable of executing an operation control method for a DC / DC converter device according to an embodiment of the present invention. It is explanatory drawing of the basic control of the electric power system mounted in the fuel cell vehicle. It is explanatory drawing of the current-voltage characteristic of a fuel cell. It is a time chart used for operation | movement description of the pressure | voltage fall operation of a DC / DC converter. It is a time chart used for operation | movement description of the pressure | voltage rise operation of a DC / DC converter. It is a 1st time chart which shows the calculation process period in a converter control part, and the relationship of the production | generation of a drive signal. It is a 2nd time chart which shows the relationship between the calculation process period in a converter control part, and the production | generation of a drive signal. It is a functional block diagram of the converter control part for calculating a duty in V2 control mode. It is a flow chart of change amount restriction processing in V2 control mode. It is a functional block diagram of the converter control part for calculating a duty in V1 control mode.

Explanation of symbols

20 ... Electric power system 22 ... Fuel cell (second electric power device)
23 ... DC / DC converter unit (VCU)
24 ... Battery (first power device) 26 ... Motor (second power device)
34 ... Inverter 36 ... DC / DC converter 54 ... Converter control part 81 (81u-81w) ... Upper arm element 82 (82u-82w) ... Lower arm element 83u-83w, 84u-84w ... Diode 90 ... Reactor Cmax_v2 ... Allowable change Upper limit value (allowable change amount setting coefficient)
Cmin_v2 ... lower limit of allowable change (allowable change setting coefficient)
DUT ... Duty Fsw ... Switching frequency Kd ... D-term coefficient Kf_V2 ... First-order lag correction coefficient Ki ... I-term coefficient T1 ... Upper arm element drive time T2 ... Lower arm element drive time Tc ... Control cycle Tsw ... Switching cycle UA ... U Phase arm VA ... V phase arm WA ... W phase arm UH, UL, VH, VL, WH, WL ... Drive signal

Claims (5)

An operation control method of a DC / DC converter device for driving a switching element by a drive signal generated using pulse frequency modulation (PFM),
A coefficient used in arithmetic processing related to driving of the switching element is weighted according to an arithmetic processing cycle that is a cycle in which the arithmetic processing is performed and changes corresponding to the switching cycle. Operation control method. In the operation control method of the DC / DC converter device according to claim 1,
The coefficient is a coefficient of an integral term (I term) used in an integral control process used to calculate the duty of the drive signal,
A method for controlling an operation of a DC / DC converter device, wherein the higher the switching frequency, the smaller the coefficient of the I term, and the lower the switching frequency, the larger the coefficient of the I term. The operation control method for a DC / DC converter device according to claim 1 or 2,
The coefficient is a coefficient of a differential term (D term) used in differential control processing used for calculating the duty of the drive signal,
A method for controlling an operation of a DC / DC converter device, wherein the lower the switching frequency, the smaller the coefficient of the D term, and the higher the switching frequency, the larger the coefficient of the D term. In the operation control method of the DC / DC converter device according to any one of claims 1 to 3,
The coefficient is a first-order lag correction coefficient used in a first-order lag process for an output value of a sensor that detects a state of a power system equipped with the DC / DC converter device,
The operation control method for a DC / DC converter device, wherein the first-order lag correction coefficient is increased as the switching frequency is lower, and the first-order lag correction coefficient is decreased as the switching frequency is higher. In the operation control method of the DC / DC converter device according to any one of claims 1 to 4,
The coefficient includes an allowable change amount setting coefficient of a change amount limiting process for a target voltage or target current used in a power system equipped with the DC / DC converter device,
An operation control method for a DC / DC converter device, wherein the allowable change amount setting coefficient is decreased as the switching frequency is higher, and the allowable change amount setting coefficient is increased as the switching frequency is lower.

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