JP4804503B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an array division configuration in which a memory array is divided into a plurality of memory blocks. More specifically, the present invention relates to a redundant circuit for repairing a defective memory cell in a semiconductor memory device having an array division configuration and a configuration of a power supply circuit provided corresponding to each block.

  In a semiconductor memory device, if a defective memory cell exists, it is replaced with a spare memory cell, so that the defective memory cell is equivalently relieved and the product yield is improved. In a redundant circuit configuration in which spare memory cells (spare word lines and spare bit lines) for repairing such defective memory cells are provided, a spare decoder for selecting spare lines (word lines or bit lines) and spare lines is selected. In order to improve utilization efficiency, flexible redundancy techniques have been proposed (for example, Non-Patent Document 1 (Horiguchi et al., “Flexible Redundancy Techniques for High-Density DRAMs”, 1991 IEEE, Journal of Solids). (See State Circuits, Vol. 20, No. 1, January 1991, pp. 12-17)).

  FIG. 53 schematically shows an entire configuration of a semiconductor memory device having a conventional flexible redundancy configuration. 53, this semiconductor memory device includes four memory arrays MA0-MA3. In each of memory arrays MA0-MA3, spare word lines for repairing defective memory cell rows are arranged. Spare word lines SW00 and SW01 are arranged in memory array MA0, and spare word lines SW10 and SW11 are arranged in memory array MA1. Spare word lines SW20 and SW21 are arranged in memory array MA2, and spare word lines SW30 and SW31 are arranged in memory array MA3.

  Corresponding to each of memory arrays MA0-MA3, row decoders X0-X3 are arranged for decoding row address signals and driving normal word lines arranged corresponding to the addressed row to a selected state. The A column decoder Y0 is arranged between memory arrays MA0 and MA1 to decode the column address signal and select this addressed column, and column data Y1 is arranged between memory arrays MA2 and MA3. Is done.

  The semiconductor memory device further stores a row address where a defective memory cell exists, and when the defective row address is addressed, a word line (defective normal word line) corresponding to the defective row address is not selected. And the spare decoders SD0 to SD3 for driving the corresponding spare word line to the selected state, the OR circuit G0 receiving the output signals of the spare decoders SD0 and SD1, and the OR receiving the output signals of the spare decoders SD2 and SD3 A circuit G1 is included.

  Output signals of OR circuits G0 and G1 are applied in common to spare word line drive circuits included in row decoders X0 to X3, respectively. Spare decoders SD0 to SD3 have array address signal bits an-2 and an-1 designating one of memory arrays MA0 to MA3 and in-array address signal bits a0-an- designating a row in the memory array, respectively. 3 is given in common. Row decoders X0-X3 are provided with array address signal bits an-2 and an-1, and the row decoder is activated when the corresponding memory array is addressed. OR circuits G0 and G1 correspond to two spare word lines provided in memory arrays MA0 to MA3, respectively.

  Consider a case where normal word lines W0 and W1 are defective in memory array MA0, normal word line W2 in memory array MA1 is defective, and normal word line W3 in memory array MA2 is defective. In this state, the address of word line W0 is programmed in spare decoder SD0, and the address of word line W1 is programmed in spare decoder SD2. The address of normal word line W2 is programmed in spare decoder SD3, and the address of normal word line W3 is programmed in spare decoder SD1.

  The OR circuit G0 specifies any one of the spare word lines SW00, SW10, SW20, and SW30, and the output signal from the OR circuit G1 selects any one of the spare word lines SW01, SW11, SW21, and SW31.

  When normal word line W0 is designated, the output signal of spare decoder SD0 is driven to the selected state, and the output signal of OR circuit G0 is activated. In this state, row decoder X0 is activated by array address signal bits an-2 and an-1, and the remaining row decoders X1-X3 maintain an inactive state. Therefore, the word line drive circuit included in row decoder X0 drives spare word line SW00 to the selected state in accordance with the output signal of OR circuit G0. At this time, in the row decoder X0, the decode circuit provided corresponding to the normal word line W0 is maintained in an inactive state. Therefore, defective normal word line W0 is replaced with spare word line SW00.

  When defective normal word line W1 is addressed, the output signal of spare decoder SD2 is at the selected H level, the output signal of OR circuit G1 is at the H level, and spare word line SW01 is selected. When the defective normal word line W2 is addressed, the output signal of the spare decoder SD3 becomes the selected H level, the output signal of the OR circuit G1 becomes the H level, and the spare word line SW11 is selected. When defective normal word line W3 is addressed, the output signal of spare decoder SD1 attains the selected H level, and accordingly, spare word line SW20 is selected by OR circuit G0. That is, defective normal word lines W0, W1, W2, and W3 are replaced with spare word lines SW00, SW01, SW11, and SW20, respectively.

In the flexible redundancy configuration shown in FIG. 53, one spare word line can be activated by any of a plurality of spare decoders. For example, spare word line SW20 can be driven to a selected state by spare decoder SD0 or SD1. One spare decoder can drive any one of a plurality of spare word lines to a selected state. For example, spare decoder SD0 can drive any one of spare word lines SW00, SW10, SW20 and SW30 to a selected state. Therefore, the correspondence relationship between the spare word line and the spare decoder is not 1: 1, and the utilization efficiency of the spare word line and the spare decoder can be improved. In addition, the number of spare word lines and the number of spare row decoders in one memory array can be selected independently from each other as long as the following relationship is satisfied:
L ≦ R ≦ M · L / m
Here, M represents the number of physical memory arrays, m represents the number of memory arrays in which defective normal word lines are simultaneously replaced with spare word lines, R represents the number of spare row decoders, L indicates the number of spare word lines in one memory array. That is, M / m indicates the number of memory arrays that are logically independent of each other. Therefore, M · L / m indicates the number of spare word lines logically independent of each other as the entire memory. Here, the logically independent spare word line indicates a spare word line selected by a different row address. For example, in FIG. 53, when normal word lines are simultaneously selected in memory arrays MA0 and MA2, memory arrays MA0 and MA2 are not logically independent. In the configuration shown in FIG. 53, L = 2, R = 4, M = 4, and m = 1.

  By providing the spare row decoder in common in the memory array, it is not necessary to provide a spare decoder corresponding to each spare word line, and an increase in the chip occupation area is suppressed.

  The flexible redundancy configuration shown in FIG. 53 can be applied to defective column relief at the same time. In this defective column relief, the above-mentioned document describes a defective column relief method when the memory array is divided into a plurality of subarrays. In particular, the above-mentioned documents describe multi-divided bit lines having a shared sense amplifier configuration and defective column relief in the shared I / O system.

  FIG. 54 schematically shows a configuration of an array section of a conventional flexible redundancy type semiconductor memory device. In FIG. 54, two memory blocks MBi and MBi + 1 are shown. Memory blocks MBi and MBi + 1 each include a normal bit line pair BL and / BL arranged corresponding to a memory cell column, and a spare bit line (spare column) for repairing a defective column. In FIG. 54, the spare bit lines included in the spare column are not clearly shown.

  Normal bit lines BL and / BL having the same column address in memory blocks MBi and MBi + 1 share sense amplifier SA. A bit line isolation gate ILG is arranged between sense amplifier SA and memory blocks MBi and MBi + 1. Sense amplifier SA is connected to internal data line pair I / O through IO gate IOG which is turned on in accordance with column selection signal YS from column decoder Y. A memory block (for example, MBi) including the selected memory cell is connected to sense amplifier SA to read data. In this case, the non-selected memory block (MBi + 1) is disconnected from the sense amplifier SA.

  In the shared sense amplifier configuration as described above, it is necessary to program a defective column address for each of a normal bit line defect, a column selection line (YS line) defect, and a sense amplifier SA defect in one memory block. . When the normal bit line is defective, the defective column address is programmed in units of memory blocks. In the case of a sense amplifier failure, a defective column address is programmed to use a spare column for each of memory blocks MBi and MBi + 1 sharing the defective sense amplifier. If the column selection line (YS line) is defective, the defective column address is programmed for each memory block connected to the column selection line (YS line).

In this programming, “don't care” is programmed at the time of defective column address programming in order to deal with each of normal bit line defects, sense amplifier defects and column selection line (YS line) defects with a single spare column decoder. An address for specifying a block is set to an invalid state, and a spare column is simultaneously replaced in a plurality of memory blocks in the case of a sense amplifier failure or a column selection line failure.
JP-A-6-232348 Horiguchi et al., “Flexible Redundancy Techniques for High-Density DRAMs”, 1991 IEEE, Journal of Solid State Circuits, Vol. 20, No. 1, January 1991, pp. 12-17

  In the above-mentioned prior art documents, the defective row is relieved by replacement with a spare word line arranged in the memory array including the defective row. Therefore, it is necessary to arrange a spare word line in each memory array, and there is a problem that the use efficiency of the spare word line is poor. Further, if a defective normal word line of a certain memory array is replaced with a spare word line of another memory array, the control of the memory array system circuit becomes complicated, so that it is not considered at all.

  Also in the defective column remedy, a spare column is provided for each memory block, and the problem of poor use efficiency of the spare column also occurs. In addition, although a shared I / O system is considered as an internal data line, the defective column remedy in a memory array having a local / global hierarchical data line structure used in a block division configuration in recent years is not considered.

  On the other hand, in a conventional CMOS (complementary MOS) type semiconductor device, the size of an element (MOS transistor: insulated gate field effect transistor) is reduced for high density and high integration. In order to ensure the reliability of such miniaturized elements and reduce the current consumption of the entire device, the power supply voltage is lowered. In order to operate the device at high speed, it is necessary to lower the threshold voltage of the MOS transistor in accordance with the power supply voltage. This is because if the ratio of the threshold voltage to the power supply voltage is high, the transition timing of the MOS transistor to the on state is delayed. However, when the absolute value of the threshold voltage is lowered, the subthreshold leakage current flowing between the source and the drain when the MOS transistor is off increases. This is due to the following reason. The threshold voltage is defined as a gate-source voltage that allows a constant drain current to flow. In the case of an n-channel MOS transistor, when the threshold voltage is lowered, the drain current-gate voltage characteristic curve moves in the negative direction. Since the subthreshold current is indicated by a current value when the gate voltage Vgs in the characteristic curve is 0 V, the subthreshold current increases when the threshold voltage is lowered.

  When the semiconductor device operates, the ambient temperature increases, the absolute value of the threshold voltage of the MOS transistor decreases, and the problem of this subthreshold leakage current becomes more serious. When this subthreshold leakage current increases, the direct current of the entire large-scale integrated circuit increases. In particular, in a dynamic semiconductor memory device, standby current (current consumed in the standby state) is increased.

  A multi-threshold CMOS configuration is used to reduce the subthreshold leakage current as described above.

  FIG. 55 is a diagram for explaining an example of a conventional multi-threshold CMOS structure. 55, main power supply line 902 for transmitting power supply voltage Vcc, sub power supply line 904 coupled to main power supply line 902 through p-channel MOS transistor 903, and main ground line 906 for transmitting ground voltage Vss. A sub-ground line 908 coupled to main ground line 906 via n-channel MOS transistor 907 is provided. MOS transistor 903 is conductive when activation signal / φACT is at L level, and MOS transistor 907 is conductive when activation signal φACT is at H level. These MOS transistors 903 and 907 have a relatively high threshold voltage (high Vth). The internal circuit operates using one voltage of power supply lines 902 and 904 and one voltage of ground lines 906 and 908 as both operation power supply voltages. In FIG. 55, three stages of cascaded inverter circuits 914a, 914b and 914c are shown as internal circuits. Inverter circuit 914a includes a p-channel MOS transistor PQ3 whose source is coupled to main power supply line 902, and an n-channel MOS transistor NQ whose source is coupled to sub-ground line 908. Input signal IN is commonly applied to the gates of these MOS transistors PQ and NQ. This input signal IN is set to L level during the standby cycle.

  Inverter circuit 914b operates using the voltages on sub power supply line 904 and main ground line 906 as both operation power supply voltages. Inverter circuit 914c operates using the voltages on main power supply line 902 and sub-ground line 908 as both operation power supply voltages. In these inverter circuits 914a to 914c, MOS transistors PQ and NQ have sufficiently small absolute values of threshold voltages (low Vth). Next, the operation of the configuration shown in FIG. 55 will be described with reference to FIG.

  In the standby cycle, input signal IN is set to L level. Control signal φACT is at L level, and control signal / φACT is at H level (Vcc level). In inverter circuit 914b, MOS transistor PQ is turned on, its source and drain are at the same voltage level, and no current flows. On the other hand, MOS transistor NQ receives input signal IN at the ground voltage level at its gate, and is off. However, MOS transistor 907 is in the off state, and the subthreshold leakage current flowing through MOS transistor 907 is sufficiently reduced because the threshold voltage is high. Therefore, even if the threshold voltage of MOS transistor NQ is small, the subthreshold current is reduced. Also, the sub-threshold current flowing through MOS transistor 907 causes the voltage level on sub-ground line 908 to be higher than the ground voltage level, and the gate-source between MOS transistor NQ of inverter circuit 914a is set in a reverse bias state. The subthreshold current is further reduced.

  In inverter circuit 914b, the input signal is at H level, MOS transistor NQ is turned on, its source and drain are at the same voltage level, and no subthreshold leakage current occurs. On the other hand, p channel MOS transistor PQ receives a signal at power supply voltage Vcc level and causes a subthreshold leak current to flow through its gate. However, since the MOS transistor 903 is in an off state and the MOS transistor 903 is a high Vth transistor, the subthreshold leakage current is sufficiently suppressed. Thereby, the subthreshold leakage current in the inverter circuit 914b is suppressed. Further, the sub-threshold leakage current of the MOS transistor 903 causes the voltage level of the sub power supply line 904 to be lower than the power supply voltage Vcc, and the inverter circuit 914b is reverse-biased between the gate and the source of the MOS transistor PQ. Subthreshold leakage is further suppressed. Also in the inverter circuit 914c, the subthreshold leakage current is suppressed as in the inverter circuit 914a.

  When the active cycle starts, control signal φACT becomes H level, control signal / φACT becomes L level, MOS transistors 903 and 907 are turned on, sub power supply line 904 is coupled to main power supply line 902, and sub ground line 908 is coupled to main ground line 906. Therefore, these inverter circuits 914a to 914c are supplied with current from the corresponding power supply line / ground line, the low Vth transistor operates at high speed, and changes its output signal in accordance with the change of the input signal IN.

  In the power supply circuit configuration as shown in FIG. 55, since the logic level of the current signal in the standby cycle is known in advance, the connection path to the power supply line is determined. When the logical state of the input signal IN during the standby cycle is indefinite, it is coupled to the sub power supply line 904 and the sub ground line 908.

  As disclosed in Japanese Patent Laid-Open No. 6-232348, a DRAM (dynamic random access memory) is provided with circuits having the same circuit configuration such as a decode circuit and a word line drive circuit. It is done. As the storage capacity increases, the number of these circuits increases significantly. In such a repeating circuit such as a decoding circuit and a word drive circuit, a predetermined number of specific circuits (addressed circuits) are selected and driven from circuits having the same format in accordance with an address signal. When these circuits are formed of low Vth transistors, a power supply circuit configuration (hierarchical power supply configuration: subthreshold leakage current reduction circuit) as shown in FIG. 55 can be used. In this case, as shown in FIG. 53, it is necessary to control the activation / inactivation of the power supply for the decoder or word driver for each block (because the word line is selected in units of blocks). Control signals φACT and / φACT are activated when an active cycle starts. Therefore, when the number of circuits connected to sub power supply line 904 or sub ground line 908 increases and the parasitic capacitance increases, sub power supply line 904 and sub ground line 908 are set to predetermined voltage (power supply voltage Vcc and ground voltage Vss) levels. It takes a long time to drive until the operation start timing of the internal circuit is delayed until these voltages are stabilized, which causes a problem that high-speed access cannot be performed.

  Further, as described above, when a defective row / column is relieved using a spare decoder, a row / column to be selected is determined after determining whether a spare is used / not used. In this case, as shown in FIG. 53, when redundant replacement is performed in the same block, a corresponding power supply circuit (a circuit that transmits either the power supply voltage or the ground voltage) is selected according to the address signal. Thus, the connection can be controlled. However, in a flexible redundancy configuration, when a spare row / column is used to repair a defective cell of another memory block, it is necessary to specify a memory block including a memory cell to be driven to a selected state according to a spare determination result. Therefore, there is a problem that the power supply voltage (power supply voltage and ground voltage) cannot be driven to a stable state at high speed, and high-speed access cannot be realized.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device having an array division structure provided with a redundant circuit in which the use efficiency of spare lines (spare word lines and spare bit line pairs) is greatly improved.

  Another object of the present invention is to provide a semiconductor memory device having an array division structure provided with a redundant circuit capable of accurately relieving a defective normal line without causing a malfunction.

  Still another object of the present invention is to provide a semiconductor memory device having an array division structure including a power supply circuit that does not increase access time and current consumption.

  Still another object of the present invention is to provide a semiconductor memory device having an array division structure including a redundant circuit with improved spare line use efficiency and a power supply circuit capable of reducing access time and power consumption.

In summary, the semiconductor memory device according to the present invention arranges spare lines together as one array, provides a plurality of memory mats corresponding to the spare arrays, and sets the defective normal lines of the plurality of memory mats to the corresponding ones. The spare line of the spare array can be replaced .

In one embodiment, a semiconductor memory device according to the present invention includes a plurality of first memory blocks each having a plurality of memory cells arranged in a matrix, and a specific first of the plurality of first memory blocks. A plurality of spare memory cells arranged in a matrix in one memory block. Each row of spare memory cells can be replaced with a defective row of a plurality of first memory blocks.

Et al., Allowed arranged alternately with a plurality of first memory blocks in the column direction, each of the plurality of second memory blocks having a plurality of memory cells arranged in rows and columns, a plurality second A plurality of spare memory cells are provided which are arranged in a matrix in a specific second memory block of the memory block and each row can be replaced with a defective row of the plurality of second memory blocks.

Et al., Allowed to shared memory blocks adjacent in the arranged and the column direction between each of the plurality of first memory blocks each and a plurality of second memory blocks, the memory containing activated when the selected memory cell A plurality of sense amplifier bands are provided for detecting and amplifying data in each column of the block.

  By providing a spare array dedicated to the spare line, the spare line can be shared by a plurality of memory blocks or sub-arrays, and the use efficiency of the spare line can be improved compared to the case where a spare line is arranged in each memory block or sub-array. It can be greatly improved.

According to the present invention, spare memory cells are arranged in a matrix in a specific first memory block of a plurality of first memory blocks, and a defective row and a spare memory cell row of the plurality of first memory blocks are replaced. Since it is configured as possible, the utilization efficiency of the spare row can be improved, and the utilization efficiency of the spare row decoder can be improved.

The second memory block is alternately arranged with the first memory block, the spare memory cells are arranged in a matrix in the specific second memory block, and the spare row of the second memory block is divided into a plurality of second memory blocks. By configuring so that any defective row in the memory block can be replaced, the utilization efficiency of the spare row decoder and the spare row can be improved.

Further, by arranging the first and second memory blocks alternately, even when the first and second memory blocks each select a row, the spare row and the normal row are simultaneously stored in one memory block. In this case, it is possible to prevent the state driven to the selected state simultaneously.

In addition, by arranging the sense amplifier between the memory blocks, the use efficiency of the sense amplifier is improved, and the memory blocks sharing the sense amplifier are included in different memory block groups. It is possible to prevent a state in which a defective normal word line of a memory block paired with one spare row of a block is repaired, and to perform repair by replacing a defective normal row with accuracy.

Further, two memory arrays having a first memory block, a second memory block, and a spare array are provided, and in the normal operation mode, one memory block is selected from the first and second memory arrays, and a specific operation mode is selected. Sometimes, by driving a predetermined number of memory blocks from each of the first and second memory arrays to the selected state at the same time, it is possible to prevent the normal row and spare row from being simultaneously driven to the selected state in one memory block. And a predetermined operation mode can be performed accurately.

[Embodiment 1]
FIG. 1 schematically shows a structure of an array portion of the semiconductor memory device according to the first embodiment of the present invention. In FIG. 1, the memory array is divided into a plurality of sense amplifier blocks (row blocks) RB # 0 to RB # m. These row blocks RB # 0 to RB # m each share a word line. Each of row blocks RB # 0-RB # m is divided into a plurality of subarrays. Row block RB # i (i = 0 to m) is divided into normal sub-arrays MB # i0 to MB # in. These normal subarrays MB # i0-MB # in have a plurality of memory cells arranged in a matrix and share a word line (row). Sense operation is performed in units of sense amplifier blocks.

  In each of row blocks RB # 0-RB # m, spare array SP # 0 is used to repair defective columns (columns including defective normal memory cells) of corresponding row blocks RB # 0-RB # m by replacement. To SP # m are provided. Each of these spare arrays SP # 0-SP # m has memory cells (spare memory cells) arranged in a plurality of columns (the number of rows of spare arrays SP # 0-SP # m is included in the normal sub-array). The same as the number of rows of memory cells).

  Normal local data buses LIO00 to LIOmn are provided corresponding to normal subarrays MB # 00 to MB # mn, respectively. Normal local data buses LIO00 to LIOmn transmit / receive data only to corresponding normal sub-arrays MB # 00 to MB # mn.

  Normal subarrays arranged in alignment along the column direction form column blocks CB # 0 to CB # n. Spare local data buses SIO0-SIOm are also provided for spare arrays SP # 0-SP # m, respectively. These spare local data buses SIO0 to SIOm exchange data only with corresponding spare arrays SP # 0 to SP # m. Normal global data buses NGIO0 to NGIOn are arranged corresponding to normal subarrays arranged in the column direction, that is, column blocks CB # 0 to CB # n. These normal global data buses NGIO0 to NGIOn are coupled to normal local data buses provided for the normal subarrays of the corresponding column blocks via block selection gates BSG, respectively. Block selection gate BSG is turned on in response to a corresponding block selection signal when a corresponding row block is selected, and connects a corresponding normal local data bus and a corresponding normal global data bus. Spare local data buses SIO0 to SIOm are also coupled to spare global data bus SGIO through corresponding block selection gates BSG, respectively. Block select gates BSG provided in spare arrays SP # 0-SP # m are rendered conductive when the corresponding row block is selected, and connect the corresponding spare local data bus to spare global data bus SGIO.

  By providing spare array SP # i in common to a plurality of normal subarrays MB # i0-MB # in in row block RB # i, spare columns included in spare array SP # i are replaced with normal subarrays MB # i0-MB #. In use, the use efficiency of the spare column is improved.

  Further, when a spare column is provided for each normal subarray, if there are more defective columns than the spare columns provided there in the normal subarray, the semiconductor memory device cannot be relieved. However, as shown in FIG. 1, by providing a spare array and arranging spare columns collectively, even if there is a normal sub-array having many defective columns, the spare column of the corresponding spare array is used. Thus, the product can be saved by replacement, and the product yield can be improved.

  FIG. 2A is a diagram illustrating an example of correspondence of defective normal column relief. In FIG. 2A, each of spare arrays SP # 0-SP # m includes four spare bit line pairs (spare columns) SBL0-SBL3.

  Column decode circuits Y0-Yn are provided corresponding to column blocks CB # 0-CB # n, respectively. Spare decode circuit SPD is provided for spare block SP #. From column decode circuits Y0-Yn, a column selection signal is transmitted via column selection line CSL in common to the memory sub-arrays included in the corresponding column block. Spare decode circuit SPD transmits a spare column selection signal via spare column selection lines SCSL0 to SCSL3 provided corresponding to spare bit line pairs SBL0 to SBL3, respectively. Consider now that normal columns (normal bit line pairs) are relieved by replacement independently of each other in normal memory sub-arrays MB # 00-MB # mn.

  FIG. 2B shows an example of the configuration of spare decode circuit SPD shown in FIG. In FIG. 2B, spare decode circuit SPD includes OR circuits OG0-OG3 provided corresponding to spare column select lines SCSL0-SCSL3, respectively. For each of OR circuits OG0-OG3, a spare decoder provided corresponding to each of row blocks RB # 0-RB # m is arranged. Spare decoders SD00 to SD0m are provided for OR circuit OG0, and spare decoders SD30 to SD3m are provided for OR circuit OG3. A defective normal bit line pair in each row block is programmed in a spare decoder provided for each OR circuit.

  As shown in FIG. 2A, normal bit line pair PBL0 of memory sub-array MB # 00 is replaced with spare bit line pair SBL0 of spare array SP # 0, and normal bit line pair of memory sub-array MB # 0n is replaced. PBL1 is replaced with spare bit line pair SBL1 of spare array SP # 0. Further, normal bit line pair PBL2 in memory sub-array MB # 10 is replaced with spare bit line pair SBL0 in spare array SP # 1, and defective normal bit line pair PBL3 included in each of memory sub-arrays MB # m0 and MB # mn. And PBL4 are replaced with spare bit line pairs SBL0 and SBL3 of spare array SP # m. In this case, the address of defective normal bit line pair PBL0 is programmed in spare decoder SB00, and the address of defective normal bit line pair PBL1 is provided corresponding to an OR circuit provided corresponding to spare column selection line CSL1. Programmed into spare decoder. The address of defective normal bit line pair PBL2 is programmed in spare decoder SD01 provided for OR circuit OG0. The addresses of defective normal bit line pairs PBL3 and PBL4 are programmed in spare decoders SD0m and SD3m, respectively. Therefore, when a defective normal bit line pair is addressed, the corresponding spare column selection line is driven to the selected state. At this time, the decoding operation of the column decoding circuits Y0 to Yn is stopped according to the output signals of these OR circuits. That is, by using the spare decode circuit shown in FIG. 2B, it is possible to repair defective normal bit line pairs independently of each other in each of memory sub-arrays MB # 00 to MB # mn.

  In the configuration of the spare decode circuit shown in FIG. 2B, the address of the defective normal bit line pair can be programmed for each row block. Thus, each spare decoder is not required to store a “don't care” state. If the normal column selection line CSL is defective, the same address signal may be programmed in each spare decoder. However, in this case, by providing the spare decoder with a function of storing the “don't care” state, in addition to repairing the defective normal bit line pair for each row block, the defective normal bit line is replaced by replacing the defective normal column selection line. Pair relief can also be performed.

[Example of change]
FIG. 3A shows a structure of a modification of the spare decode circuit shown in FIG. In FIG. 3A, spare decoders are arranged corresponding to column blocks. That is, spare decoders SD00 to SD0n are arranged for OR circuit OG0, and spare decoders SD30 to SD3n are arranged for OR circuit OG3. Spare decoders SD00-SD0n correspond to column block blocks CB # 0-CB # n, respectively, and spare decoders SD30-SD3n also correspond to column blocks CB # 0-CB # n, respectively.

  Consider a case where normal bit line pair PBL0 of memory sub-array MB # 00 is defective and column select line CSL from column decode circuit Yn is defective as shown in FIG. 3B. In this case, the address of defective normal bit line pair PBL0 is programmed in spare decoder SD00, and the address of normal column selection line CSL is programmed in spare decoder SD3n. At the time of programming of defective normal column selection line CSL, spare decoder SD3n disables the column block designation bit and selects any defective column of memory sub-arrays MB # 0n to MB # mn of column block CB # n. Even if the normal bit line pair corresponding to line CSL is addressed, the output signal of spare decoder SD3n indicates the selected state.

  In this case, defective normal bit line pair PBL0 is replaced by spare bit line pair SBL0 of spare array SP # 0, and defective normal column selection line CSL from column decode circuit Yn is replaced by spare column selection line SCSL3.

  In the configuration shown in FIG. 1, one memory sub-array is selected and connected to the corresponding normal global data bus. Therefore, 1-bit data is input / output.

  FIG. 4 schematically shows a configuration of the data reading unit. In FIG. 4, main amplifiers MAP0 to MAPn are provided corresponding to normal global data buses NGIO0 to NGIOn, respectively, and spare main amplifiers MAPs are provided corresponding to spare global data bus SGIO. Main amplifiers MAP0 to MAPn are selectively activated in response to activation of main amplifier activation signals PAE0 to PAEn, and spare main amplifier MAPs is activated in response to spare main amplifier activation signal PAEs. . When spare main amplifier activation signal PAEs is activated, all main amplifier activation signals PAE0 to PAEn are held in an inactive state. Thereby, 1-bit data can be accurately read at the time of repair by replacing defective bits. For data writing, a write driver may be provided instead of the main amplifier.

  Spare main amplifier PAEs is activated when any of the output signals of OR circuits OG0-OG3 becomes H level.

  In the configuration of the reading unit shown in FIG. 4, normal global data buses NGIO0 to NGIOn are connected to normal local data buses provided corresponding to the selected row block, respectively. However, since only one of column decode circuits Y0-Yn transmits a column selection signal activated on a column selection line, only one of these normal global data buses NGIO0-NGIOn is connected to the selected memory cell. Data is transmitted (when a normal memory cell is accessed).

  In the configuration in which all the memory subarrays are selected in the selected row block, each spare array is provided with a spare local data bus corresponding to each spare subbit line pair and corresponding to the plurality of spare local data buses. This can be dealt with by providing a spare global data bus. Spare decoders SD00 to SD3n having the configuration shown in FIG. 3A are used to selectively activate one of the main amplifiers provided corresponding to a plurality of spare global data buses. Further, a column block in which a defective normal column is repaired is detected using the output signals of spare decoders SD00 to SD3n, and an output signal of a spare main amplifier is transmitted to the detected column block. This can be realized by using a switch circuit.

  In FIG. 2A and FIG. 3A, a spare decoder is used corresponding to each row block or column block. However, the number of spare decoders may be appropriately determined according to the number of defective normal bit line pairs to be relieved in the entire memory array.

  Further, the number of spare bit line pairs in each of spare arrays SP # 0-SP # m is also appropriately determined. Spare bit line pairs may be provided at a rate of a plurality of lines per column block.

  As described above, according to the first embodiment of the present invention, a spare array is provided for each row block, and any defective normal column of a plurality of subarrays included in the corresponding row block is configured to be relieved. Therefore, defective normal columns can be efficiently relieved in each row block.

  Further, since the spare decoder for selecting a spare column (spare bit line pair) is configured to be shared by a plurality of memory subarrays, it is not necessary to provide a spare decoder corresponding to each memory subarray. The area occupied by the circuit is reduced, and the utilization efficiency of the spare decoder is improved.

[Embodiment 2]
FIG. 5 schematically shows a structure of a memory array portion of the semiconductor memory device according to the second embodiment of the present invention. In the array configuration shown in FIG. 5, block selection gates BSGs provided corresponding to spare arrays SP # 0-SP # m receive signals φso-φsm different from signals φ0-φm for selecting corresponding row blocks. receive. That is, at the time of repairing a defective normal column, a predetermined number of spare local data buses among spare local data buses SIO0 to SIOm are simultaneously connected to spare global data bus SGIO. Other configurations are the same as those shown in FIG. 1, and corresponding portions are denoted by the same reference numerals.

  FIG. 6 is a diagram schematically showing a connection between a normal global data bus, a local data bus, and a spare local data bus during memory access. In FIG. 6, normal global data bus NGIO is connected to local data bus LIOi through block select gate BSG. This block selection gate BSG is turned on in response to a row block selection signal φi. On the other hand, spare global data bus SGIO is connected to spare local data bus SIOi through spare block selection gate BSGs and simultaneously connected to a plurality of spare local data buses. FIG. 6 representatively shows a correspondence in which spare local data bus SIOj is simultaneously connected to spare global data data bus SGIO via block selection gate BSGs.

  In the memory subarray, normal memory cells are arranged in a plurality of rows and a plurality of columns. On the other hand, in the spare array, spare memory cells are arranged in a matrix. However, the number of columns in this spare array is merely provided to relieve a defective column of the normal sub-array in the corresponding row block, and the number of columns is much larger than the number of columns of the normal sub-array. Very few. Therefore, when the parasitic capacitance Ca is connected to the bus line of the local data bus LIOi, the parasitic capacitance Cc smaller than the parasitic capacitance Cc exists on the bus line of the spare local data bus SIOi.

  On the other hand, normal global data bus NGIO and spare global data bus SGIO are arranged extending in the column direction in the memory array, and have substantially the same parasitic capacitance Cb. Therefore, when only one spare local data bus is connected to spare global data bus SGIO, its parasitic capacitance is Cb + Cc. On the other hand, when a normal memory cell is accessed, the parasitic capacitance of the bus line is Ca + Cb. When the spare memory cell is accessed, the signal changes at a faster timing than when the normal memory cell is accessed because the parasitic capacitance of the bus is small. Therefore, since the signal propagation delay is different between the normal memory cell access and the spare column selection, the internal signal change timing is different, and internal timing mismatch and malfunction may occur. In particular, when a plurality of memory arrays shown in FIG. 5 are provided and a plurality of bits of data are input / output, a spare column is selected in one memory array, and a normal column is selected in another memory array. When selected, the data transfer timing is different and the setup / hold time of the internal data is different, so that the circuit operation becomes unstable.

  In the case where the column is sequentially selected in synchronization with the clock signal, it is read out and latched in parallel with the selection data of the other memory array and then alternately read out to the outside. If the transmission time of the data signal is different between when the normal memory cell is selected and when the spare column is selected, it is considered that the setup / hold time with respect to the latch timing is different and accurate data reading cannot be performed.

  Therefore, as shown in FIG. 6, when accessing a defective spare memory cell, a plurality of spare local data buses are simultaneously connected to spare global data bus SGIO. Thereby, the signal propagation delay time is the same when the normal memory cell is selected and when the spare memory cell is accessed.

  The number k of spare local data buses that are simultaneously driven to the selected state is given by the following equation.

Cb + Ca = Cb + k · Cc
Therefore, the following equation is obtained.

Ca = k · Cc
As a result, problems caused by timing mismatch can be avoided.

  Now, as shown in FIG. 7, a case is considered where eight row blocks RB # 0 to RB # 7 are provided. Row blocks RB # 0-RB # 7 are designated by 3-bit address signals ai, aj and ak. The block selection signal φi is generated by decoding these 3-bit address signals ai, aj and ak.

  One of row blocks RB # 0-RB # 3 and row blocks RB # 4-RB # 7 is designated by address signal bit ai, and row blocks RB # 0, RB # 1, RB # 4 and RB One of the group of # 5 and the group of row blocks RB # 2, RB # 3, RB # 6 and RB # 7 is designated by address signal bit aj, and row blocks RB # 0, RB # 2, RB # 4 and Consider a case where a group of RB # 6 and one of groups of row blocks RB # 1, RB # 3, RB # 5 and RB # 7 are designated by address signal bit ak. In this case, the spare array block selection signal φsi can be generated by appropriately setting the address signal bits ai to ak to an invalid state (don't care state). For example, if the address signal bit ak is disabled, two row blocks are designated at the same time, so that two spare local data buses can be connected to the spare global data bus. If the address signal bit aj is disabled, two row blocks can be designated similarly. If both address signal bits aj and ak are disabled, four row blocks can be specified simultaneously. If all the 3-bit address signals ai to ak are disabled, all row blocks can be designated. Therefore, by using these configurations, it is possible to connect a required number (a multiple of 2) of spare local data buses of spare arrays to a spare global data bus.

  FIG. 8 schematically shows a configuration of a spare block column selection unit. FIG. 8 shows a configuration of two spare arrays SP # i and SP # j.

  Referring to FIG. 8, in spare array SP # i, spare column selection gate CSGi for connecting spare bit line pair SBL to spare local data bus SIOi has a column selection signal and a row block designation from a spare column decode circuit (not shown). Conduction is made in response to local column selection signal YSi output from AND circuit SCGi receiving signal φi. In spare array SP # j, spare column selection gate CSGj connecting spare bit line pair SBL and spare local data bus SIOj is connected to a spare column selection signal SCSL transmitted on spare column selection line SCSL from the spare column decode circuit. Conduction is made in response to spare local column selection signal YSj from AND circuit SCGj receiving block selection signal φj. Spare local data buses SIOi... SIOj are connected to spare global data bus SGIO via spare block selection gates BSGs that are turned on in response to block selection signals φsi and φsj, respectively.

  In the configuration shown in FIG. 8, when the spare array is accessed, spare local data buses SIOi... SIOj are coupled in parallel to spare global data bus SGIO. In this state, spare bit line pair SBL of the spare array provided corresponding to the selected row block is connected to the corresponding spare local data bus. Thus, in a configuration in which a spare column selection signal applied from spare column decode circuit to spare column selection line SCSL is applied in common to spare arrays SP # 0-SP # m, a plurality of spare local data buses are simultaneously connected to spare global data. Even when connected to the bus, data access can be performed by accurately selecting a spare column corresponding to the addressed defective column. As a result, it is possible to prevent the spare bit line pair held in the precharged state from being connected to the spare global data bus via the corresponding spare local data bus and destroying the spare memory cell data.

  In the above description, the address signal bits for specifying row blocks are set to a degenerated state (don't care state), and a plurality of spare local data buses are simultaneously connected to the spare global data bus. However, a configuration may be used in which a separate decoding circuit is provided and a pair of spare local data buses selected simultaneously when each row block is designated is determined by the output of this decoding circuit.

  As described above, according to the second embodiment of the present invention, since a plurality of spare local data buses are connected in parallel to the spare global data bus, normal memory cell access and spare memory cell access are performed. The signal propagation delay of the global data bus at the same time can be made the same, the problem caused by the internal timing mismatch can be avoided, and a semiconductor memory device that operates stably can be realized.

[Embodiment 3]
FIG. 9 schematically shows a structure of a main portion of the semiconductor memory device according to the third embodiment of the present invention. In FIG. 9, the memory array is divided into a plurality of row blocks (sense amplifier blocks) RBX # 0 to RBX # m along the column direction. Row blocks RBX # 1 to RBX # m are configured by normal memory sub-arrays MA # 1 to MA # m in which normal memory cells are arranged in a matrix. In row block RBX0, a normal memory sub-array MA # 0 having normal memory cells arranged in a matrix, and a spare having spare memory cells arranged in a plurality of rows in common with the normal memory sub-array MA # 0. Array SPX #. A plurality of spare rows (spare word lines) included in spare array SPX # can be replaced with defective normal word lines included in normal memory sub-arrays MA # 0-MA # m. Row decoders X0 to Xm are provided corresponding to normal memory subarrays MA # 0 to MA # m, respectively, and spare row decode circuit SPDX is arranged for spare array SPX #.

  In the configuration shown in FIG. 9, spare array SPX # is arranged commonly for normal memory subarrays MA # 0 to MA # m. Therefore, even when defective rows are concentrated in one normal memory sub-array, replacement repair can be performed using spare word lines included in spare array SPX #, and the product yield can be improved. Further, the number of spare decoders can be reduced by sharing the spare row decoder among a plurality of normal memory subarrays (row blocks).

  FIG. 10 schematically shows a configuration of spare row decoder circuit SPDX shown in FIG. In FIG. 10, in spare array SPX #, the configuration of spare row decode circuit SPDX in the case where four spare word lines SWL0 to SWL3 are provided is shown as an example. Spare row decode circuit SPDX includes spare row decoders SDX0 to SDX3 provided corresponding to spare word lines SWL0 to SWL3, respectively. These spare row decoders SDX0 to SDX3 are programmed with both a block address specifying a memory sub-array and a row address in the sub-array, respectively. Now, as shown in FIG. 10, defective normal word line WL0 included in normal memory sub-array MA # 0, defective normal word lines WL1 and WL2 included in normal memory sub-array MA # 1, and included in normal memory sub-array MA # m. Consider a case where a defective normal word line WL3 is relieved by replacement with a spare word line. In this case, the address (including the block address) of word line WL0 is programmed in spare row decoder SDX0, the addresses of defective normal word lines WL1 and WL2 are programmed in spare row decoders SDX1 and SDX2, respectively, and spare row decoder SDX3 is programmed. The address of the defective normal word line WL3 is programmed. Therefore, defective normal word lines WL0, WL1, WL2, and WL3 are replaced by spare word lines SWL0, SWL1, SWL2, and SWL3, respectively.

  Therefore, since the spare row decoder is shared by normal memory sub-arrays MA # 0 to MA # m, it is not necessary to provide a spare row decoder corresponding to each normal memory sub-array, and an increase in the area occupied by the array is suppressed. be able to. Spare word lines are shared by normal memory sub-arrays MA # 0 to MA # m, so that the use efficiency of spare word lines is improved.

  Further, by providing spare array SPX # in common to normal memory subarrays MA # 0-MA # m in row block RBX # 0, spare word line SWL included in spare array SPX # can be connected to any normal memory. Subarrays can be used, and the utilization efficiency of spare word lines can be improved.

  In addition, by including spare array SPX # in normal memory sub-array MA # 0, when one of spare decoders SDX0 to SDX3 is selected, a sense amplifier provided for row block RBX # 0 is activated. The configuration only needs to be used, and the control operation of the sense amplifier is simplified.

  In the configuration shown in FIGS. 9 and 10, in row blocks RBX # 0 to RBX # m, one row block is selected and a sensing operation is performed (word line selection is performed).

The number of spare word lines SWL included in spare array SPX # is arbitrary.
As described above, according to the third embodiment of the present invention, spare word lines are collectively provided in one spare array so as to be commonly used for a plurality of normal memory subarrays. The number of decoders is reduced, and the use efficiency of spare word lines is improved.

[Embodiment 4]
FIG. 11 schematically shows a structure of the array portion of the semiconductor memory device according to the fourth embodiment of the present invention. In FIG. 11, normal memory subarrays MA # 0-0 to MA # 0-N and normal memory subarrays MA # 0-0 to MA # 0-N are arranged alternately in the column direction. Subarrays MA # 1-0 to MA # 1-N are included. For normal memory sub-array MA # 0-0, spare array SPX # 0 having a predetermined number of spare word lines SWL is arranged to form one row block (sense amplifier block) RBX # 0, and normal memory In sub-array MA # 1-N, spare array SPX # 1 in which a predetermined number of spare word lines SWL are arranged is provided, and row block RBX # 1 is configured. Normal memory subarrays MA # 0-0 to MA # 0-N and MA # 1-0 to MA # 1-N each have normal memory cells arranged in a matrix.

  Sense amplifier bands SAB1 to SABm are arranged between memory subarrays adjacent in the column direction. Sense amplifier band SAB0 is arranged outside normal memory subarray MA # 0-0, and sense amplifier band SABm + 1 is arranged adjacent to normal memory subarray MA # 1-N.

  These sense amplifier bands SAB0 to SABm + 1 have a configuration of alternately arranged type sheared sense amplifiers. When one normal memory sub-array or row block is selected, a sense operation is performed by sense amplifiers included in sense amplifier bands provided on both sides thereof.

  Spare word lines in spare array SPX # 0 included in row block RBX # 0 can be replaced with normal word lines included in memory subarrays MA # 0-0 to MA # 0-N. Normal memory subarray MA # 1 Each spare word line of spare array SPX # 1 provided at −N can be replaced with a normal word line included in normal memory sub-arrays MA # 1-0 to MA # 1-N.

  During normal operation, any one of normal memory subarrays MA # 0-0 to MA # 0-N is selected, or any one of normal memory subarrays MA # 1-0 to MA # 1-N. Is selected. That is, in the configuration shown in FIG. 11, one normal memory sub-array is driven to the selected state. In the following, normal memory sub-arrays MA # 0-0 to MA # 0-N and normal memory sub-arrays MA # 1-0 to MA # 1-N are alternately arranged in the column direction and each of these sub-array groups is provided. The effect obtained by providing the spare array will be described.

  Consider the case where the spare word lines of spare array SPX # included in row block RBX # 0 can be replaced with defective normal word lines of all normal memory sub-arrays as shown in FIG. In the shared sense amplifier configuration, row block RBX # 0 and normal memory sub-array MA # 1-0 are arranged on both sides of sense amplifier band SAB1. Bit line isolation gate BLIG0 is arranged between sense amplifier band SAB1 and row block RBX # 0, and bit line isolation gate BLIG1 is arranged between sense amplifier band SAB1 and normal memory subarray MA # 1-0. The To bit line isolation gate BLIG0, an output signal of NOR circuit OGa receiving replacement instruction signal / φsp and subarray designating signal φ1 is applied as a bit line isolation control signal. For bit line isolation gate BLIG1, an output signal of NOR circuit OGb receiving replacement instruction signal φsp and subarray specifying signal φ0 is applied as a bit line isolation instruction signal. Replacement instruction signal φsp is selectively set to an active H level when a defective normal cell is addressed and a spare word line included in spare array SPX # is selected. Subarray designating signal φ1 is set to the active H level when normal memory subarray MA # 1-0 is designated, and subarray designating signal φ0 is activated when normal memory subarray MA # 0-0 is designated. The state is at the H level.

  Consider a case where a defective normal word line included in normal memory sub-array MA # 1-0 is replaced with a spare word line included in spare array SPX #. When a defective normal word line of normal memory subarray MA # 1-0 is addressed, subarray designating signal φ1 attains H level, while subarray designating signal φ0 maintains L level. Therefore, the output signal of NOR circuit OGa attains L level, bit line isolation gate BLIG0 is rendered non-conductive, and spare array SPX # is disconnected from sense amplifier band SAB1. On the other hand, since replacement of this defective normal word line with a spare word line included in spare array SPX # is performed, replacement instruction signal φsp is also driven to the H level, so that the output signal of NOR circuit OGb also rises to the H level, and the bit line Isolation gate BLIG1 is also turned off. Therefore, sense amplifier band SAB1 is isolated from both spare array SPX # and normal memory sub-array MA # 1-0, and cannot repair a defective normal word line.

  In order to prevent this, it is conceivable to use the circuit shown in FIG. 13 as the bit line isolation control circuit in order to make the bit line isolation gate BLIG0 conductive when the spare word line is used.

  13, bit line isolation control circuit includes an inverter OGaa receiving subarray designating signal φ1 and an OR circuit OGab receiving the output signal of inverter OGaa and replacement instruction signal φsp. In the bit line isolation control circuit shown in FIG. 13, when the normal memory sub-array is addressed, the output signal of inverter OGaa is at L level. When the defective normal word line is not addressed, replacement instruction signal φsp is at L level, so that the output signal of OR circuit OGab is at L level, and bit line isolation gate BLIG0 can be rendered non-conductive. . On the other hand, when replacement instruction signal φsp is activated and the spare word line included in the spare array is used, the output signal of OR circuit OGab becomes H level, and bit line isolation gate BLIG0 is rendered conductive.

  However, when the bit line isolation control circuit shown in FIG. 13 is used, the circuit configuration is different from the control circuit provided for the other bit line isolation gates, and the number of gate stages is different. And an inverter that receives the output signal). Therefore, the gate delay is different, the timing margin is reduced, and a malfunction may occur.

  As shown in FIG. 11, in spare array SPX # 0, a spare word line replaceable with a defective normal word line of normal memory subarrays MA # 0-0 to MA # 0-N is arranged, whereby normal memory subarrays are arranged. When the defective normal word line of MA # 1-0 is addressed, the spare word line included in the spare array included in row block RBX # 0 is not used. Therefore, in this case, by using a bit line isolation control circuit as shown in FIG. 14, it is possible to accurately perform repair by replacing a defective normal word line.

  In FIG. 14, a 2-input NOR circuit OGc receiving subarray designating signal φ1 is provided for bit line isolation gate BLIG0, and spare replacement designating signal φsp0 and subarray designating signal φ0 are received for bit line isolation gate BLIG1. A NOR circuit OGd is provided. Spare replacement instructing signal φsp0 is driven to an active H level when a defective normal word line is addressed in any of normal memory subarrays MA # 0-0 to MA # 0-N. Subarray designating signal φ0 is driven to an active H level when normal memory subarray MA # 0-0 is designated, and subarray designating signal φ1 is activated when normal memory subarray MA # 1-0 is designated. It is driven to the H level of the state. When spare array SPX # 0 provided corresponding to subarray MA # 0-0 is used, normal memory subarray MA # 1-0 is not addressed. This is because spare word lines included in spare array SPX # 0 are selected when defective normal word lines included in normal memory sub-arrays MA # 0-0 to MA # 0-N are addressed. . In this case, the output signal of NOR circuit OGc maintains the H level, while the output signal of NOR circuit OGd becomes the L level, and sense amplifier band SAB1 is connected to row block RBX # 0, and normal memory subarray MA Disconnected from # 1-0. Conversely, when normal memory sub-array MA # 1-0 is addressed, the output signal of NOR circuit OGc attains the L level, row block RBX # 0 is disconnected from sense amplifier band SAB1, and normal memory sub-array MA # 1-0 is connected to sense amplifier band SAB1 (the output signal of NOR circuit OGd maintains the H level).

  A similar configuration is provided for the other row block RBX # 1. As a result, the memory block including the spare array and the memory sub-array adjacent to the memory block are not simultaneously addressed, and accurate defect repair can be performed.

  FIG. 15 schematically shows an example of replacement of defective normal word lines in the semiconductor memory device according to the fourth embodiment of the present invention. In FIG. 15, spare array SPX # 0 includes spare word lines that can replace defective normal word lines of normal memory sub-arrays MA # 0-0 to MA # 0-N. Spare array SPX # 1 includes spare word lines that can replace defective normal word lines included in normal memory sub-arrays MA # 1-0 to MA # 1-N. The normal subarrays sharing the sense amplifier band have different values of the address signal bits RAj. As a result, malfunction due to access collision (simultaneous selection of normal / spare word lines) can be prevented, and correct defect repair can be performed.

[Embodiment 5]
FIG. 16 is a diagram showing a configuration of a memory cell included in the semiconductor memory device. FIG. 16 representatively shows two memory cells MCa and MCb arranged corresponding to the intersections of word lines WLa and WLb and bit line BL. Each of memory cells MCa and MCb includes a capacitor MQ and an access transistor MT formed of an n-channel MOS transistor that connects capacitor MQ to bit line BL in response to the signal potential of the corresponding word line (WLa or WLb). Including. These memory cells MCa and MCb are dynamic memory cells, and bit lines BL and / BL are arranged in pairs, and a potential difference generated in bit lines BL and / BL is differentially amplified by a sense amplifier. The

  In the arrangement shown in FIG. 16, when word line WLa is driven to a selected state, the voltage level of unselected word line WLb rises due to capacitive coupling due to parasitic capacitance between word lines WLa and WLb, and memory cell MCb The access transistor MT included in is turned on weakly, and the charge stored in the capacitor MQ is transmitted to the bit line BL. In addition, when the selected word line WLa is not selected, the voltage level of the bit line BL decreases due to capacitive coupling between the word line WLa and the bit line BL (when the bit line BL is driven to the ground voltage level). The voltage level of the bit line BL is lowered, the access transistor MT of the memory cell MCb connected to the unselected word line WLb is weakly turned on, and the stored charge of the capacitor flows out to the bit line BL. Such a phenomenon in which current leakage occurs in the memory cells connected to the unselected word line when selecting the word line is called “disturb refresh”. If the charge retention characteristic of the memory cell is poor, the stored data in the memory cell is lost and a soft error occurs before refresh is performed at a constant cycle. In order to test such “disturb refresh” characteristics, a “disturb refresh test” is performed in which the word lines are sequentially driven to a selected state to test the charge retention characteristics of the memory cells. In the “disturb refresh test”, the word line is driven to a selected state a predetermined number of times in order to give a predetermined number of disturbances to each memory cell. As the storage capacity of the semiconductor memory device increases, the number of word lines increases accordingly, and the time required for this “disturb refresh test” increases. In order to perform such a disturb refresh test at a high speed, in this “disturb refresh test”, more word lines are selected simultaneously than the number of word lines simultaneously selected in the normal operation mode. Is driven to. In this case, depending on the word line selection mode, when the flexible redundancy configuration is used, the spare word line and the normal word line are simultaneously driven to the selected state in one subarray, causing access contention, and the storage data of the memory cell. Is destroyed and the disturb refresh test cannot be performed. Below, select normal word lines and spare word lines simultaneously in one memory sub-array even when driving more word lines to the selected state than in normal operation mode, such as disturb refresh test. A configuration capable of preventing this will be described.

  FIG. 17 schematically shows a structure of the array portion of the semiconductor memory device according to the fifth embodiment of the present invention. In FIG. 17, the memory array includes two memory mats B # 0 and B # 1. Memory mat B # 0 includes normal memory subarrays MB # 00-0 to MB # 00-N and normal memory subarrays MB # 01-0 to MB # 01-N. Normal memory subarrays MB # 00-0 to MB # 00-N and normal memory subarrays MB # 01-0 to MB # 01-N are alternately arranged. Between these normal memory sub-arrays MB # 00-0 to MB # 00-N and MB # 01-0 to MB # 01-N, sense amplifier bands indicated by hatched areas are arranged. Spare array SPX # 00 including a spare word line is arranged in normal subarray MB # 00-0, and spare array SPX # 01 including a spare word line is arranged corresponding to normal memory subarray MB # 01-N. . Normal memory sub-array MB # 00-0 and spare array SPX # 00 constitute row block (sense amplifier block) RB # 00, and normal memory sub-array MB # 01-N and spare array SPX # 01 consist of row block RB #. 01 is configured. Normal memory subarrays MB # 00-0 to MB # 00-N form memory block group B # 00 designated when row address signal bit RAj is 1, for example, and normal memory subarrays MB # 01-0 to MB # 01 # 01-N constitutes memory block group B # 01 selected when row address signal bit RAj is, for example, 0.

  Memory mat B # 1 includes normal sub-arrays MB # 10-0 to MB # 10-N and normal memory sub-arrays MB # 11-0 to MB # 11-N. Normal memory subarrays MB # 10-0 to MB # 10-N and normal memory subarrays MB # 11-0 to MB # 11-N are alternately arranged in the column direction. Between these normal memory sub-arrays MB # 10-0 to MB # 10-N and normal memory sub-arrays MB11-0 to MB # 11-N, a sense amplifier band indicated by a hatched area is arranged. Spare array SBX # 10 including a spare word line is arranged corresponding to normal memory subarray MB # 10-0, and spare array SPX # 11 is arranged for normal memory subarray MB # 11-N. Normal memory sub-array MB # 10-0 and spare array SPX # 10 constitute row block (sense amplifier block) RB # 10-0, and normal memory sub-array MB # 11-N and spare array SPX # 11 are row blocks. RB # 11-N is configured. Normal memory subarrays MB # 10-0 to MB # 10-N are included in memory block group B # 10, and normal memory subarrays MB # 11-0 to MB # 11-N are included in memory block group B # 11. It is.

  In the array configuration shown in FIG. 17, spare array SPX # 00 provided in row block RB # 00 has spare word lines replaceable with defective normal word lines of normal memory subarrays included in memory block group B # 10. Including. Spare array SPX # 01 included in row block RB # 01 includes a spare word line that can replace a defective normal word line of a normal memory sub-array included in memory block group B # 11. Spare array SPX # 10 included in row block RB # 10-0 includes a spare word line that can replace a defective normal word line of a normal memory sub-array included in memory block group B # 00. Spare array SPX # 11 included in row block RB # 11-N includes a spare word line that can replace a defective normal word line of a normal memory sub-array included in memory block group B # 01. Next, the operation will be described.

  Now, consider a case where one normal memory sub-array is designated by address signal bits RA0 to RAh as shown in FIG. The memory mat is designated by row address signal bit RAi, and the memory block group is designated by row address signal bit RAj.

  In the normal operation mode, all of these address signal bits RA0 to RAj are valid, one mat is designated, one memory block group is designated in the designated mat, and the designated memory block group is designated. One normal memory sub-array is designated. When the addressed word line is a defective normal word line, the spare word line to be replaced is included in a memory mat different from the selected memory mat. Therefore, the defective normal word line can be replaced without any problem (there is no problem of sharing the sense amplifier band).

  On the other hand, in a test operation mode different from the normal operation mode, row address signal bit RAj is set in a degenerated state as shown in FIG. Thus, one memory mat is designated from memory mats B # 0 and B # 1, and a normal memory sub-array is designated from each of the two memory block groups in the designated memory mat. Since two normal memory sub-arrays are designated in one memory mat, address signal bits are assigned so that a normal sub-array not sharing the sense amplifier band is designated at the time of selection. When the addressed normal word line is a defective normal word line, a corresponding spare word line is prepared in the non-selected memory mat. Therefore, even when a plurality of (two) normal word lines are simultaneously specified in one memory mat, spare words are simultaneously set in row blocks RB # 00, RB # 01, RB # 10, and RB # 11. The line and normal word line are prevented from being driven to the selected state. In the non-selected memory mat, the spare word line of the row block is only driven to the selected state when the defective normal word line is replaced, and the problem of sharing the sense amplifier band does not occur.

  For example, in the test operation mode, when memory mat B # 0 is designated and a normal memory sub-array is selected from each of memory block groups B # 00 and B # 01, the corresponding spare word line is not selected memory mat B Spare array SPX # 10 included in row block RB # 10 of # 1 and / or spare array SPX # 11 included in row block RB # 11 are prepared. Therefore, since the memory mat from which the spare word line is selected and the memory mat from which the normal word line is selected are different from each other, it is possible to prevent the normal word line and the spare word line from being simultaneously selected in one memory array. . In addition, two normal subarrays that do not share the sense amplifier band in one memory mat can be simultaneously driven to a selected state by appropriate assignment of address signal bits. If the number of memory mats is increased, the number of normal word lines that are simultaneously driven to the selected state can be further increased.

  FIG. 19 is a diagram showing a configuration of a portion for changing the number of selected sub-arrays according to the operation mode. In FIG. 19, a gate circuit (OR circuit) GT receiving address signal bit RAj and test mode instruction signal TE is provided. When test mode instruction signal TE attains an active H level, memory block group designating signal φB attains an active H level regardless of the value of row address signal bit RAj. Therefore, in the test operation mode, the row address signal bit RAj is in a degenerated state, and a normal subarray can be designated from each of two memory block groups in one memory mat.

  In order to designate a normal sub-array that does not share a sense amplifier band, the address assignment of one memory block group and the address assignment of the other memory block group may be reversed (one memory block group is When addresses 0 to N are assigned from top to bottom along the column direction, the normal subarrays of the other memory group are assigned sequentially from bottom to top from addresses 0 to N).

  Further, for the connection and sense operation between the sense amplifier band and the spare array in the non-selected memory mat, the spare decoder is always operated to perform the comparison operation, and the result is the same as the configuration shown in FIG. This is realized by supplying to the spare array. A configuration may be used in which a sense amplifier control circuit provided corresponding to a corresponding row block is driven to an active state when an output signal of the spare decoder is in an active state. Thereby, a corresponding sense amplifier can be activated when a spare word line is used in the non-selected memory mat.

  For data access, a configuration similar to that shown in FIG. 4 may be used (data access is not performed during the disturb refresh test).

[Example of change]
FIG. 20 schematically shows a configuration of a modification of the fifth embodiment of the present invention. Also in FIG. 20, as in the configuration shown in FIG. 17, the memory array is divided into two memory mats B # 0 and B # 1. In memory mat B # 0, normal memory subarrays MB # 00-0 to MB # 00-N belonging to memory block group B # 00 and normal memory subarrays MB # 01-0 to MB # included in memory block group B # 01 01-N are alternately arranged along the column direction. Spare array SPX # 00 is arranged corresponding to normal memory subarray MB # 00-0, and spare array SPX # 01 is arranged corresponding to normal memory subarray MB # 01-N. Spare array SPX # 00 includes a plurality of sub-spare word lines that can be replaced with defective normal word lines of normal memory sub-arrays belonging to memory block group B # 00, and spare array SPX # 01 belongs to memory block group B # 01. A spare word line replaceable with a defective normal word line of the normal memory sub-array is included.

  In memory mat B # 1, normal memory subarrays MB # 10-0 to MB # 10-N included in memory block group B # 10 and normal memory subarrays MB # 11-0 to MB # 10-0 included in memory block group B # 11. MB # 11-N are alternately arranged along the column direction. Spare array SPX # 10 is arranged corresponding to normal memory subarray MB # 10-0, and spare array SPX # 11 is arranged corresponding to normal memory subarray MB # 11-N. Spare array SPX # 10 includes a plurality of sub-word lines that can be replaced with defective normal word lines of normal memory sub-arrays included in memory block group B # 10, and spare array SPX # 11 is included in memory block group B # 11. A plurality of spare word lines replaceable with defective normal word lines of the normal subarray.

  Also in the arrangement shown in FIG. 20, sense amplifier bands indicated by hatched areas are arranged between the normal sub-arrays.

  In the configuration shown in FIG. 20, in the normal mode, one of memory mats B # 0 and B # 1 is selected, and one normal memory sub-array is selected in the selected memory mat. Therefore, in the selected one memory mat, the same normal word line selection and defective normal word line replacement and relief as those shown in FIG. 11 are performed.

  In the test mode, for example, row address signal bit RAi is in a degenerated state, and both memory mats B # 0 and B # 1 are designated. In each of memory mats B # 0 and B # 1, one normal subarray is selected. In each of memory mats B # 0 and B # 1, normal subarrays included in different memory block groups are alternately arranged, and normal subarrays sharing a sense amplifier band are included in different memory block groups. Therefore, in the test mode, a plurality of (two) normal word lines or spare word lines are driven to a selected state without causing a sense amplifier contention problem that normal memory sub-arrays sharing a sense amplifier are specified at the same time. Thus, a test operation can be performed (in any of row blocks RB # 00-RB # 11, the normal word line and the spare word line are not driven to the selected state at the same time). Thereby, the disturb refresh test can be performed at high speed.

  In the fifth embodiment, a disturb refresh test is described. However, in the self-refresh mode, when a configuration in which more word lines are driven to the selected state than in the normal operation mode is used, if the self-refresh instruction signal is used instead of the test mode instruction signal, the same An effect is obtained. In the configuration of this modification, the same configuration as that shown in FIG. 19 can be used as the configuration for degenerating the address signal bits (address signal bits for specifying the memory mat) RAi.

  As described above, according to the fifth embodiment of the present invention, a plurality of memory mats are provided, and more normal word lines are driven to a selected state in a specific operation mode such as a disturb refresh test than in a normal operation mode. In this case, since the normal word line and the spare word line are not selected at the same time in one row block, the characteristic of the flexible redundancy configuration, that is, the efficient use of the spare decoder and the spare word line. A desired operation mode can be accurately realized without impairing the characteristics.

  Even in the configuration of this modified example, by increasing the number of memory mats, more normal word lines (4 or 8) can be easily driven to the selected state at the same time.

[Embodiment 6]
FIG. 21A schematically shows a structure of a main portion of the semiconductor memory device according to the sixth embodiment of the present invention. In FIG. 21A, the memory array is divided into a plurality of memory array blocks 2a to 2n. Memory array blocks 2a-2n include a plurality of memory cells arranged in a matrix. A memory cell row is selected in units of blocks. Row-related peripheral circuits 3a-3n for driving memory cell rows of memory array blocks 2a-2n to a selected state are arranged corresponding to memory array blocks 2a-2n, respectively. These row peripheral circuits 3a to 3n will be described in detail later, but the memory cell row is selected in accordance with a decode circuit (which may include a predecoder) for decoding an address signal and an output signal of the decode circuit. A word line drive circuit for driving the

  Between each of the row peripheral circuits 3a to 3n and the main power supply line 1, power switch circuits (SW) 4a to 4n that are driven to a selected state in response to selection signals φBa to φBn are provided. Each of these power switch circuits 4a-4n generates a larger current flow when driven to the selected state than when in the non-selected state. A predetermined voltage Vr is applied to the main power supply line 1. This voltage Vr may be any one of power supply voltage Vcc, ground voltage Vss and high voltage Vpp, or a combination thereof. An appropriate voltage is selected as the voltage Vr according to the configuration of the row-related peripheral circuits 3a to 3n.

  Power supply block for generating selection signals φBa to φBn (collectively referred to as control signals) in accordance with address signal AD and self-refresh mode instruction signal SR to determine selection / non-selection of power supply switch circuits 4a to 4n A decoder 6 is provided. Address signal AD is also applied to row-related peripheral circuits 3a-3n as a memory cell row (word line) designation address.

  The power supply block decoder 6 varies the number of power supply switch circuits driven to the selected state in the normal operation mode (normal mode) and the self-refresh mode. The power supply block decoder 6 changes the selection sequence of the power supply switch circuits 4a to 4n between the self-refresh mode and the normal mode. With these features, even when spare lines are included in the memory array blocks 2a to 2n, it is possible to realize a semiconductor memory device that operates with low current consumption without increasing the access time.

  FIG. 21B is a diagram showing an example of the configuration of row related peripheral circuits 3a-3n shown in FIG. FIG. 21B representatively shows the configuration of one row-related peripheral circuit 3.

  In memory array block 2 (2a to 2n), memory cells MC are arranged in a matrix, and word lines WLa to WLm are arranged corresponding to the respective rows of memory cells MC. A bit line pair BL, / BL is arranged corresponding to each column of memory cells, but only bit line BL is shown in FIG.

  Row related peripheral circuit 3 includes a repetitive circuit provided corresponding to each of these word lines WLa to WLm. Here, the repeating circuit has the same circuit configuration and realizes the same function. A predetermined number of repeating circuits among the plurality of repeating circuits are selected by the address signal.

  In FIG. 21B, the repetitive circuit includes a NAND decode circuit 11 (11a to 11m) and a word line drive that drives the corresponding word line WL (WLa to WLm) to a selected state in accordance with an output signal of the NAND decoder circuit. The circuit 12 (12a-12m) is included.

  In the standby cycle, the output signals of NAND type decode circuits 11a-11m are at the H level. Therefore, during the standby cycle, sub-threshold leakage current to the ground node occurs in these NAND type decode circuits 11a to 11m. Therefore, each of the NAND type decode circuits 11a to 11m is coupled to the sub-ground line 15n. Sub-ground line 15n is coupled to the ground node via power switch transistor 14n. The power switch transistor 14n is turned on in response to the control signal φBin.

  On the other hand, in inverter type word line drive circuits 12a-12m, the input signal at the standby cycle is at the H level, and a subthreshold leakage current flows from the power supply node. Therefore, the power supply nodes of these inverter type word line drive circuits 12a-12m are coupled to sub power supply line 15p. Sub power supply line 15p is coupled to voltage source node 16 through power supply switch transistor 14p which is turned on in response to selection signal φBip. Power supply voltage Vcc or high voltage Vpp is applied to voltage source node 16. The voltage applied to voltage source node 16 is appropriately determined according to the configuration of the repetitive circuit.

  NAND type decode circuits 11a-11m have the other power supply node commonly coupled to the main power supply line, and the ground nodes of inverter type word line drive circuits 12a-12m are coupled to the main ground line.

  In the standby cycle, control signal φBin is set to L level (ground voltage level), and control signal φBip is set to H level of the voltage level of node 16. As a result, power supply switch transistors 14n and 14p are turned off. These power switch transistors 14n and 14p have a large threshold voltage, and their subthreshold leakage current is extremely small in the off state. On the other hand, NAND decode circuits 11a to 11m and word line drive circuits 12a to 12m include a low Vth MOS transistor as a constituent element. Therefore, current consumption in these repetitive circuits, that is, row-related peripheral circuits during the standby cycle can be reduced. Also, since these repetitive circuits operate at high speed, the access time can be shortened.

  21A and 21B, each of power supply switch circuits 4a to 4n corresponds to power supply switch transistors 14n and 14p, and each of sub power supply voltage supply lines 5a to 5n is This corresponds to the sub-ground line 15n and the sub-voltage supply line 15p. The ground node and voltage source node 16 correspond to main power supply line 1. Next, a specific selection mode of the power switch circuits 4a to 4n will be described.

  First, in order to simplify the description, the selection operation when no spare line is included will be described.

[Hierarchical power supply configuration 1]
FIG. 22 schematically shows a structure of a main portion of the semiconductor memory device according to the sixth embodiment of the present invention. In FIG. 22, the memory array is divided into eight memory blocks MAB1 to MAB8. Each of memory blocks MAB1-MAB8 includes memory array block 2 (2a-2n) and corresponding row related peripheral circuits (3a-3n) shown in FIG. Memory blocks MAB1 to MAB4 constitute one global block GAB0, and memory blocks MAB5 to MAB8 constitute one global block GAB1.

  Power switch circuits SW1 to SW8 are arranged corresponding to memory blocks MAB1 to MAB8, respectively. Each of power supply switch circuits SW1 to SW8 couples a sub-voltage supply line arranged corresponding to each of memory blocks MAB1 to MAB8 and a corresponding memory block.

  In address allocation, 3-bit address signals RA1, RA2, and RA3 are used for block designation. One of global blocks GAB0 and GAB1 is designated by address bit RA1. A combination of address bits RA2 and RA3 designates one memory block in global blocks GAB0 and GAB1. Therefore, one memory block can be selected by these 3-bit address signals RA1 to RA3 to select a memory cell row.

  FIG. 23A shows a selected memory block and a selected power switch circuit in the normal mode. In FIG. 23A, in the normal mode, one memory block is selected from memory blocks MAB1 to MAB8, and the addressed word line is driven to the selected state. In FIG. 23A, as an example, the word line WL is driven to the selected state in the memory block MAB2. When memory block MAB2 is selected, all power supply switch circuits SW1-SW4 provided for global block GAB0 including memory block MAB2 are driven to a selected state.

  As shown in FIG. 23B, selection of a group of power switch circuits SW1 to SW4 and a group of power switch circuits SW5 to SW8 is performed by an address signal bit RA1. Therefore, by decoding the 1-bit address signal, the control signals φB1 to φB4 for the power switch circuit can be driven to a selected state, and a desired voltage can be supplied at an access cycle at a fast timing.

  On the other hand, in order to select memory block MAB2, it is necessary to decode 3-bit address signals RA1-RA3. In consideration of the timing skew of these 3-bit address signals RA1-RA3, a row decoding operation for activating memory block designating signal φB2 is performed. Compared with the case of decoding a 1-bit address signal, when a 3-bit address signal is decoded, the load on the output signal line of the decoding circuit is increased, and the decoding time is increased due to skew.

  Therefore, in the normal mode, by driving the power switch circuit for the global block including the selected memory block MAB2 to the selected state, the desired memory can be stably supplied to the selected memory block at a fast timing after the active cycle starts in the normal mode. A voltage can be supplied, and an increase in access time can be prevented.

  FIG. 24 is a diagram showing a selection mode of the power switch circuit in the refresh mode. In FIG. 24, the word line WL is selected in one memory block even in the refresh mode. FIG. 24 also shows a state in which the memory block MAB2 is selected and the word line WL to be refreshed is selected therein. In this refresh mode, only power switch circuit SW2 provided for selected memory block MAB2 is driven to the selected state. The remaining power switch circuits SW1, SW3 to SW8 are held in a non-selected state. In the refresh mode, the stored data is simply rewritten, and no data access is performed. Therefore, since high-speed access is not required, there is no particular problem even if 3-bit refresh address signals QA1 to QA3 are used to select this power switch circuit. By driving one power switch circuit to the selected state and holding the remaining power switch circuits in the non-selected state, the current flowing through the power switch circuit is reduced, and an increase in current consumption in the refresh mode can be suppressed. A refresh mode with low current consumption can be realized.

  FIG. 25 schematically shows a structure of a control portion of the semiconductor memory device according to the sixth embodiment of the present invention. In FIG. 25, the semiconductor memory device receives an external control signal CMD and generates an operation mode instruction signal, and a refresh mode detection circuit 22 included in the operation mode detection circuit 20. The refresh control circuit 23 is activated in response to the activation of the self-refresh mode instruction signal SR, starts the timer 24, and generates the refresh cycle activation signal QACT at a predetermined time interval. The refresh address QA from the refresh address counter 25 is controlled under the control of the refresh address counter 25 for generating a refresh address for designating a refresh row and the refresh control circuit 23. Multiplexer 26 for selecting one of externally applied row address signals RA, refresh cycle activation signal QACT from refresh control circuit 23, or array activation signal RACT from an array activation detection circuit included in operation mode detection circuit 20 A row control circuit 27 for generating a control signal necessary for row selection is included.

  The operation mode detection circuit 20 generates an instruction signal corresponding to each designated operation mode in accordance with a control signal CMD given from the outside. This external control signal CMD may be a command (combination of a plurality of control signal states) as in a normal synchronous semiconductor memory device, or in a standard DRAM (Dynamic Random Access Memory). The row address strobe signal / RAS, the column address strobe signal / CAS, the write enable signal / WE, and the chip select signal / CS may be used. An external control signal applied to operation mode detection circuit 20 is appropriately determined according to the configuration of the semiconductor memory device.

  Refresh control circuit 23 drives refresh cycle activation signal QACT to an H level active state for a predetermined period at a predetermined time interval according to the count-up signal of timer 24 when self refresh mode instruction signal SR is activated. Row-related control circuit 27 generates a control signal necessary for row selection when one of activation signals QACT and RACT is activated. In FIG. 25, this row-related control circuit 27 is shown to generate a word line drive signal φWL that gives the timing for driving the word line to the selected state. During the activation period of these activation signals QACT and RACT, the row (word line) is held in the selected state in the memory block designated by the address signal. The active periods of these activation signals QACT and RACT define one memory cycle (for the selected memory block).

  The timer 24 generates a refresh request signal at a predetermined time interval in response to a self-refresh instruction from the refresh control circuit 23 and supplies it to the refresh control circuit 23. Refresh address counter 25 increments or decrements the count value by 1 in accordance with count-up instruction signal φCUP applied at the completion of this memory cycle. Multiplexer 26 selects refresh address QA from refresh address counter 25 in the self-refresh mode in accordance with switching control signal φMUX from refresh control circuit 23, and selects external row address signal RA in the normal mode. Address signal AD from multiplexer 26 is applied to the row peripheral circuit of each memory block. Of these address signals, address signal bits QA1-QA3 or RA1 are applied to power supply block decoder 6 (see FIG. 21A). Since the address signal bits are transmitted from the multiplexer 26 via the same bus line, a 3-bit address signal is applied to the power supply block decoder via the same address signal line. The internal address bit supply path is different.

  FIG. 26 shows a configuration of power supply block decoder 6 shown in FIG. FIG. 26 shows a configuration of a portion that generates one power supply block selection signal φBi (i = 1-8). In FIG. 26, power supply block decoder 6 receives inverter circuit 6a for inverting self-refresh instruction signal SR and a predetermined 3-bit address signal among address signal bits QA1-QA3 and / QA1- / QA3 in the refresh mode. AND circuit 6b receiving, NAND circuit 6c receiving output signal / SR of inverter circuit 6a and address bit RA1 or / RA1, NAND circuit 6d receiving self-refresh mode instruction signal SR and output signal of AND circuit 6b, NAND NAND circuit 6e is generated which receives the output signals of circuits 6c and 6d and generates power supply block selection signal φBi. AND circuit 6b is supplied with an address signal bit corresponding to the address of a memory block provided corresponding to power supply block selection signal φBi. Similarly, in NAND circuit 6c, address bit RA1 or / RA1 designating a global block including a memory block corresponding to power supply block selection signal φBi is applied.

  In the self-refresh mode, the self-refresh mode instruction signal SR is at the H level, the signal / SR from the inverter circuit 6a is at the L level, and the NAND circuit 6c does not depend on the state of the address bits RA1 and / RA1. A level signal is output. On the other hand, the NAND circuit 6a operates as an inverter and inverts the output signal of the AND circuit 6b. Therefore, in the self refresh mode, power supply block selection signal φBi is generated in accordance with address bits QA1-QA3 and / QA1- / QA3.

  On the other hand, in the normal mode, self-refresh mode instruction signal SR is at L level, and output signal / SR of inverter circuit 6a is at H level. In this state, the output signal of NAND circuit 6d is at H level, NAND circuit 6c operates as an inverter, and power supply block selection signal φBi is generated according to address bit RA1 or / RA1. Thereby, in the normal mode, power supply block selection signal φBi for the global block including the selected memory block (memory block including the selected row) is activated. On the other hand, in the self-refresh mode, power supply block selection signal φBi for the power switch circuit provided for the memory block to be refreshed is driven to the selected state.

  FIG. 27 is a diagram showing a configuration of a portion for generating power supply block selection signal φB2 for power supply switch circuit SW2. For power supply block selection signal φB2, AND circuit 6b receives address bits / QA1, / QA2 and QA3, and NAND circuit 6c receives address bit / RA1. The address (QA1, QA2, QA3) of the memory block provided with the power switch circuit SW2 is (0, 0, 1). Therefore, when memory block MAB2 is designated, the output signal of AND circuit 6b is at H level. On the other hand, in the normal mode, address bit / RA1 is at the H level ("1"), and power supply block selection signals φB1-φB4 for power supply switch circuits SW1-SW4 provided corresponding to global block GB0 including memory block MAB2 Are driven to the selected state of H level. By changing the number of decode bits according to the operation mode, the number of power switch circuits driven to the selected state can be changed in the normal mode and the self-refresh mode.

  When the number of memory blocks is 8, the block is divided into two global blocks. Therefore, a 1-bit address signal is decoded in the normal mode, and a 3-bit address signal is decoded in the self-refresh mode. However, the number of address signal bits used in the normal mode and the self-refresh mode is appropriately determined according to the number of memory blocks and global blocks. It is sufficient that the number of address signal bits that are valid in the normal mode is smaller than the number of address signal bits that are decoded in the self-refresh mode.

[Example of change]
FIG. 28 schematically shows a configuration of a modified example of hierarchical power supply configuration 1 according to the sixth embodiment of the present invention.

  In the configuration shown in FIG. 28, refresh address QA from the refresh address counter and external row address signal RA are applied to multiplexer 26. The row peripheral circuit is supplied with an internal row address signal from the multiplexer 26. On the other hand, address bits QA1-QA3 from refresh address counter 25 and internal row address bit RA1 from multiplexer 26 are applied to the power supply block decode circuit. In this configuration, therefore, address bits QA1-QA3 are applied directly from refresh address counter 25 to the power supply block decode circuit. Since the signal does not pass through the multiplexer 26, the influence of the gate delay (signal propagation delay) in the multiplexer 26 can be eliminated in the self-refresh mode, and the decoding operation can be performed at a fast timing.

  As described above, according to this hierarchical power supply configuration 1, since the number of address bits used for power supply block selection differs between the normal mode and the refresh mode, the access time in the normal mode is reduced. The current consumption is not increased and the current consumption can be reduced in the refresh mode.

[Modification 2]
FIG. 29 is a diagram schematically showing a configuration of a modified example 2 of the hierarchical power supply configuration 1. 29 shows a configuration of a portion of row-related control circuit 27 shown in FIG. 29, row-related control circuit 27 receives an OR circuit 30 receiving activation signals QACT and RACT, and a word line for driving word line activation signal φRX to an active state in response to a rise of the output signal of OR circuit 30. Activation signal generation circuit 31, delay circuit 32 for delaying word line activation signal φRX from word line activation signal generation circuit 31 for a predetermined time, and output of delay circuit 32 in accordance with self-refresh mode instruction signals SR and / SR A selection circuit 33 is provided which selects one of the signal and the signal φRX from the word line activation signal generation circuit 31 to generate the word line drive signal φWL. Select circuit 33 is rendered conductive when self-refresh mode instruction signal SR is activated, and is rendered conductive when CMOS transmission gate 33a for allowing the output signal of delay circuit 32 to pass through, and when self-refresh mode instruction signal SR is deactivated, and word line activation. CMOS transmission gate 33b for allowing word line activation signal φRX from activation signal generating circuit 31 to pass therethrough is included.

  Next, the operation of the row control circuit 27 shown in FIG. 29 will be described with reference to the signal waveform diagram shown in FIG.

  In the normal mode, array activation signal RACT is driven to an active state in accordance with a memory cycle start instruction signal (or active command). When the array activation signal RACT is activated, the output signal of the OR circuit 30 is activated, and the word line activation signal generation circuit 31 generates the word line activation signal φRX at a predetermined timing. In the normal mode, the CMOS transmission gate 33b is in a conductive state and the CMOS transmission gate 33a is in a nonconductive state. Therefore, word line drive signal φWL is generated in accordance with word line activation signal φRX. When one active cycle is completed, array activation signal RACT falls to the L level non-selected state, and accordingly, word line activation signal φRX is also deactivated, and the selected word line is driven to the non-selected state. .

  In the self-refresh mode, the refresh activation signal QACT is activated. Word line activation signal generating circuit 31 drives word line activation signal φRX to an active state in response to activation of refresh activation signal QACT. In the self-refresh mode, the CMOS transmission gate 33a is conductive and the CMOS transmission gate 33b is non-conductive. Therefore, word line drive signal φWL is driven to an active state in accordance with a delayed word line activation signal from delay circuit 32.

  By delaying the activation timing of the word line drive signal φWL in the self-refresh mode, the power switch circuit is selected, and after the predetermined supply voltage to the refreshed memory block is stabilized, the selection of the word line is performed. Therefore, it is possible to accurately perform the decoding operation and drive the addressed word line (refresh row) to the selected state.

  As shown by the wavy waveform in the signal waveform diagram shown in FIG. 30, delay circuit 32 is a rising delay circuit, and deactivation of word line drive signal φWL responds to deactivation of refresh activation signal QACT. May be performed. Even if the word line is driven to the selected / unselected state later than the refresh activation signal QACT, the sense amplifier is activated and deactivated in accordance with the word line drive signal φWL, so that there is a particular problem. Absent. The so-called RAS precharge time problem does not occur particularly in the self-refresh mode. In the self-refresh mode, the refresh interval is a sufficiently long period of 16 μs, for example, and therefore a sufficient RAS precharge period can be ensured even using such a delay circuit 32.

Figure 31 is a Ru FIG der showing a structure of a portion of a row-related peripheral circuitry that operates according to the word line drive signal φWL shown in FIG. 29. FIG. 31 shows a configuration of a repetitive circuit for one word line WL. In FIG. 31, the repetition circuit selectively receives an output signal of NAND type decode circuit 41 according to address bit (predecode signal) Xl and NAND type decode circuit 41 receiving address bits (predecode signals) Xi, Xj and Xk. Decode transistor 42 composed of an n-channel MOS transistor transmitted onto node 41, p-channel MOS transistor 43 for precharging node 49 to high voltage Vpp level in response to reset signal RST, and a signal on node 49 When L level, p channel MOS transistor 44 for transmitting signal SDX from word line decode signal generation circuit 40 onto word line WL and when signal on node 49 is at H level, the word line WL is set to the ground voltage level. N-channel MOS transistors that discharge to 45, when the signal on word line WL is at L level, p channel MOS transistor 46 holding node 49 at high voltage Vpp level, and when signal / STX from word line decode signal generation circuit 40 is at H level An n channel MOS transistor 47 which conducts and discharges word line WL to the ground voltage level is included.

  Here, the decoding circuit includes a NAND type decoding circuit 41 and a decoding transistor 42. The word line drive circuit is composed of MOS transistors 44-47.

  Word line decode signal generation circuit 40 is activated when word line drive signal φWL is activated, and generates signals SDX and / SDX in accordance with address bits (predecode signal) Xm. Signal SDX changes between high voltage Vpp and ground voltage Vss. Signal / SDX changes between power supply voltage Vcc and ground voltage.

  In standby mode, address bits Xi, Xj and Xk are all at L level. Therefore, since a subthreshold leakage current flows to the ground potential in NAND type decode circuit 41, the ground node of NAND type decode circuit 41 is connected to the main ground line via MOS transistor 48. MOS transistor 48 receives power supply block selection signal φBi at its gate. Next, the operation will be briefly described.

  In the standby state, address bits Xi, Xj and Xk are all at L level, and the output signal of NAND decode circuit 41 is at H level of power supply voltage Vcc level. MOS transistor 48 is in an off state since power supply block selection signal φBi is at the L level. In the standby state, word line decode signal generation circuit 40 holds signal SDX at the ground voltage level L level and signal / SDX at the H level. Node 49 is held at high voltage Vpp level via MOS transistor 43 by reset signal RST. In this state, word line WL is held at the ground voltage level by MOS transistors 45 and 47.

  When the active cycle starts, power supply block selection signal φBi attains an H level at the time of selection, and NAND type decode circuit 41 receives power supply voltage Vcc and ground voltage Vss as both operation power supply voltages and performs a decoding operation. When address bits Xi, Xj, Xk and Xl are all at the H level, node 49 is discharged to the ground voltage level by NAND type decode circuit 41 (reset MOS transistor 49 is in the OFF state). Since MOS transistor 46 has a small current driving capability, node 49 is reliably discharged to the ground voltage level by NAND type decode circuit 41 and decode transistor 42. When the voltage level on node 49 becomes L level, MOS transistor 45 is turned off. Since the signal SDX is at the L level, the MOS transistor 44 has the same gate and source potential and transitions to the off state.

  A word line decode signal generation circuit 40. It operates in response to activation of word line drive signal φWL, and drives signals SDX and / SDX to H level / L level according to address bit Xm. When address bit Xm is at H level, signal SDX is driven to high voltage Vpp level, and signal / SDX is discharged to the ground voltage level. Therefore, at this time, word line WL is driven to high voltage Vpp level via MOS transistor 44. On the other hand, when address bit Xm is at L level, signal SDX is at L level and signal / SDX is at H level. Therefore, p channel MOS transistor 44 maintains an off state. When both MOS transistors 44 and 45 are turned off, MOS transistor 47 is turned on by signal / SDX, and word line WL is reliably held at the ground voltage level.

  In the case of the repetition circuit shown in FIG. 31, one row decoding circuit is provided for two word lines WL. One of the two word lines is selected by signals SDX and / SDX. When address signal bit Xm applied to word line decode signal generation circuit 40 is 2 bits, one row decode circuit is provided for four word lines.

  Thus, in the case of the configuration of the repetitive circuit as shown in FIG. 31, in the normal mode, the word line drive signal φWL is driven to the active state at an early timing, and accordingly the word line WL is activated at the early timing. Driven to. On the other hand, in the self-refresh mode, activation of word line drive signal φWL is slower than activation of power supply block selection signal φBi. Power supply block selection signal φBi is driven to an active state at a relatively late timing (in order to fully decode the power supply block address signal) in the self-refresh mode. After the voltage level of the ground node of NAND type decode circuit 41 reliably reaches the ground voltage, signals SDX and / SDX from word line decode signal generation circuit 40 are driven to a specific state. Thereby, in the self-refresh mode, it is possible to reliably perform the decoding operation and transmit high voltage Vpp or ground voltage Vss onto selected word line WL.

  In the configuration shown in FIG. 31, the sub ground line is connected to the NAND type decode circuit 41 as a so-called hierarchical power supply configuration. When word line decode signal generation circuit 40 is provided corresponding to each memory block, a power switch circuit is provided for each memory block for the signal line supplying high voltage Vpp, and high voltage Vpp is provided. May be provided in the manner described above. This is because in the word line decode signal generation circuit 40, the leakage current from the high voltage Vpp flows due to the subthreshold leakage current, and the current is prevented from being consumed. In this configuration, the power supply nodes (sources) of MOS transistors 43 and 46 may be coupled to a sub-high voltage supply line common to word line decode signal generation circuit 40.

  As described above, according to the configuration of the second modification, in addition to the above-described effects, the word line can be driven after the voltage of the operating voltage supply node is stabilized, and the decoding operation can be performed accurately. Rows can drive the addressed word line to the selected state.

  Even when the high voltage Vpp has a hierarchical power supply configuration, the word line can be driven after the high voltage Vpp is stabilized.

[Hierarchical power supply configuration 2]
FIGS. 32A and 32B are diagrams showing a selection mode of the power switch circuit of the hierarchical power supply configuration 2 according to the sixth embodiment of the present invention. As shown in FIG. 32A, in the normal mode, the word line WL is driven to a selected state in one memory block. In this case, the power switch circuit provided for the global block including the selected memory block is driven to the selected state. In FIG. 32A, a word line WL is selected in memory block MAB2, and power supply switch circuits SW1-SW4 for global array block GAB0 including memory block MAB2 are driven to a selected state. This is the same as the operation of the previous hierarchical power supply configuration 1 in the normal mode.

  Next, as shown in FIG. 32B, in the refresh mode, one memory block is selected in each of global array blocks GAB0 and GAB1, and refresh is performed. In FIG. 32B, refresh is performed in memory blocks MAB and MAB6. In this case, power switch circuits SW2 and SW6 provided for memory blocks MAB2 and MAB6 are driven to a selected state. Assume that the address bit allocation is the same as the address bit allocation shown in FIG. In this case, in the self-refresh mode, the address bit QA1 designating the global block is put into a degenerated state (ignored). Therefore, a power supply block selection signal is generated according to address bits QA2 and QA3.

  FIG. 33 schematically shows a structure of a power supply block decoding circuit. The power supply block decoding circuit shown in FIG. 33 has the configuration shown in FIG. 26 except that AND circuit 6f for decoding refresh address bits receives a predetermined set of refresh address bits QA2, QA3, / QA2 and / QA3. The corresponding parts are denoted by the same reference numerals, and detailed description thereof is omitted.

  In power supply block decode circuit 6 shown in FIG. 33, refresh address bits QA1 and / QA1 are not used. Therefore, in the refresh mode, one memory block is selected in each of global blocks GAB0 and GAB1.

  FIG. 34 shows a configuration of a portion for generating a control signal (power supply block selection signal) φB2 for power supply switch circuit SW2 provided for memory block MAB2. In FIG. 34, in this power supply block decode circuit, refresh address bits / QA2 and Q3 are applied to AND circuit 6f. The memory block MAB2 is selected when the refresh address bits (QA2, QA3) are (0, 1). Therefore, when memory block MAB2 is designated, the output signal of AND circuit 6f attains an H level, and power supply block selection signal φB2 is driven to an active state at an H level. In this power supply block decoding circuit, since address bit QA1 is not used, memory block MAB6 is also selected in global block GAB1, and corresponding power supply switch circuit SW6 is driven to the selected state.

  Also in this hierarchical power supply configuration 2, as shown in FIG. 35, word line drive signal φWL is applied to row selection circuit 50 included in row peripheral circuit 3. A predetermined voltage Vr is applied to the row selection circuit 50 via the power switch circuit SW. When selected, row-related selection circuit 50 drives one of word lines WL0 to WLm to a selected state in accordance with address signal Ad. Power supply switch circuit SW is driven to a selected state in response to power supply block selection signal φBi. Row related select circuit 50 includes a word line decode signal generating circuit 40 shown in FIG. This word line drive signal φWL is generated from the control circuit shown in FIG. Therefore, the activation timing of word line drive signal φWL applied to row-related selection circuit 50 is later than the activation timing in the normal memory in the self-refresh mode. As a result, the power switch circuit SW is driven to the selected state, and after the stable voltage Vr is supplied to the row-related selection circuit 50, the row-related selection circuit 50 executes the word line selection operation. As a result, the selected word line can be stably driven to the selected state.

  According to hierarchical power supply configuration 2, in the refresh mode, even when more word lines are driven to the selected state than in the normal mode, the power switch circuit of the global block is driven to the selected state in the normal mode. On the other hand, in the self-refresh mode, by driving only the power switch circuit for the selected memory block to the selected state, the power consumption in the refresh mode can be reduced without increasing the access time. Further, the word line drive timing is delayed in the self-refresh mode, so that the word line selection operation can be performed accurately.

  In this hierarchical power supply configuration 2, the number of memory blocks is eight, but the number of memory blocks is arbitrary, and the number of global blocks is also arbitrary. In the self-refresh mode, two word lines are selected, but the number of rows refreshed at the same time is arbitrary, and the refresh address bit to be used depends on the number of rows refreshed at the same time. The number may be adjusted appropriately.

[Hierarchical power supply configuration 3]
FIG. 36 schematically shows a structure of hierarchical power supply configuration 3 according to the sixth embodiment of the present invention. FIG. 36 shows a configuration of a portion that controls this hierarchical power supply circuit.

  In FIG. 36, the power supply block selection signal generator decodes the refresh address output from the refresh address counter 25 one cycle ahead, latches the decoded result, and outputs the latched result in the current refresh cycle. A decoder 6 is included. The refresh address counter 25 performs a count operation according to the count-up instruction signal CUP activated during the refresh cycle, and holds the count value. The output count value of refresh address counter 25 is also applied to register 65. This register 65 takes in and outputs the output count value of the refresh address counter 25 in response to the instruction signal φCUP activated when the refresh cycle is completed. The address signal output from register 65 is applied to multiplexer (MUX) 26 as refresh address signal QA.

  The power supply block decoder 6 includes a power supply block decode circuit 60 that decodes the output count of the refresh address counter 25, a latch 61 that latches the output signal of the power supply block decode circuit 60 in response to activation of the count-up instruction signal CUP, In response to refresh cycle activation signal QACT, latch 62 for fetching and outputting latch data of latch 61, and one of output signal of latch 62 and address bit RA1 from multiplexer 26 in accordance with self-refresh mode instruction signal SR are selected. Then, a selector 63 for outputting power supply block selection signals φB1-φB8 is included. Here, the memory array is divided into eight memory blocks MAB1 to MAB8, and a global block, that is, four memory array blocks are selected according to row address bit RA1. Next, the operation of the control signal generator shown in FIG. 36 will be described with reference to the signal waveform diagram shown in FIG.

  In the self-refresh mode, when the refresh cycle activation signal QACT is inactivated, the latch 61 receives a power supply block selection signal φBi (N−1) generated by the power supply block decode circuit 60 in the previous cycle (N−1). Is latched. The latch 62 also latches the power supply block signal φBi (N−1). Selector 63 selects an output signal of latch 62 in accordance with self-refresh mode instruction signal SR.

  When refresh cycle activation signal QACT is activated, latch 62 outputs the latch data, and power supply block selector signal φBi is transmitted through selector 63 in accordance with the decoding result of the previous memory cycle (N−1). Driven to selected / unselected state. In this cycle (N), the register 65 generates the refresh address fetched in the previous cycle. Therefore, in cycle (N), selection control and refresh operation of the power switch circuit are performed in accordance with power supply block selection signal φBi (N−1) and refresh address QA (N−1) decoded in the previous cycle. . In the previous cycle, the decoding operation for generating the power supply block selection signal is completed. When the refresh cycle activation signal QACT is activated, the power supply block selection signal φBi (N−1) is immediately It becomes a definite state. Therefore, it is not necessary to delay the word line selection timing in the refresh cycle, and the refresh can be executed at an early timing. It is not necessary to make the word line selection timing different between the normal mode and the refresh mode, and the control of the word line selection becomes easy.

  In response to activation of refresh cycle activation signal QACT, count up instruction signal CUP is activated at a predetermined timing. In response to the activation of the count-up instruction signal CUP, the refresh address counter 25 performs a counting operation, and this count value is incremented or decremented by one. Power supply block decode circuit 60 decodes the refresh address from refresh address count 25 and generates a power supply block selection signal according to the decoding result. Latch 61 takes in the output signal of power supply block decode circuit 60 in accordance with count-up instruction signal CUP, and enters a latch state in accordance with deactivation of count-up instruction signal CUP. During this time, the refresh operation is performed according to the refresh address QA (N-1) of the previous cycle.

  When refresh cycle activation signal QACT is inactivated, latch 62 takes in the latch signal of latch 61 and drives its output signal to the inactive state. Thus, power supply block selection signals φB1-φB8 are all driven to a non-selected state. In response to activation of refresh cycle activation signal QACT, count up instruction signal φCUP is activated, and register 65 takes in and outputs the output count value of refresh address counter 25. As a result, the refresh address QA changes by one.

  When refresh cycle activation signal QACT is then activated again, latch 62 outputs the latched power supply block selection signal, and power is supplied in accordance with power supply block selection signal φBi (N) obtained in the previous cycle (N). Block selection signals .phi.B1-.phi.B8 are driven to the selected / unselected state. In this cycle (N + 1), the register 65 also outputs the refresh address fetched when the previous cycle is completed and gives it to the row peripheral circuit. A refresh operation is executed in accordance with refresh address QA (N) and power supply block selection signal φBi (N) generated in the previous cycle (N).

  During the activation period of the refresh cycle activation signal QACT, the count up instruction signal CUP is activated again, and the refresh address counter 25 performs a count operation to update the count value. Power supply block decode circuit 60 performs a decoding operation again to generate power supply block selection signal φBi (N + 1), and latch 61 latches power supply block selection signal φBi (N + 1) from power supply block decode circuit 60.

  When refresh cycle activation signal QACT is deactivated, latch 62 takes in the output signal of latch 61 again, and its contents are updated to power supply block selection signal φBi (N + 1). In accordance with deactivation of refresh cycle activation signal QACT, latch 62 drives its output signal φBi (N) to a non-selected state. In response to deactivation of refresh cycle activation signal QACT, count up instruction signal φCUP is activated, and register 65 takes in the output count value of refresh address counter 25 and updates the refresh address. Thereafter, every time the refresh cycle activation signal QACT is activated at predetermined time intervals, the above-described operation is repeated.

  During the refresh operation, a refresh address is generated according to the count operation of the refresh address counter 25. Therefore, in each refresh cycle, the next refresh address can be known, and in the previous cycle, a power supply block selection signal can be generated in advance by decoding the refresh address. Thus, it is not necessary to perform a decoding operation for selecting a power supply block at the start of the refresh cycle, and the word line for the refresh row can be driven to the selected state at an early timing.

  FIG. 38 shows an example of the configuration of power supply block decoder 6 shown in FIG. 38, power supply block decode circuit 60 includes a NAND type decode circuit 60a that receives predetermined refresh address bits QAi, / QAi. The combination of refresh address bits QAi and / QAi applied to NAND decode circuit 60a is determined by the address of the memory block corresponding to the power supply switch circuit controlled by power supply block selection signal φBi.

  Latch 61 conducts when count-up instruction signal CUP is activated (at the H level), and latches a transfer gate 61a that passes the output signal of NAND-type decode circuit 60a, and a signal applied via transfer gate 61a. Inverters 61b and 61c constituting a latch circuit for performing the above are included. Inverters 61b and 61c are arranged in antiparallel or input and output are cross-coupled to form a so-called inverter latch.

  Latch 62 is turned on when complementary refresh cycle activation signal / QACT is activated, and includes a transfer gate 62a for passing the output signal of latch 61, and a latch circuit for latching a signal applied via transfer gate 62a. Inverters 62b and 62c to be configured, and an AND circuit 62d which is activated when refresh cycle activation signal QACT is activated and generates power supply block selection signal φBi in accordance with the output signal of inverter 62a are included. Inverters 62b and 62c constitute a so-called inverter latch.

  In the configuration shown in FIG. 38, power supply block decode circuit 60 decodes refresh address bits QAi and / QAi from the refresh address counter and outputs a signal indicating the decoding result. In latch 61, transfer gate 61a is rendered conductive when count-up instruction signal CUP is activated, and a power supply block selection signal newly generated by activation of count-up instruction signal CUP is passed. Inverters 61b and 61c The newly generated power supply block selection signal is latched. During the refresh cycle, complementary refresh cycle activation signal / QACT is inactive, and the latch content of latch 62 does not change regardless of the change in the output signal of latch 61.

  During the refresh cycle, AND circuit 62d operates as a buffer and outputs a power supply block selection signal latched by inverters 62b and 62c. When the refresh cycle is completed and refresh cycle activation signal QACT becomes inactive at L level, AND circuit 62d is disabled and power supply block selection signal φBi becomes inactive at L level. As a result, all the power switch circuits are in a non-selected state, and current consumption is reduced. On the other hand, complementary refresh cycle activation signal / QACT becomes H level active state, transfer gate 62a conducts, takes in and latches the signal latched by latch 61, and latches a new power supply block selection signal.

  The power supply block selection signal can be generated and latched by decoding the refresh address in the next cycle without adversely affecting the refresh operation in the current cycle.

  FIG. 39 is a diagram showing an example of the configuration of a 1-bit register circuit of register 65 shown in FIG. In FIG. 39, a register 60 is turned on when the count-up instruction signal φCUP is activated, and a transfer gate 65a that allows a count bit from the refresh address counter to pass therethrough, and a latch circuit that latches a signal applied via the transfer gate 65a. Inverters 65b and 65c, inverter 65d that inverts the output signal of inverter 65b, and an AND circuit that is activated when refresh cycle activation signal QACT is activated and generates refresh address bit QAi according to the output signal of inverter 65d 65e is included.

  In the configuration of register 65 shown in FIG. 39, the refresh address bit latched by inverters 65b and 65c is updated when count-up instruction signal φCUP is activated. When refresh cycle activation signal QACT is activated, refresh address bit QAi used in the current cycle is generated in accordance with the latched refresh address bit.

  When the multiplexer 26 is provided before the row address buffer / latch, the AND circuit 65e need not be provided. This is because the row address buffer / latch has a function of keeping the internal row address signal bit in an inactive state during the standby cycle.

  FIG. 40 schematically shows a structure for generating count-up instruction signals CUP and φCUP. In FIG. 40, the count-up instruction signal generator generates a one-shot pulse signal in response to the delay circuit 67 delaying the refresh cycle activation signal QACT for a predetermined period and the rise of the output signal of the delay circuit 67. A pulse generation circuit 68, an inverter circuit 69 that inverts the refresh cycle activation signal QACT, and a one-shot pulse generation circuit 70 that generates a one-shot pulse signal in response to the rise of the output signal of the inverter circuit 69 are included. The one-shot pulse generation circuit 68 outputs a count-up instruction signal CUP, and the one-shot pulse generation circuit 70 generates a count-up instruction signal φCUP. By setting the delay time of the delay circuit 67 to an appropriate value, it is possible to cause the refresh address counter to perform a count-up operation at an appropriate timing within the refresh cycle period. The activation period of the count-up instruction signals CUP and φCUP may be set to an appropriate period according to the latch capability of each circuit.

  Note that the count-up instruction signal generator may be included in the refresh instruction control circuit 23 shown in FIG.

  In hierarchical power supply configuration 3, power supply block selection signal φBi is set to the H level when in the selected state. However, the logic level in the selected state of power supply block selection signal φBi is appropriately determined according to the voltage level of the applied voltage supply line. For example, when the power switch circuit is provided between the main ground line and the sub ground line, this power block selection signal φBi is at the H level when selected, but the power switch circuit is connected to the main power line. And power supply block selection signal φBi is at the L level when selected.

  In the configuration shown in FIG. 36, in the normal mode, selector 63 selects row address signal bit RA1 from multiplexer 26 in accordance with self-refresh mode instruction signal SR. Therefore, a global block is selected according to row address signal bit RA1.

  As described above, according to hierarchical power supply configuration 3 in the sixth embodiment of the present invention, in the self-refresh mode, the source block selection signal used in the next cycle is incremented and the count value of the refresh address counter is incremented in the current cycle. It is generated by latching the decoding result after generating and decoding. Therefore, the decoding operation of the power supply block selection signal is completed at the start of the next cycle, and the state of the power supply block selection signal φBi can be set at a high speed in the next cycle, and the word line at the early timing in the refresh cycle can be set. Can be driven to the selected state. Therefore, it is not necessary to make the activation timing of the word line different between the refresh mode and the normal mode, and the configuration of the word line driver is simplified.

[Embodiment 7]
[Hierarchical power supply configuration 1]
FIG. 41 schematically shows a structure of the array portion of the semiconductor memory device according to the seventh embodiment of the present invention. In FIG. 41, the memory mat is divided into eight memory blocks MAB1 to MAB8. Memory blocks MAB2-MAB8 include normal memory blocks NMAB2-NMAB8 including normal memory cells, respectively. Memory block MAB1 includes a normal memory block NMAB1 and a spare block SPB including a spare element for relieving a defective memory cell. Memory block MAB1 corresponds to block RBX # formed of the normal memory sub-array and spare array shown in FIG.

  Power switch circuits SW1 to SW8 are provided corresponding to memory blocks MAB1 to MAB8, respectively. These power supply switch circuits SW1 to SW8 are driven to a selected state in accordance with power supply block selection signals φB1 to φB8, as in the sixth embodiment. Spare block SPB of memory block MAB1 is shared by normal memory blocks NMAB1 to NMAB8, and defective cells (defective rows) in any normal memory block can be repaired by replacement. It is assumed that block address bits RA1 to RA3 and QA1 to QA3 are assigned to the memory blocks MAB1 to MAB8 in the same manner as in the sixth embodiment.

  First, the operation in the normal mode will be described with reference to FIG. In this normal mode, power switch circuit SW1 provided for memory block MAB1 including spare block SPB is driven to the selected state regardless of the applied address signal (row address signal). Further, before the spare determination, the power switch circuit for the memory block including the addressed word line WL is also driven to the selected state. FIG. 42 shows a state in which memory block MAB2 includes addressed word line WL. In other memory blocks, the power switch circuit is held in a non-selected state. A spare determination as to whether the defective memory cell is addressed is then made based on the address comparison, and the addressed word line or spare word line is driven to the selected state according to the determination result.

  Before the spare determination, the power switch circuit for the memory block including the memory cell to be selected (the addressed word line or the memory block including the spare word line) is driven to the selected state. Therefore, when the word line is actually driven to the selected state in the memory block including the memory cell to be selected, the predetermined voltage is stably supplied, and the memory cell to be selected is accurately driven to the selected state. can do. This operation will be described in more detail with reference to the signal waveform diagram shown in FIG.

  First, when the active cycle starts, array activation signal RACT is driven to an active state of H level. In accordance with the activation of array activation signal RACT, row address signal RA is determined, and the addressed memory block is designated. In accordance with activation of array activation signal RACT, power supply block selection signal φB1 for memory block MAB1 including the spare block is driven to an active state regardless of applied row address signal RA. One of memory blocks MAB2-MAB8 is selected according to address signal RA, and one of corresponding power supply block selection signals φB2-φB8 is driven to a selected state. In accordance with row address signal RA, a spare determination is made as to whether or not a defective row has been designated. When the spare determination result indicates that the defective row is addressed (spare hit), the spare word line SWL included in the spare block SPB is driven to the selected state. On the other hand, when it is determined that a normal memory cell is addressed (when a spare miss occurs), normal word line NWL is driven to a selected state.

  When the word line NWL or SWL is driven to the selected state, the corresponding power switch circuit has already been selected to supply a predetermined voltage to the corresponding memory block. Therefore, these word lines NWL or SWL can be accurately driven to the selected state.

  When a memory block is selected according to this spare determination, after a spare hit / miss determination is made, the power switch circuit for the corresponding memory block is driven to a selected state (shown by a broken line waveform in FIG. 43). After this, it is necessary to drive the word line WL or SWL to the selected state, and therefore it is necessary to delay the word line activation timing, and the access time becomes long. However, before determining whether or not the defective normal word line is addressed, by driving the power switch circuit for the memory block MAB1 including the spare block and the memory block including the addressed normal word line to a selected state. In this spare determination time, a predetermined voltage can be supplied from the corresponding power switch circuit, and a high-speed operation is realized (it is not necessary to delay the word line selection timing).

  Next, the operation in the self-refresh mode will be described with reference to FIGS. In the self-refresh mode, as shown in FIG. 44, the power switch circuit is selected according to the spare determination result. Now, consider the case where the normal word line NWL of the memory block MAB2 is designated by the refresh address signal QA as shown in FIG. Spare determination of whether normal word line NWL is normal or defective is performed by address comparison. At this time, the decoding operation for selecting the power switch circuit is also performed in parallel, but all the power block selection signals are held in the non-selected state. When a spare hit is determined, it is necessary to drive spare word line SWL to a selected state instead of normal word line NWL. In this case, the power switch circuit SW1 is driven to the selected state according to the spare hit determination result. The remaining power switch circuits SW2-SW8 are held in a non-selected state. In accordance with this spare hit determination result, spare word line SWL is driven to a selected state, and normal word line NWL is held in a non-selected state.

  On the other hand, when the spare determination result indicates a spare miss, power switch circuit SW2 is driven to the selected state, and normal word line NWL is driven to the selected state.

  Since no data access is required in the refresh mode, there is no particular problem even if the power switch circuit is driven to the selected state after the spare determination. By driving only the power switch circuit for the memory block to which the memory cell to be selected belongs to the selected state, current consumption in the refresh mode can be reduced.

  FIG. 46A shows an example of the configuration of a power supply block decoding circuit that generates power supply block selection signal φB1. 46A, a power supply block decode circuit includes a NAND circuit 71 receiving refresh address bits / QA1, QA2 and QA3, a complementary array activation signal / RACT, a complementary spare hit signal / SHIT and a NAND circuit 71. A NAND circuit 72 that receives the output signal and outputs power supply block selection signal φB1 is included. Array activation signal / RACT is set to L level when the active cycle starts in the normal mode. Spare hit signal / SHIT is set to L level when a defective cell is addressed. NAND circuit 71 outputs an L level signal when memory block MAB1 is designated. Next, the operation of the power supply block decoding circuit shown in FIG. 46A will be described with reference to the signal waveform diagram shown in FIG.

  In the normal mode, when the active cycle starts, complementary array activation signal / RACT is driven to L level. Therefore, regardless of the state of spare hit signal / SHIT and the output signal of NAND circuit 71, power supply block selection signal φB1 is driven to the active state. That is, in the normal mode, when the active cycle starts, power supply block selection signal φB1 is driven to the selected state.

  In the refresh mode, array activation signal / RACT is fixed at the H level. In the refresh cycle, refresh cycle activation signal QACT is driven to an active state of H level, and accordingly, refresh address signal QA is determined. Spare determination is made, and in the case of a spare hit, spare hit signal / SHIT attains L level and power supply block selection signal φB1 is driven to a selected state of H level. Next, the spare word line of the spare block is driven to the selected state.

  On the other hand, when spare hit signal / SHIT is at the H level and it is not necessary to perform spare replacement, power supply block selection signal φB1 is driven to the selected / unselected state in accordance with the output signal of NAND circuit 71. When memory block MAB1 is addressed, the output signal of NAND circuit 71 attains an L level, and accordingly, power supply block selection signal φB1 is driven to a selected state (H level). On the other hand, when any of the other memory blocks MAB2-MAB8 is addressed, the output signal of NAND circuit 71 is at the H level, and power supply block selection signal φB1 maintains the L level.

  In the configuration of the power supply block decoding circuit shown in FIG. 46A, when spare hit signal / SHIT is at L level, the output signal of NAND circuit 71 is at L level, and corresponding memory block MAB1 is addressed. There is no particular problem. In this case, it is a spare hit and the memory block MAB1 is selected. In order to drive the power supply block selection signal φB1 to the selected / unselected state after the state of the spare hit signal / SHIT is determined, the spare hit signal SHIT may be further supplied to the NAND circuit 71. After the spare hit / miss determination result is confirmed, the output signal of NAND circuit 71 is confirmed, and accordingly, power supply block selection signal φB1 is driven to the selected state.

  FIG. 47A shows a configuration of a power supply block decoding circuit for power supply block selection signal φBj (j = 2-8). 47A, a power supply block decode circuit includes an inverter circuit 73 that inverts self-refresh mode instruction signal / SR, and a NAND circuit 74 that receives a predetermined combination of refresh address bits QA1-QA3 and / QA1- / QA3. NAND circuit 75 receiving a predetermined combination of self-refresh mode instruction signal / SR and row address bits RA1-RA3 and / RA1- / RA3, output signal SR of inverter circuit 73, output signal of NAND circuit 74, and spare hit signal NAND circuit 76 that receives / SHIT, and a NAND circuit 77 that receives the output signals of NAND circuits 75 and 76 and generates power supply block selection signal φBj (j = 2-8). Instead of self-refresh mode instruction signal / SR, refresh cycle activation signal / QACT may be used. Next, the operation of the power supply block decoding circuit shown in FIG. 47A will be described with reference to the signal waveform diagram shown in FIG.

  In the normal mode, when the array activation signal RACT is activated, the row address signal RA is determined. When row address signal RA is determined, in the normal mode, self-refresh mode instruction signal / SR is at H level, so that the output signal of NAND circuit 75 is H in accordance with row address bits RA1-RA3 and / RA1- / RA3. Level or L level. Since the output signal of NAND circuit 76 is at the H level in the normal mode, power supply block selection signal φBj is driven to the selected / unselected state in accordance with the output signal of NAND circuit 75.

  On the other hand, in the self-refresh mode, self-refresh mode instruction signal / SR is at L level, and the output signal of NAND circuit 75 is set at H level. Self-refresh mode instruction signal SR is at H level. In the self-refresh mode, when refresh cycle activation signal QACT is driven to an active state of an H level, refresh address signal QA is determined. Spare determination is performed according to refresh address signal QA, and spare hit signal / SHIT is driven to H level or L level. At the time of spare hit, spare hit signal / SHIT is at L level, the output signal of NAND circuit 76 is at H level, and power supply block selection signal φBj is maintained at L level. On the other hand, if the spare determination results in a spare miss, spare hit signal / SHIT maintains the H level. Therefore, power supply block selection signal φBj is driven to the selected / unselected state in accordance with the output signal of NAND circuit 74.

  In the configuration shown in FIG. 47A, in order to prevent the power supply block selection signal φBj from being driven to the selected state in accordance with the output signal of the NAND circuit 74 before the spare determination result is determined, Spare hit signal SHIT may be provided as an input.

[Example of change]
FIG. 48 is a diagram showing a configuration of a modified example of the hierarchical power supply configuration 1. In the configuration shown in FIG. 48, word line drive timing control circuit 78 varies the activation timing of word line drive signal φWL in accordance with self-refresh mode instruction signal SR. Word line drive timing control circuit 78 generates word line drive signal φWL in accordance with word line activation signal φRX in the normal mode. On the other hand, in the self refresh mode, word line drive signal φWL is generated by delaying word line activation signal φRX. The configuration of this word line drive timing control circuit 78 is the same as that shown in FIG. By using the word line drive timing control circuit 78, even when the activation timing of the power supply block selection signal φBi is delayed in the self-refresh mode, the word line selection timing can be delayed accordingly to accurately select the word line. Operation can be performed. This word line drive signal φWL determines the activation timing of both the spare word line and the normal word line.

[Modification 2]
FIG. 49 shows a structure of a second modification of the hierarchical power supply structure 1 according to the seventh embodiment of the present invention. FIG. 49 shows the configuration of the power supply block selection signal generation unit. In FIG. 49, a power supply block selection signal generating unit selects a self-refresh address from refresh address counter 25 and an internal row address signal RA from multiplexer 26 in response to self-refresh mode instruction signal SR; OR circuit 81 that receives array activation signal RACT and count-up instruction signal CUP, and spare determination that is activated in response to activation of the output signal of OR circuit 81 and performs spare determination for the address signal applied from multiplexer 80 Power supply block decode circuit 8 which decodes a power supply block address signal in accordance with circuit 82, address signal from multiplexer 80, self-refresh mode instruction signal SR and spare hit signal SHIT from spare determination circuit 82 A latch 84 for latching the power supply block selection signal output from the power supply block decode circuit 83 according to the count-up instruction signal CUP, a latch 85 for taking in and transferring the latch signal of the latch 84 in response to the refresh cycle activation signal QACT, A multiplexer (MUX) 86 for selecting one of the output signal of latch 85 and the output signal of power supply block decode circuit 83 in accordance with self-refresh mode instruction signal SR is included.

  The configuration of power supply block decode circuit 83 is the same as that shown in FIGS. 46A and 47A, and a power supply block is selected according to self-refresh mode instruction signal SR, spare hit signal SHIT and row address signal RA or QA. A signal φBi is generated. The latches 84 and 85 have the same configuration as that shown in FIG. 38. When the count-up instruction signal is activated, latch 84 takes in and latches the output signal of power supply block decode circuit 83, and latch 85 refreshes refresh cycle activation signal QACT. When inactive, the output signal of latch 84 is taken in and latched, and then the latched signal is output in response to activation of refresh cycle activation signal QACT.

  Multiplexer 86 selects and outputs the output signal of latch 85 in the self-refresh mode, and selects the output signal of power supply block decode circuit 83 in the normal mode. Power supply block selection signal φBi from multiplexer 86 is applied to the power switch circuit.

  The power supply block selection signal generator further takes in and transfers a latch 87 that latches spare hit signal SHIT output from spare determination circuit 82 in accordance with count-up instruction signal CUP and an output signal of latch 87 in accordance with refresh cycle activation signal QACT. And a multiplexer (MUX) 89 that selects one of the spare hit signal SHIT output from the spare determination circuit 82 and the signal output from the latch 88 in accordance with the self-refresh mode instruction signal SR. The latches 87 and 88 have the same configuration as the latches 84 and 85.

  Multiplexer 26 selects refresh address signal QA from register 65 in the self-refresh mode, and selects external row address signal RA in the normal mode. The refresh address counter 25 and the register 65 are the same as those shown in FIG.

  In the configuration shown in FIG. 49, in the previous refresh cycle, spare determination and power supply block decoding operation in the next cycle are executed. These determination results and decoding results are output in the next refresh cycle. Therefore, the decoding operation has already been completed in the previous cycle, and power supply block selection signal φBi and spare hit signal SHIT can be driven to the selected / unselected state at high speed when the next refresh cycle is executed. Thereby, it is not necessary to delay the word line selection timing in the refresh cycle, and the configuration of the word line drive control unit can be simplified.

Te is the normal mode smell, the multiplexer 80 selects and applies the internal address signal Ad from the multiplexer 26 to the power supply block decode circuit 83 of spare determination circuit 82. Spare hit signal SHIT output from spare determination circuit 82 is selected and output by multiplexer 89, and a power supply block selection signal output from power supply block decode circuit 83 is selected and output by multiplexer 86. Latches 84, 85, 87 and 88 are bypassed in this normal mode. Therefore, when the array activation signal is activated, spare determination circuit 82 performs a determination operation, and spare hit signal SHIT is generated according to the determination result. In the normal mode, power supply block decode circuit 83 decodes the address signal from multiplexer 80 regardless of spare hit signal SHIT, and provides power supply block for memory block MAB1 including the spare block and the addressed memory block. Drive the selection signal to the selected state.

  By using the configuration shown in FIG. 49, the current consumption in the self-refresh mode can be reduced without increasing the access time in the normal mode.

  As described above, according to the hierarchical power supply configuration of the seventh embodiment of the present invention, in the normal mode, the memory block including the spare block and the addressed memory block are driven to the selected state regardless of the spare determination result. In the refresh mode, the power switch circuit for the addressed memory block is driven to the selected state. In the normal mode, the voltage from the power switch circuit is stably supplied before the spare determination result is determined. In the refresh mode, a predetermined voltage is supplied only to the minimum necessary memory blocks, so that current consumption can be reduced.

[Hierarchical power supply configuration 2]
50A and 50B are diagrams illustrating the operation of hierarchical power supply configuration 2 according to the seventh embodiment of the present invention. In FIG. 50A, in the normal mode, the power supply switch circuit for both memory block MAB1 including spare block SPB and the addressed memory block is driven to a selected state in response to the activation of the array activation signal. FIG. 50A shows a state where the memory block MAB2 is addressed. When the array activation signal RACT is activated and the active cycle starts, the memory block MAB1 including the spare block and the addressed memory block MAB2 are first driven to the selected state, so that it is not necessary to wait for the spare determination result. A desired voltage can be supplied at high speed.

  Next, as shown in FIG. 50B, when the spare determination result is confirmed, only the power switch circuit for the memory block including the memory cell to be selected is driven to the selected state according to the spare determination result. In FIG. 50B, normal word line NWL of memory block MAB2 is driven to the selected state, and power supply switch circuit SW2 is held in the selected state, while power supply switch circuit SW1 for memory block MAB1 is set to the unselected state. Indicates the driven state. After the determination result, normal word line NWL is driven to the selected state. Therefore, when driving the selected normal word line, the voltage is stably supplied from the power switch circuit SW2, and the selected normal word line can be driven to the selected state at high speed and accurately. In addition, since the memory block MAB1 is held in the non-selected state, the power switch circuit SW1 can be driven to the non-selected state to reduce current consumption.

  In the refresh mode, as shown in FIG. 44, only the power switch circuit for the memory cell block including the memory cell to be selected is driven to the selected state, and the remaining power switch circuits are held in the non-selected state. . This reduces current consumption during the refresh cycle.

  FIG. 51A shows a configuration of a power supply block decoding circuit for power supply block selection signal φB1. 51A, a power supply block decode circuit includes a one-shot pulse generation circuit 90 that generates a one-shot L-level pulse signal in response to a fall of array activation signal / RACT, and row address bit / RA1. , RA2 and RA3, a NAND circuit 91 receiving refresh address bits / QA1, QA2 and QA3, an output signal of one-shot pulse generation circuit 90, an output signal of NAND circuits 91 and 92, and a spare hit signal / It includes a NAND circuit 93 that receives SHIT and outputs a power supply block selection signal φB1. Address bits / RA1, RA2, RA3, / QA1, QA2, and QA3 are at the L level during standby. Next, operation of the power supply block decoding circuit shown in FIG. 51A will be described with reference to a signal waveform diagram shown in FIG.

  When the active cycle starts, array activation signal / RACT falls to L level. In response to the fall of array activation signal / RACT, one-shot pulse generation circuit 90 generates a one-shot pulse signal that is L level for a predetermined period. In response, power supply block selection signal φB1 output from NAND circuit 93 rises to the H level. On the other hand, NAND circuit 91 decodes applied address bits / RA1, RA2 and RA3. When memory block MAB1 is addressed, the output signal of NAND circuit 91 attains L level, and power supply block selection signal φB1 output from NAND circuit 93 is driven to H level. In this state, power supply block selection signal φB1 is at the H level during this active cycle regardless of whether the spare word line is used.

  On the other hand, when a memory block different from memory block MAB1 is addressed, the output signal of NAND circuit 91 is at H level. In this state, before the output signal of one shot pulse generation circuit 90 rises to H level, spare hit signal SHIT is driven to H level or L level according to the spare determination result. When the normal word line is used, spare hit signal / SHIT is kept at the H level. Therefore, in this state, power supply block selection signal φB1 falls to the L level in response to the rise of the output signal of one shot pulse generation circuit 20. Row selection is performed in this memory block.

  On the other hand, when spare hit signal / SHIT falls to L level while the output signal of NAND circuit 91 is at H level and another memory block is designated, power supply block selection signal φB1 holds H level. To do. By setting the pulse width of the pulse signal output from this one-shot pulse generation circuit 90 to a time width for the spare hit signal / SHIT to be in a definite state, the power supply block selection signal φB1 is used for the corresponding memory block MAB1. / It can be driven to the selected / unselected state according to the non-use.

  FIG. 52 shows a structure of a power supply block decoding circuit for power supply block selection signal φBj (j = 2-8). The power supply block decode circuit shown in FIG. 52 differs from the power supply block decode circuit shown in FIG. 47A in the following points. That is, between the NAND circuit 75 and the NAND circuit 77, an OR circuit 94 that receives the output signal of the NAND circuit 75 and the spare hit signal SHIT is arranged. Other structures are the same as those shown in FIG. 47A, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  In the configuration of the power supply block decoding circuit shown in FIG. 52, power supply block selection signal φBi is driven to the selected / unselected state at the start of the active cycle in accordance with address bits RA1-RA3 and / RA1- / RA3. When spare bit signal SHIT is at L level, power supply block selection signal φBi is held in a state according to address bits RA1-RA3 and / RA1- / RA3 during the active cycle period. On the other hand, when spare hit signal SHIT is driven to H level, the output signal of OR circuit 94 becomes H level. In the normal mode, the output signal of NAND circuit 76 is at the H level. Therefore, in response to the rise of spare hit signal SHIT, power supply block selection signal φBj falls to the L level. Thus, when the spare word line is used, only the power switch circuit for the memory block including the spare block is driven to the selected state, and the power switch circuit for the memory block including the addressed defective normal word line is not selected. Driven to state.

  The operations in the refresh mode of the power supply block decode circuits shown in FIGS. 51A and 52 are the same as the operations of the power supply block decode circuits shown in FIGS. 46A and 47A. Their operation waveforms are the same as the signal waveforms shown in FIGS. 46 (B) and 47 (B), respectively. That is, in the refresh cycle, the power switch circuit is driven to the selected state only for the memory cell block including the memory cell row to be driven to the selected state.

  In addition, the circuit configuration shown in FIG. 49 can be used for the configuration of the power supply block decoding circuit shown in FIGS. That is, in the refresh mode, the selection / non-selection state of the power supply block selection signal in the next cycle can be determined according to the refresh address signal from the refresh address counter in the previous cycle.

  As described above, according to the seventh embodiment, in the normal mode, the addressed memory block is driven to the selected state, and then power is supplied only to the memory block including the memory cell row to be selected. Since the switch circuit is held in the selected state, current consumption during the active cycle can be reduced. Simultaneously with the start of the active cycle, the power switch circuit for the memory block including the addressed memory block and the spare block is driven to the selected state, thereby preventing an increase in access time.

  In the above description, the memory block including the spare word line is described. However, this hierarchical power supply configuration can also be used for the configuration for repairing the spare column.

  In the seventh embodiment, it is described that there is one memory block including a spare block. However, the hierarchical power supply configuration of the seventh embodiment can also be applied to the first to fifth embodiments. The repeating circuit may be a sense amplifier that detects and amplifies memory cell data.

  As described above, according to the present invention, the spare line can be replaced with the normal line of a plurality of memory blocks, so that the spare line can be used efficiently and flexible redundancy is achieved. Since the configuration is used, the number of spare decoders can be reduced, and an increase in array area can be suppressed.

  In addition, a power switch circuit is provided for each memory block, and the number of power switch circuits driven to the selected state is different between the normal mode and the refresh mode, so that the current consumption can be reduced without reducing the access time. Can be reduced. In the configuration including the spare block, the power switch circuit for the memory block including the spare block is always driven to the selected state in response to the start of the active cycle. A predetermined voltage can be supplied from the power switch circuit, and an increase in access time can be suppressed.

The present invention can be applied to a semiconductor memory device for repairing defective cells having an array division structure.

1 schematically shows a structure of a main portion of the semiconductor memory device according to the first embodiment of the invention. FIG. (A) is a diagram showing a defective column relief mode of the memory array shown in FIG. 1, and (B) is a diagram schematically showing a configuration of a spare decoder for defective column relief. (A) shows a modified example of the spare decoder, and (B) is a diagram showing an aspect of defective column relief by the spare decoder shown in (A). FIG. 2 schematically shows a configuration of an internal data reading unit in the array arrangement shown in FIG. 1. FIG. 11 schematically shows a structure of a main portion of a semiconductor memory device according to the second embodiment of the present invention. FIG. 6 is a diagram schematically showing a connection mode of a normal local data bus and a normal global data bus and a connection mode of a spare local data bus and a spare global data bus in the memory array shown in FIG. 5. It is a figure for demonstrating the method for generating a spare local data bus selection signal. FIG. 6 schematically shows a configuration of a column selection unit of a spare array of the memory array shown in FIG. 5. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device according to Embodiment 3 of this invention. FIG. 10 is a diagram showing an example of a defective row relief mode in the memory array shown in FIG. 9. It is a figure which shows roughly the structure of the array part of the semiconductor memory device of Embodiment 4 of this invention. FIG. 12 is a diagram for explaining the effect of the memory block arrangement shown in FIG. 11. FIG. 13 is a diagram schematically showing a configuration of a bit line isolation instruction signal generation unit for solving the problems of the configuration shown in FIG. 12. FIG. 12 schematically shows a configuration of a bit line isolation instruction signal generation unit in the memory block arrangement shown in FIG. 11. It is a figure which shows roughly the replacement aspect of the spare line and defective normal line in Embodiment 4 of this invention. It is a figure which shows the structure of a memory cell. FIG. 11 schematically shows a configuration of an array portion of a semiconductor memory device according to a fifth embodiment of the present invention. (A) is a diagram showing a correspondence relationship between the address signal bits in the normal operation mode and the selected memory unit in the array arrangement shown in FIG. 17, and (B) is a diagram showing the address signal bits and the selected memory block in the test mode. It is a figure which shows roughly the correspondence of these. FIG. 19 is a diagram schematically showing an example of a configuration of a control unit for memory block selection in the test mode shown in FIG. 18B. It is a figure which shows schematically the structure of the example of a change of Embodiment 5 of this invention. (A) is a figure which shows roughly the hierarchy power supply structure 1 according to Embodiment 6 of this invention, (B) is a figure which shows the structure of the power switch circuit of the row-system peripheral circuit shown to (A). is there. It is a figure which shows roughly arrangement | positioning of the memory array and memory switch circuit in Embodiment 6 of this invention. (A) shows the selection mode of the power supply switch circuit in the normal mode of hierarchical power supply configuration 1 according to the sixth embodiment of the present invention, and (B) is a diagram showing its operation waveform. It is a figure which shows schematically the selection aspect at the time of the refresh mode of the hierarchical power supply structure shown in FIG. It is a figure which shows roughly the structure of the row type | system | group control part of the semiconductor memory device in Embodiment 6 of this invention. FIG. 22 is a diagram showing an example of a configuration of a power supply block decoder shown in FIG. 21. FIG. 11 is a diagram showing a configuration of a power supply block decoding circuit for a power supply block selection signal φB2. It is a figure which shows roughly distribution of the address bit in the hierarchical power supply structure 1 in Embodiment 6 of this invention. It is a figure which shows the example of a change of the hierarchical power supply structure of Embodiment 6 of this invention. FIG. 30 is a signal waveform diagram representing an operation of the hierarchical power supply configuration shown in FIG. 29. It is a figure which shows an example of a structure of the repetition circuit of the row-system peripheral circuit in the example of a change of hierarchy power supply structure. It is a figure which shows the selection mode of the power switch circuit at the time of the normal mode and refresh mode of hierarchy power supply structure 2 of Embodiment 6 of this invention. It is a figure which shows schematically the structure of the power supply block decoder with respect to FIG. 32 (A) and (B). FIG. 11 is a diagram showing a configuration of a power supply block decoding circuit for a specific power supply block selection signal φB2. It is a figure which shows roughly the structure of the example of a change of the hierarchy power supply structure 2 of Embodiment 6 of this invention. It is a figure which shows roughly the structure of the control part of the hierarchical power supply structure 3 of Embodiment 6 of this invention. It is a signal waveform diagram which shows operation | movement of the hierarchical power supply structure 3 of Embodiment 6 of this invention. FIG. 37 is a diagram showing an example of a configuration of a power supply block decoder shown in FIG. 36. FIG. 37 is a diagram illustrating an example of a configuration of a register illustrated in FIG. 36. FIG. 37 schematically shows an example of the configuration of a count-up instruction signal generator shown in FIG. 36. It is a figure which shows roughly the arrangement | positioning of the hierarchical power supply structure 1 of Embodiment 7 of this invention. It is a figure which shows roughly the selection mode of the power switch circuit at the time of the normal mode in the hierarchical power supply structure 1 of Embodiment 7 of this invention. FIG. 43 is a signal waveform diagram representing an operation when the memory switch circuit shown in FIG. 42 is selected. It is a figure which shows schematically the power switch circuit selection mode at the time of the refresh mode of hierarchical power supply structure 1 of Embodiment 7 of this invention. FIG. 45 is a signal waveform diagram representing an operation for the memory switch circuit selection mode shown in FIG. 44. (A) shows an example of the structure of the power supply block decoder of hierarchical power supply structure 1 of Embodiment 7 of this invention, (B) is a signal waveform diagram which shows operation | movement of the power supply block decoder circuit shown to (A). is there. (A) shows the structure of the power supply block decoder of hierarchical power supply structure 1 of Embodiment 7 of this invention, (B) is a signal waveform diagram which shows the operation | movement of the power supply block decoder shown to (A). It is a figure which shows schematically the structure of the example of a change of the hierarchical power supply structure 1 of Embodiment 7 of this invention. It is a figure which shows schematically the structure of the control part of the hierarchical power supply structure 1 of Embodiment 7 of this invention. (A) And (B) is a figure which shows schematically the selection mode of the power switch circuit of the hierarchical power supply structure 2 of Embodiment 7 of this invention. (A) shows an example of the structure of the power supply block decoding circuit of the hierarchical power supply structure 2 of Embodiment 7 of this invention, (B) is a figure which shows the operation | movement waveform. It is a figure which shows the structure of the power supply block decoder of the hierarchical power supply structure 2 of Embodiment 7 of this invention. It is a figure which shows schematically the structure of the array part of the semiconductor memory device of the conventional flexible row redundancy structure. It is a figure which shows schematically the structure of the array part of the conventional flexible column redundancy. It is a figure which shows an example of the conventional hierarchical power supply structure. FIG. 56 is a waveform diagram showing an operation of the hierarchical power supply configuration shown in FIG. 55.

Explanation of symbols

  RB # 0-RB # m memory block, MB # 00-MB # mn normal memory sub-array, LIO00-LIOmn normal local data bus, SP # 0-SP # m spare array, SIO0-SIOm spare local data bus, NGIO0-NGIOn Normal global data bus, SGIO spare global data bus, BSG block selection gate, SD00 to SD0m, SD30 to SD3m spare decoder, SPD spare decoding circuit, Y0 to Yn column decoding circuit, SD00 to SD0n, SD30 to SD3n spare decoder, BSGs spare Block selection gate, CB # 0 to CB # n column block, SB # spare block, MA # 0 to MA # m normal memory subarray, SPX # spare array, RBX # 0 to RBX # m row block, MA # 0-0 to MA # 0-N, MA # 1-0 to MA # 1-N normal memory subarray, SPX # 0, SPX # 1 spare array, SAB0 to SABm + 1 sense Amplifier band, MB # 00-0 to MB # 00-N, MB # 01-0 to MB # 01-N, MB # 10-0 to MB # 10-N, MB # 11-0 to MB # 11-N Normal memory subarray, SPX # 00, SPX # 01, SPX # 10, SPX # 11 Spare array, B # 0, B # 1 memory mat, B # 00, B # 01, B # 10, B # 11 memory block group 1 main voltage supply line, 2a to 2n, 2 memory block, 3a to 3n, 3 row peripheral circuit, 4a to 4n, SW1-SW8 power switch circuit, 5a-5n sub voltage supply line, 6 power block deco , WLa-WLm word line, 11a-11m NAND type decode circuit, 12a-12m inverter type word line drive circuit, 14p, 14n power switch transistor, MAB1-MAB8 memory block, GAB0, GAB1 global block, 22 refresh mode detection Circuit, 23 refresh control circuit, 24 timer, 25 refresh address counter, 26 multiplexer, 27 row system control circuit, 30 OR circuit, 31 word line activation signal generation circuit, 32 delay circuit, 33 selector, 40 word line decode signal generation Circuit, 50 row selection circuit, 60 power supply block decode circuit, 61, 62 latch, 63 selector, 65 register, NMAB1-NMAB8 normal memory block, 78 word lines Operation timing control circuit, 80 multiplexer, 82 spare determination circuit, 83 power supply block decoding circuit, 84, 85, 87, 88 latch, 86, 89 multiplexer (MAX), 90 one-shot pulse generation circuit, 91, 92, 93 NAND circuit 94 OR circuit, 74, 75, 76, 77 NAND circuit.

Claims (1)

A plurality of first memory blocks each having a plurality of normal memory cells arranged in a matrix ;
A plurality of first rows arranged in a matrix in a specific first memory block of the plurality of first memory blocks and each row replaceable with a defective row including a defective normal memory cell of the plurality of first memory blocks. Spare memory cells,
A plurality of second memory blocks each having a plurality of normal memory cells, each of which is alternately arranged with the plurality of first memory blocks along a column direction, and each of which is arranged in a matrix;
A plurality of second rows arranged in a matrix in a specific second memory block of the plurality of second memory blocks and each row being replaceable by a defective row including a defective normal memory cell of the plurality of second memory blocks. Spare memory cells, and
Arranged between each of the plurality of first memory blocks and each of the plurality of second memory blocks and shared by the first and second memory blocks adjacent in the column direction, and when activated, A semiconductor memory device comprising a plurality of shared sense amplifier type sense amplifier bands for detecting and amplifying data in each column of a memory block including a selected memory cell.

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