JP4794400B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that reduces the influence of noise received by a circuit inside the semiconductor device.

  A conventional semiconductor device that can reduce the influence of noise on the internal circuit is disclosed in, for example, Japanese Patent Laid-Open No. 5-128855.

FIG. 28 is a schematic block diagram showing a conventional semiconductor device.
28, the conventional semiconductor device 5 includes a package frame 1, a bonding wire 3, a pad 11, an internal power supply line 1511, an internal circuit 21, a stabilization circuit 23, a GND package frame 7, a GND bonding wire 9, a GND pad 17, and an internal structure. It consists of a GND line 19.

  One end of the bonding wire 3 is connected to the package frame 1. The other end of the bonding wire 3 and the internal power supply line 1511 are connected to the pad 11. Internal power supply line 1511 is connected to internal circuit 21 and stabilization circuit 23. One end of the GND bonding wire 9 is connected to the GND package frame 7. The other end of the GND bonding wire 9 and the internal GND line 19 are connected to the GND pad 17. The internal GND line is connected to the internal circuit 21 and the stabilization circuit 23.

  A power supply potential is supplied to the internal circuit 21 and the stabilization circuit 23 of the semiconductor device 5 from the outside of the semiconductor device 5 through the package frame 1, the bonding wire 3, the pad 11, and the internal power supply line 1511. From the outside of the semiconductor device 5, the internal circuit 21 and the stabilization circuit 23 of the semiconductor device 5 are connected to the power supply potential supplied through the package frame 1 through the GND package frame 7, the GND bonding wire 9, the GND pad 17 and the internal GND line 19. Different power supply potentials (for example, ground potential) are supplied.

  The internal circuit 21 is a circuit related to the operation inside the semiconductor device 5. That is, it is a circuit that causes noise. For example, a word line driving circuit, a data bus driving circuit, a data output circuit, and the like.

  The stabilization circuit 23 is a circuit that is easily affected by noise. For example, a circuit that operates with a very small current (for example, μA order) or a circuit that controls a signal with a very small analog value when the semiconductor device 5 is in a standby state. The circuit that controls a minute analog value is, for example, a reference potential generation circuit.

  When the internal circuit 21 operates, the internal circuit 21 consumes a considerable amount of power. For this reason, noise appears on the internal power supply line 1511 and the internal GND line 19.

  FIG. 29 is a diagram illustrating the level of noise generated when the internal circuit 21 of the semiconductor device 5 operates.

  As indicated by an arrow a, noise having a level lower than the level of the power supply potential Vcc is generated in the internal power supply line 1511. As indicated by an arrow b, noise having a level higher than the level of the ground potential GND is generated in the internal GND line 19.

Further, when such noise is propagated to the stabilization circuit 23, the noise is somewhat reduced by a low-pass filter composed of the wiring resistance and parasitic capacitance of the internal power supply line 1511 or a low-pass filter composed of the wiring resistance and parasitic capacitance of the internal GND line 19. Is absorbed, but the influence on the stable circuit 23 is large.
JP-A-5-128855

As described above, in the conventional semiconductor device 5, the power supply line for supplying the power supply potential Vcc to the internal circuit 21 and the stabilization circuit 23 is shared. That is, power supply potential Vcc is supplied to internal circuit 21 and stabilization circuit 23 by internal power supply line 1511. For this reason, noise accompanying the operation of the internal circuit 21 is supplied to the stabilization circuit 23 together with the power supply potential Vcc. Therefore, there is a problem that the stabilization circuit 23 malfunctions.

  The ground potential GND is supplied to the internal circuit 21 and the stabilization circuit 23 through the internal GND line 19. Therefore, noise accompanying the operation of the internal circuit 21 is supplied to the stabilization circuit 23 together with the ground potential GND. Therefore, there is a problem that the stabilization circuit 23 malfunctions.

  The present invention has been made to solve the above problems, and reduces the influence of noise from the internal circuit that causes noise, which is received by the internal circuit (stable circuit) that is susceptible to noise. An object of the present invention is to provide a semiconductor device that can be used.

  Another object of the present invention is to provide a semiconductor device capable of facilitating voltage exchange at an arbitrary point on the semiconductor device.

The present invention of claim 1, generating a first internal circuit causing noise, and a second internal circuit being affected by noise, the first internal potential supplied to the first internal circuit Generating a first internal potential generating means, a first internal potential supply line for supplying the first internal potential to the first internal circuit, and a second internal potential for supplying at least the second internal circuit Second internal potential generating means, a second internal potential supply line for supplying a second internal potential to the second internal circuit, a first internal potential supply line, and the second internal potential supply line And a noise blocking means for blocking noise propagating from the first internal circuit to the second internal circuit via the first internal potential supply line and the second internal potential supply line. .

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first internal potential generating means generates the first internal potential when the semiconductor device is in an operating state, and the noise blocking means is depending on the state of the semiconductor device, comprising the first internal circuit and before Symbol connection control means to control the connection between the first internal voltage supply line and said second internal voltage supply lines.

  According to a third aspect of the present invention, in the second aspect of the present invention, the connection control means includes the first internal circuit and the second internal potential supply line when the semiconductor device is in an operating state. The first internal circuit and the first internal potential supply line are connected to each other, and when the semiconductor device is in a standby state, the first internal circuit and the first internal potential supply line are connected to each other. While disconnecting, the first internal circuit and the second internal potential supply line are connected.

According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the first internal potential generating means is connected to the first internal circuit and the second internal circuit when the state of the semiconductor device is in an operating state. generating a first internal potential supply, noise blocking means is provided between the first and second internal voltage supply lines, Ru provided with a filter to reduce the noise.

  The present invention according to claim 5 is a semiconductor device, wherein the first internal circuit causing the first noise, the second internal circuit affected by the first noise, and the first internal circuit A first internal potential generating means for generating a first internal potential to be supplied to the circuit; a second internal potential generating means for generating a second internal potential to be supplied to the second internal circuit; A potential generating means and a first internal circuit are connected to supply a first internal potential, and a first internal potential supply line, a second internal potential generating means, and a second internal circuit are connected. The second internal potential supply line for supplying the second internal potential, and provided between the first internal potential supply line and the second internal potential supply line, and depending on the state of the semiconductor device, First connection control means for controlling connection between the first internal potential supply line and the second internal potential supply line;

  According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the first connection control means includes the first internal potential supply line when the semiconductor device is in the first state. When the second internal potential supply line is disconnected and the state of the semiconductor device is in the second state, the first internal potential supply line and the second internal potential supply line are connected, and the state of the semiconductor device However, when in the second state, the second internal potential generating means also supplies the second internal potential to the first internal circuit.

  According to a seventh aspect of the present invention, in the sixth aspect of the invention, the first state is an operating state of the semiconductor device, and the second state is a standby state of the semiconductor device. The first internal potential generating means stops.

  In the present invention described in claim 8, in the present invention described in claim 6, the first state is a first operation state of the semiconductor device, and the second state is a second operation of the semiconductor device. State.

  A ninth aspect of the present invention according to the fifth aspect further includes a resistance element connected between the first internal potential supply line and the second internal potential supply line.

  According to a tenth aspect of the present invention, in the fifth aspect of the present invention, a third internal circuit that causes the second noise and a third internal potential supplied to the third internal circuit are generated. Third internal potential generating means, third internal potential generating means and third internal circuit are connected to supply a third internal potential; a third internal potential supply line; a second internal potential supply line; A second internal potential supply line that is provided between the potential supply line and the third internal potential supply line and controls connection between the second internal potential supply line and the third internal potential supply line in accordance with the state of the semiconductor device; And a connection control means.

  According to an eleventh aspect of the present invention, in the invention according to the tenth aspect, the circuit further includes a resistance element connected between the second internal potential supply line and the third internal potential supply line.

  According to a twelfth aspect of the present invention, in the fifth aspect of the invention, a third internal circuit that causes the second noise and a third internal potential supplied to the third internal circuit are generated. Third internal potential generating means, a third internal circuit and third internal potential generating means are connected, a third internal potential supply line for supplying a third internal potential, and a first internal potential supply A second connection that is provided between the first internal potential supply line and the third internal potential supply line, and controls connection between the first internal potential supply line and the third internal potential supply line according to the state of the semiconductor device. And a control means.

  In the first aspect of the present invention, the first internal potential generating means supplies the first internal potential to the first internal circuit through the first internal potential supply line. The second internal potential generating means supplies the second internal potential to the second internal circuit through the second internal potential supply line. As described above, the first internal potential supply line for supplying the first internal potential and the second internal potential supply line for supplying the second internal potential are provided separately. For this reason, noise does not propagate directly from the first internal circuit to the second internal circuit. Further, the first internal potential generating means and the second internal potential generating means function as a filter, and noise transmitted from the first internal circuit to the second internal circuit via the power supply potential supply line can be reduced. it can.

  Furthermore, in the first aspect of the present invention, the third internal potential generating means is configured to pass through the third internal potential supply line and the fifth internal potential supply line when the semiconductor device is in an operating state. A third internal potential is supplied to the first internal circuit. The fourth internal potential generating means supplies the fourth internal potential to the first internal circuit via the fourth internal potential supply line and the fifth internal potential supply line when the semiconductor device is in the operating state or the standby state. Supply internal potential. The second internal potential generating means supplies the second internal potential to the second internal circuit via the second internal potential supply line when the semiconductor device is in an operating state or a standby state.

  As described above, when the semiconductor device is in the operating state or the standby state, the internal potential supply line for supplying the fourth internal potential to the first internal circuit, and when the semiconductor device is in the operating state or the standby state, An internal potential supply line for supplying a second internal potential to the two internal circuits is provided separately.

  For this reason, noise does not propagate directly from the first internal circuit to the second internal circuit. Further, the second internal potential generating means, the third internal potential generating means, and the fourth internal potential generating means function as a filter, and noise generated during the operation of the semiconductor device, that is, during the operation of the first internal circuit. Propagation to the second internal circuit through the power supply potential supply line can be reduced.

  According to a second aspect of the present invention, the connection control means controls the connection between the first internal circuit and the first internal potential supply line or the second internal potential supply line in accordance with the state of the semiconductor device. To do. In other words, the connection control means can disconnect the first internal circuit and the second internal potential supply line when the first internal circuit generates noise.

  For this reason, noise does not directly propagate from the first internal circuit to the second internal circuit via the second internal potential supply line.

  According to a third aspect of the present invention, the connection control means disconnects the first internal circuit and the second internal potential supply line when the semiconductor device is in an operating state, and the first internal circuit The circuit is connected to the first internal potential supply line. When the semiconductor device is in an operating state, the first internal circuit is supplied with the first internal potential, and the second internal circuit is supplied with the second internal potential.

  When the semiconductor device is in the standby state, the first internal circuit and the first internal potential supply line are disconnected, and the first internal circuit and the second internal potential supply line are connected. That is, when the semiconductor device is in a standby state, the first internal circuit and the second internal potential supply line are connected, and the second internal potential is applied to the first internal circuit and the second internal circuit. Will be supplied.

  As described above, when the semiconductor device is in an operating state, that is, when the first internal circuit is in an operating state and generates noise, the first internal circuit and the second internal potential supply line are disconnected. Therefore, noise does not directly propagate to the second internal circuit via the second internal potential supply line.

  According to the fourth aspect of the present invention, noise generated when the semiconductor device is in an operating state, that is, when the first internal circuit is in an operating state, is generated before the second internal circuit is reached. This is reduced by a filter provided in the internal potential supply line.

  In the present invention, the first connection control means controls the connection between the first internal potential supply line and the second internal potential supply line in accordance with the state of the semiconductor device. In other words, the first connection control means can disconnect the first internal potential supply line and the second internal potential supply line when the first internal circuit generates the first noise.

  For this reason, the first noise is not directly propagated to the second internal circuit via the first internal potential supply line and the second internal potential supply line.

  In the present invention described in claim 6, the first connection control means disconnects the first internal potential supply line and the second internal potential supply line when the semiconductor device is in the first state. Release. That is, when the semiconductor device is in the first state, the first internal circuit is supplied with the first internal potential, and the second internal circuit is supplied with the second internal potential. .

  When the semiconductor device is in the second state, the first internal potential supply line and the second internal potential supply line are connected.

  As described above, when the semiconductor device is in the first state, that is, when the first internal circuit generates the first noise, the first internal potential supply line and the second internal potential supply line are Since they are separated, the first noise does not directly propagate to the second internal circuit via the first internal potential supply line and the second internal potential supply line.

  According to a seventh aspect of the present invention, the first connection control means disconnects the first internal potential supply line and the second internal potential supply line when the semiconductor device is in an operating state. That is, when the semiconductor device is in an operating state, the first internal circuit is supplied with the first internal potential, and the second internal circuit is supplied with the second internal potential.

  When the semiconductor device is in the standby state, the first internal potential supply line and the second internal potential supply line are connected. Then, the first internal potential generating means stops.

  That is, when the semiconductor device is in a standby state, the first internal potential supply line and the second internal potential supply line are connected, and the first internal circuit and the second internal circuit are connected to the second internal potential supply line. A potential is supplied.

  As described above, when the semiconductor device is in the operating state, that is, when the first internal circuit is in the operating state and generates the first noise, the first internal potential supply line and the second internal potential supply are supplied. Since it is separated from the line, the first noise does not directly propagate to the second internal circuit via the first internal potential supply line and the second internal potential supply line.

  In the present invention according to claim 8, the first connection control means connects the first internal potential supply line and the second internal potential supply line when the semiconductor device is in the first operation state. Separate. In other words, when the semiconductor device is in the first operation state, the first internal circuit is supplied with the first internal potential, and the second internal circuit is supplied with the second internal potential. Become.

  When the semiconductor device is in the second operation state, the first internal potential supply line and the second internal potential supply line are connected. That is, when the semiconductor device is in the second operation state, the first internal circuit and the second internal potential supply line are connected, and the first internal circuit and the second internal circuit are connected to the first internal circuit. The internal potential and the second internal potential are supplied.

  As described above, when the semiconductor device is in the first operation state, that is, when the first internal circuit generates the first noise, the first internal potential supply line and the second internal potential supply line. Therefore, the first noise does not directly propagate to the second internal circuit via the first internal potential supply line and the second internal potential supply line.

  According to the ninth aspect of the present invention, the first connection control means controls the connection between the first internal potential supply line and the second internal potential supply line in accordance with the state of the semiconductor device. In other words, the first connection control means may connect the first internal potential supply line and the second internal potential supply line only by the resistance element when the first internal circuit generates the first noise. it can.

  For this reason, the resistance element and its parasitic capacitance function as a filter, and the first noise propagated to the second internal circuit via the first internal potential supply line and the second internal potential supply line is reduced.

  According to the tenth aspect of the present invention, the second connection control means controls the connection between the second internal potential supply line and the third internal potential supply line in accordance with the state of the semiconductor device. In other words, the second connection control means can disconnect the second internal potential supply line from the third internal potential supply line when the third internal circuit generates the second noise.

  Therefore, the second noise does not directly propagate to the second internal circuit via the second internal potential supply line and the third internal potential supply line.

  Further, when the third internal circuit does not generate the second noise, the second internal potential supply line and the third internal potential supply line can be connected. Furthermore, when the first internal circuit does not generate the first noise, the first internal potential supply line and the second internal potential supply line can be connected.

  Therefore, the second internal potential generating means can be shared by the first internal circuit, the second internal circuit, and the third internal circuit.

  According to the eleventh aspect of the present invention, the second connection control means controls the connection between the second internal potential supply line and the third internal potential supply line in accordance with the state of the semiconductor device. That is, the second connection control means may connect the second internal potential supply line and the third internal potential supply line only by the resistance element when the third internal circuit generates the second noise. it can.

  For this reason, the resistance element and its parasitic capacitance function as a filter, and the second noise propagated to the second internal circuit via the second internal potential supply line and the third internal potential supply line is reduced.

  According to a twelfth aspect of the present invention, the second connection control means controls the connection between the first internal potential supply line and the third internal potential supply line in accordance with the state of the semiconductor device. In other words, the second connection control means can disconnect the first internal potential supply line and the third internal potential supply line when the third internal circuit generates the second noise.

  For this reason, the second noise does not directly propagate to the second internal circuit via the first internal potential supply line, the second internal potential supply line, and the third internal potential supply line. In addition, when the third internal circuit does not generate the second noise, the first internal potential supply line and the third internal potential supply line can be connected. Furthermore, when the first internal circuit does not generate the first noise, the first internal potential supply line and the second internal potential supply line can be connected.

  Therefore, the second internal potential generating means can be shared by the first internal circuit, the second internal circuit, and the third internal circuit.

  In the first aspect of the present invention, since the first internal potential generating means and the second internal potential generating means function as a filter, the first internal circuit is received by the second internal circuit through the power supply potential supply line. The influence of noise from Furthermore, noise does not propagate directly from the first internal circuit to the second internal circuit. In addition, since the second internal potential generating means, the third internal potential generating means, and the fourth internal potential generating means act as a filter, the second internal circuit receives via the power supply potential supply line. The influence of noise generated during the operation of the semiconductor device, that is, during the operation of the first internal circuit is reduced. Furthermore, noise does not propagate directly from the first internal circuit to the second internal circuit.

  According to the second aspect of the present invention, the connection control means can separate the first internal circuit from the second internal potential supply line when the first internal circuit generates noise. For this reason, the second internal circuit is not directly affected by noise via the second internal potential supply line.

  According to a third aspect of the present invention, when the semiconductor device is in an operating state, that is, when the first internal circuit is in an operating state and generates noise, the connection control means is connected to the first internal circuit and the first internal circuit. 2 is disconnected from the internal potential supply line. For this reason, the second internal circuit is not directly affected by noise via the second internal potential supply line.

  According to the fourth aspect of the present invention, noise generated when the semiconductor device is in an operating state, i.e., when the first internal circuit is in an operating state is generated by a filter provided in the third internal potential supply line. Therefore, the influence of noise on the second internal circuit is reduced.

  In the present invention according to claim 5, the first connection control means connects the first internal potential supply line and the second internal potential supply line when the first internal circuit generates the first noise. Separate. Therefore, the second internal circuit is not directly affected by noise via the first internal potential supply line and the second internal potential supply line.

  In the present invention described in claim 6, the first connection control means includes the first connection control means when the semiconductor device is in the first state, that is, when the first internal circuit generates the first noise. The internal circuit is disconnected from the second internal potential supply line. For this reason, the second internal circuit is not directly affected by the first noise via the first internal potential supply line and the second internal potential supply line.

  In the present invention described in claim 7, when the semiconductor device is in the operating state, that is, when the first internal circuit is in the operating state and generates the first noise, The first internal potential supply line and the second internal potential supply line are separated. For this reason, the second internal circuit is not directly affected by the first noise via the first internal potential supply line and the second internal potential supply line.

  In the present invention according to claim 8, the first connection control means is configured such that when the semiconductor device is in the first operation state, that is, when the first internal circuit generates the first noise, The internal potential supply line is disconnected from the second internal potential supply line. For this reason, the second internal circuit is not directly affected by the first noise via the first internal potential supply line and the second internal potential supply line.

  In the present invention according to claim 9, the first connection control means includes the first internal potential supply line and the second internal potential supply line when the first internal circuit generates the first noise. Are connected only by a resistance element. For this reason, the influence of the first noise on the second internal circuit via the first internal potential supply line and the second internal potential supply line is reduced.

  In the tenth aspect of the present invention, the second connection control means includes the second internal potential supply line and the third internal potential supply line when the second internal circuit generates the second noise. Can be separated. For this reason, the second internal circuit is not directly affected by the second noise via the second internal potential supply line and the third internal potential supply line.

  Further, the first connection control means and the second connection control means are configured such that when the first internal circuit and the third internal circuit do not generate the first noise and the second noise, respectively, Each of the supply line and the second internal potential supply line, and the second internal potential supply line and the third internal potential supply line can be connected. Therefore, the second internal potential generating means can be shared by the first internal circuit, the second internal circuit, and the third internal circuit.

  In the present invention described in claim 11, when the third internal circuit generates the second noise, the second connection control means includes the second internal potential supply line and the third internal potential supply line. Are connected only by a resistance element. For this reason, the influence of the second noise on the second internal circuit via the second internal potential supply line and the third internal potential supply line is reduced.

  In the present invention as claimed in claim 12, the second connection control means includes the first internal potential supply line, the third internal potential supply line, and the third internal potential supply line when the third internal circuit generates the second noise. Can be separated. For this reason, the second internal circuit is not directly affected by the second noise via the first internal potential supply line, the second internal potential supply line, and the third internal potential supply line.

  Further, the first connection control means and the second connection control means are configured such that when the first internal circuit and the third internal circuit do not generate the first noise and the second noise, respectively, Each of the supply line and the second internal potential supply line, and the first internal potential supply line and the third internal potential supply line can be connected. Therefore, the second internal potential generating means can be shared by the first internal circuit, the second internal circuit, and the third internal circuit.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a schematic block diagram showing a semiconductor device according to a first embodiment of the present invention.

  The semiconductor device 5 according to the first embodiment of the present invention includes a package frame 1, a bonding wire 3, a pad 11, a first internal power supply line 13, a second internal power supply line 15, an internal circuit 21, a stabilization circuit 23, and a GND. It comprises a package frame 7, a GND bonding wire 9, a GND pad 17 and an internal GND line 19. Here, the same parts as those in FIG. 28 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

  A power supply potential Vcc supplied from the outside is supplied to the internal circuit 21 through the package frame 1, the bonding wire 3, the pad 11, and the first internal power supply line 13. The power supply potential Vcc from the outside is supplied to the stabilization circuit 23 through the package frame 1, the bonding wire 3, the pad 11 and the second internal power supply line 15. That is, internal circuit 21 and stabilization circuit 23 are each supplied with power supply potential Vcc from different power supply lines separated from pad 11.

  For this reason, the internal circuit 21 and the stabilization circuit 23 are connected via the pad 11, and the noise propagation path based on the operation of the internal circuit 21 becomes long. Furthermore, the positional relationship between the internal circuit 21 that causes noise and the stabilization circuit 23 is parallelized.

  From the above, noise based on the operation of the internal circuit 21 propagated to the stable circuit 23 is reduced. In this case, if a decoupling capacitance is added to the base of the first internal power supply line 13 and the second internal power supply line 15 (connection portion with the pad 11), the propagation of noise to the stable circuit 23 is further reduced.

  Next, the reason why the propagation of noise based on the internal circuit 21 to the stable circuit 23 is reduced will be described in detail. In general, as can be said, the noise transmitted at the point where the resistance component (R component) and the capacitance component (C component) are connected is attenuated. The magnitude of this noise attenuation is proportional to the product of the resistance component and the capacitance component. When a large capacitance component is added to the noise passing point, the noise attenuation effect is increased.

  In FIG. 1, a large capacitance component is added to the pad 11. The resistance component is based on the first internal power supply line 13 and the second internal power supply line 15.

  Furthermore, when an inductance component (L component) is added in addition to the resistance component and the capacitance component, the noise attenuation effect is further increased. This is because when a current flows through the inductance component, a reverse current is generated, so that the current generated by noise is canceled out. In FIG. 1, the inductance component due to the bonding wire 3 connected to the pad 11 increases the noise attenuation effect. The noise attenuation effect increases as the inductance component increases.

  As described above, in the semiconductor device according to the first embodiment of the present invention, the internal power supply line for supplying the power supply potential Vcc to the internal circuit 21 and the stabilization circuit 23 is separated from the pad 11 portion into two. .

  For this reason, in the semiconductor device according to the first embodiment of the present invention, noise is propagated to the stable circuit 23 through the pad 11, and the pad 11, the first internal power supply line 13, and the second The internal power supply line 15 functions as a filter as a whole, and noise transmitted to the stabilization circuit 23 is reduced.

  FIG. 2 is a schematic block diagram showing a modification of the semiconductor device according to the first embodiment of the present invention.

  The modification of the semiconductor device according to the first embodiment of the present invention includes a package frame 1, a bonding wire 3, a pad 11, a first internal power supply line 13, a second internal power supply line 15, an internal circuit 21, and a stabilization circuit 23. , A GND package frame 7, a GND bonding wire 9, a GND pad 17, a first internal GND line 25, and a second internal GND line 27. Here, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  In FIG. 2, the ground potential GND is supplied to the internal circuit 21 by the GND package frame 7, the GND bonding wire 9, the GND pad 17, and the first internal GND line 25. The ground potential GND is supplied to the stabilization circuit 23 by the GND package frame 7, the GND bonding wire 9, the GND pad 17, and the second internal GND line 27. That is, the ground potential GND is supplied to the internal circuit 21 and the stabilization circuit 23 through different internal power supply lines separated by the GND pad 17 portion. For this reason, noise based on the operation of the internal circuit 21 that propagates to the stable circuit 23 is reduced for the same reason as described above.

  As described above, in the modification of the semiconductor device according to the first embodiment of the present invention, the internal power supply line for supplying the power supply potential Vcc to the internal circuit 21 and the stabilization circuit 23 is separated at the pad 11 and The internal GND line for supplying the ground potential GND to the stabilization circuit 23 is also separated at the GND pad 17.

  Therefore, in the modified example of the semiconductor device according to the first embodiment of the present invention, the propagation of noise to the stable circuit 23 can be further reduced as compared with the semiconductor device according to the first embodiment.

(Second embodiment)
FIG. 3 is a schematic block diagram showing a semiconductor device according to the second embodiment of the present invention.

  3, the semiconductor device 5 according to the second embodiment of the present invention includes a package frame 1, a bonding wire 3, a pad 11, a first internal power supply line 101, a second internal power supply line 103, and a third internal power supply. A line 105, a low-pass filter (LPF) 107, an internal circuit 21, a stabilization circuit 23, a GND package frame 7, a GND bonding wire 9, a GND pad 17, and an internal GND line 19. Here, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  A power supply potential Vcc from the outside is supplied to the internal circuit 21 by the package frame 1, the bonding wire 3, the pad 11, the first internal power supply line 101 and the second internal power supply line 103. A power supply potential Vcc from the outside is supplied to the internal circuit 21 by the package frame 1, the bonding wire 3, the pad 11, the first internal power supply line 101 and the third internal power supply line 105. The power supply potential Vcc to the stabilization circuit 23 is passed through a low pass filter (LPF) 107 provided on the third internal power supply line 105.

  The low-pass filter 107 reduces the noise based on the operation of the internal circuit 21 that is propagated to the stable circuit 23 together with the power supply potential.

FIG. 4 is a circuit diagram showing details of the low-pass filter 107 of FIG.
In FIG. 4, the low-pass filter 107 in FIG. 3 includes a resistor 105 and a capacitor 107. In this case, if decoupling capacitance is added to both ends of the low-pass filter 107, the noise reduction effect is further increased.

  The effect of reducing the noise propagating to the stable circuit 23 by providing the low-pass filter 107 will be described in detail.

  FIG. 5 is a diagram showing the noise received by the stabilization circuit 23 in FIG. 3 in a case where the low-pass filter 107 is used and in a case where the low-pass filter 107 is not used.

  In FIG. 5, a line a <b> 1 indicates noise generated in the internal circuit 21 portion. The noise is a periodic application of ± 1 V around the power supply potential Vcc 5 V. That is, it is assumed that when the internal circuit 21 operates, noise as shown by the line a is on the power supply potential Vcc. A line b1 indicates the potential of the node N1 in FIG. 3 when the noise shown in the line a1 is applied to the power supply potential Vcc in the internal circuit 21 portion when the low-pass filter 107 is not used.

  A line c1 and a line d1 indicate the potential of the node N1 in FIG. 3 when the noise shown in the line a1 is added to the power supply potential Vcc in the internal circuit 21 when the low-pass filter 107 is used. In the line c1, the resistance value of the resistor 105 in FIG. 4 constituting the low-pass filter 107 is 4 KΩ, and the capacitance value of the capacitor 107 is 100 pF. In the line d1, the resistance value of the resistor of FIG. 4 constituting the low-pass filter 107 is 10 KΩ, and the capacitance value of the capacitor is 300 pF.

  As described above, the noise propagated to the node N1 in FIG. 3 is smaller when the low-pass filter 107 is used (line c1, line d1) than when the low-pass filter 107 is not used (line b1). ing. Further, when the resistance value of the resistor 105 and the capacitance value of the capacitor 107 constituting the low-pass filter 107 are large (line d1), the noise at the node N1 in FIG. 3 is smaller than when the resistance value is small (line c1).

  In FIG. 5, a reference potential B indicates a reference potential generated by a reference potential generation circuit as the stabilization circuit 23. A line b2 indicates a reference potential generated by a reference potential generation circuit as the stabilization circuit 23 when the power supply potential Vcc indicated by the line b1 is applied to the stabilization circuit 23. A line c2 indicates a reference potential generated by the reference potential generation circuit as the stabilization circuit 23 when the power supply potential Vcc indicated by the line c1 is applied to the reference potential generation circuit as the stabilization circuit 23. A line d2 indicates a reference potential generated by a reference potential generation circuit as the stabilization circuit 23 when the power supply potential Vcc of the line d1 is applied to the stabilization circuit 23.

  That is, the reference potential B indicated by the line b2 is a reference potential generated by the reference potential generation circuit as the stabilization circuit 23 when the low-pass filter 107 is not provided. A reference potential B indicated by lines c2 and d2 indicates a reference potential generated from a reference potential generation circuit as the stabilization circuit 23 when the low-pass filter 107 is used. Further, on the line c2, the resistance value of the resistor 105 of the low-pass filter 107 is 4 KΩ, and the capacitance value of the capacitor 107 is 100 pF. In the line d2, the resistance value of the resistor 105 of the low-pass filter 107 is 10 KΩ, and the capacitance value of the capacitor 107 is 300 pF.

  As described above, the reference potential B generated by the reference potential generation circuit as the stabilizing circuit 23 is greater when the low-pass filter 107 is used (line c2, line d2) and when the low-pass filter 107 is not used (line b2). Level fluctuations are small. Further, the fluctuation of the level of the reference potential B is smaller when the resistance value of the resistor 105 of the low-pass filter 107 and the capacitance value of the capacitor 107 are larger (line d2) than when they are small (line c2). In FIG. 5, the ground potential C indicates the ground potential.

  FIG. 6 shows the noise level on the reference potential generated from the reference potential generating circuit as the stabilizing circuit 23 when the noise frequency indicated by the line a1 in FIG. 5 is changed.

  In FIG. 6, the vertical axis represents the noise level, and the horizontal axis represents the noise frequency. The noise level shown in FIG. 6 is the absolute value of the difference between the potential level BB of the reference potential B in FIG. 5 and the noise peak value. In FIG. 6, a point indicated by an arrow b indicates a noise level when the low pass filter 107 is not used. A point indicated by an arrow c and a point indicated by an arrow d are noise levels when the low-pass filter 107 is used.

  At the point indicated by the arrow c, the resistance value of the resistor 105 of the low-pass filter 107 is 4 KΩ, and the capacitance value of the capacitor 107 is 100 pF. At the point indicated by the arrow d, the resistance value of the low-pass filter 107 is 10 KΩ, and the capacitance value of the capacitor 107 is 300 pF.

  As shown in FIG. 6, the higher the noise frequency, the smaller the noise level on the reference potential generated from the reference potential generating circuit as the stabilizing circuit 23.

  Here, as indicated by a line a1 in FIG. 5, the power supply potential Vcc supplied to the reference potential generation circuit as the stabilization circuit 23 is affected by noise in the internal circuit 21 and fluctuates greatly. The fluctuation of the power supply potential Vcc in the internal circuit 21 is caused by resistance and capacitance components parasitic on the internal power supply line supplying the power supply potential Vcc even when the low-pass filter 107 is not provided, as shown by the line b1 in FIG. Is absorbed somewhat, but to a lesser extent. Therefore, as shown by the line b2 in FIG. 5, when the low-pass filter 107 is not provided, the fluctuation of the power supply potential Vcc affects the reference potential generation circuit as the stabilization circuit 23, and the output greatly fluctuates. It will be.

  As described above, in the semiconductor device according to the first embodiment of the present invention, the low-pass filter 107 is provided in the third internal power supply line 105 that supplies the power supply potential Vcc to the stabilization circuit 23, thereby supplying the stabilization circuit 23. The noise on the power supply potential Vcc is absorbed. That is, in the semiconductor device according to the second embodiment of the present invention, by providing the low pass filter 107, the propagation of noise to the stabilization circuit 23 based on the operation of the internal circuit 21 is reduced.

  FIG. 7 is a schematic block diagram showing a modification of the semiconductor device according to the second embodiment of the present invention.

  In FIG. 7, the modification of the semiconductor device according to the second embodiment of the present invention includes a package frame 1, a bonding wire 3, a pad 11, a first internal power supply line 101, a second internal power supply line 103, a third Internal power line 105, low pass filter (LPF) 107, internal circuit 21, stabilization circuit 23, GND package frame 7, GND bonding wire 9, GND pad 17, first internal GND line 109, second internal GND line 111, It consists of a third internal GND line 113 and a low pass filter (LPF) 114. The same parts as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  The ground potential GND is supplied to the internal circuit 21 via the GND package frame 7, the GND bonding wire 9, the GND pad 17, the first internal GND line 109, and the second internal GND line 111. The ground potential GND is supplied to the stabilization circuit 23 via the GND package frame 7, the GND bonding wire 9, the GND pad 17, the first internal GND line 109, and the third internal GND line 113.

  Note that the third internal GND line 113 is provided with a low-pass filter 114, and the ground potential GND is supplied to the stabilization circuit 23 through the low-pass filter 114. The configuration of the low pass filter 114 is the same as the configuration of the low pass filter 107.

  That is, since the noise based on the internal circuit 21 is absorbed by the low-pass filter 114, the noise propagating to the stable circuit 23 is reduced together with the ground potential GND.

  As described above, in the modified example of the semiconductor device according to the first embodiment of the present invention, the low-pass filter 107 is provided on the third internal power supply line 105 and the low-pass filter 114 is also provided on the third internal GND line 113. Provided. Therefore, the propagation of noise to the stable circuit 23 is further reduced as compared with the semiconductor device according to the first embodiment shown in FIG. In addition, in the low-pass filters 107 and 114 of FIG. 3 and FIG. 7, the passive filter by resistance and a capacitor was used, However, Other passive filters may be used. An active filter may be used.

  The low pass filter used in the first embodiment and the modified example of the first embodiment can also be used for the internal power supply line of the first embodiment shown in FIGS.

(Third embodiment)
FIG. 8 is a schematic block diagram showing a general semiconductor device.

  In FIG. 8, a general semiconductor device includes a well 203, transistors 205 and 207, an internal circuit well fixed diffusion layer 213, a stable circuit well fixed diffusion layer 215, and an internal power supply line 201. The plurality of transistors 205 constitute an internal circuit 209. The plurality of transistors 207 form a stabilization circuit 211.

  The power supply potential Vcc is supplied to the internal circuit 209 through the internal power supply line 201. A power supply potential Vcc is supplied to the stabilization circuit 211 from the internal power supply line 201. The internal circuit well fixing diffusion layer 213 fixes the well in the region where the internal circuit 209 is formed to the power supply potential. The stable circuit well fixed diffusion layer fixes the well in the region where the stable circuit 211 is formed to the power supply potential Vcc.

  In such a general semiconductor device, noise generated when the internal circuit 209 is operated passes through the internal circuit well fixed diffusion layer 213 and the stable circuit well fixed diffusion layer 215 to the stable circuit 211 as indicated by an arrow a. There is a problem that the stabilization circuit 211 is propagated and malfunctions. Further, there is a problem that noise when the internal circuit 209 is operated directly propagates to the stable circuit 211 via the internal power supply line 201. The third embodiment has been made to solve such a problem.

FIG. 9 is a schematic block diagram showing a semiconductor device according to the third embodiment.
9, the semiconductor device according to the third embodiment of the present invention includes a well 203, transistors 205 and 207, a well fixed diffusion layer 215 for a stable circuit, a low-pass filter (LPF) 107, a first internal power supply line 217, a first 2 internal power supply lines 219, third internal power supply lines 221, and fourth internal power supply lines 223.

  The plurality of transistors 205 constitute an internal circuit 209. The plurality of transistors 207 form a stabilization circuit 211. The properties of the internal circuit 209 and the stabilization circuit 211 are the same as those of the internal circuit 25 and the stabilization circuit 23 of FIG. The same parts as those in FIG. 8 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. The configuration of the low-pass filter 107 is the same as the configuration of the low-pass filter 107 in FIG.

  The internal circuit 209 is supplied with the power supply potential Vcc via the first internal power supply line 217 and the second internal power supply line 219. The stabilization circuit 211 is supplied with the power supply potential Vcc via the first internal power supply line 217 and the third internal power supply line 221. The stable circuit well fixed diffusion layer 215 is supplied with the power supply potential Vcc through the first internal power supply line 217, the third internal power supply line 221, and the fourth internal power supply line 223.

  Here, since the third internal power supply line 221 is provided with the low-pass filter 107, the power supply potential Vcc supplied to the stable circuit 211 and the well fixed diffusion layer for stable circuit 215 passes through the low-pass filter 107. That is, noise based on the operation of the internal circuit 209 is caused by the stable circuit well fixed diffusion layer 215 and the stable circuit 211 via the first internal power supply line 217, the second internal power supply line 219, and the third internal power supply line 221. Is absorbed by the low-pass filter 107 when propagating to.

  As described above, in the semiconductor device according to the third embodiment of the present invention, the internal power supply line (third internal power supply line 221) for supplying the power supply potential Vcc to the well fixed diffusion layer for stable circuit and the stable circuit 211 is provided. The internal power supply line (second internal power supply line 219) that supplies the power supply potential Vcc to the internal circuit 209 is distinguished, and the third internal power supply line 221 is provided with a low-pass filter 107.

  As a result, noise accompanying the operation of the internal circuit 209 is propagated to the stable circuit 211 via the internal power supply lines (the first internal power supply line 217, the second internal power supply line 219, and the third internal power supply line 221). Is attenuated by the low-pass filter 107 and does not affect the stable circuit 211. Further, noise is generated in the stable circuit well fixed diffusion layer 215 by the internal power lines (first internal power line 217, second internal power line 219, third internal power line 221 and fourth internal power line 223). , The noise is absorbed by the low-pass filter 107. For this reason, noise propagating to the stable circuit 211 through the well fixed diffusion layer 215 for the stable circuit is reduced.

  In addition, only very small noise from the diffusion layer connected to the internal power supply line (second internal power supply line 219) for supplying the power supply potential Vcc to the internal circuit 209 is propagated to the stable circuit 211. The stabilization circuit 211 is less susceptible to noise associated with the operation of the internal circuit 209. Furthermore, noise is added by fixing the well between the internal circuit 209 and the well by the stable circuit well fixing diffusion layer 215 connected to the internal power supply line (fourth internal power supply line 223) through the low-pass filter 107. The transmitted noise (arrow a) can be absorbed by the potential of the fourth internal power supply line 223 that is not present.

  FIG. 10 is a schematic block diagram showing a modification of the semiconductor device according to the third embodiment of the present invention.

  In FIG. 10, the modification according to the third embodiment of the present invention includes a well 203, transistors 205 and 207, a well fixed diffusion layer 215 for a stable circuit, low-pass filters 227 and 229, a first internal power supply line 217, a second Internal power supply line 219, third internal power supply line 221, and fourth internal power supply line 225. The same parts as those in FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. The configuration of the low-pass filters 227 and 229 is the same as the configuration of the low-pass filter 107 in FIG.

  In FIG. 10, the stable potential well fixing diffusion layer 215 is supplied with the power supply potential Vcc via the first internal power supply line 217, the third internal power supply line 221, and the fourth internal power supply line 225. The fourth internal power supply line 225 is provided with a low pass filter 227.

  Therefore, noise when the internal circuit 209 operates is propagated to the well fixed diffusion layer 215 for the stable circuit via the low pass filter 227. Therefore, the noise propagated to the stable circuit well fixed diffusion layer 215 is reduced. Furthermore, the power supply potential Vcc is also supplied to the stabilization circuit 211 via the low pass filter 229. For this reason, the noise propagated to the stable circuit 211 is absorbed by the low-pass filter 229, and the stable circuit 211 is hardly affected by the noise.

  As described above, in the modification according to the third embodiment of the present invention, the power supply potential Vcc is supplied to the fourth internal power supply line 225 for supplying the power supply potential Vcc to the well fixing diffusion layer 215 for the stable circuit and the stabilization circuit 211. A low-pass filter 227 and a low-pass filter 229 are provided for the third internal power supply line 221 to be supplied, respectively. For this reason, also in the modification of the third embodiment, the same effects as in the embodiment shown in FIG. 9 are obtained.

  The use of the low pass filter for the internal power supply line for supplying the power supply potential Vcc to the well fixed diffusion layer for the stable circuit can also be applied to the first and second embodiments.

(Fourth embodiment)
FIG. 11 is a schematic block diagram showing a semiconductor device according to the fourth embodiment of the present invention.

  11, the semiconductor device according to the fourth embodiment of the present invention includes an internal potential generation circuit 303, an internal circuit 305, a low-pass filter (LPF) 107, a stabilization circuit 307, an external power supply line 301, an internal GND line 309, Internal potential line 311, second internal potential line 313, and third internal potential line 315.

  In the second embodiment, a filter is arranged for a power supply potential or a signal input from the outside, and the output of the filter is transmitted to the next circuit. In this embodiment, an internal power supply potential and an internal signal generated inside are transmitted to the next circuit through a filter.

  In FIG. 11, internal potential generation circuit 303 is, for example, an internal power supply potential drop circuit (VDC), a substrate bias circuit, a 1/2 Vcc generation circuit, a boosted potential generation circuit, or the like. The boosted potential generated from the boosted potential generating circuit is supplied as a potential when a word line (not shown) is activated. In addition, it may be supplied to an analog circuit that requires a high potential level.

  In this embodiment, a description will be given assuming that a boosted potential generation circuit is used as the internal potential generation circuit 303. In this case, the internal circuit 305 indicates a word line activation circuit that activates the word line, and the stabilization circuit 307 indicates an analog circuit that requires a high potential level.

  An external power supply potential is supplied from the external power supply line 301 to the boosted potential generation circuit as the internal potential generation circuit 303. A ground potential is supplied from the internal GND line 309 to the word line activation circuit as the internal circuit 305 and the analog circuit as the stabilization circuit 307.

  The boosted potential generated by the boosted potential generating circuit as the internal potential generating circuit 303 is supplied to the word line activation circuit as the internal circuit 305 through the first internal potential line 311 and the second internal potential line 313. . The boosted potential generated by the boosted potential generating circuit as the internal potential generating circuit 303 is supplied to the analog circuit as the stabilizing circuit 307 via the first internal potential line 311 and the third internal potential line 315. The Note that the boosted potential supplied to the analog circuit serving as the stabilization circuit 307 passes through the low-pass filter 107 provided in the third internal potential line.

  When the word line is activated, a large current flows from the boosted potential level to the word line, so that the boosted potential level generates noise. In general, this noise affects an analog circuit (stabilization circuit 307) that requires a high potential level, and may cause a malfunction. Therefore, in this embodiment, the low-pass filter 107 is provided in the third internal potential line 315 that supplies the boosted potential to the analog circuit as the stabilization circuit 307, and the noise propagated to the stabilization circuit 307 by the low-pass filter 107 is reduced. It is decreasing.

  As described above, in the semiconductor device according to the fourth embodiment of the present invention, the internal potential that supplies the internal potential (boosted potential) generated from the internal potential generation circuit 303 to the stabilization circuit 307 that is susceptible to noise. A low-pass filter 107 is provided on the line (third internal potential line 315). Therefore, noise generated based on the operation of the internal circuit 305 is transferred to the stabilization circuit 307 via the internal potential lines (first internal potential line 311, second internal potential line 313, third internal potential line 315). The propagation of is small.

(Fifth embodiment)
FIG. 12 is a schematic block diagram showing a general semiconductor device.

  12, a general semiconductor device includes a DC-DC converter 401, a minute current DC-DC converter 403, an internal circuit 21, a stabilization circuit 23, an external power supply line 301, an external GND line 405, and an internal power supply line 407. .

  The DC-DC converter 401 and the micro-current DC-DC converter 403 lower the external power supply potential supplied from the external power supply line 301 to a power supply potential lower than the external power supply potential (hereinafter referred to as “internal power supply potential”). The internal circuit 21 and the stabilization circuit 23 are operated. The internal power supply potential is supplied to the internal circuit 21 and the stabilization circuit 23 through the internal power supply line 407.

  Here, the DC-DC converter 401 performs a potential drop when the semiconductor device is in an operating state. The micro-current DC-DC converter 403 performs a potential drop when the semiconductor device is in an operating state or a standby state. At the time of standby of the semiconductor device, the DC-DC converter 401 is in an inactive state to reduce current consumption.

  The internal circuit 21 generates noise during its operation. The stabilization circuit 23 is a circuit that is susceptible to noise. The internal circuit 21 and the stabilization circuit 23 are supplied with the ground potential from the external GND line.

  As shown in FIG. 12, in a general semiconductor device, the power supply potential is supplied to the internal circuit 21 and the stabilization circuit 23 through one internal power supply line 407. For this reason, when the internal circuit 21 is operated, the noise accompanying the operation of the internal circuit 21 is transmitted to the stable circuit 23 via the internal power supply line 407, causing the stable circuit 23 to malfunction. . The present embodiment has been made to solve such problems.

FIG. 13 is a schematic block diagram showing a semiconductor device according to the fifth embodiment of the present invention.
13, the semiconductor device according to the fifth embodiment of the present invention includes a DC-DC converter 401, a first minute current DC-DC converter 415, a second minute current DC-DC converter 417, and an internal circuit 21. , A stable circuit 23, an external power supply line 301, an internal GND line 309, a first internal power supply line 409, a second internal power supply line 411, a third internal power supply line 413, and a fourth internal power supply line 419. The same parts as those in FIG. 12 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  In FIG. 13, a first micro-current DC-DC converter 415 generates a power supply potential obtained by stepping down an external power supply potential supplied from the external power supply line 301 (hereinafter referred to as “first internal power supply potential”) of the semiconductor device. It is supplied to the internal circuit 21 during operation or standby. The first internal power supply potential generated from the first minute current DC-DC converter 415 is supplied to the internal circuit 21 via the second internal power supply line 411 and the third internal power supply line 413. A power supply potential generated from the DC-DC converter 401 (hereinafter referred to as a “second internal power supply potential”) is transmitted through the first internal power supply line 409 and the third internal power supply line 413 during the operation of the semiconductor device. It is supplied to the internal circuit 21.

  Second minute current DC-DC converter 417 generates a power supply potential obtained by stepping down the external power supply potential supplied from external power supply line 301 (hereinafter referred to as “third internal power supply potential”). The third internal power supply potential generated from the second minute current DC-DC converter 417 is supplied to the stabilization circuit 23 via the fourth internal power supply line 419.

The internal GND line 309 supplies a ground potential to the internal circuit 21 and the stabilization circuit 23.
As described above, in the semiconductor device according to the fifth embodiment of the present invention, the internal power supply line (first internal power supply potential, first internal power supply potential) that supplies the internal circuit 21 with the internal power supply potential (first internal power supply potential). Internal power supply line 409, second internal power supply line 411, third internal power supply line 413) and internal power supply line (fourth internal power supply) for supplying the internal power supply potential (third internal power supply potential) to the stabilization circuit 23. Line 419) is provided separately.

  Therefore, noise accompanying the operation of the internal circuit 21 does not propagate directly to the stable circuit 23. Furthermore, noise based on the operation of the internal circuit 21 that propagates through the external power supply line 301 is caused by the DC-DC converter 401, the first minute current DC-DC converter 411, and the second minute current DC-DC converter. 417 is absorbed. That is, since the DC-DC converter 401, the first minute current DC-DC converter 411, and the second minute current DC-DC converter 417 function as a filter, the possibility that noise is propagated to the stable circuit 23 is low. Become.

  In this embodiment, as a circuit for generating an internal power supply potential, a DC-DC converter 401, a minute current DC-DC converter 403, a first minute current DC-DC converter 415, and a second minute current use circuit. Although the DC-DC converter 417 is used, the present invention is not limited to this, and any other circuit may be used as long as it generates an internal potential. For example, a boosted potential generating circuit, a substrate bias circuit, and a 1/2 Vcc generating circuit.

(Sixth embodiment)
FIG. 14 is a schematic block diagram showing a semiconductor device according to the sixth embodiment of the present invention.

  14, the semiconductor device according to the sixth embodiment of the present invention includes a DC-DC converter 401, an internal circuit 21, a minute current DC-DC converter 501, a stabilizing circuit 23, an external power supply line 301, and a first internal power supply. Line 505, switch 503, second internal power supply line 507, and internal GND line 309 are included. The same parts as those in FIG. 12 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  The minute current DC-DC converter 501 steps down the external power supply potential supplied from the external power supply line 301 to generate a first internal power supply potential. When the semiconductor device is in an operating state, the switch 503 is connected to the first internal power supply line 505. Then, the DC-DC converter 401 supplies the internal circuit 21 with the first internal power supply potential obtained by reducing the external power supply potential.

  When the semiconductor device is in a standby state, the switch 503 is connected to the second internal power supply line 507. Then, the second internal power supply potential obtained by stepping down the external power supply potential generated from the minute current DC-DC converter 501 is supplied to the internal circuit 21 and the stabilization circuit 23.

  As described above, in the semiconductor device according to the sixth embodiment of the present invention, the internal circuit 21 and the second internal power supply line 507 are disconnected during the operation of the semiconductor device, that is, during the operation of the internal circuit. Therefore, noise accompanying the operation of the internal circuit 21 does not propagate directly to the stable circuit 23. Further, during the operation of the semiconductor device, the internal circuit 21 and the first internal power supply line 505 are connected, so that noise may be propagated to the stable circuit 23 via the external power supply line 301. However, in this case, since the DC-DC converter 401 and the minute current DC-DC converter 501 function as filters and absorb noise, the possibility of noise propagation to the stable circuit 23 is reduced.

  In the present embodiment, the DC-DC converter 401 and the minute current DC-DC converter 501 are used as the circuit for generating the internal power supply potential. However, the present invention is not limited to these circuits. Any other circuit may be used. For example, a boosted potential generating circuit, a substrate bias circuit, and a 1/2 Vcc generating circuit.

(Seventh embodiment)
FIG. 15 is a schematic block diagram showing a semiconductor device according to the seventh embodiment of the present invention.

  15, the semiconductor device according to the seventh embodiment of the present invention includes a DC-DC converter 401, a minute current DC-DC converter 501, an internal circuit 21, a stabilization circuit 23, a low-pass filter (LPF) 107, an external power supply line. 301, a first internal power supply line 601, a second internal power supply line 603, a third internal power supply line 605, and an internal GND line 309. The same parts as those in FIG. 14 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  The low-pass filter (LPF) 107 is the same as the low-pass filter (LPF) 107 according to the second embodiment. When the semiconductor device is in an operating state, the first internal power supply potential is supplied from the DC-DC converter 401 to the internal circuit 21 via the first internal power supply line 601. Further, the stabilization circuit 23 is supplied with the first internal power supply potential from the DC-DC converter 401 via the first internal power supply line 601, the second internal power supply line 603, and the third internal power supply line 605. The In this case, the first internal power supply potential is supplied to the stabilization circuit 23 via the low-pass filter 107 provided on the third internal power supply line 605.

  Further, the minute current DC-DC converter 501 supplies the second internal power supply potential to the stabilization circuit 23 via the second internal power supply line 603. The minute current DC-DC converter 501 supplies the second internal power supply potential to the internal circuit 21 via the second internal power supply line 603, the third internal power supply line 605, and the first internal power supply line 601. To do.

  The second internal power supply potential supplied from the minute current DC-DC converter 501 is supplied to the internal circuit 21 via the low-pass filter 107 provided in the third internal power supply line 605. When the semiconductor device is in a standby state, the DC-DC converter 401 is deactivated.

  Thus, in the semiconductor device according to the seventh embodiment of the present invention, the low-pass filter 107 is provided in the third internal power supply line 605. For this reason, the noise generated by the operation of the internal circuit 21 is absorbed by the low-pass filter 107 when propagating through the third internal power supply line 605, and the possibility that the noise propagates to the stable circuit 23 becomes low.

  Furthermore, in this embodiment, the noise propagated to the stable circuit 23 is not reduced by switching the switch 503 as in the sixth embodiment shown in FIG. 14, but between the internal circuit 21 and the stable circuit 23. The low-pass filter 107 provided reduces noise propagating to the stable circuit 23. For this reason, it is not necessary to consider the noise generated in the switching of the switch 503 as in the sixth embodiment shown in FIG.

  In the present embodiment, the DC-DC converter 401 and the minute current DC-DC converter 501 are used as the circuit for generating the internal power supply potential. However, the present invention is not limited to these circuits. Any other circuit may be used. For example, a boosted potential generating circuit, a substrate bias circuit, and a 1/2 Vcc generating circuit.

(Eighth embodiment)
FIG. 16 is a schematic block diagram showing a semiconductor device according to an eighth embodiment of the present invention.

  In FIG. 16, the semiconductor device according to the eighth embodiment of the present invention includes a first comparator 701, a second comparator 705, PMOS transistors 703 and 707, a switch 709, a sense system circuit 711, a 1/2 Vcc generation circuit 713, an external circuit. A power supply line 301, a reference potential supply line 715, a first internal power supply line 717, and a second internal power supply line 719 are included.

  In this embodiment, a case where a memory cell array of a dynamic random access memory (hereinafter referred to as “DRAM”) is driven will be considered. In the case of DRAM, recently, the external power supply potential (external Vcc) is lowered by using an internal power supply potential drop circuit composed of a DC-DC converter using a comparator and a PMOS driver, as compared with the external power supply potential. I am letting.

  In FIG. 16, the first comparator 701 compares the reference potential level of the reference potential supply line 715 with the potential level of the first internal power supply line 717. Based on the comparison result, on / off of the PMOS transistor 703 is controlled to step down the external power supply potential supplied from the external power supply line 301. Here, the first comparator 701 and the PMOS transistor 703 constitute an active internal power supply potential drop circuit (VDC) of the semiconductor device.

  The second comparator 705 compares the reference potential level supplied from the reference potential supply line 715 with the potential level of the second internal power supply line 719. Based on the comparison result, on / off of the PMOS transistor 707 is controlled to step down the external power supply potential supplied from the external power supply line 301. Here, the second comparator 705 and the PMOS transistor 707 constitute an internal power supply potential drop circuit (VDC) for standby of the semiconductor device.

  In FIG. 16, as a circuit example using an internal power supply potential obtained by stepping down an external power supply potential by an internal power supply potential dropping circuit, a sense system circuit 711 that consumes a large current during an active period, and a 1 that constantly consumes a minute current. A / 2 Vcc generation circuit 713 is used.

  Here, the sense system circuit 711 is a circuit that amplifies a slight change in the bit line potential, using an initial charge transmitted from a memory cell (not shown) to the bit line. The 1/2 Vcc generation circuit 713 is a circuit that generates a potential for holding the bit line at an intermediate potential during standby of the semiconductor device. The ½ Vcc generation circuit 713 is a circuit that operates mainly when the semiconductor device is on standby and continues to consume a small amount of current at all times.

  The first internal power supply line 717 connected to the sense system circuit 711 and the second internal power supply line 719 connected to the 1/2 Vcc generation circuit 713 are connected via a switch 709. The switch 709 is a PMOS transistor, and has one electrode connected to the first internal power supply line 717 and the other electrode connected to the second internal power supply line 719. The activation signal ACT of the semiconductor device is input to the control electrode of the PMOS transistor constituting the switch 709.

  The switch 709 is connected by setting the activation signal ACT to the “L” level during standby of the semiconductor device. During standby, the active internal power supply potential drop circuit including the first comparator 701 and the PMOS transistor 703 is inactivated. Therefore, sense system circuit 711 and ½ Vcc generation circuit 713 receive the internal power supply potential generated from the standby internal power supply potential drop circuit formed of second comparator 705 and PMOS transistor 707. .

  When the semiconductor device is active, the switch 709 is off and the first internal power supply line 717 and the second internal power supply line 719 are disconnected. For this reason, the sense system circuit 711 is supplied with the internal power supply potential generated from the active internal power supply potential drop circuit including the first comparator 701 and the PMOS transistor 703. On the other hand, ½ Vcc generation circuit 713 is supplied with an internal power supply potential generated from a standby internal power supply potential drop circuit composed of second comparator 705 and PMOS transistor 707.

  As described above, in the semiconductor device according to the eighth embodiment of the present invention, when the semiconductor device is active, the first internal power supply line 717 and the second internal power supply line 719 are disconnected by the switch 709. Yes. For this reason, the possibility that the noise accompanying the operation of the sense circuit 711 is propagated to the 1/2 Vcc generation circuit 713 is reduced.

  Furthermore, another application example of the present embodiment will be described. When the semiconductor device is in the high speed mode (when the sense circuit 711 generates a large noise), the switch 709 is turned off and the first internal power supply line 717 and the second internal power supply line 719 are disconnected. In this case, the sense system circuit 711 is supplied with the internal power supply potential generated from the internal power supply potential drop circuit for the high speed mode, which includes the first comparator 701 and the PMOS transistor 703. 1/2 Vcc generation circuit 713 is supplied with the internal power supply potential generated from the internal power supply potential drop circuit for the normal mode including second comparator 705 and PMOS transistor 707.

  When the semiconductor device is in the normal mode (when the noise generated from the sense system circuit 711 is small), the switch 709 is turned on, and the first internal power supply line 717 and the second internal power supply line 719 are connected. In this case, the sense system circuit 711 and the 1/2 Vcc generation circuit 713 include the internal power supply potential generated from the internal power supply potential drop circuit including the first comparator 701 and the PMOS transistor 703, the second comparator 705, and the PMOS. The internal power supply potential generated from the internal power supply potential drop circuit composed of the transistor 707 is supplied.

  Thus, in the eighth embodiment of the present invention, the first internal power supply line 717 and the second internal power supply line 719 are disconnected when the sense circuit 711 is in a high-speed mode that generates a lot of noise. Release. For this reason, the possibility that noise based on the sense system circuit 711 is propagated to the 1/2 Vcc generation circuit 713 is reduced.

  FIG. 17 is a schematic block diagram showing a modification of the semiconductor device according to the eighth embodiment of the present invention.

  The modification according to the eighth embodiment shown in FIG. 17 is obtained by adding a resistor 721 to the configuration of the eighth embodiment shown in FIG. Therefore, the same parts as those in FIG. 16 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  When the semiconductor device is in the operating state or the high-speed mode, the switch 709 is turned off. However, since the resistor 721 is connected in parallel to the switch 709, the first internal power supply line 717 and the second internal power supply line 719 are not completely disconnected. In this case, the resistor 721 and its parasitic capacitance serve as a filter.

  As described above, in the modification of the semiconductor device according to the eighth embodiment of the present invention, the noise generated when the sense circuit 711 is in the operating state or the high speed mode is propagated to the 1/2 Vcc generation circuit 713. It is absorbed by the resistor 721 acting as a filter and its parasitic capacitance. For this reason, the noise propagated to the 1/2 Vcc generation circuit 713 is reduced.

  FIG. 18 is a schematic block diagram showing another modification of the semiconductor device according to the eighth embodiment of the present invention.

  Another modification of the eighth embodiment shown in FIG. 18 is the same as that of the modification of the eighth embodiment shown in FIG. 17 except that a resistor 729, a switch 731, a third comparator 723, a PMOS transistor 725, A third internal power supply line 733 and a sense system circuit 727 are added. Therefore, the same parts as those in FIG. 17 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  The third comparator 723 and the PMOS transistor 725 form an active internal power supply potential drop circuit for the semiconductor device.

  The second comparator 723 compares the level of the reference potential supplied from the reference potential supply line 715 with the potential level of the third internal power supply line 733. Based on the comparison result, on / off of the PMOS transistor 725 is controlled, and the external power supply potential supplied from the external power supply line 301 is stepped down to generate the internal power supply potential.

  Similarly to the switch 709, the switch 731 is turned on by setting the activation signal ACT of the semiconductor device input to the control electrode to the “L” level when the semiconductor device is in the standby state or the normal mode. .

  In this case, the active internal power supply potential drop circuit composed of the third comparator 723 and the PMOS transistor 725 is inactivated.

  That is, when the semiconductor device is in the standby state or the normal mode, the switch 709 and the switch 731 are turned on, and the first internal power supply line 717, the second internal power supply line 719, the second internal power supply line 719, 3 internal power supply lines 733 are connected.

  Further, the internal power supply potential drop circuit composed of the first comparator 701 and the PMOS transistor 703 and the internal power supply potential drop circuit composed of the third comparator 723 and the PMOS transistor 725 are inactive. Therefore, sense system circuit 711, sense system circuit 727, and 1/2 Vcc generation circuit 713 are supplied with the internal power supply potential generated from the internal power supply potential drop circuit formed of second comparator 705 and PMOS transistor 707. become. The sense system circuit 727 is the same as the sense system circuit 711.

  When the semiconductor device is in the operating state or the high speed mode, the switch 709 and the switch 731 are turned off. However, since the resistor 721 and the resistor 729 are connected in parallel to the switch 709 and the switch 731, respectively, the first internal power supply line 717 and the second internal power supply line 719, the second internal power supply line 719 and the third internal power supply line 719 are connected. The internal power line 733 is not completely disconnected. Therefore, the resistor 721 and its parasitic capacitance and the resistor 729 and its parasitic capacitance serve as a filter.

  Therefore, when the semiconductor device is in the operating state or in the high-speed mode, noise generated from the sense system circuit 711 is absorbed by the resistor 721 and the filter composed of its parasitic capacitance when propagating to the 1/2 Vcc generation circuit 713. become. Further, when the noise generated from the sense circuit 727 is propagated to the 1/2 Vcc generation circuit 713, it is absorbed by the filter composed of the resistor 729 and its parasitic capacitance.

  As described above, in another modification of the eighth embodiment of the present invention, when the semiconductor device is in the operating state or the high-speed mode, the switches 709 and 731 are turned off, thereby causing the resistors 721 and 729 and Since the parasitic capacitance acts as a filter, the noise propagated to the 1/2 Vcc generation circuit 713 is reduced.

  Further, when the semiconductor device is in the standby state or the normal mode, both the switch 709 and the switch 731 are turned on, so that the sense system circuit 711 and the sense system circuit 727 are composed of the second comparator 705 and the PMOS transistor 707. The internal power supply potential drop circuit for standby or normal mode can be shared.

  For this reason, the current consumption during the standby period or the normal mode period of the semiconductor device is reduced as compared with the case where each of the sense system circuit 711 and the sense system circuit 727 is provided with a standby or normal mode internal power supply potential drop circuit. It becomes possible to suppress.

  It should be noted that the influence of noise received by ½ Vcc generation circuit 713 can also be reduced by removing resistors 721 and 729. Further, when the semiconductor device is in the standby state or the normal mode, the sense system circuit 711 and the sense system circuit 727 can share the internal power supply potential drop circuit for the standby or normal mode, and the standby period or the normal mode of the semiconductor device It becomes possible to suppress current consumption in the period.

(Ninth embodiment)
In this embodiment, the case of driving a DRAM memory cell array is considered.

FIG. 19 is a schematic block diagram showing a semiconductor device according to the ninth embodiment of the present invention.
19, the semiconductor device 800 according to the ninth embodiment of the present invention includes active internal power supply potential drop circuits (VDC) 801 and 807, standby internal power supply potential drop circuits (VDC) 803, and a 1/2 Vcc generation circuit. 805, 809, switches 811, 815, 813, sense system circuits 817, 819, 821, 823, a first internal power supply line 825, a second internal power supply line 827, and a third internal power supply line 829.

  The sense system circuits 817, 819, 821, and 823 are the same as the sense system circuit 711 in FIG. The active VDCs 801 and 807 are the same as the active internal power supply potential drop circuit including the first comparator 701 and the PMOS transistor 703 in FIG. The standby VDC 803 is the same as the standby internal power supply potential drop circuit including the second comparator 705 and the PMOS transistor 707 shown in FIG. 1/2 Vcc generation circuits 805 and 809 are the same as 1/2 Vcc generation circuit 713 shown in FIG. The switches 811 815 and 813 are the same as the switch 709 shown in FIG. In this case, resistors can be connected in parallel to both ends of the switches 811, 815, and 813.

  When the semiconductor device is in an operating state, the switches 811 815 813 are turned off. As a result, the second internal power supply line 827 and the first internal power supply line 825 are disconnected. In addition, first internal power supply line 825 and third internal power supply line 829 are disconnected. Therefore, the internal power supply potential is supplied from the active VDC 801 to the sense system circuits 817 and 819. The sense system circuits 821 and 823 are supplied with the internal power supply potential from the active VDC 807.

  When the semiconductor device is in a standby state, the switches 811, 815, and 813 are turned on. As a result, the first internal power supply line 825 and the second internal power supply line 827 are connected. The first internal power supply line 825 and the third internal power supply line 829 are connected. Since the active VDCs 801 and 807 are inactivated, the internal power supply potential is supplied from the standby VDC 803 to the sense system circuits 817, 819, 821 and 823 and the 1/2 Vcc generation circuits 805 and 809. Will be. When the semiconductor device is in an operating state, standby VDC 803 supplies an internal power supply potential to 1/2 Vcc generation circuits 805 and 809.

  As described above, in the semiconductor device according to the ninth embodiment of the present invention, the switches 811, 815, and 813 are turned off when the semiconductor device is in an operating state. For this reason, the possibility that noise generated from the sense system circuits 817, 819, 821 and 823 during operation of the semiconductor device is propagated to the ½ Vcc generation 805 and 809 is reduced.

  Further, the standby VDC 803 can be shared by the sense system circuit 817, the sense system circuit 819, the sense system circuit 821, and the sense system circuit 823 during standby of the semiconductor device. Therefore, current consumption in the standby period can be suppressed as compared with the case where each of the sense system circuit 817, the sense system circuit 819, the sense system circuit 821, and the sense system circuit 823 is provided with a standby VDC. It becomes possible.

  Here, the first internal power supply line 825 and the third internal power supply line 829 can be connected without providing the switch 815 and the switch 813. Even in this case, the same effects as those of the semiconductor device of FIG.

  In the same manner as described in the eighth embodiment, this embodiment can be applied even when the semiconductor device 800 is in the high speed mode or the normal mode.

(Tenth embodiment)
FIG. 20 is a schematic block diagram showing a semiconductor device according to the tenth embodiment of the present invention.

  20, the semiconductor device according to the tenth embodiment of the present invention has the same structure as the semiconductor device according to the ninth embodiment shown in FIG. 19, except that an external lead 1001, an internal lead 1003, a reference potential generating circuit 1013, a wire 1005, 1007, 1009 and pad 1011 are added. Therefore, the same parts as those in FIG. 19 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  In FIG. 20, a power supply potential is supplied from the outside to the active VDC 801 from the power supply external lead 1001 through the wire 1005 and the pad 1011. In FIG. 20, external leads related to other power sources and control signals are not shown for ease of explanation.

  Referring to FIG. 20, a normal circuit such as sense system circuits 817, 819, 821, and 823 is connected to supply a power supply potential to a circuit that performs analog operation that dislikes noise such as reference potential generation circuit 1013. If the same power supply line as that of the active VDC 801 is used, noise when a normal circuit such as the sense system circuits 817, 819, 821, and 823 operates becomes a reference potential generation circuit 1013 (analog operation that dislikes noise). The reference potential generating circuit 1013 may malfunction. For example, the power supply potential may be supplied from the external lead 1001 to the reference potential generation circuit 1013 with a direct wire.

  Therefore, in this embodiment, the internal lead 1003 different from the external lead 1001 is used, and the reference potential generation circuit 1013 (circuit that performs analog operation) receives supply of the power supply potential from the outside via the internal lead 1003. Configure as follows. A normal lead such as the external lead 1001 is outside the package and exchanges voltage with the outside. However, the internal lead 1003 does not come out of the package. The internal lead 1003 is a portion connected to the outside as a function for transmitting a signal and a power supply potential to the inside even if the cut section of the support base in the original mold is exposed to the outside of the package. It is characterized by not having.

  The external lead 1001 and the internal lead 1003 are connected by a wire 1007. The internal lead 1003 is connected to the reference potential generation circuit 1013 with a wire 1009. That is, the power supply potential is transmitted from the external lead 1001 to the reference potential generation circuit 1013 through the wire 1007, the internal lead 1003, and the wire 1009.

  Here, noise accompanying the operation of the sense system circuits 817 and 819 is transmitted to the external lead 1001 via the active VDC 801, the pad 1011, and the wire 1005. This noise must pass through the two wires 1007 and 1009 before reaching the reference potential generation circuit 1013. In this case, an inductance component (L component) and a capacitance component (C component) are parasitic on the wires 1007 and 1009, and the inductance component and the capacitance component serve as a filter. Attenuated.

  A power supply potential is supplied to the active VDC 801 from an external lead 1001 which is a normal lead to an internal circuit via a wire 1005. In this embodiment, another lead different from the normal lead such as the external lead 1001, that is, the internal lead 1003 is provided, and the power supply potential is supplied to the internal circuit via the two wires 1007 and 1009 and the internal lead 1003. Is supplied to a reference potential generating circuit 1013.

  As described above, in the semiconductor device according to the tenth embodiment of the present invention, the internal lead 1003 different from the normal lead such as the external lead 1001 is provided, and the plurality of wires 1007 and 1009 and the internal lead 1003 are used. A power supply potential is supplied to a reference potential generation circuit 1013 that is susceptible to noise.

  For this reason, noise accompanying the operation of the sense system circuits 817, 819, 821, and 823 is transmitted to the reference potential generation circuit 1013 that is affected by noise through a plurality of paths after reaching the external lead 1001. During this time, the noise decreases. Further, the wires 1007 and 1009 function as a filter, and the noise is attenuated before reaching the reference potential generating circuit 1013 that is easily affected by the noise. In addition, the present embodiment has the same effect as the ninth embodiment.

  In the present embodiment, the means for transmitting the power supply potential from the outside has been described. However, the present embodiment can also be used for a ground potential, a normal control signal, and the like. Furthermore, in this embodiment, the power supply potential is supplied from the external lead 1001 through the two wires 1007 and 1009 and one internal lead 1003. However, the influence of noise such as the reference potential generation circuit via more internal frames or wires. The power supply potential may be transmitted to an internal circuit that is susceptible to power. Further, instead of the internal lead 1003, a package wiring can be used.

(Eleventh embodiment)
FIG. 21 is a schematic block diagram showing a semiconductor device according to the eleventh embodiment of the present invention.

  21, the semiconductor device according to the eleventh embodiment of the present invention is obtained by adding internal leads 901 and wires 903, 905, and 907 to the configuration of the semiconductor device according to the ninth embodiment of FIG. Therefore, the same parts as those in FIG. 19 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  In FIG. 21, leads for inputting signals from the outside are not shown. Generally, an internal power supply potential generated by an internal potential generation circuit such as an internal power supply potential drop circuit (VDC) is transmitted to a circuit inside the semiconductor device via an aluminum wiring. However, when transmission is performed only with this aluminum wiring, the resistance increases, the power supply impedance increases at the end far from the supply source of the internal power supply potential, and normal operation of the circuit receiving the internal power supply potential is expected. It may not be possible.

  Therefore, in this embodiment, as shown in FIG. 21, the internal power supply potential generated by the active VDC 801 is transmitted to the internal lead 901 through the wire 903. Then, a power supply potential is supplied from the internal lead 901 to the sense system circuit 817 through wires 907 and 905. The internal lead 901 is the same as the internal lead 1003 shown in FIG. The internal lead 901 is thicker than the aluminum wiring and has a small resistance.

  As described above, in the eleventh embodiment of the present invention, the internal power supply potential is supplied to the sense system circuit 817 through the internal lead 901 having a resistance smaller than that of the aluminum wiring. Therefore, even when the internal power supply potential is supplied to a circuit away from the active VDC 801 that generates the internal power supply potential, the potential drop is reduced, and the circuit that has received the internal power supply potential can operate normally. it can. In addition, the present embodiment has the same effect as the ninth embodiment.

  FIG. 22 is a schematic block diagram showing a modification of the semiconductor device according to the eleventh embodiment of the present invention.

  22 is different from FIG. 21 in connection means between the active VDC 801 and the internal lead 901 and connection means between the sense system circuit 817 and the internal lead 901. That is, in FIG. 21, the active VDC 801 and the internal lead 901 are connected by the wire 903, whereas in FIG. 22, they are connected by the interconnect 909. In FIG. 21, the internal lead 901 and the sense system circuit 817 are connected by wires 905 and 907, whereas in FIG. 22, they are connected by interconnects 911 and 913. Therefore, the same parts as those in FIG. 21 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  The internal power supply potential generated from the active VDC 801 is transmitted to the internal lead 901 via the interconnect 909. Further, the internal power supply potential transmitted to the internal lead 901 is transmitted to the sense system circuit 817 via the interconnects 911 and 913. Here, although not shown, the internal leads 901 are connected to pads on the chip by bumps. The bump is a conductive material such as solder. The interconnects 909, 911, and 913 are means for connecting the upper layer and the lower layer, and use an aluminum material.

  As described above, in the modified example of the eleventh embodiment of the present invention, the internal power supply potential generated from the active VDC 801 is applied to the end of the sense system circuit 817 through the internal lead 901 having a resistance smaller than that of the aluminum wiring. Supply. For this reason, the potential drop of the internal power supply potential can be reduced even at the end portion of the sense system circuit 817 away from the active VDC 801, and malfunction of the sense system circuit 817 can be prevented. In addition, the present embodiment has the same effect as the ninth embodiment.

  The interconnects 909, 911, and 913 are used for the connection between the active VDC 801 and the internal lead 901, and the connection between the sense system circuit 817 and the internal lead 901. However, the connection can also be made by bumps.

  FIG. 23 is a schematic block diagram showing another modification of the semiconductor device according to the eleventh embodiment.

  In FIG. 23, another modification of the eleventh embodiment is different from the configuration of the ninth embodiment shown in FIG. 19 in that internal leads 901, 919, 921, aluminum wiring 923, internal circuit 917, interconnects 909, 913 are provided. , 911, 925, 927, 929 and bumps 915 are added. Accordingly, the same parts as those in FIG. 19 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  Internal leads 901 are connected to pads on the chip using bumps 915. The bump 915 is a conductive material such as solder. The other internal leads 919 and 921 are not shown, but are connected to pads on the chip by bumps.

  The active VDC 801 and the internal lead 901 are connected by an interconnect 909. Internal lead 901 and sense system circuit 817 are connected by interconnects 911 and 913. The internal lead 901 and the aluminum wiring 923 are connected by an interconnect 925. Aluminum wiring 923 and internal lead 919 are connected by interconnect 927.

  Internal lead 919 and internal circuit 917 are connected by interconnect 929. The internal lead 901, the internal lead 919, and the internal lead 921 are provided in the same layer. In order to avoid contact between the internal lead 921 and the internal leads 901, 919, the internal lead 901 and the internal lead 919 are They are connected via an aluminum wiring 923 provided in a different layer.

  The internal power supply potential generated from the active VDC 801 is transmitted to the internal lead 901 via the interconnect 909. Further, the internal power supply potential is supplied to the sense system circuit 817 via the interconnects 911 and 913. Further, the internal power supply potential is transmitted to the internal lead 919 via the interconnect 925, the aluminum wiring 923 and the interconnect 927. The internal power supply potential is supplied from the internal lead 919 to the internal circuit 917 via the interconnect 929.

  Here, the internal leads 901, 919, and 921 are the same as the internal leads 1003 shown in FIG. Interconnects 909, 911, 913, 925, 927 and 929 are means for connecting the upper layer and the lower layer, and are the same as the interconnects 909, 911 and 913 shown in FIG.

  As described above, in another modification of the eleventh embodiment, the internal power supply potential generated from the active VDC 801 is converted to the sense system circuit 817 and the internal circuit using the internal leads 901 and 919 having a resistance smaller than that of the aluminum wiring. 917.

  For this reason, even when the internal power supply potential is supplied to the terminal portion of the sense circuit 817 or the internal circuit 917 that is remote from the active VDC 801 that is the supply source of the internal power supply potential, the potential drop is small and the sense circuit 817 A malfunction of the circuit 917 can be prevented. In addition, the present embodiment has the same effect as the ninth embodiment.

  Instead of the internal leads 901, 919, and 921, package wiring can be used. Bumps can be used in place of the interconnects 909, 913, 911, 925, 927, and 929.

(Twelfth embodiment)
FIG. 24 is a schematic block diagram showing a semiconductor device according to the twelfth embodiment of the present invention.

  24, the semiconductor device according to the twelfth embodiment is different from the semiconductor device according to the ninth embodiment shown in FIG. 19 in that external leads 1001, 1101, internal leads 1103, 1105, 1/2 Vcc generation circuit 1107, A reference potential generating circuit 1013, 1109, a filter 1111, wires 1005, 1007, 1009, 1113, 1117, 1115, 1119 and a pad 1011 are added. Therefore, the same parts as those in FIG. 19 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  The external lead 1001 is the same as the external lead 1001 in FIG. The internal leads 1103 and 1105 are the same as the internal lead 1003 in FIG. Reference potential generation circuits 1013 and 1109 are the same as reference potential generation circuit 1013 in FIG. 1/2 Vcc generation circuit 1107 is similar to 1/2 Vcc generation circuits 805 and 809. The external lead 1101 is for transmitting other control signals different from the external power supply potential applied to the external lead 1001.

  External lead 1001 and active VDC 801 are connected via wire 1005 and pad 1011. The internal lead 1103 and the external lead 1001 are connected by a wire 1007. Internal lead 1103 and reference potential generation circuit 1013 are connected via wire 1009 and pad 1011. The internal lead 1103 and the filter 1111 are connected via the wire 1113 and the pad 1011. The filter 1111 and the internal lead 1105 are connected via the wire 1117 and the pad 1011. Internal lead 1105 and reference potential generation circuit 1109 are connected via wire 1119 and pad 1011. Internal lead 1103 and 1/2 Vcc generation circuit 1107 are connected through wire 1115 and pad 1011.

  In order for internal lead 1103 receiving external power supply potential from external lead 1001 through wire 1007 to supply potential to a desired circuit such as reference potential generation circuit 1013 or 1/2 Vcc generation circuit 1107, external lead It is necessary to pass over the lead 1101. That is, the external lead 1101 provided in the same layer as the external lead 1001 and the internal lead 1103 are provided so as to overlap.

  In this case, an insulating film is inserted between the internal lead 1103 and the external lead 1101 so that the external lead 1101 and the internal lead 1103 come into contact with each other and do not malfunction. Alternatively, a space is provided between the external lead 1101 and the internal lead 1103 so that the space is not contacted by being filled with an insulating resin or the like. Thus, in this embodiment, the external lead 1101 and the internal lead 1103 are provided in different layers via an insulating film or the like.

  The internal lead 1103 is branched into a plurality of parts b, c, and d with reference to the part a. Further, the internal lead 1103 is formed in a frame shape. That is, the internal lead 1103 is formed in a stitch shape.

  An external power supply potential supplied to the external lead 1001 is transmitted to the internal frame 1103 via the wire 1007. The power supply potential is supplied from the internal frame 1103 to the reference potential generation circuit 1013 through the wire 1009 and the pad 1011.

  The power supply potential is further supplied from internal lead 1103 to ½ Vcc generation circuit 1107 via wire 1115 and pad 1011. The power supply potential is supplied from the internal lead 1103 to the internal lead 1105 via the wire 1113, the filter 1111, the pad 1011, and the wire 1117. The power supply potential is supplied from the internal lead 1105 to the reference potential generation circuit 1109 via the wire 1119 and the pad 1011. The internal lead 1105 may be provided in the same layer as the external lead 1101 or in the same layer as the internal lead 1103.

  As described above, in the semiconductor device according to the twelfth embodiment of the present invention, the external lead 1101 and the internal lead 1103 are provided in different layers. For this reason, the freedom degree of the shape of the external lead 1101 or the internal lead 1103 increases. In FIG. 24, the external lead 1101 is provided in the lower layer and the internal lead 1103 is provided in the upper layer, but this vertical relationship may be reversed. Further, the external leads 1101 for inputting external signals may be upper layers or lower layers. Thus, by providing the external leads 1101 randomly regardless of the upper layer and the lower layer, the degree of freedom of the shape of the external leads 1101 and the internal leads 1103 is further improved.

  In the twelfth embodiment of the present invention, the power supply potential is supplied to the reference potential generating circuits 1013 and 1109 and the 1/2 Vcc generating circuit 1107 via the internal leads 1103 and 1105 having a resistance higher than that of the aluminum wiring. . Therefore, even if the reference potential generation circuits 1013 and 1109 and the 1/2 Vcc generation circuit 1107 are separated from the external lead 1001 which is the supply source of the power supply potential, the potential drop until reaching them is small, and the reference potential generation circuit 1013 It is possible to prevent the 1109 and 1/2 Vcc generation circuit 1107 from malfunctioning.

  Furthermore, in the twelfth embodiment of the present invention, the power supply potential is supplied from the external lead 1001 to the reference potential generation circuit 1013 via the wire 1007, the internal lead 1103, and the wire 1109. For this reason, the noise accompanying the operation of the sense system circuits 817 and 819 is reduced while passing through these plural paths.

  Furthermore, since the wires 1007 and 1009 function as a filter composed of an inductance component and a capacitance component, noise transmitted to the reference potential generation circuit 1013 is also reduced by the wires 1007 and 1009. The same can be said for the noise propagated to the ½ Vcc generation circuit 1107 and the reference potential generation circuit 1109.

  When the power supply potential is supplied from the external lead 1001 to the reference potential generation circuit 1109, the reference potential generation circuit 1109 further passes through the filter 1111. For this reason, the filter 1111 absorbs noise, and the noise propagated to the reference potential generation circuit 1109 is further reduced. In addition, the present embodiment has the same effect as the ninth embodiment.

  FIG. 25 is a schematic block diagram showing a modification of the semiconductor device according to the twelfth embodiment of the present invention.

  25, a modification of the twelfth embodiment is the same as that of the semiconductor device according to the ninth embodiment shown in FIG. 19, except that external leads 1001, 1211, 1213, 1233, first internal leads 1215, second Internal lead 1217, wires 1005, 1219, 1229, 1223, 1221, 1231, 1227, 1225 and a pad 1011 are added. Therefore, the same parts as those in FIG. 19 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  The first internal lead 1215 and the second internal lead 1217 are the same as the internal lead 1003 in FIG. The external leads 1001 and 1233 are the same as the external leads 1001 in FIG. The external leads 1211 and 1213 are the same as the external leads 1101 in FIG.

  The active VDC 801 and the external lead 1001 are connected via a wire 1005 and a pad 1011. The active VDC 801 and the first internal lead 1215 are connected through a pad 1011 and a wire 1219. First internal lead 1215 and sense system circuit 817 are connected via wire 1223 and pad 1011. Each of the plurality of external leads 1211 is connected to each of the plurality of pads 1011 on the chip by wires 1229.

  External lead 1233 and active VDC 807 are connected by wire 1225 and pad 1011. The active VDC 807 and the second internal lead 1217 are connected via a wire 1227 and a pad 1011. Second internal lead 1217 and sense system circuit 821 are connected through wire 1221 and pad 1011. Each of the plurality of external leads 1213 is connected to each of a plurality of pads 1011 provided on the chip via wires 1231.

  The external lead 1211 and the first internal lead 1215 are provided in different layers in the same manner as described in FIG. Here, the external leads 1001 and 1211 are provided in the first layer (lower layer), and the first internal lead 1215 is provided in the second layer (upper layer). The external leads 1213 and 1233 and the second internal lead 1217 are provided in the first layer. Therefore, the wire 1231 that connects each of the plurality of external leads 1213 and the plurality of pads 1011 on the chip straddles the second internal lead 1217.

  The internal power supply potential generated in the active VDC 801 is supplied to the sense system circuit 817 via the wire 1219 and the first internal lead 1215. The internal power supply potential generated from the active VDC 807 is supplied to the sense system circuit 821 via the wire 1227, the second internal lead 1217, and the wire 1221.

  As described above, in the modification of the twelfth embodiment, the plurality of external leads 1211 and the first internal leads 1215 are provided in different layers. Further, sense system circuit 817 and sense system circuit 821 are supplied with an internal power supply potential via first internal lead 1215 and second internal lead 1217, respectively. For this reason, also in the modified example of the twelfth embodiment, the same effect as that of the twelfth embodiment is obtained.

  FIG. 26 is a schematic block diagram showing another modification of the semiconductor device according to the twelfth embodiment.

  In another modification of the twelfth embodiment shown in FIG. 26, a wire 1237 and a pad 1239 are provided in the configuration of the modification of the twelfth embodiment shown in FIG. Further, a first internal lead 1235 is provided instead of the first internal lead 1215 of FIG. Therefore, the same parts as those in FIG. 25 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

  The first internal lead 1235 is formed in a frame shape. Similarly to FIG. 25, the plurality of external leads 1211 and the first internal leads 1235 are provided in different layers. The pad 1039 provided on the chip and the first internal lead 1235 in the gap between the external leads 1211 is connected by a wire 1237.

  As described above, in another modification of the twelfth embodiment of the present invention, a wire can be arbitrarily provided on each surface of the first internal lead 1235 that extends two-dimensionally. Therefore, connection with a pad provided arbitrarily on the chip is possible, and an internal power supply potential can be supplied to any point on the chip. Other effects are the same as those of the modified example of the twelfth embodiment shown in FIG.

(Thirteenth embodiment)
FIG. 27 is a circuit diagram showing in detail the configuration of the filter according to the thirteenth embodiment of the present invention.

  In FIG. 27, the filter according to the thirteenth embodiment includes a plurality of first fuses 1411, a plurality of resistors 1413, a plurality of second fuses 1415, and a plurality of capacitors 1417. Note that the filter in FIG. 27 constitutes a low-pass filter.

  The plurality of resistors 1413 are connected in series. A first fuse 1411 is connected in parallel to each of the plurality of resistors 1413. Each of the plurality of second fuses 1415 and each of the plurality of capacitors 1417 are connected in series between the node N and the ground. The node N is connected to one end of a plurality of resistors 1413 connected in series.

  Polysilicon or the like is used for the first fuse 1411. Accordingly, since each of the plurality of resistors 1413 is connected to each of the plurality of first fuses 1411 made of polysilicon or the like, each of the plurality of resistors 1413 does not function as a resistor. The first fuse 1411 made of polysilicon or the like is blown by a laser or the like. The resistor 1413 corresponding to the blown first fuse 1411 acts as a resistor. That is, the total resistance value of the filter can be adjusted by the number of first fuses 1411 to be blown.

  Each of the plurality of capacitors 1417 is connected to the node N via each of the plurality of second fuses 1415. In this case, each of the plurality of capacitors 1417 functions as a capacitor. Here, the plurality of second fuses 1415 are made of polysilicon or the like, like the first fuses 1411. The second fuse 1415 made of polysilicon or the like is blown by a laser or the like.

  In this case, the capacitor 1417 corresponding to the blown second fuse 1415 is disconnected from the node N. That is, the separated capacitor 1417 does not function as a capacitance. Thereby, the total capacity value of the filter can be adjusted by the number of second fuses to be blown.

  As described above, in the filter according to the thirteenth embodiment of the present invention, each of the plurality of first fuses 1411 is connected in parallel to each of the plurality of resistors 1413, and each of the plurality of capacitors 1417 is connected in series. Each of the plurality of second fuses 1415 is connected. For this reason, the resistance value and the capacitance value of the entire filter can be adjusted by the number of fusing of the first fuse 1411 or the second fuse 1415.

  The filter according to the thirteenth embodiment can be used as the low-pass filter or filter described in FIGS. 3, 7, 9, 10, 11, 15, and 24.

  It should be noted that any combination of the first to thirteenth embodiments may be used in a path from a package frame (lead) of the semiconductor device to a node that receives a predetermined voltage or a predetermined signal in an internal circuit of the semiconductor device. it can. In this case, the synergistic effect of each embodiment can be obtained.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing a semiconductor device according to a first embodiment of the present invention. It is a schematic block diagram which shows the example of a change of the semiconductor device by the 1st Example of this invention. It is a schematic block diagram which shows the semiconductor device by the 2nd Example of this invention. FIG. 4 is a circuit diagram showing details of a low-pass filter (LPF) shown in FIG. 3. It is a figure which compares and shows the noise which the stable circuit of FIG. 3 receives with the case where a low pass filter is not used and the case where it is not used. FIG. 6 is a diagram showing a noise level riding on a reference potential generated from a reference potential generation circuit as a stable circuit when the noise frequency indicated by line a1 in FIG. 5 is changed. It is a schematic block diagram which shows the example of a change of the semiconductor device by the 2nd Example of this invention. It is a schematic block diagram which shows a general semiconductor device. It is a schematic block diagram which shows the semiconductor device by the 3rd Example of this invention. It is a schematic block diagram which shows the example of a change of the semiconductor device by 3rd Example of this invention. It is a schematic block diagram which shows the semiconductor device by the 4th Example of this invention. It is a schematic block diagram which shows a general semiconductor device. It is a schematic block diagram which shows the semiconductor device by the 5th Example of this invention. It is a schematic block diagram which shows the semiconductor device by the 6th Example of this invention. It is a schematic block diagram which shows the semiconductor device by the 7th Example of this invention. It is a schematic block diagram which shows the semiconductor device by the 8th Example of this invention. It is a schematic block diagram which shows the example of a change of the semiconductor device by the 8th Example of this invention. It is a schematic block diagram which shows the other modification of the semiconductor device by the 8th Example of this invention. It is a schematic block diagram which shows the semiconductor device by the 9th Example of this invention. It is a schematic block diagram which shows the semiconductor device by the 10th Example of this invention. It is a schematic block diagram which shows the semiconductor device by 11th Example of this invention. It is a schematic block diagram which shows the example of a change of the semiconductor device by 11th Example of this invention. It is a schematic block diagram which shows the other modification of the semiconductor device by 11th Example of this invention. It is a schematic block diagram which shows the semiconductor device by the 12th Example of this invention. It is a schematic block diagram which shows the example of a change of the semiconductor device by the 12th Example of this invention. It is a schematic block diagram which shows the other modification of the semiconductor device by the 12th Example of this invention. It is a circuit diagram which shows the filter by 13th Example of this invention in detail. It is a schematic block diagram which shows the conventional semiconductor device. It is a figure which shows the level of the noise which generate | occur | produces when the internal circuit of FIG. 28 operate | moves.

Explanation of symbols

  1 Package frame, 3 bonding wire, 5,800 semiconductor device, 7 GND package frame, 9 GND bonding wire, 11, 1011, 1039 pad, 13, 101, 217, 409, 505, 601, 717, 825 First internal Power line, 15, 103, 219, 411, 507, 603, 827 Second internal power line, 17 GND pad, 19, 309 Internal GND line, 21, 209, 305, 917 Internal circuit, 23, 211, 307 Stable Circuit, 25, 109 First internal GND line, 27, 111 Second internal GND line, 105, 221, 413, 605, 733, 829 Third internal power supply line, 107, 114, 227, 229 Low-pass filter ( LPF), 113 Third internal GND line, 105, 721, 7 29, 1413 Resistance, 107, 1417 Capacitor, 201, 407, 1511 Internal power supply line, 203 well, 205, 207 transistor, 213 Well fixed diffusion layer for internal circuit, 215 Well fixed diffusion layer for stable circuit, 223, 225, 419 4th internal power supply line, 301 external power supply line, 303 internal potential generation circuit, 311 1st internal potential line, 313 2nd internal potential line, 315 3rd internal potential line, 401 DC-DC converter, 403, 501 Micro-current DC-DC converter, 405 External GND line, 415 First micro-current DC-DC converter, 417 Second micro-current DC-DC converter, 503, 709, 731, 811, 813, 815 switch , 701 First comparator, 703, 707, 725 PM S transistor, 705 second comparator, 711, 727, 817, 819, 821, 823 sense system circuit, 713, 805, 809, 1107 1/2 Vcc generation circuit, 715 reference potential supply line, 723 third comparator, 801 Active internal power supply potential drop circuit (VDC), 803 Standby internal power supply potential drop circuit (VDC), 901, 919, 921, 1003, 1103, 1105, internal lead, 903, 905, 907, 1005, 1007, 1009, 1113, 1115, 1117, 1119, 1219-1231, 1237 Wire, 909, 911, 913, 925, 927, 929 Interconnect, 915 Bump, 923 Aluminum wiring, 1001, 1101, 1211, 1213, 1233 External Lead, 1013, 1109 Reference potential generation circuit, 1111 filter, 1215, 1235 first internal lead, 1217 second internal lead, 1411 first fuse, 1415 second fuse.

Claims (12)

A first internal circuit causing noise,
A second internal circuit affected by the noise;
First internal potential generating means for generating a first internal potential to be supplied to the first internal circuit;
A first internal potential supply line for supplying the first internal potential to the first internal circuit;
Second internal potential generating means for generating a second internal potential to be supplied to at least the second internal circuit;
A second internal potential supply line for supplying the second internal potential to the second internal circuit ;
The first internal potential supply line and the second internal potential supply line are coupled to the first internal potential supply line and the second internal potential supply line from the first internal circuit via the first internal potential supply line and the second internal potential supply line. And a noise blocking means for blocking noise propagating to the internal circuit. The first internal potential generating means generates the first internal potential when the semiconductor device is in an operating state,
The noise blocking means is
Wherein in accordance with the state of the semiconductor device, comprising the first internal circuit and before Symbol connection control means to control the connection between the first internal voltage supply line and said second internal voltage supply lines, according to claim 1 The semiconductor device described . The connection control means includes
When the semiconductor device is in an operating state, the first internal circuit and the second internal potential supply line are separated from each other, and the first internal circuit and the first internal potential supply line are separated from each other. Connect
When the semiconductor device is in a standby state, the first internal circuit and the first internal potential supply line are disconnected, and the first internal circuit and the second internal potential supply line are separated from each other. The semiconductor device according to claim 2, wherein: The first internal potential generating means generates a first internal potential to be supplied to the first internal circuit and the second internal circuit when the semiconductor device is in an operating state .
The noise blocking means is
Wherein provided between the first and second internal voltage supply lines, Ru provided with a filter to reduce the noise, the semiconductor device according to claim 1, wherein. The noise blocking means is
The first internal potential supply line and the second internal potential supply line are provided between the first internal potential supply line and the second internal potential supply line, depending on the state of the semiconductor device. controlling the connection between, and a first connection control hand stage, the semiconductor device according to claim 1, wherein. The first connection control means includes:
When the semiconductor device is in the first state, the first internal potential supply line and the second internal potential supply line are disconnected,
When the semiconductor device is in the second state, the first internal potential supply line and the second internal potential supply line are connected,
6. The second internal potential generation unit supplies the second internal potential to the first internal circuit when the semiconductor device is in the second state. Semiconductor device. The first state is an operating state of the semiconductor device,
The second state is a standby state of the semiconductor device,
The semiconductor device according to claim 6, wherein in the standby state, the first internal potential generating means stops. The first state is a first operation state of the semiconductor device,
The semiconductor device according to claim 6, wherein the second state is a second operation state of the semiconductor device.   The semiconductor device according to claim 5, further comprising a resistance element connected between the first internal potential supply line and the second internal potential supply line. A third internal circuit causing the second noise;
Third internal potential generating means for generating a third internal potential to be supplied to the third internal circuit;
A third internal potential supply line for connecting the third internal potential generating means and the third internal circuit and supplying the third internal potential;
The second internal potential supply line and the third internal potential supply line are provided between the second internal potential supply line and the third internal potential supply line, depending on the state of the semiconductor device. The semiconductor device according to claim 5, further comprising second connection control means for controlling connection to the.   The semiconductor device according to claim 10, further comprising a resistance element connected between the second internal potential supply line and the third internal potential supply line. A third internal circuit causing the second noise;
Third internal potential generating means for generating a third internal potential to be supplied to the third internal circuit;
A third internal potential supply line for connecting the third internal circuit and the third internal potential generating means and supplying the third internal potential;
The first internal potential supply line and the third internal potential supply line, which are provided between the first internal potential supply line and the third internal potential supply line, depending on the state of the semiconductor device. The semiconductor device according to claim 5, further comprising second connection control means for controlling connection to the.

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