JP2006041555A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an output circuit integrating a termination circuit with a small occupied area that can transmit signals/data at a high speed. <P>SOLUTION: Termination transistors (11a, 11b, 15a, 15b) that combine termination resistors (13, 14), which are jointed by an output pad (5), with power nodes are arranged on the opposite side of the pad and output transistors (2a, 2b, 4a, 4b) that drive the output pad, in accordance with internal signals. The termination transistors and output transistors drive the pad from the both sides of the pad. The area of the termination circuit can be reduced, while the reliability with respect to surge can be secured. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device for driving an output node, and more particularly to a semiconductor device having a bus termination function.

  In a semiconductor device, a transistor connected to a pin terminal is directly connected to the outside of the device through the pin terminal, and thus is easily affected by noise from the outside. Among noises, a noise that destroys a device (transistor) is called a surge. The breakdown of the semiconductor device due to the surge is called electrostatic breakdown (ESD), and the breakdown of the gate insulating film of the MOS transistor (insulated gate field effect transistor) occurs. In view of the reliability of the semiconductor device, therefore, a required withstand voltage against a surge is required.

  For an input pin that receives an external signal, an input protection circuit is usually constituted by a diode or a diode-connected MOS transistor (insulated gate field effect transistor) or a field transistor having a sufficiently thick gate insulating film. . With this input protection circuit, a surge is passed to the power supply terminal or the ground terminal to prevent the surge from being transmitted to the internal circuit.

  In the output circuit, since the output transistor functions as a surge absorbing transistor, it is not necessary to provide a special protection circuit. However, in a MOS output circuit composed of MOS transistors, a large current flows through the output transistor due to a surge voltage, and a high drain electric field may be generated to cause electrostatic breakdown. In order to prevent such electrostatic breakdown, in order to reduce the drain current and the drain electric field, it is necessary to increase the resistance value (drain diffusion resistance) of the drain region in the output transistor. Usually, in order to increase the drain resistance, it is required to make the distance between the gate of the output transistor and the drain contact for connecting to the output node sufficiently long. That is, the area of the diffusion region in the drain portion of the output transistor is increased, and the size of the output transistor is increased.

  Japanese Patent Application Laid-Open No. 2001-127173 proposes a configuration that suppresses an increase in the area of the output circuit and prevents electrostatic breakdown. In Patent Document 1, in the output transistor, the drain diffusion resistance value is increased by making the impurity concentration of the drain diffusion region different from that of the source diffusion region.

  Japanese Patent Laid-Open No. 11-214621 discloses a configuration in which a termination resistance element and a protection element for the termination resistance element are provided between an output transistor and an output pad. In this Patent Document 2, an electrostatic protection element is. The distance between the gate and the drain contact is increased in order to increase the resistance of the drain region, that is, the drain diffusion resistance. Taking advantage of the large area of the drain diffusion region, the termination resistance element is disposed above the throat region of the electrostatic protection element to suppress an increase in the layout area of the entire output circuit. This termination resistance element is a current limiting resistance element for preventing reflected waves such as ringing during signal transmission, and is connected between the output pad and the output node (drain) of the output transistor.

In Patent Document 3 (Japanese Patent Laid-Open No. 10-65744), impedance switching means is arranged between the output terminal and the output circuit, and this impedance switching means lowers the impedance during transmission and increases the impedance during reception. Thus, a configuration for reducing the reflection noise caused by the capacitive load of the transmission path is shown.
JP 2001-127173 A Japanese Patent Laid-Open No. 11-214621 JP-A-10-65744

  In the configuration shown in Patent Document 1, it is necessary to change the impurity concentration of the source and drain of the output transistor, which increases the number of manufacturing steps. This drain diffusion resistor is always connected to an external bus via a pin terminal. When the drain diffusion resistor functions as a termination resistor, when the signal is output, the output signal is driven through the high drain diffusion resistor, and the signal cannot be transmitted at high speed.

  Further, in the configuration shown in Patent Document 2, a protection circuit for the termination resistance element is arranged corresponding to the output circuit. In the MOS transistor of this protection circuit, the distance between the drain contact and the gate electrode is sufficiently large so that a termination resistor can be arranged on the upper part. Therefore, the area of the boundary between the drain region and the substrate region is large, the large drain junction capacitance of this protection circuit is connected to the output pin terminal, the parasitic capacitance of the output pin terminal is increased, and signals can be transferred at high speed. become unable. In addition, since the terminating resistance element is connected between the drain of the output transistor and the output pad and functions as a current limiting element for the output signal, a signal cannot be output at high speed. In addition, a voltage drop occurs due to this termination resistor, and thus a CMOS level signal cannot be transmitted.

  In the configuration shown in Patent Document 3, an impedance switching circuit that switches the impedance at the time of transmission and at the time of reception is arranged for the output pin terminal. However, even in this case, it is necessary to provide a protection element against surge, and the area occupied by the circuit for changing the termination resistance according to the operation mode increases. In particular, if this termination resistance control circuit part is configured with a transistor that increases the drain diffusion resistance, the load on the output pin will increase in the same manner, making it impossible to transfer signals at high speed, and the area occupied by the output circuit. Will increase. In Patent Document 3, only suppression of ringing at the time of signal transmission / reception is considered, and a configuration for reducing the area of the main circuit and the load on the transmission path is not considered.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device capable of accurately transferring a signal at high speed without causing an increase in area and a decrease in reliability.

  Another object of the present invention is to provide a semiconductor circuit device including an output circuit having a built-in termination circuit with a small occupying area and capable of transferring a CMOS level signal at high speed.

  The semiconductor device according to the present invention includes a pad, a first output transistor formed in the first active region, and a second active region disposed opposite to the first active region. Output transistor, a first termination resistance element having one end coupled to the pad, a first termination transistor formed in the third active region and coupled to the first termination resistance element, and coupled to the pad A second termination resistance element having one end and a second termination transistor formed in the fourth active region and coupled to the other end of the second termination low-term element.

  The first output transistor has a first source region coupled to a first voltage node, and a first drain region coupled to a pad via a first control gate and a first drain contact. Then, the pad is driven in accordance with an internal signal given to the first control gate.

  The second output transistor has a second source region coupled to the second voltage node, a second control gate, and a second drain region coupled to the pad via the second drain contact. And has a second distance, and drives the pad in accordance with an internal signal applied to the second control gate.

  A third control gate for receiving a first termination transistor termination operation activation signal; and a third drain region coupled to the other end of the first termination resistance element via a third drain contact; It selectively conducts in accordance with a termination operation activation signal applied to the third control gate. The second termination transistor is coupled to the other end of the second termination resistance element via a fourth source region coupled to the fourth voltage node, a fourth control gate, and a fourth drain contact. A fourth drain region, and is selectively rendered conductive in accordance with a termination operation activation signal applied to the fourth control gate.

  Also, by arranging the output circuit components and the termination circuit components on both sides of the pad, the termination circuit can be arranged without affecting the layout of the internal circuit of the output circuit. The output circuit and the termination circuit can be arranged by using the layout of the output circuit of the semiconductor device that is not provided.

  Further, the surge resistance of the termination transistor can be guaranteed by arranging the termination resistor. As a result, a semiconductor device including an output circuit that can transfer signals at high speed with high reliability and a small occupation area can be realized.

[Embodiment 1]
FIG. 1 shows a structure of a main portion of the semiconductor device according to the first embodiment of the present invention. In FIG. 1, an output circuit 1 and a termination circuit 10 provided for the external pad 5 are representatively shown. The pad 5 is connected to a pin terminal (not shown).

  Output circuit 1 is connected between a power supply node and output node 3, and is connected between P channel MOS transistors 2a and 2b which are selectively turned on according to output control signal ZOTH, and between output node 3 and the ground node. N channel MOS transistors 4a and 4b selectively conducting according to signal OTL are included. Power supply voltage VCCQ for output circuit is applied to the power supply node, and ground voltage VSSQ for output circuit is applied to the ground node. Output node 3 is connected to output pad 5.

  Output control signals ZOTH and OTL have their logic levels set according to the operation state of output circuit 1 and internal signals. When output control signal ZOTH is at H level and output control signal OTL is at L level, MOS transistors 2a, 2b, 4a and 4b are all in an off state, and output circuit 1 is set to an output high impedance state. . In this output high impedance state, the output circuit 1 is in a standby state. When output control signals ZOTH and OTL both attain an H level, MOS transistors 2a and 2b are both turned off and MOS transistors 4a and 4b are both turned on, and output node 3 is driven to the level of ground voltage VSSQ.

  When output control signals ZOTH and OTL are both at L level, MOS transistors 2a and 2b are turned on, and both MOS transistors 4a and 4b are turned off. In response, output node 3 is driven to output circuit power supply voltage VCCQ level.

  During the operation of the output circuit 1, the output control signals ZOTH and OTL are generated according to internal signals. This internal signal is internal read data when the semiconductor device is applied to a memory device, and output control signals ZOTH and OTL are generated based on the internal data and the read operation timing control signal.

  The reason why two MOS transistors 2a and 2b are provided in parallel or two MOS transistors 4a and 4b are provided in parallel is as follows. Each of these MOS transistors 2a, 2b, 4a and 4b is constituted by a unit MOS transistor, and a plurality of unit transistors are used in order to give a necessary driving force to the output circuit 1. Therefore, the number of pull-down N-channel MOS transistors for output discharge and the number of pull-up P-channel transistors for output charging depend on the driving force required for external pad 5 and the current driving force of the unit MOS transistor. Determined appropriately.

  Termination circuit 10 includes a resistance element 13 having one end connected to output node 12, a P-channel MOS transistor 11a connected between the other end of resistance element 13 and the power supply node and receiving termination control signal ZTERM at the other gate. 11b, a resistance element 14 having one end connected to output node 14, and N channel MOS transistors 15a and 15b connected between the other end of resistance element 14 and the ground node and receiving termination control signal TERM at its gate. .

  Voltages VCC and VSS applied to termination circuit 10 are voltages applied from power supply terminals different from voltages VCCQ and VSSQ applied to output circuit 1. The operation power supply voltages VCCQ and VSSQ are given exclusively to the output circuit 1, thereby stabilizing the operation of the output circuit 1 or preventing the power supply noise during the output operation from being transmitted to other circuits. However, voltages VCC and VSS applied to termination circuit 10 may be voltages supplied from the same power supply terminal as voltages VCCQ and VSSQ applied to output circuit 1. The voltages VCC and VCCQ may be at the same voltage level or may be at different voltage levels.

  The termination control signals ZTERM and TERM are mutually complementary control signals. When the termination operation of termination circuit 10 is activated, termination control signal ZTERM is set to L level and termination control signal TERM is set to H level. When stopping the termination operation of the termination circuit 10, the termination control signal ZTERM is set to H level and the termination control signal TERM is set to L level.

  In this termination circuit 10, two MOS transistors 11 a and 11 b are provided on the H level side, and two MOS transistors 15 a and 15 b are provided on the L level side, as in the output circuit 1. Is used to form P and N channel switching MOS transistors for termination control.

  In termination circuit 10, MOS transistors 11 a and 11 b are connected to output node 12 through resistance element 13, and MOS transistors 15 a and 15 b are connected to output node 12 through resistance element 14. The output node 12 is connected to the pad 5. Therefore, the termination controlling MOS transistors 11a, 11b, 15a and 15b are specified from the viewpoint of reliability against electrostatic breakdown like the output MOS transistors 2a, 2b, 4a and 4b directly connected to the output pins. It is not always necessary to comply with the distance between the drain contact and the gate. Therefore, the drain contact-gate distance of MOS transistors 11a and 11b is made shorter than that of MOS transistors 2a and 2b, or the drain contact-gate distance of MOS transistors 15a and 15b is set to that of MOS transistors 4a and 4b. Shorter than. By shortening the distance between the drain contact and the gate, the drain resistance is reduced, and the layout area of the drain region of the termination transistors 11a, 11b, 15a and 15b is reduced.

  The relationship between termination control signals TERM and ZTERM for termination circuit 10 and output control signals ZOTH and OTL is not particularly defined. During the signal / data output operation of the output circuit 1, the termination operation of the termination circuit 10 may be activated. Also, a configuration may be used in which the termination operation of the termination circuit 10 is stopped and the termination circuit of a circuit connected to another signal bus (not shown) is activated during the signal / data output operation of the output circuit 1. . Further, when this pad 5 is also connected to a signal input pin and this pad 5 is connected to an input circuit (not shown), the termination operation of the termination circuit 10 may be stopped or activated during this signal input operation. May be.

  Further, the activation period of the termination operation of the termination circuit 10 may be set according to the condition of the load connected to the external bus.

  Therefore, the activation / activation timing and period of termination control signals TERM and ZTERM are appropriately determined according to the termination control conditions of the bus of the system to which this semiconductor circuit device is applied.

  FIG. 2 schematically shows a planar layout of the MOS transistors of output circuit 1 and termination circuit 10 shown in FIG. 2, MOS transistors 2a and 2b of output circuit 1 are formed in a rectangular active region 18, or output MOS transistors 4a and 4b are arranged in a rectangular active region facing this active region 18. 19 is formed.

  The active region 18 includes a drain impurity region PDa formed in the central portion and source impurity regions PSa and PSb formed on both sides thereof. A gate electrode 22a is disposed between the source impurity region PSa and the drain impurity region PDa, and a gate electrode 22b is disposed between the drain impurity region PDa and the source impurity region PSb. Drain impurity region PDa is shared by transistors 2a and 2b. An output control signal ZOTH is commonly applied to these gate electrodes 22a and 22b.

  Source impurity regions PSa and PSb are connected to a power supply node via source contacts 20a and 20b, respectively. Drain impurity region PDa is connected to output node 3 through drain contact 21a. The distance between the drain contact 21a and the gate electrode 22a is Lpo. Similarly, although not clearly shown, the distance between the drain contact 21a and the gate electrode 22b of the MOS transistor 2b is also Lpo.

  Also in active region 19, N-type drain impurity region NDa is arranged at the center, and N-type source impurity regions NSa and NSb are arranged on both sides thereof. A gate electrode 22c is disposed between the N-type source impurity region NSa and the N-type drain impurity region NDa, and a gate electrode 22d is disposed between the drain impurity region NDa and the source impurity region NSb. This drain impurity region NDa is shared by MOS transistors 4a and 4b. Drain impurity region NDa is connected to output node 3 through drain contact 21b. The distance between the drain contact 21b and the gate electrode 22c is Lno. Similarly, although not clearly shown in FIG. 2, the same distance Lno is secured for the drain contact 21b and the gate electrode 22b. Source impurity regions NSa and NSb are electrically connected to the ground node via source contacts 22c and 22d, respectively.

  In termination circuit 10, termination MOS transistors 11 a and 11 b are formed in P-type active region 30, and MOS transistors 15 a and 15 b are formed in N-type active region 32. In P type active region 30, drain impurity region PDb is formed at the center, and source impurity regions PSc and PSd are formed on both sides thereof. A gate electrode 22e is disposed between the drain impurity region PDb and the source impurity region PSc, and a gate electrode 22f is disposed between the drain impurity region PDb and the source impurity region PSd.

  Impurity region PDb is shared by MOS transistors 11a and 11b. The drain impurity region PDb is connected to the other end of the resistance element 13 through the drain contact 21c. Source impurity regions PSc and PSd are electrically connected to a power supply node via source contacts 20e and 20f, respectively. The distance between the drain contact 21c and the gate electrode 22e is Lpt. Similarly, the distance between the drain contact 21c and the gate electrode 22f is Lpt. FIG. 2 shows the distance between the drain contact and the gate of the MOS transistor 11a.

  In the N-type active region 32, an N-type drain impurity region NDb is formed at the center, and N-type source impurity regions NSc and NSd are arranged on both sides thereof. A gate electrode 22g is disposed between the N-type source impurity region NSc and the N-type drain impurity region NDb, and a gate electrode 22h is disposed between the N-type drain impurity region NDb and the N-type source impurity region NSd. Source impurity regions NSc and NSd are electrically connected to the ground node via source contacts 20g and 20h, respectively. Drain impurity region NDb is connected to the other end of resistance element 14 through drain contact 21d. Each of resistance elements 13 and 14 has one end connected to node 12. The distance between drain contact 21d and gate electrodes 22g and 22h of MOS transistors 15a and 15b is Lnt.

  MOS transistor 2a and 2b have a drain contact-gate distance Lpo longer than the drain contact-gate electrode distance Lpt of MOS transistors 11a and 11b. Further, the drain contact-gate distance Lno of MOS transistors 4a and 4b is longer than the drain contact-gate electrode distance Lnt of MOS transistors 15a and 15b.

  If the drain impurity regions PDa and PDb have the same impurity concentration and the drain impurity regions NDa and NDb have the same impurity concentration, the drain resistance becomes smaller as the distance between the drain contact and the gate electrode is shorter. In this case, the electric field relaxation by the resistance elements 13 and 14 compensates for the drain resistance reduction of the MOS transistors 11a, 11b, 15a and 15b in the termination circuit 10.

  Termination resistor elements 13 and 14 may be formed of a diffused resistor, or may be formed of a polysilicon resistor.

  As shown in FIG. 2, the horizontal length of the P-type active region 30 in FIG. 2 is at least 2 · (Lpo−Lpt) shorter than the P-type active region 18. Similarly, the horizontal length of the N-type active region 32 is at least 2 · (Lno−Lnt) shorter than that of the N-type active region 19. Therefore, in this termination circuit 10, the area occupied by active regions 30 and 32 can be reduced as compared to the case where the same electrostatic discharge damage as that of MOS transistors 2a, 2b, 4a and 4b of output circuit 1 is performed. it can. Accordingly, the occupation area of termination circuit 10 can be reduced, and an increase in the occupation area of the semiconductor circuit device including output circuit and termination circuit 10 can be suppressed. Relaxation of the drain electric field / current of termination transistors 11a, 11b, 15a and 15b is realized by resistance elements 13 and 14, respectively, and electrostatic breakdown of termination transistors 11a, 11b, 15a and 15b can be prevented.

  Further, by using the termination circuit 10, it is possible to transmit signals at high speed via the pad 5 while maintaining impedance matching with the bus.

  In FIG. 2, the following formula is satisfied for the distance between the drain contact and the gate electrode.

Lpo> Lpt, Lno> Lnt.
However, in this case, the following conditional expression may be satisfied.

Lpo> Lpt, Lno> Lpt,
Lpo> Lnt and Lno> Lnt.

  In the configuration shown in FIG. 2, the output transistors 2a, 2b, 4a, and 4b are configured by two unit transistors. Also in the termination circuit 10, the MOS transistors 11a, 11b, 15a, and 15b, In the unit transistors, termination transistors for pull-up and pull-down are formed, respectively. However, depending on the load of the pad 5, they may be formed as an output control transistor or a termination control transistor using three or more unit transistors. If the number of unit transistors used increases, the effect of area reduction due to the reduction of the distance between the drain contact and the gate electrode becomes more remarkable.

[Modification 1]
FIG. 3 schematically shows a layout of the transistors of output circuit 1 and termination circuit 10 according to the first modification of the first embodiment of the present invention. The layout of the semiconductor circuit device shown in FIG. 3 differs from the layout of the semiconductor circuit device shown in FIG. 2 in the following points. That is, in the termination circuit 10, a circuit portion that performs pull-down termination is not arranged. Termination resistance element 13 and P activation region 30 for forming P channel MOS transistors 11a and 11b are provided. In P active region 30, distance Lpt between drain contact 21 c and gate electrodes 22 e and 22 f is made sufficiently smaller than the corresponding distance Lpo of the P channel MOS transistor included in output circuit 1. In this case, the distance Lpt is shorter than the drain contact-gate electrode distance Lno of the N-channel MOS transistor of the output circuit 1.

  Other configurations of the circuit layout shown in FIG. 3 are the same as those shown in FIG. 2, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration shown in FIG. 3, the configuration of output circuit 1 is the same as the configuration shown in FIG. Since the pull-down resistance element and the N-channel MOS transistor are not arranged in termination circuit 10, the area occupied by termination circuit 10 can be reduced, and the parasitic capacitance coupled to node 12 is also reduced. Thus, the pad 5 can be driven.

  FIG. 4 is a diagram showing an electrical equivalent circuit of the configuration shown in FIG. As shown in FIG. 4, in termination circuit 10, resistance element 13 has one end connected to node 12, and between this resistance element 13 and a power supply node, P channel MOS transistor 11a receiving termination control signal ZTERM at the gate and 11b is connected.

  The output circuit 1 includes pull-up transistors 2a and 2b and pull-down transistors 4a and 4b, similarly to the configuration shown in FIG.

  Termination circuit 10 has a low drain diffusion resistance of MOS transistors 11a and 11b and is not provided with pull-down transistors 15a and 15b. Therefore, termination circuit 10 performs a termination operation on node 12 with reduced parasitic capacitance at high speed. Can do. This termination operation condition is the same as that described above with reference to FIG. 1, and is appropriately determined according to the bus termination condition of the system used.

  Further, in this termination circuit 10, the drain junction capacitances of the MOS transistors 15a and 15b shown in FIG. 1 are not coupled to the pad 5 via the resistance element 13, so that the load on the pad 5 can be reduced and the pad 5 can be connected at high speed. The output circuit 1 can be driven.

  The configuration of the output circuit 1 is the same as that of the output circuit 1 shown in FIG. 1, and drives the pad 5 via the output node 3 in accordance with the output control signals ZOTH and OTL.

  In the termination control circuit 10 shown in FIG. 3, during the pull-down operation, the pad 5 is pulled up to the power supply voltage VCC level. The termination voltage VCC may be the same voltage as the power supply voltage VCCQ of the output circuit 1 or may be a voltage applied from a power supply terminal different from the power supply terminal of the power supply voltage VCCQ. Further, the voltages VCC and VCCQ may be at different voltage levels, or may be at different voltage levels. Termination circuit 10 may be composed of only a pull-down circuit that drives pad 5 to the ground voltage level during this termination operation (consisting of resistance element 14 and MOS transistors 15a and 15b).

[Modification 2]
FIG. 5 schematically shows a layout of the output circuit and termination circuit according to the second modification of the first embodiment of the present invention. The layout shown in FIG. 5 is different from the layout shown in FIG. 2 in the following points. That is, in the output circuit 1, the N-type active region 19 is disposed, and the P-type active region 18 is not disposed. The distance between the drain contact 21b and the gate electrode 22c in the N-type active region 19 is set to Lno. Source impurity regions NSa and NSb are coupled to the ground node via source contacts 20c and 20d, respectively.

  In this output circuit 1, MOS transistors 4a and 4b are arranged to drive output node 3 in accordance with output control signal OTL applied to gate electrodes 22c and 22d. Therefore, this output circuit drives the external signal line via the output pad 5 in accordance with the open drain method.

  The configuration of the termination circuit 10 is the same as the layout of the termination circuit 10 shown in FIG. 2, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration shown in FIG. 5, the drain contact-gate electrode distance Lpt of P channel MOS transistors 11a and 11b included in termination circuit 10 is equal to the gate electrode-drain contact of the N channel MOS transistor included in output circuit 1. It is made smaller than the distance Lno. Similarly, the drain contact-gate electrode distance Lnt of N channel MOS transistors 15a and 15b in termination circuit 10 is made smaller than the drain contact-gate electrode distance Lno of N channel MOS transistors 4a and 4b of output circuit 1. .

  In this output circuit 1, only an open drain circuit for pulling down the output node 3 in accordance with the output control signal OTL is arranged. Only the pull-down N-channel MOS transistor is connected to output node 3, the load on output node 3 can be reduced, and pad 5 can be driven at high speed.

  FIG. 6 is a diagram showing an electrical equivalent circuit of the configuration shown in FIG. In FIG. 6, in output circuit 1, N channel MOS transistors 4a and 4b receiving output control signal OTL at their gates are arranged in parallel between output node 3 and the ground node. Termination circuit 10 has the same circuit configuration as termination circuit 10 shown in FIG. Termination transistors 11a, 11b, 15a and 15b and termination resistors 13 and 14 are arranged.

  After the output circuit 1 drives the output pad 5 to the ground voltage VSSQ level according to the output control signal OTL, the pad 5 can be precharged again to the power supply voltage VCC level using the termination circuit 10. Further, since an open drain type output circuit is used, the load on the output circuit 1 is reduced, and an output signal can be generated at high speed.

  Also in the configuration of the open drain type output circuit 1, in the termination circuit 10, the distance between the gate electrode and the drain contact of the constituent MOS transistor is made small, and the occupied area can be made sufficiently small. It is possible to generate an output signal at high speed and accurately while suppressing an increase in the area occupied by the circuit.

[Modification 3]
FIG. 7 schematically shows a layout of a third modification of the semiconductor device according to the first embodiment of the present invention. The layout of the semiconductor device shown in FIG. 7 is different from the layout of the semiconductor device shown in FIG. That is, in termination circuit 10, resistance element 14 and N active region 32 are not arranged. Resistance element 13 and P active region 30 are arranged. That is, in termination circuit 10, P channel MOS transistors 11a and 11b terminating at the power supply voltage level are arranged. The distance Lpt between the drain contact 21c and the gate electrodes 22e and 22f of these P channel MOS transistors 11a and 11b is made smaller than the drain contact-gate electrode distance Lno of the N channel MOS transistor included in the output circuit 1. The Source impurity regions PSc and PSd are connected to a power supply node via source contacts 20a and 20f, respectively.

  Also in output circuit 1, source impurity regions NSa and NSb are connected to the ground node via source contacts 20c and 20d, respectively. That is, in the output circuit 1, N channel MOS transistors 4a and 4b are arranged, and a pull-up P channel MOS transistor is not arranged, as in the configuration shown in FIG.

  In the configuration shown in FIG. 7, pad 5 is driven to the ground voltage level by N channel MOS transistors 4a and 4b according to the open drain method, and pad 5 is terminated to the power supply voltage level.

  In the configuration of termination circuit 10 and output circuit 1 shown in FIG. 7, output pad 5 is driven in an open drain manner, and termination circuit 10 is connected to output pad 5 at an appropriate timing according to the bus conditions. To the power node. The load on the output pad 5 is only the drain junction capacitance and the wiring capacitance of the active regions 19 and 30, the drain junction capacitance of the N channel MOS transistor in the termination circuit 10 can be eliminated, and the output pad 5 is driven at a higher speed. can do.

  FIG. 8 is a diagram showing an electrical equivalent circuit of the semiconductor device shown in FIG. As shown in FIG. 8, in termination circuit 10, resistance element 13 and P channel MOS transistors 11a and 11b for selectively connecting resistance element 13 to a power supply node in accordance with termination control signal ZTERM are arranged.

  In output circuit 1, N channel MOS transistors 4a and 4b for driving output node 3 to ground voltage VSSQ level according to output control signal OTL are connected in parallel. Therefore, by driving the output pad 5 in an open drain manner and terminating the pad 5 at the power supply voltage VCC level, the load on the pad 5 can be reduced and signals can be transferred at high speed. The power supply voltage VCC applied to the termination circuit 10 may be the power supply voltage VCCQ or a different voltage.

  Even in this case, the drain contact-gate electrode distance Lpt of termination P-channel MOS transistors 11a and 11b is sufficiently smaller than the drain contact-gate electrode distance Lno of N-channel MOS transistors 4a and 4b of output circuit 1. Thus, the area occupied by the termination circuit 10 can be made sufficiently small.

  In the open drain method, the output pad is generally driven to the ground voltage VSSQ level. Instead, a pull-up transistor that pulls up according to the output control signal may be disposed in the power supply voltage level in the output circuit 1, and a transistor that terminates in the ground voltage level may be disposed in the termination circuit 10.

  In the output circuit 1, when both the P-channel MOS transistor and the N-channel MOS transistor are used, the drain contact-gate electrode distance Lpo and the N-channel MOS transistor drain contact-gate electrode distance Lno are not equal to each other. May be. In the termination circuit 10, when a P channel MOS transistor and an N channel MOS transistor are used, their drain contact-gate electrode distances Lpt and Lnt may not be equal to each other.

  At a minimum, the distance between the drain contact and the gate electrode of the MOS transistor of the termination circuit is smaller than the distance between the drain contact and the gate electrode of the MOS transistor included in the output circuit, and the layout area of the termination MOS transistor is the same as that for output. It is sufficient that the condition that it is sufficiently smaller than the layout area of the MOS transistor is satisfied.

  As described above, according to the first embodiment of the present invention, the distance between the drain contact and the gate electrode of the termination MOS transistor is made small, and the distance between the drain contact and the gate electrode of the output MOS transistor is made small. The layout area of the termination circuit can be sufficiently reduced as compared with a configuration in which a general countermeasure against electrostatic breakdown is taken, and the area occupied by the signal output unit can be reduced.

  In addition, a termination circuit is arranged in the semiconductor device, and the termination condition of the bus can be optimized according to the use condition of the bus, and signal / data is transferred at high speed and accurately while maintaining impedance matching. be able to.

[Embodiment 2]
FIG. 9 schematically shows structures of an output circuit and a termination circuit (hereinafter collectively referred to as a semiconductor device) according to the second embodiment of the present invention. In the configuration shown in FIG. 9, output node 3 of output circuit 1 is electrically connected to pad 5 via wiring 50. A termination circuit 10 is disposed far from the pad 5 with respect to the output circuit 1. The termination node 12 of the termination circuit 10 is connected to the same wiring 50 again. Termination node 12 of termination circuit 10 and output node 3 of output circuit 1 are electrically connected to pad 5 via common wiring 50.

  Output circuit 1 includes pull-up P-channel MOS transistors 2a and 2b and pull-down N-channel MOS transistors 4a and 4b as in the first embodiment, and outputs node 3 according to output control signals ZOTH and OTL, respectively. Drive.

  Termination circuit 10 includes, similarly to the first embodiment, resistance elements 13 and 14, P channel MOS transistors 11a and 11b that are selectively turned on in response to termination control signal ZTERM, and termination control signal. N channel MOS transistors 15a and 15b selectively conducting in response to TERM are included.

  The operations of the termination circuit 10 and the output circuit 1 are the same as those of the first embodiment, and the termination circuit 10 is operated according to the operation of the output circuit 1 according to the termination condition of the external bus connected to the pad 5. The logic levels of termination control signals ZTERM and TERM are set.

  In the configuration shown in FIG. 9, termination node 12 of termination circuit 10 and output node 3 of output circuit 1 are connected to pad 5 through common wiring 50. The wiring 50 extends from the pad 5 to the termination circuit 10 via the output circuit 1. Therefore, the distance L2 between the termination node 12 of the termination circuit 10 and the pad 5 is longer than the distance L1 between the output node 3 of the output circuit 1 and the pad 5.

  The output circuit 1 and the termination circuit 10 drive the pad 5 through the common wiring 50 during operation. In the output circuit 1, there is an input capacitance to the pad 5 due to the wiring and the junction capacitance of the MOS transistors 2a, 2b, 4a and 4b. In addition, the wiring 50 also has a wiring resistance. Therefore, a low-pass filter is formed by parasitic capacitance and wiring resistance before transmission from the pad 5 to the termination circuit 10 via the wiring 50. Even if a surge occurs in the pad 5, this steep surge is alleviated by the parasitic low-pass filter and transmitted to the termination circuit 10.

  In the output circuit 1, the MOS transistors 2a, 2b, 4a, and 4b have a sufficiently large drain contact-gate electrode distance, a large drain resistance, and a guaranteed reliability against surge. On the other hand, in the termination circuit 10, the surge is mitigated by the parasitic low-pass filter formed by the output circuit 1 and the wiring 50 and transmitted. Therefore, in this termination circuit 10, the constraint for ensuring the reliability against the surge on the MOS transistors 11a, 11b, 15a and 15b is further relaxed. In the termination circuit 10, the distance between the drain contact and the gate electrode of the MOS transistors 11 a, 11 b, 15 a and 15 b in the termination circuit 10 is limited by design, that is, the minimum design, when the resistance elements 13 and 14 and the surge low-pass filter are sufficiently reduced The size can be reduced to the size, and the area occupied by the termination circuit 10 can be further reduced.

  FIG. 10 schematically shows a layout of the semiconductor device shown in FIG. In FIG. 10, the output circuit 1 is disposed close to the pad 5, and the termination circuit 10 is disposed farther from the pad 5 than the output circuit 1. Termination node 12 of termination circuit 10 and output node 3 of output circuit 1 are connected to pad 5 by a common wiring 50.

  As in the first embodiment, output circuit 1 includes a P active region 18 for forming a P channel MOS transistor and an N active region 19 for forming an N channel MOS transistor. In this output circuit 1, the same reference numerals are assigned to the portions corresponding to the configuration of the output circuit 10 of the first embodiment shown in FIG. 2, and the detailed description thereof is omitted.

  In the P active region 18, the distance between the drain contact 21a formed for the drain impurity region PDa and the gate electrodes 22a and 22b is Lpo. In the N active region 19, the distance between the drain contact 21b formed in the drain impurity region NDa and each of the gate electrodes 22c and 22d is Lno. FIG. 10 shows the distance between one drain contact and the gate electrode in each active region. By increasing these distances Lpo and Lno, the drain resistance is increased and the reliability against the surge generated in the pad 5 is ensured.

  The layout of termination circuit 10 is the same as that of termination circuit 10 shown in FIG. 2 except that termination circuit 10 is arranged farther from pad 5 than output circuit 1 via wiring 50. For the termination circuit 10, corresponding parts are denoted by the same reference numerals, and detailed description thereof is omitted.

  In P active region 30, the distance between drain contact 21c formed for drain impurity region PDb and gate electrodes 22e and 22f of MOS transistors 11a and 11b is Lpt. In N active region 32, the distance between drain contact 21b formed for drain impurity region NDb and gate electrodes 22g and 22h of MOS transistors 15a and 15b is Lnt. As described above, since termination node 12 is electrically connected to pad 5 via wiring 50 and output node 3, a parasitic low-pass filter is equivalently connected to termination node 12. Therefore, the drain contact-gate electrode distances Lpt and Lnt are set to the minimum design dimensions Lpt (min) and Lnt (min) for design, respectively. Thereby, the layout area of the active regions 30 and 32 can be reduced, and the area occupied by the termination circuit 10 can be further reduced.

  In the second embodiment, Lpt and Lnt need not be set equal to each other, and Lpo and Lno need not be set equal to each other.

[Modification 1]
FIG. 11 is a diagram showing a configuration of a first modification of the second embodiment of the present invention. In the semiconductor device shown in FIG. 11, termination circuit 10 terminates pad 5 to power supply voltage VCC. This termination voltage VCC is a voltage applied from a power supply terminal different from the power supply voltage VCCQ applied to the output circuit 1. These voltages VCCQ and VCC may be at the same voltage level or different voltage levels.

  Termination circuit 10 includes a resistance element 13 having one end connected to termination node 12 and P channel MOS transistors 11a and 11b connecting the other end of resistance element 13 to a power supply node in accordance with termination control signal ZTERM.

  In the termination circuit 10, a transistor that terminates at ground is not arranged. The configuration of the output circuit 1 is the same as the configuration of the output circuit 1 shown in FIG. 9, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  Also in the configuration shown in FIG. 11, termination circuit 12 of termination circuit 10 has output circuit 1 connected to pad 5 through output node 3 by wiring 50. Therefore, the distance L2 from the termination node 12 of the termination circuit 10 to the pad 5 is sufficiently longer than the distance L1 between the output node 3 of the output circuit 1 and the pad 5 as in the configuration shown in FIG. In this wiring 50, the surge that has entered the output pad 5 is mitigated by the parasitic resistance and parasitic capacitance, and the surge voltage is mitigated by the termination resistor 13, and the steep voltage due to the surge is mitigated to a gentle voltage. Therefore, in the termination circuit 10, the distance between the drain contacts and the gate electrodes of the MOS transistors 11a and 11b is made sufficiently smaller than that of the MOS transistors 2a and 2b of the output circuit 1, and the drain resistance is reduced.

  FIG. 12 schematically shows a layout of the semiconductor device shown in FIG. The layout of the semiconductor device shown in FIG. 12 is the same as that shown in FIG. 10 except that resistance element 14 and N active region 32 are simply removed in termination circuit 10. Therefore, in the configuration shown in FIG. 12, parts corresponding to those in the configuration shown in FIG.

  Even in the configuration in which the termination circuit 10 terminates at the power source, the drain contact-gate electrode distance Lpt is made smaller than the drain contact-gate electrode distance Lpo of the MOS transistors 2a and 2b of the output circuit 1, and preferably This distance Lpt is set to the minimum design dimension Lpt (min). In this case, the distance Lpt is set shorter than the drain contact-gate electrode distance Lno of the conductive MOS transistor of the output circuit 1.

  Therefore, even in the configuration in which the termination circuit 10 terminates at the power supply voltage VCC, the wiring 50 has the input capacitance, the wiring capacitance, and the wiring resistance of the output circuit 1, and a low-pass filter is formed to reduce the surge. , To the termination circuit 10. Even if the distance between the drain contact and the gate electrode of the MOS transistors 11a and 11b in the main short circuit 10 is set to the design minimum dimension Lpt (min), the surge is sufficiently relaxed and transmitted. The reliability of these transistors 11a and 11b can be sufficiently ensured.

  Therefore, the same effect as the configuration shown in FIGS. 9 and 10 can be obtained. Termination circuit 10 only terminates at power supply voltage VCC level and does not terminate at the ground voltage level, so that the area occupied by termination circuit 10 can be further reduced. Termination voltage VCC of termination circuit 10 may be the same voltage as power supply voltage VCCQ or a different voltage level.

[Modification 2]
FIG. 13 shows a structure of a modification of the semiconductor device according to the second embodiment of the present invention. In the semiconductor device shown in FIG. 13, an open drain type output circuit that drives output node 3 to the ground voltage level is used as output circuit 1. In other words, output circuit 1 is provided with N channel MOS transistors 4a and 4b for driving output node 3 to the ground voltage level in response to output control signal OTL. The pull-up P channel MOS transistor is not arranged in the output circuit 1.

  The configuration of termination circuit 10 is the same as the configuration of termination circuit 10 shown in FIG. 9, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. The termination node 12 of the termination circuit 10 is connected to the pad 5 via the output node 3 of the output circuit 1 by the wiring 50. The distance between the termination node 12 and the pad 5 is L2, and the distance between the output node 3 and the pad 5 is L1. Even if a surge occurs in the pad 5, this surge is transmitted to the termination circuit 10 via the wiring 50. Therefore, the surge can be sufficiently relaxed and transferred to the termination circuit 10.

  Therefore, even if the output circuit 1 is an open drain type output circuit, the input capacitance and the parasitic capacitance of the wiring 50 due to the drain junction capacitance of the MOS transistors 4a and 4b exist, and the parasitic resistance of the wiring 50 exists. . Therefore, since a low-pass filter is parasitically connected to the termination node 12, a countermeasure against surge is realized by these, so that these four MOS transistors 11a, 11b, 15a and 15b particularly take a countermeasure against surge. This is not necessary, and the distance between the drain and gate electrodes can be shortened, and the layout area of the termination circuit 10 can be reduced.

  FIG. 14 schematically shows a layout of the semiconductor device shown in FIG. The layout shown in FIG. 14 is the same as the layout shown in FIG. 11 except that the P active region 15 is removed in the output circuit 1. The detailed description of is omitted.

  In the layout shown in FIG. 14, in termination circuit 10, the drain contact-gate electrode distance Lpt of P channel MOS transistors 11a and 11b is shorter than the drain contact-gate electrode distance Lno of MOS transistors 4a and 4b of the output circuit. Preferably, it is set to the minimum design dimension Lpt (min). Similarly, in the termination circuit 10, the drain contact-gate electrode distance Lnt of the MOS transistors 15a and 15b is made shorter than the contact-gate electrode distance Lno of the MOS transistors 4a and 4b of the output circuit 1, and preferably the minimum design. The dimension is set to Lnt (min).

  As can be clearly seen in the layout shown in FIG. 14, active areas 30 and 32 of termination circuit 10 can reduce the layout area. In output circuit 1, only active area 19 is arranged. Thus, the layout area can be reduced. Thereby, it is possible to realize an output circuit that drives the pad 5 at a high speed with a small occupation area in accordance with the open drain method. Note that the ground voltage applied to the termination circuit 10 and the ground voltage applied to the output circuit 1 may be applied from the same terminal or may be applied from different terminals.

[Modification 3]
FIG. 15 is a diagram showing a configuration of a third modification of the second embodiment of the present invention. The configuration shown in FIG. 15 is different from the semiconductor device shown in FIG. 13 in the following points. That is, in termination circuit 10, MOS transistors 11 a and 11 b for terminating to the power supply voltage and resistance element 13 connected to termination node 12 are provided. These MOS transistors 11a and 11b connect resistance element 13 to the power supply node in accordance with termination control signal ZTERM.

  Output circuit 1 has a configuration similar to that shown in FIG. 13, and includes N channel MOS transistors 4a and 4b for driving pad 5 to the ground voltage level via output node 3 in accordance with output control signal OTL.

  Also in the configuration shown in FIG. 15, termination node 12 of termination circuit 10 is electrically connected to pad 5 via output node 3 via wiring 50. The distance L2 between the termination node 12 and the pad 5 and the distance L1 between the output node 3 and the pad 5 satisfy the relationship of L2> L1, and the surge is sufficiently reduced by the parasitic low-pass filter in the wiring 50. It can be transmitted to the termination circuit 10. Therefore, in the termination circuit 10, the distance between the drain contact and the gate electrode of the MOS transistors 11a and 11b is set to the minimum dimension (design minimum dimension) allowed in design.

  FIG. 16 schematically shows a layout of the semiconductor device shown in FIG. The layout of the semiconductor device shown in FIG. 16 differs from the layout of the semiconductor device shown in FIG. 14 in the following points. That is, in the termination circuit 10, the resistive element 14 and the active region 32 are not disposed, but the resistive element 13 and the P active region 30 are disposed. Other configurations are the same as those in the layout shown in FIG. 14, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the layout shown in FIG. 16, the drain contact-gate electrode distance Lpt of P-channel MOS transistors 11a and 11b is shorter than the drain contact-gate electrode distance Lno of MOS transistors 4a and 4b in output circuit 1. The design dimension Lpt (min) is set.

  As shown in FIG. 16, in termination circuit 10, only P active region 30 and resistance element 13 are arranged, and the layout area can be reduced. In output circuit 1, N active region can also be reduced. Only 19 is arranged, and the layout area can be reduced. Simply, as a restriction on the wiring 50, the termination node 12 and the output node 3 need to be connected to the wiring 50 in common and satisfy the condition L2> L1.

  FIG. 17 schematically shows a whole structure of the semiconductor circuit device according to the invention. In FIG. 17, a semiconductor circuit device 70 drives the pad 5 through the output node 3 according to the output control signals ZOTH and OTL, and the pad 5 through the termination node 12 according to the termination control signals ZTERM and TERM. Includes a termination circuit 10 that terminates at a voltage level of.

  Output circuit 1 includes a pull-up transistor 2 that drives output node 3 to the power supply voltage level in accordance with output control signal ZOTH, and a pull-down transistor 4 that drives output node 3 to the ground voltage level in accordance with output control signal OTL. These pull-up transistor 2 and pull-down transistor 4 correspond to MOS transistors 2a and 2b and MOS transistors 4a and 4b shown in the first and second embodiments, respectively. Termination circuit 10 has a configuration similar to that shown in FIG.

  The semiconductor circuit device 70 further includes a main control circuit 72 for controlling various designated operations in accordance with an external control signal, and performs a predetermined processing operation under the control of the main control circuit 72 to output a control signal ZOTH. And an internal circuit 74 for generating OTL and a termination control circuit 76 for generating termination control signals ZTERM and TERM under the control of the main control circuit 72.

  When internal circuit 74 is a memory circuit, output control signals ZOTH and OTL are generated as a combined signal of internal read data and output control signal. When the pad 5 is used as an input pad for inputting a signal, a predetermined signal / data is given to the internal circuit 74 to the main control circuit 72 via the pad 5. When the output pad and the input pad are provided separately, signals / data are given to the main control circuit 72 and the internal circuit 71 through an input pad (not shown).

  Termination control circuit 76 changes the states of termination control signals ZTERM and TERM in accordance with the bus use conditions in which semiconductor circuit device 70 is used.

  In the output circuit 1 shown in FIG. 17, an open drain type output circuit may be provided, and only the pull-down transistor 4 may be arranged. Termination circuit 10 may have any of the configurations shown in FIGS. 9 to 16. Further, the power supply voltage and / or the ground voltage may be applied to the termination circuit 10 through the same terminal as the output circuit 1 or may be applied through a different terminal.

  As described above, according to the second embodiment of the present invention, the termination circuit and the output circuit are connected via the common wiring, and the termination circuit is arranged farther from the output circuit than the output circuit. . Therefore, a low-pass filter is formed by the parasitic capacitance and parasitic resistance of the wiring, and the surge can be mitigated. Thereby, the drain resistance of the transistor of the termination circuit can be reduced, the distance between the drain contact and the gate electrode can be reduced, and the distance between the drain contact and the gate electrode can be set to the minimum design size. Accordingly, the layout area of the signal / data output section can be reduced.

  The distance between the gate electrode and the drain contact corresponds to the distance between the portion where the drain node of the MOS transistor is connected to the internal node and the portion where the drain region is in contact with the channel region. In a MOS transistor, a high drain electric field is usually generated immediately below the gate electrode in the drain region. By adjusting the distance that the signal charge propagates to the boundary between the drain and the channel, the high drain electric field when a surge occurs can be relaxed. Therefore, the distance between the drain contact and the gate electrode is a distance when viewed in a planar layout.

  In the above configuration, the output circuit is composed of MOS transistors. However, even when the output circuit is composed of bipolar transistors, the same effect can be obtained by replacing the drain with the collector and the gate with the base.

  The semiconductor device according to the present invention can be applied to a semiconductor device used in a system in which a bus is terminated.

It is a figure which shows the structure of the semiconductor device according to Embodiment 1 of this invention. FIG. 2 schematically shows a planar layout of the semiconductor device shown in FIG. 1. It is a figure which shows roughly the planar layout of the modification 1 of Embodiment 1 of this invention. It is a figure which shows the electrical equivalent circuit of the layout shown in FIG. It is a figure which shows roughly the planar layout of the modification 2 of Embodiment 1 of this invention. It is a figure which shows the electrical equivalent circuit of the planar layout shown in FIG. It is a figure which shows roughly the planar layout of the modification 3 of Embodiment 1 of this invention. It is a figure which shows the electrical equivalent circuit of the layout shown in FIG. It is a figure which shows the structure of the semiconductor device according to Embodiment 2 of this invention. FIG. 10 schematically shows a planar layout of the circuit shown in FIG. 9. It is a figure which shows the structure of the modification 1 of Embodiment 2 of this invention. FIG. 12 schematically shows a planar layout of the circuit shown in FIG. 11. It is a figure which shows the structure of the modification 2 of Embodiment 2 of this invention. FIG. 14 schematically shows a planar layout of the circuit shown in FIG. 13. It is a figure which shows schematically the structure of the modification 3 of Embodiment 2 of this invention. FIG. 16 schematically shows a planar layout of the circuit shown in FIG. 15. 1 schematically shows an entire configuration of a semiconductor device according to the present invention. FIG.

Explanation of symbols

  1 output circuit, 2a, 2b MOS transistor, 2 pull-up transistor, 3 output node, 4a, 4b MOS transistor, 4 pull-down transistor, 5 pad, 10 termination circuit, 11a, 11b MOS transistor, 12 termination node, 13, 14 resistance Element, 15a, 15b MOS transistor, PDa, PDb, NDa, NDb Drain impurity region, 21a, 21b, 21c, 21d Drain contact, 22a-22h Gate electrode, 50 wiring.

Claims (2)

pad,
A first source region formed in the first active region and coupled to the first voltage node; a first control gate; a first drain region coupled to the pad via a first drain contact; A first output transistor for driving the pad in accordance with an internal signal applied to the first control gate;
A second source region, a second control gate, and a second drain contact are formed in a second active region disposed opposite to the first active region and coupled to a second voltage node. A second drain region coupled to the pad, and a second output transistor for driving the output node in accordance with an internal signal applied to the second control gate, and having a first end coupled to the pad. And a third source region formed in the third active region and coupled to a third voltage node, a third control gate, and a third terminal at the other end of the first termination resistor element. A first termination transistor that is selectively turned on in accordance with a termination operation activation signal applied to the third control gate,
A second termination resistor having one end coupled to the pad; a fourth source region formed in a fourth active region and coupled to a fourth voltage node; a fourth control gate; And a fourth drain region coupled to the other end of the termination resistance element via a fourth drain contact, and is selectively rendered conductive according to a termination operation activation signal applied to the fourth control gate. A second termination transistor,
A semiconductor device, wherein the pad is disposed in a region between the region where the first and second active regions are disposed and the region where the third and fourth active regions are disposed. The first active region and the third active region are first conductivity type active regions,
2. The semiconductor device according to claim 1, wherein the second active region and the fourth active region are active regions of a second conductivity type different from the first conductivity type.

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