KR20060020339A - Control circuit for pull-up and pull-down resistor in a semiconductor chip - Google Patents

Abstract

The present invention is to prevent the leakage current caused by the pull-up and pull-down resistor in the pad having a pull-up resistor and pull-down resistor. An output signal controller including a tri-state buffer for controlling a pad output signal according to an operation mode of the pad using a signal ENB, and a pull-up including the pull-up resistor and the pull-down resistor implemented in CMOS And a pull-up / down resistor controller configured to control the pull-up / down resistor by using a pull-up / down resistor unit and the output control signal ENB. The present invention has the effect of reducing the current consumption of the semiconductor chip by automatically disconnecting or connecting the pull-up / down resistance at the pad without additional software control.

Pads, Pull-Up Resistors, Pull-Down Resistors

Description

CONTROL CIRCUIT FOR PULL-UP AND PULL-DOWN RESISTOR IN A SEMICONDUCTOR CHIP}             

1 is a diagram illustrating a leakage current generated in a connection state between two semiconductor chips.

2 is a diagram illustrating a leakage current generated when a pull-up resistor implemented with a PMOS is connected to an output terminal of a tri-state pad inside a semiconductor chip.

3 is a diagram illustrating a leakage current generated when a pull-down resistor implemented with an NMOS is connected to an output terminal of a tri-state pad inside a semiconductor chip.

4 is a diagram illustrating a circuit configuration of a pad having a pull-up and pull-down resistor that is conventionally switched by software.

5 is a diagram showing the configuration of a pull-up resistor control circuit according to a preferred embodiment of the present invention.

6 is a diagram showing the configuration of a pull-down resistor control circuit according to a preferred embodiment of the present invention;

7 is a view showing the configuration of a pull-up / down resistance control circuit according to a preferred embodiment of the present invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal control circuit of a semiconductor chip, and in particular, to prevent leakage current consumed by built-in pull-up or pull-down resistors provided in a pad of a semiconductor chip. The present invention relates to a pull-up and pull-down resistor control circuit for a semiconductor chip.

 In general, a pad for input / output of a semiconductor chip prevents a chip malfunction caused by an uncertain state (High-Z) of an internal terminal voltage when an internal circuit is operated in an open state, and prevents electrostatic discharge. Circuits with pull-up or pull-down resistors are included to reduce losses caused by ESD).

The pull-up or pull-down resistors have been provided in a fixed form according to the type of pads provided in the semiconductor chip. However, recently, the pull-up or pull-down resistors are implemented using switching elements such as field effect transistors that are switched on / off according to control signals. In addition, the user may program the switching device according to the connection state between the semiconductor chips to control the pull-up or pull-down resistor on / off.

The pads provided with the pull-up and pull-down resistors have unnecessary power consumption because leakage current flows according to an external device or an internal drive value when the system is implemented. In particular, the leakage current is considered to be a very important factor in a product such as a mobile phone, in which power consumption is an important factor of product competitiveness.                         

First, in FIG. 1, when two semiconductor chips are referred to as semiconductor chips A and B, the leakage current generated in the connection state between the two semiconductor chips is shown.

Referring to FIG. 1, the first pad 101 of the semiconductor chip A and the second pad 103 of the semiconductor chip B are electrically connected through the pad terminals 109 and 111, respectively. The first pad 101 is an input / output pad (tri-state buffer) 105 for controlling the output of the input signal A using the output control signal ENB as an in-out pad and a pull-down resistor ( 107 and pad terminals 109. In addition, the second pad 103 is configured to include a receiving buffer 160, a pad terminal 111, and a pull-up resistor 115 as an input pad.

First, a low level output control signal ENB is applied to the control terminal of the three-state buffer 105 from the first pad 101 in the semiconductor configured as described above so that the three-state buffer 301 is turned on. Assuming that the second pad 103 is not connected in the on state, when the input signal A is driven to a high level, a leakage current is generated because the input signal A flows to the ground terminal through the pull-down resistor 107. . In addition, when power is applied to the semiconductor chip when the first pad 101 and the second pad 103 are connected, the pull-up resistor 115 to which the operating voltage V _D of the second pad 103 is applied is grounded. The leakage current is generated in the arrow direction 113 due to the voltage difference between the pull-down resistors 107.

FIG. 2 is a diagram illustrating a pull-up resistor implemented as a P-type MOS field-effect transistor (hereinafter referred to as a "PMOS") at an output terminal of a three-state pad in a semiconductor chip. A diagram showing the leakage current.

Referring to FIG. 2, the pad 200 of the semiconductor chip is for connecting the output terminal of the tri-state buffer 201 that controls the output of the input signal A according to the signal level of the output control signal ENB and an external device. The pad terminal 205 is configured by connecting a pull-up resistor 203 implemented with a PMOS.

When the low-level output control signal ENB is applied to the control terminal of the tri-state buffer 201 in the pad 200 as shown in FIG. 2, the tri-state buffer 201 is turned on. When the low-level input signal A is driven to an input terminal of the state buffer 201 and the pull-up resistor 203 is in an on state, the operating voltage V _D and the input signal A applied to the pull-up resistor 203 Due to the voltage difference, a leakage current is generated in the direction of the arrow 207.

3 is a diagram illustrating a leakage current generated when a pull-down resistor implemented with an NMOS is connected to an output terminal of a tri-state pad inside a semiconductor chip.

Referring to FIG. 3, the pad 300 of the semiconductor chip connects an output terminal of the tri-state buffer 301 that controls the output of the input signal A based on the signal level of the output control signal ENB to an external device. The pad terminal 505 is connected to a pull-down resistor 303 implemented by an N-type MOS field effect transistor (hereinafter referred to as "NMOS").

In the pad 300 as shown in FIG. 3, when the low level output control signal ENB is applied to the control terminal of the tri-state buffer 301 and the tri-state buffer 301 is turned on, the tri-state buffer 301 is turned on. When the pull-down resistor 303 is in an on state while the low level input signal A is driven to the input terminal of the input signal A, the input signal A flows to the ground terminal through the driven-down pull-down resistor 303, so as to the direction of the arrow 307. This causes leakage current.

In the pad configuration of FIGS. 2 and 3 described above, when the pad is turned on, a problem arises in that a leakage current is generated due to the pull-up and pull-down resistors which are fixed to the driving state at all times. To solve this problem, there is a method of switching control of the pull-up resistor or the pull-down resistor in software.

That is, FIG. 4 is a diagram illustrating a circuit configuration of a pad provided with a pull-up and pull-down resistor that is conventionally controlled by software.

Referring to FIG. 4, the pad of FIG. 4 includes an output signal controller B1 having a three-state buffer 401 for controlling the output of the input signal A according to the output control signal ENB 421, and a CMOS. The pull-up and down resistors B3 including the implemented pull-up and pull-down resistors 415 and 417 and a resistance controller B2 for switching and controlling the pull-up / down resistor B3.

Here, the resistance controller B2 is referred to as a pull-up / down enable (PUDE), which controls on / off driving of the pull-up / down resistor B3 according to a predetermined software routine. PUDE terminal 403 to which the signal is output and a predetermined pull-up / down control for selectively driving the pull-up or pull-down resistors 415 and 417 when the pull-up / down resistor unit B3 is turned on. Up / Down Control (hereinafter referred to as “PUDC”) PUPU terminal 405 to which the signal is output.

In addition, the resistance controller B2 switches on / off the pull-up and pull-down resistors 415 and 417 by performing a logic operation on the PUDE signal output from the PUDE terminal 403 and the PUDC signal output from the PUDC terminal 405. It consists of a number of logic elements (409, 411, 413). Next, the operation principle of the pad shown in FIG. 4 is described. Table 1 shows the signal levels of the PUDE and PUDC signals determined by software for the pad operation. Here, Table 1 shows a case where ENB = 1.

PUDE PUDC pad 0 X High-z One 0 Pull-down resistor One One Pullup resistor

First, when the signal level of the PUDE terminal 403 is '0', the NAND gate 409 and the NOR gate of the resistor control unit B2 regardless of the signal level of the PUDC terminal 405. The output signal level of 413 is constantly output as '1' and '0'. The constant output signal is applied to gate terminals of the pull-up and pull-down resistors 415 and 417 implemented in CMOS to turn off the operation of the pull-up / down resistor portion B3. Therefore, since the tri-state buffer 401 blocks the input signal A and the pull-up / down resistors 415 and 417, the pad terminal 419 of the tri-state pad 400 has the terminal voltage floating. Indeterminate state (High-Z).

Next, when the signal level of the PUDE terminal 403 is '1', the resistance control unit B2 according to the signal level of the PUDC terminal 405, pull-up or pull-down resistors 415, 417 as shown in Table 1 below. Is selectively turned on. Therefore, in the pad circuit of FIG. 4, when the programmer uses a program to set on / off of the pull-up and pull-down resistors according to the situation of the system, leakage current can be prevented.                         

However, when the pull-up and pull-down resistors are controlled by software as in the pad circuit of FIG. 4, the system always monitors the operation state of the pad according to the operation mode of the semiconductor chip. After storing the operating state, a cumbersome operation is required, such as newly setting the PUDC signal and the PUDE signal so that leakage current does not occur, and resetting the previously stored values when restoring the operation mode. In addition, when the switching operation of the pull-up and pull-down resistors is frequently required according to the operation mode of the semiconductor chip, there is a problem in that leakage current cannot be prevented properly.

An object of the present invention is to provide a pull-up resistor control circuit that can easily control the pull-up resistor embedded in the pad of the semiconductor chip without a separate software operation.

An object of the present invention is to provide a pull-down resistor control circuit that can easily control the pull-down resistor embedded in the pad of the semiconductor chip without a separate software operation.

An object of the present invention is to provide a pull-up and pull-down resistor control circuit that can easily control the pull-up and pull-down resistors embedded in the pad of the semiconductor chip without a separate software operation.

Pull-up resistor control circuit of the semiconductor chip according to the present invention for achieving the above object is a three-state buffer for controlling the output of the external input signal by a predetermined output control signal (ENB) and on / off control using the output control signal It is characterized by including a pull-up resistor implemented by the field effect transistor.

The pull-down resistor control circuit of the semiconductor chip according to the present invention is implemented as a three-state buffer controlling the output of an external input signal by a predetermined output control signal (ENB) and a field effect transistor controlled on / off using the output control signal. It is characterized in that it is configured to include a pull-down resistor.

The pull-up / down-resistance control circuit of the semiconductor chip according to the present invention uses an output signal control unit including a three-state buffer for controlling the output of the external input signal using the first control signal, and the output signal control unit using the second control signal. An output signal control unit including a three-state buffer for controlling an output, a pull-up / down resistor unit including the pull-up resistor and the pull-down resistor driven using a second control signal, and the first and second control signals And a resistance controller configured to control on / off of the pull-up / down resistor unit.

The second control signal includes a pull / up-down enable (PUDE) signal for simultaneously controlling on / off of the pull-up resistor and the pull-down resistor, and a pull / up-down control (PUDC) for selectively controlling the pull-up resistor and the pull-down resistor on / off. ) Signal.

The pull-up resistor is composed of a PMOS transistor, the pull-down resistor is characterized in that it is composed of NMOS transistor.

The resistor controller is configured to output the logic operation to the gate terminal of the PMOS by inputting the AND gate, the output signal of the AND gate, and the PUDC signal as inputs of the first control signal and the PUDE signal. And an invertor for inverting an output signal value of the AND gate, and a noar gate for outputting a logic operation signal to the gate terminal of the NMOS by inputting the output signal of the inverter and the PUDC signal.

The PUDE signal and the PUDC signal is characterized in that set only once at the time of system initialisation.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In the detailed description below, three representative embodiments of the present invention will be shown. First, the first embodiment will show a circuit that can control the pull-up resistor in the pad, and the second embodiment will show a circuit that can control the pull-down resistor in the pad. Finally, the third embodiment will be described a circuit that can simultaneously control the pull-up and pull-down resistor in the pad. Other embodiments that may be presented with the present invention are replaced by the configuration of the present invention.

A. First Embodiment

5 is a diagram showing the configuration of a pull-up resistor control circuit according to a preferred embodiment of the present invention, which prevents leakage current when a pull-up resistor implemented with a PMOS is connected to an output terminal of a tri-state pad provided inside a semiconductor chip. The control circuit is shown.

Referring to FIG. 5, the pull-up resistor control circuit 500 may include a three-state buffer 507 for controlling the output of the input signal A according to the signal level of the output control signal ENB 501, and the three-state buffer ( A pull-up resistor 503 implemented with a PMOS and a signal level of the output control signal (ENB) 501 are inverted between the output terminal of the input terminal 507 and the pad terminal 515 for connecting to an external device. It is configured to include an inverter 509 to apply. Here, the output control signal (ENB) 501 is applied to the control terminal of the three-state buffer 507 and to the gate terminal via the inverter 509.

The operation principle of the pull-up resistor control circuit 500 is as follows.

When the high-level output control signal (ENB) 507 is applied to the control terminal of the tri-state buffer 507 by the pull-up resistor control circuit 500 and the tri-state buffer 507 is turned off, the input signal A Is blocked, and the inverter 509 receives the output control signal (ENB) 501 and outputs a low level '0' signal. Accordingly, the pull-up resistor 503 is driven on by applying the low level signal to the gate terminal of the pull-up resistor 503 implemented with the PMOS.

On the other hand, when the low level output control signal (ENB) 501 is applied to the control terminal of the tri-state buffer 507 and the tri-state buffer 507 is turned on, the input signal A is turned on. The inverter 509 inverts the signal level of the output control signal (ENB) 501 to apply a high level ('1') signal to the gate terminal of the pull-up resistor 503 to block the pull-up resistor 503. do. Therefore, according to the first embodiment, when the tri-state buffer 507 is turned on, the pull-up resistor 503 is cut off to prevent the occurrence of leakage current as shown in FIG. 2.

B. Second Embodiment

6 is a view showing the configuration of a pull-down resistor control circuit according to a preferred embodiment of the present invention, which is a control circuit for preventing leakage current when connecting the pull-down resistor implemented by NMOS to the output terminal of the pad provided inside the semiconductor chip It is shown.

Referring to FIG. 6, the pull-down resistor control circuit 600 includes a three-state buffer 607 for controlling the output of the input signal A according to the signal level of the output control signal (ENB) 609, and the three-state buffer ( Between the output terminal of the 607 and the pad terminal 613 for the connection to the external device is configured to include a pull-down resistor 611 implemented in NMOS. The output control signal ENB 609 is applied to the control terminal of the tri-state buffer 607 and to the gate terminal of the pull-down resistor 611.

The operation of the pull-down resistor control circuit 600 is as follows.

First, the output control signal (ENB) 609 of a high level ('1') is applied to the control terminal of the tri-state buffer 607 in the pull-up resistor control circuit 600, so that the tri-state buffer 607 is turned off. In this case, the tri-state buffer 607 blocks the input signal A. In addition, the high level output control signal ENB 609 is applied to the gate terminal of the pull-down resistor 611 so that the pull-down resistor 611 is driven on.                     

On the other hand, when the low level ('1') output control signal (ENB) 609 is applied to the control terminal of the tri-state buffer 607 and the tri-state buffer 607 is turned on, the input signal A is At the same time, a low level signal is applied to the gate terminal of the pull-down resistor 611 so that the pull-down resistor 611 is cut off. Therefore, according to the second embodiment, when the tri-state buffer 607 is turned on, the pull-up resistor 611 is cut off to prevent the occurrence of leakage current as shown in FIG.

 C. Third Embodiment

FIG. 7 is a diagram illustrating a configuration of a pull-up / down-resistance control circuit according to a preferred embodiment of the present invention, which is implemented by a complementary metal-oxide semiconductor (CMOS) at an output terminal of a pad provided inside a semiconductor chip. Shows a control circuit that prevents leakage current when connected.

Referring to FIG. 7, the pull-up / down resistance control circuit 700 according to the present embodiment has an output including a three-state buffer 709 that controls input and output based on a signal level of an output control signal ENB 707. A pull-up / down-resistor section B6 composed of a signal controller B4, a pull-up resistor 723 implemented with a PMOS and a pull-down resistor 725 implemented with an NMOS, and the output control signal (ENB) 707. And a resistance controller B5 for controlling the pull-up and pull-down resistors 723 and 725 of the pull-up / down resistor unit B6.

In this case, the output signal controller B4 may include a reception buffer 729 as shown in FIG. 7 to operate the input mode of the pad. The pull-up / down-resistance control unit B5 has an input gate having a signal of the output control signal (ENB) 707 and a signal of the PUDE terminal 711 for outputting the above-described pull / up-down enable (PUDE) signal. 715 and a NAND gate 717 for inputting the output signal of the AND gate 715 and the aforementioned pull / up-down control (PUDC) signal and outputting a control signal for controlling the pull-up resistor 723 on / off. ). In addition, the pull-up / down resistor controller B5 receives an inverter 719 for inverting the output signal level of the AND gate 711, an output signal of the inverter 719, and the PUDC signal, and the pull-down resistor ( And a noble gate 721 for outputting a control signal for controlling the on / off of the 725.

Next, the operation principle of the pull-up / down resistance control circuit 700 will be described. The output level control signal (ENB) 707 of the pull-up / down resistance control circuit 700 and the signal level for each condition of the PUDE signal and the PUDC signal are shown in Table 2 below. In the following description, an operation in the case where the pad in the semiconductor chip operates in the output mode will be described.

ENB PUDE PUDC pad 0 × × Input signal One One 0 Pull-down resistor One One One Pullup resistor One 0 × High-z

Referring to Table 2, first, when the output control signal (ENB) 707 is at a low level, the output control signal (ENB) 707 is applied to the control terminal of the three-state buffer 709. To conduct the input signal A, and at the same time, it is applied as an input signal of the AND gate 715 of the pull-up / down-resistance control unit B5. In this case, the output level of the AND gate 715 is always '0' regardless of the signal level of the PUDE signal.                     

When the output level of the AND gate 715 is always '0', the output level of the NAND gate 717 is '1'. Therefore, the high level signal output from the NAND gate 717 is applied to the gate terminal of the pull-up resistor 723 so that the pull-up resistor 723 is cut off. In addition, since the inverter 719 inverts the output level of the AND gate 715, the output level of the NOA gate 721 is always '0'. As a result, the low-level signal output from the noble gate 721 is applied to the gate terminal of the pull-down resistor 725 to block the pull-down resistor 725. In this case, the signal level of the pad is determined according to the input signal A.

Secondly, when the output control signal (ENB) 707 is at a high level, the output control signal (ENB) 707 is applied to the control terminal of the tri-state buffer 709 to block the input signal A and simultaneously. The input signal is applied to the AND gate 715 of the pull-up / down resistance controller B5. In this case, when the PUDE signal output from the PUDE terminal 711 becomes '1', the output level of the AND gate 715 is pulled up and pulled down according to the signal level of the PUDC signal output from the PUDC 713 terminal. 723 and 725 are selectively turned on and off.

Here, if the PUDC signal level is '0', the output level of the NAND gate 717 becomes '1' so that the pull-up resistor 723 is driven off, while the output level of the NOR gate 721 is '0'. ', The pull-down resistor 725 is turned on. Next, when the PUDC signal level is '1', the NAND gate 717 and the noble gate 721 operate in the opposite manner to the first case to drive the pull-up resistor 723 on, and the pull-down resistor 725 ) Off.

Next, a case in which the pad in the semiconductor chip operates in the input mode will be described. Since the output control signal ENB 707 is at a high level, the tri-state buffer 709 is blocked. The PUDE signal is at a low level. In this case, since the PUDE signal is low level, as in the first operation, all pull-up / down resistors 723 and 725 are driven off and cut off. Thus, in input mode, the leakage current from the pullup / down resistors can be cut off.

As described above, the pull-up / down-resistance control circuit 700 of FIG. 7 performs a change every time the system operation mode is changed when the three-state buffer 709 is turned on, that is, when the output control signal ENB is applied at a low level. After the operation state of the pad is stored, the pull-up and pull-down resistors can be blocked without performing separate control operations such as newly setting the PUDC signal and the PUDE signal. When turned off, setting the pull-up or pull-down resistor only once during initial system startup prevents leakage currents.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments. It should be determined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

 As described above, the pad circuit according to the present invention detects a signal level change of an output control signal for controlling the output of the input signal, and disconnects or connects pull-up and pull-down resistors on the pad to generate leakage current without additional software control. And thereby reduce the current consumption of the semiconductor chip.

Claims (7)

In a control circuit provided in a pad having a pull-up resistor and a pull-down resistor, An output signal controller including a three-state buffer that controls the output of the external input signal by using the first control signal; A pull-up / down resistor unit having the pull-up resistor and the pull-down resistor driven using a second control signal; And a resistance controller configured to perform logic operations on the first and second control signals to control on / off of the pull-up / down resistor unit. The method of claim 1, wherein the second control signal, And a pull / up-down enable (PUDE) signal for simultaneously controlling the pull-up resistor and the pull-down resistor on / off, and a pull / up-down control (PUDC) signal for selectively controlling the pull-up resistor and the pull-down resistor. Said circuit. The method of claim 1, wherein the pull-up resistor, Wherein said pull-down resistor is comprised of an NMOS transistor. The method of claim 3, wherein the resistance control unit, The AND gate having the first control signal and the PUDE signal as inputs; A NAND gate which outputs a logic operation signal to the gate terminal of the PMOS by inputting the output signal of the AND gate and the PUDC signal; An inverter for inverting an output signal value of the AND gate; And a NOR gate configured to output a logic operation signal to a gate terminal of the NMOS by inputting an output signal of the inverter and the PUDC signal. The method of claim 2, wherein the PUDE signal and the PUDC signal, Said circuit being set only once at the beginning of the system. In the control circuit provided in the pad provided with a pull-up resistor, A three-state buffer that controls the output of the external input signal by a predetermined output control signal ENB, And a pull-up resistor implemented by a field effect transistor controlled on / off using the output control signal. In the control circuit provided in the pad provided with a pull-down resistor, A three-state buffer that controls the output of the external input signal by a predetermined output control signal ENB, And a pull-down resistor implemented by a field effect transistor controlled on / off using the output control signal.

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