JP4793585B2 - Programmable controller - Google Patents

Description

  The present invention relates to a programmable controller (hereinafter referred to as PLC) having both a dedicated LSI (hereinafter referred to as ASIC) and a microprocessor (hereinafter referred to as MPU).

  Various types of PLCs that include an ASIC and an MPU so as to realize a function as a PLC have been conventionally known (see Patent Document 1). An example of such a PLC, more specifically, a hardware configuration diagram of a CPU unit of a building block type PLC having both an ASIC and an MPU is shown in FIG.

  As shown in the figure, the CPU unit 12 includes an MPU 121 that executes a program described in an MPU language represented by C language and a program written in a PLC language represented by ladder diagram language. ASIC 122 to be executed, system program memory (configured by ROM) 123 for storing a system program for realizing system control specifications as a PLC, and working for providing a work area when the MPU executes the program A memory (configured by RAM) 124, a setting memory (configured by flash memory (hereinafter referred to as FROM)) 125 for storing abnormality notification settings and abnormality status, and a device control specification desired by the user To store user programs written in PLC language A user program buffer memory 126 (configured by a flash memory (hereinafter referred to as FROM)) 126 and an ASIC execution target memory (configured by a high-speed RAM) 127 for storing a program to be executed by the ASIC. And an input / output memory (comprising a high-speed RAM) 128 for storing input / output data corresponding to the input / output assignment of the external input / output unit and various data used in the user program.

  The system program stored in the system program memory includes initial processing at power-on, common processing, arithmetic processing (such as complicated data arithmetic processing portion that cannot be executed by ASIC in the user program), I / O refresh processing, and A program portion corresponding to each peripheral service process is included. Each program portion corresponding to these processes is described in the MPU language.

  A function for transferring a user program written in the PLC language from the user program buffer memory (FROM) 126 to the ASIC execution target memory 127 as an initial process at the time of power ON (see FIG. 8 ST01) is incorporated.

  In addition, the program part corresponding to the initial process at the time of power-on includes other functions such as a function for initializing hard memory and system work, a function for recognizing the installed unit, and automatic transfer from the memory card when the power is turned on. Functions, such as a function for checking the power supply unit and the mounted I / O table, a function for clearing the input / output memory, a function for checking the user program memory, a function such as forced set and reset release, are incorporated as necessary.

  The ASIC 122 includes a circuit part that implements a function for executing most of the PLC language instruction words that can be used in the user program (except for the instruction word that the MPU 121 is responsible for processing), and functions as a communication unit interface. And a circuit part for realizing a bus arbitration function for memory access, and the like.

  Next, a general flowchart (conventional example) showing the operation of the CPU unit 12 of the PLC 1 is shown in FIG. In the figure, when the processing is started by turning on the power, the MPU 121 first reads and executes the program portion corresponding to the initial processing (step 901) when the power is turned on from the system program memory 123.

  Then, various functions corresponding to the initial process when the power is turned on are realized. These functions include a function of transferring a user program written in the PLC language from the user program buffer memory (FROM) 126 to the ASIC execution target memory 127 (see ST01 in FIG. 8).

  Thereafter, as shown in the flowchart of FIG. 9, common processing (step 902), calculation processing (step 903), I / O refresh processing (step 904), and peripheral service processing (step 905) are cyclically executed. . Here, a round execution time of the common process (step 902), the calculation process (step 903), the I / O refresh process (step 904), and the peripheral service process (step 905) is referred to as a cycle time. In this type of scanning PLC, in order to improve the input / output response, it is necessary to shorten the cycle time as much as possible.

  Conventionally, in the above-described processing (steps 902 to 905) for determining the cycle time, the program portion corresponding to the arithmetic processing (step 903) is mainly the ASIC 122 except for the complicated data arithmetic processing that is left to the MPU 121. As a result, the cycle time is shortened.

  That is, the ASIC 122 sequentially reads out each instruction word of the user program described in the PLC language from the ASIC execution target memory 127 (see ST02 in FIG. 8). Next, the ASIC 122 decodes and executes each read instruction word while referring to the input / output data and setting data of the input / output memory 128, and rewrites the output data of the input / output memory 128 with the execution result (FIG. 8). (See ST03). The above operation is repeated until the end of the user program.

  When the execution of the arithmetic processing (step 903) is completed, program portions corresponding to the I / O refresh processing (step 904) and the peripheral service processing (step 905) are sequentially executed. These processes are realized by the MPU 121 sequentially reading out the corresponding program parts (both described in MPU language such as C language) from the system program memory 123 (see ST04 in FIG. 8). . Note that the system work area in the working memory is used when the MPU 121 executes the program portions.

  The program corresponding to the common processing (step 902) includes, for example, a battery abnormality check function, a memory card power supply check function, a DIP switch monitoring function, an input / output bus (system bus) check function, and a user program memory check function. , Etc. are incorporated.

  The program corresponding to the I / O refresh process (step 904) includes, for example, (1) a data exchange function with the basic I / O unit, and (2) an allocation relay area of the high function I / O unit. Cyclic data exchange and unit-specific data exchange functions, (3) allocation relays for CPU high-function units, cyclic data exchange functions for DM areas, unit-specific data exchange functions, and the like are incorporated.

Further, the program corresponding to the peripheral service processing (step 905) includes, for example, (1) an event service function with a high-function I / O unit that is executed only when an event occurs, and (2) a CPU high-function unit. Event service function, (3) peripheral port service function, (4) RS232C port service function, (5) file access service function, (6) communication port service function, and the like.
JP 2002-358104 A

  However, in such a conventional PLC, various processes necessary for realizing the PLC (initial processing at power-on, common processing, arithmetic processing for executing a user program described in the PLC language, I / O refresh processing) In the peripheral service processing), most of the arithmetic processing is left to the ASIC capable of executing the PLC language (ladder diagram language or the like), while the MPU that executes the MPU language (C language or the like) is used for other processing. Therefore, in order to further reduce the cycle time in this method, either an element structure capable of high-speed operation is adopted as an ASIC, or a high-speed operation speed is adopted as an MPU. Or processing other than arithmetic processing (initial processing at power-on, common processing, I / O refresh processing, peripheral service processing ), But in addition to entrust the newly fabricated ASIC and, in any event, change large-scale design there is a problem that not be put to practical use leads to significant cost-up is required.

  The present invention has been made paying attention to the above-mentioned problems, and the object of the present invention is to input / output while effectively utilizing existing PLC resources in a PLC having both of this type of MPU and ASIC. The object is to provide a PLC with high responsiveness at low cost.

  In order to achieve the above object, the present invention provides a PLC having the following configuration.

  That is, the PLC includes a system program memory for storing a system program for realizing system control specifications as a PLC, and a user program written in a PLC language for realizing device control specifications desired by the user. User program buffer memory for storing, MPU for executing a program described in MPU language, ASIC for executing a program described in PLC language, and ASIC execution for storing a program to be executed by ASIC And a target memory.

  The system program stored in the system program memory has a first program part described in the MPU language and including at least an initial process at power-on, and a second program part described in the PLC language, and Initial processing at power-on includes first transfer processing for transferring a user program written in the PLC language from the user program buffer memory to the ASIC execution target memory, and PLC language from the system program memory to the ASIC execution target memory. And a second transfer process for transferring the second program part described in (1). Here, “written in the PLC language” means that the PLC language (ladder diagram language or the like) is used when creating the source program of the program, and is stored in the ASIC execution target memory. In FIG. 2, the ASIC is converted into an executable code (executable program). “Written in MPU language” means that the MPU language (C language or the like) was used when creating the source program of the program, and in the state stored in the system program memory, The MPU is converted into executable code (executable program).

  According to such a configuration, when the power is turned on and the MPU executes the first transfer process and the second transfer process, the ASIC execution target memory has the second program part of the user program and the system program. Are transferred and stored, and the two program parts are both described in the PLC language, so that these two program parts can be executed by the ASIC. Therefore, according to the present invention, not only the user program but also a part of the system program is executed by the ASIC at a speed higher than that of the MPU. Therefore, the existing PLC resources are effectively used and the input / output response is good. PLC can be realized at low cost.

  In the preferred embodiment, the user program portion transferred in the first transfer process is stored in the ASIC execution target memory from the beginning, and the system program portion transferred in the second transfer process is stored in the ASIC execution target. Store in an empty area following the user program portion of the memory.

  According to such a configuration, a part of the system program can be arranged in the ASIC execution target memory without changing the user program arrangement in the ASIC execution target memory. The invention can be implemented with only minor changes.

  In a preferred embodiment, each time an instruction word constituting the PLC language is read, the ASIC determines whether or not the access target address specified by the operand falls within a predetermined user program access range. An access range check circuit having an access range check function for controlling whether or not to access to the memory to be accessed based on the check result is included, and each read instruction word is included in the access range check circuit. Only when it is determined that the instruction word is an access range check enable instruction, a protect circuit for enabling the access range check function may be included.

  According to such a configuration, for each instruction word in the PLC language describing the user program, for example, the access range check is disabled by setting a specific bit of the operation code as the first logical value, while For each instruction language in the PLC language that describes two program parts, for example, by enabling the access range check by setting a specific bit of the operation code as the second logical value, the user program is set in the predetermined address space. While guaranteeing access, the second program portion of the system program can secure a degree of freedom in system design by enabling access to a wider address space.

  The second program portion of the system program can include common processing, I / O refresh processing, and / or peripheral service processing. That is, according to the present invention, the common process, the I / O refresh process, and / or the peripheral service process are executed by the ASIC, so that the input / output response constraint can be improved while shortening the cycle time.

  According to this invention, when the power is turned on and the MPU executes the first transfer process and the second transfer process, the user program and the second program part of the system program are stored in the ASIC execution target memory. Since these two program parts are transferred and stored and are both described in the PLC language, these two program parts can be executed by the ASIC. Therefore, according to the present invention, not only the user program but also a part of the system program is executed by the ASIC at a speed higher than that of the MPU. Therefore, the existing PLC resources are effectively used and the input / output response is good. PLC can be realized at low cost.

  Hereinafter, a preferred embodiment of a PLC according to the present invention will be described in detail with reference to the accompanying drawings.

  An explanatory diagram of the basic configuration of the entire PLC is shown in FIG. As shown in FIGS. 4A and 4B, the PLC 1 according to this embodiment is configured in a building block type, and includes a power supply unit 11, a CPU unit 12, and one or more units. And input / output units (I / O units) 13, 13... And a special function unit 14.

  These units 11 to 14 are detachably connected to a system bus (also referred to as an input / output bus) 31 laid on the backplane 3 via connectors 3a, 3a.

  The CPU unit 12 performs overall control of the entire PLC 1. In this example, the development support apparatus 2 is connected via the cable 5. In this example, the development support apparatus 2 is configured by installing a predetermined application program in a personal computer (hereinafter referred to as a personal computer).

  The development support apparatus 2 includes a function for downloading and monitoring a user program from the PLC 1, a function for creating a user program and uploading it to the PLC 1, a function for downloading input / output data and setting data from the PLC 1, and the like. ing.

  FIG. 2 shows a hardware configuration diagram (the present invention) of the CPU unit 12. As shown in the figure, the CPU unit 12 according to the present invention is described in an MPU 121 that executes a program described in an MPU language typified by C language and the PLC language typified by a ladder diagram language. An ASIC 122 for executing the program, a system program memory (configured by ROM) 123 for storing a system program for realizing system control specifications as a PLC, and a work area for the MPU to execute the program. Working memory (configured by RAM) 124 to be provided, setting memory (configured by flash memory (hereinafter referred to as FROM)) 125 for storing anomaly notification settings and anomaly status, and user desired A user program written in the PLC language for realizing device control specifications is stored. A user program buffer memory (consisting of a flash memory (hereinafter referred to as FROM)) 126 and an ASIC execution target memory for storing a program to be executed by the ASIC (high-speed RAM) ) 127 and an input / output memory (comprising a high-speed RAM) 128 for storing input / output data corresponding to the input / output assignment of the external input / output unit and various data used in the user program.

  A system program memory (ROM) 123 stores a system control program for realizing system control specifications as a PLC. As will be described in detail later with reference to FIG. 7, this system control program includes initial processing at power-on, common processing, arithmetic processing (however, processing excluding the portion executed by the ASIC), I / O refresh A program portion corresponding to each of the processing and the peripheral service processing is included.

  The program part corresponding to the initial process when the power is turned on is composed of a first program part described in MPU language such as C language and a second program part described in PLC language such as ladder language. ing.

  The first program part includes a process for initializing hard memory and system work, a process for recognizing a mounted unit, a process for automatically transferring power from a memory card, and a process for checking a power supply unit and a mounted I / O table. In addition to program portions corresponding to general power-on processing such as input / output memory clear processing, user program memory check processing, forced set and reset release processing, etc., a user program buffer memory (FROM) 126 From the system program memory (ROM) 123 to the execution execution target memory (high-speed RAM), and the program portion corresponding to the processing (first transfer processing) for transferring the user program from the memory to the ASIC execution execution target memory (high-speed RAM) 127. ) 127 to the second program part of the system program A program portion corresponding to the process of transferring (second transfer process) are included.

  In this example, the second program portion corresponds to each of common processing, arithmetic processing (except for the portion corresponding to the function executed by the ASIC), I / O refresh processing, and peripheral service processing. The program is included.

  Here, as described above in the conventional example, the program corresponding to the common process includes, for example, a battery abnormality check process, a memory card power check process, a DIP switch monitoring process, and an input / output bus (system bus) check process. A program corresponding to the memory check process of the user program, etc. is incorporated.

  The program corresponding to the I / O refresh processing includes, for example, data exchange processing with the basic I / O unit, cyclic data exchange in the assigned relay area of the high-function I / O unit, and unit-specific data. Programs corresponding to exchange processing, CPU high-function unit allocation relay, cyclic data exchange processing in the DM area, unit-specific data exchange processing, and the like are included.

  Further, the program corresponding to the peripheral service process includes, for example, an event service process with a high function I / O unit, an event service process with a CPU high function unit, a peripheral port service process, which are executed only when an event occurs. Programs corresponding to RS232C port service processing, file access service processing, communication port service processing, and the like are included.

  An explanatory diagram of the contents stored in the ASIC execution target memory 127 is shown in FIG. As shown in the figure, the user program transferred from the user program buffer memory (FROM) 126 to the ASIC execution target memory (high-speed RAM) 127 is sequentially stored from the head (AD0) in the ASIC execution target memory 127. . On the other hand, the second part of the system program transferred from the system program memory (ROM) 123 to the ASIC execution target memory (high-speed RAM) 127 is an empty area (system) following the user program storage area 127a in the ASIC execution target memory 127. Control program storage area) 127b is stored in an appropriate position.

  According to such an arrangement in the memory, since the user program is arranged as before, the ASIC 122 can adopt the conventional circuit configuration related to the user program processing as it is, while the second program of the system program. For the portion, it is possible to freely select the arrangement in the memory according to the size of the user program.

  By the way, the ASIC 122 checks whether or not the access target address specified by the operand is within a predetermined user program access range every time each instruction word constituting the PLC language is read. An access range check circuit having an access range check function for controlling whether or not to access the access target memory is included based on the check result.

  According to this access range check circuit, it is possible to prevent the risk of unexpected malfunction or failure of the PLC due to an unexpected access to the address space caused by the execution of the user program due to a programming error of the user program. Can do.

  However, in the present invention, not only the user program but also the second program part of the system control program is stored in the ASIC execution target memory 127, and the ASIC 122 includes both of these programs. You must respond. In other words, as shown in FIG. 4, the ASIC has access to the address space defined by the extended operand range for system control beyond the address space defined by the user program operand. Must be guaranteed.

  Therefore, in this embodiment, a protection circuit that enables the access range check function only when it is determined that each read instruction word is an access range check enable instruction word for the access range check circuit. Incorporated.

  A block diagram of the access range check circuit of the user program and the system control program is shown in FIG. The access range check circuit 20 is incorporated in the ASIC 122.

  As shown in the figure, the access range check circuit 20 includes an access range check circuit 20a for a user program, a first AND gate 20b, a second AND gate 20c, and one gate circuit 20d. I have.

  The user program access range check circuit 20a checks the user program access range based on the address data (ADx) that specifies the access target and the address data (Dk) that specifies the access range of the user program, and accesses the address outside the range. A signal S1 is generated. Here, the out-of-range address access signal S1 is in the “1” state when it is out of the range, and is in the “0” state when it is within the range.

  The first AND gate 20b is controlled to be opened and closed by an enable setting state ST1 of an access range check circuit set in a predetermined setting register (not shown), and an access range check enable set in a specific bit of an instruction word opcode. Pass or block the logically inverted version of state ST2. Here, the enable setting state ST1 of the access range check circuit is “1” when enabled and “0” when disabled. The instruction code opcode access range check enable state ST2 is "0" when disabled and "1" when enabled.

  The second AND gate 20c functions as a protect circuit, is controlled to open / close by the output signal S2 of the first AND gate 20b, and is out-of-range address access signal S1 output from the access range check circuit 20a of the user program. Pass or block. Here, the output signal of the second AND gate 20c is supplied as the protect signal S3 to the open / close control input of the gate circuit 20d. Here, the protect signal S3 is “1” when protection is provided, and is “0” when protection is not provided.

  The gate circuit 20d is interposed in the passage path of the control signal (chip enable signal) reaching the access target memory 20e, and is controlled to be opened and closed by the protect signal S3, thereby passing or blocking the control signal S4. Here, the gate circuit 20d is opened when the protect signal S3 is "1", and is closed when "0".

  The access target memory 20e can read or write data (DATA) to an address specified by the access address data (ADx) when the control signal S4 is supplied. Note that DB is a data bus and AB is an address bus.

  In the above configuration, if the enable setting state ST1 of the access range check circuit is enabled (“1”), the first AND circuit 20b is maintained in the open state, so that the access range check enable state of the opcode of the instruction word ST2 appears as an output signal S2 of the first AND gate after logical determination.

  Therefore, the specific bit of the opcode of the PLC instruction describing the user program is set to the first logical value (for example, “0”), while the specific bit of the opcode of the PLC instruction describing the system program is set to the second logical value ( For example, if “1” is set, when the user program is executed, the output signal S2 of the first AND gate 20b becomes “1”, and the second AND gate constituting the protect circuit is opened. It will remain as it is. Then, the value of the protect signal S3 that is the output of the second AND gate 20c changes following the value of the out-of-range address access signal S1 that is the output of the access range check circuit 20a of the user program.

  Therefore, the gate circuit 20d is in a closed state when the value of the access address data (ADx) exceeds the user program access range and cuts off the control signal S4 supplied to the access target memory 20e. Data read or data write is prohibited, and access by erroneous data is protected.

  On the other hand, when the second program portion of the system program is executed, the output signal S2 of the first AND gate 20b becomes “0”, and the second AND gate constituting the protect circuit remains closed. It becomes a state. Then, the value of the protect signal S3, which is the output of the second AND gate 20c, is always “0”, so that the gate circuit 20d remains open, and it is assumed that the access address data (ADx) Even if the value exceeds the user program access range, the access to the access target memory 20e is not protected, and the system program can be handled without any trouble.

  If the enable setting state ST1 of the access range check circuit is disabled (“0”), the output signal S2 of the first AND gate 20b is set regardless of the value of the access range check enable state ST2 of the instruction code opcode. Is always "0", the value of the protect signal S3 is also always unprotected ("0"), the gate circuit 20d remains open, and the address outside the range of the access range check circuit 20a of the user program The access signal S1 is invalidated and the memory access is not protected.

  A flowchart showing the enable setting process of the access range check circuit described above is shown in FIG. As shown in the figure, when the enable setting state ST1 of the access range check circuit stored in the setting register (not shown) is enabled ("1") (step 601 YES), the access range check circuit 20a of the user program Is enabled (step 602), and thereafter, whether or not the access range check enable state of the instruction word opcode is disabled is repeatedly checked every time the instruction is executed (step 603), and the access target memory 20e is checked. It will be protected.

  On the other hand, when the enable setting state ST1 of the access range check circuit is disabled (“0”) (NO in step 601), the access range check circuit 20a is always disabled and the access target memory 20e is protected. There is no.

  Next, FIG. 7 shows a flowchart showing the CPU processing in comparison between the present invention and the conventional example.

  When the process is started in the figure, the cycle time is determined after executing the initial process at the time of turning on the power in both the conventional process shown in the figure (a) and the process of the present invention shown in the figure (b). A series of processes (common processing, arithmetic processing, I / O refresh processing, and peripheral service processing) that define the above are cyclically executed.

  At this time, focusing on the initial process at power-on, in the conventional process, the general initial process (step 711) and the first transfer process (step 711) and the first transfer process (from the FROM 125 to the ASIC execution target memory 127) Whereas step 712) is executed by the MPU 121, in the process of the present invention, general initial processing (step 721) and the first transfer for transferring the user program from the FROM 125 to the ASIC execution target memory 127 In addition to the processing (step 722, see ST11 in FIG. 2), the second transfer processing for transferring the second program part of the system program from the ROM 123 to the ASIC execution target memory 127 (step 722A, see ST12 in FIG. 2) Is executed by the MPU 121. Therefore, although both the present invention process and the conventional process are processes by the MPU 121, the time required for the initial process when the power is turned on in the present process (T21) is the amount of the process (step 722A) added. It takes longer (T21> T11) than the time required for initial processing (T11) when the power is turned on in the conventional processing.

  Similarly, focusing on common processing, in the conventional processing, the MPU 121 executes hardware and user program memory check processing (step 713) and other check processing (step 714). In the processing of the present invention, hardware and user program memory check processing (step 723) and other check processing (step 724) are executed by the ASIC 122. For this reason, although the processing content does not change in both the processing of the present invention and the conventional processing, the execution subject is different between the MPU 121 and the ASIC 122. Therefore, the time required for the common processing in the processing of the present invention (T22) is common in the conventional processing. This is shorter than the time required for processing T12 (T22 <T12).

  Similarly, focusing on the arithmetic processing, in the conventional processing, the execution processing of the user program (step 715) is executed by the ASIC 122, whereas in the processing of the present invention, the execution of the user program is executed. The process (step 725) is executed by the ASIC 122 (see ST13 and ST14 in FIG. 2). Therefore, the time required for the arithmetic processing in the processing of the present invention (T23) is not substantially different from the time required for the processing of the present invention in the conventional processing (T13) (T23 = T13).

  Similarly, focusing on the I / O refresh process, in the conventional process, the I / O refresh process (step 716) is executed by the MPU 121, whereas in the process of the present invention, the I / O refresh process is performed. The / O refresh process (step 726) is executed by the ASIC 122. Therefore, the time required for the I / O refresh process (T24) in the process of the present invention is shorter (T24 <T14) than the I / O refresh process (T14) in the conventional process.

  Similarly, focusing on the peripheral service processing, in the conventional processing, the peripheral service processing (step 717) is executed by the MPU 121, whereas in the processing of the present invention, the peripheral service processing (step 727) is executed by the ASIC 122. Therefore, the time required for the peripheral service process (T25) in the process of the present invention is shorter (T25 <T15) than the peripheral service process (T15) in the conventional process.

  As a result, according to a trial calculation by the present inventors, the cycle time in the process of the present invention shown in FIG. 6B is shortened to about 1/3 of the cycle time in the conventional process shown in FIG. It was confirmed that

  In the above embodiment, the common process, the I / O refresh process, and the peripheral service process are all described in the PLC language so that all the processes are executed by the ASIC 121. Whether the process is described in the PLC language and executed by the ASIC 121 may be arbitrarily determined in consideration of the required cycle time and the cost of design change.

  When a system control program written in the MPU language is converted into the PLC language via the compiler, the instruction word is used for checking the access range in the specific bit of the operation code of each instruction word constituting the PLC language. It is preferable to set disable (“0”) so that it does not occur.

  According to the present invention, in a PLC having both this type of MPU and ASIC, it is possible to provide a PLC with high input / output responsiveness at low cost while effectively utilizing existing PLC resources.

It is explanatory drawing of the basic composition of the whole PLC. It is a hardware block diagram (this invention) of a CPU unit. It is explanatory drawing which shows the storage content of ASIC execution object memory. It is explanatory drawing of the address space which compares and shows this invention and a prior art example regarding an operand range. It is a block diagram of the access range check circuit of a user program and a system control program. It is a flowchart which shows an access range check circuit enable setting process. It is a flowchart which compares and shows CPU processing by this invention and a prior art example. It is a hardware block diagram (conventional example) of a CPU unit. It is a general flowchart (conventional example) which shows operation | movement of CPU unit of PLC.

Explanation of symbols

1 PLC
2 Development Support Device 3 Backplane 11 Power Supply Unit 12 CPU Unit 13 Input / Output Unit (I / O Unit)
14 Special Function Unit 121 MPU
122 ASIC
123 System program memory (ROM)
124 Working memory (RAM)
125 Setting memory (FROM)
126 User program buffer memory (FROM)
127 ASIC execution target memory (high-speed RAM)
127a User program storage area 127b System control program storage area 128 Input / output memory (high-speed RAM)
20 Access Range Check Circuit ST1 Access Range Check Circuit Enable Setting State ST2 Instruction Opcode Access Range Check Enable State 20a User Program Access Range Check Circuit 20b First AND Gate 20c Second AND Gate (Protect Circuit)
20d Gate circuit 20e Access target memory ADx Address data ADk to be accessed Address data indicating user program access range S1 Out-of-range address access signal S2 Output signal of first AND gate S3 Output of second AND gate (protection circuit) Signal (Protect signal)
S4 Control signal DATA Data to be written DB Data bus AD Address data

Claims (4)

A system program memory composed of a non-volatile memory for storing a system program for realizing system control specifications as a PLC;
A user program buffer memory composed of a non-volatile memory for storing a user program written in the PLC language for realizing a device control specification desired by the user;
An MPU that executes a program written in the MPU language;
An ASIC that executes a program written in the PLC language;
An ASIC execution target memory composed of a system program memory for storing a program to be executed by the ASIC and a memory capable of operating at a higher speed than the user program buffer memory ,
The system program stored in the system program memory has a first program part described in the MPU language and including at least an initial process at power-on, and a second program part described in the PLC language, and Initial processing at power-on includes first transfer processing for transferring a user program written in the PLC language from the user program buffer memory to the ASIC target memory, and from the system program memory to the ASIC execution target memory in the PLC language. A PLC comprising: a second transfer process for transferring a second program portion described.   The user program part transferred in the first transfer process is stored in the ASIC execution target memory from the beginning, and the system program part transferred in the second transfer process is continued from the user program part of the ASIC execution target memory. The PLC according to claim 1, wherein the PLC is stored in an empty area. Each time an instruction word constituting the PLC language is read, the ASIC checks whether the access target address specified by the operand falls within a predetermined user program access range. And an access range check circuit having an access range check function for controlling whether or not access to the access target memory is possible, and each read instruction word includes an access range check enable instruction word. 3. The PLC according to claim 1, further comprising a protect circuit that enables the access range check function only when it is determined that In the second program part,
4. The PLC according to claim 1, wherein common processing, I / O refresh processing, and / or peripheral service processing are included.

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