JP4792766B2 - Data transfer device and imaging device - Google Patents

Description

  The present invention relates to a data transfer apparatus and an imaging apparatus that perform DMA (Direct Memory Access) transfer.

In an imaging apparatus such as a digital camera, a DMA transfer technique is adopted to perform a lot of processing using a common data bus. For example, when display data is supplied to a display unit and displayed. DMA transfer is used (see, for example, Patent Document 1).
Further, in an electronic device that performs DMA transfer, particularly an electronic device that uses a battery as a power supply voltage, the clock frequency is switched to a low speed when high-speed processing is not required in order to reduce power consumption (for example, , See Patent Document 2).
JP 2003-132007 A JP 2003-242104 A

  However, conventionally, the clock frequency value is switched depending on the rough operation mode, etc., and it does not correspond to the optimal clock frequency value for the bus traffic state during DMA transfer, so wasted power consumption. May be made. Further, switching of the clock frequency value depending on the operation mode has a drawback that normal transfer operation cannot be performed when bus traffic (bus occupation) is concentrated.

  An object of the present invention is to solve the above-mentioned problem, and is a data transfer apparatus capable of preventing wasteful power consumption by performing DMA transfer with an optimal clock frequency value according to the state of bus traffic. And providing an imaging device.

2. The data transfer apparatus according to claim 1, wherein a DMA bus control means for performing DMA transfer control of data among a plurality of circuits sharing the DMA transfer section, and a clock for controlling a clock frequency of data transfer in the DMA transfer section. And a clock number setting means for setting the number of clocks per unit time necessary for the data transfer between the respective circuits based on the operating state of the data transfer apparatus every time DMA transfer is started. When,
A clock frequency setting means for setting the clock frequency of the data transfer in the DMA transfer portion on the basis of the number of clocks sum between each circuit set by the clock count setting means,
It is characterized by providing.

  The invention according to claim 2 is the data transfer device according to claim 1, further comprising frequency storage means for storing a value of the clock frequency set by the clock frequency setting means, and data in the DMA transfer section At the end of the transfer, low frequency setting means for setting the clock frequency stored in the frequency storage means to a low clock frequency required for continuing the operation of the entire system is provided.

  According to a third aspect of the present invention, in the data transfer device according to the first or second aspect, the clock frequency set by the clock frequency setting means is equal to or greater than a total value of the number of clocks and the transfer is normally performed. The clock frequency is within a range to be performed.

  According to a fourth aspect of the present invention, in the data transfer device according to any one of the first to third aspects, the clock number data per unit time necessary for the data transfer between the circuits is further obtained. It comprises clock number data storage means for storing.

An imaging apparatus according to a fifth aspect includes the data transfer apparatus according to any one of the first to fourth aspects.

  According to the first to fourth aspects of the present invention, it is possible to switch to a clock frequency value required at the time of DMA transfer in the driving state of each circuit by software processing before starting DMA transfer or after completing DMA transfer. .

According to the invention described in claim 5 , in the imaging apparatus, it is possible to switch to a clock frequency value suitable for the state of bus traffic by software processing.

  According to the present invention, since it is possible to switch to a clock frequency value suitable for the state of bus traffic by software processing, consumption without impairing the performance of an imaging device such as a digital camera or a camera mounted on a mobile phone. It becomes possible to reduce electric power.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, the embodiments described below are provided with various technically preferable limitations for carrying out the present invention, but the scope of the invention is not limited to the following embodiments and illustrations.

[First Embodiment]
FIG. 1 is a circuit configuration diagram of a digital camera which is an example of an imaging apparatus to which a data transfer apparatus according to the present invention is applied.

  The control unit 1 includes a CPU, a ROM, a RAM, and the like. The ROM stores a program for controlling the operation of the entire digital camera and for performing various operations described later, and is supplied to each circuit described later via the data bus DB. The ROM stores transfer parameters, which will be described in detail later, and function information of the digital camera. The function information is stored in the recording unit via the DMA bus control unit 2, the DMA transfer unit (data bus) 10, and the memory control unit 11. 12 to be stored.

  The DMA transfer unit 10 has a common data bus and DMA-transfers data output from each circuit. The DMA bus control unit 2 controls the DMA transfer channel and the transfer clock frequency. The DMA bus control unit 2 controls DMA data transfer between a plurality of circuits sharing the DMA transfer unit 10 according to an instruction from the control unit 1.

  The input unit 3 includes a plurality of operation buttons (not shown). The operation button includes a setting button for setting the operation mode and shooting conditions of the digital camera, a shutter button for instructing shooting, a playback button for instructing playback of the recorded image, and the like. Note that examples of the operation mode include a recording mode, a reproduction mode, and an erasing mode.

  A CCD (Charge Coupled Devices) 4 that is an imaging element captures and captures an external subject image via an optical system (not shown) such as a lens. The analog signal of the subject image imprinted on the CCD 4 is read out by the readout pulse supplied from the CCD drive circuit 6 based on the pulse signal output from the timing generator 5 that supplies the timing pulse signal to each part, and the CDS ( Correlated Double Sampling) / amplification circuit 7

  The CDS / amplifier circuit 7 performs correlated double sampling of the analog signal to remove noise and perform gain adjustment. The gain-adjusted signal is converted into a digital signal by an analog / digital (A / D) conversion circuit 8 and sequentially sent to a buffer 9 and also sent to a memory control unit 11 via a DMA transfer unit 10. The memory control unit 11 controls writing and reading of information to and from the recording unit 12, and causes the recording unit 12 to record the digital signal transmitted via the DMA transfer unit 10.

  The recording unit 12 is composed of a large-capacity RAM or a flash memory. The recording unit 12 sequentially records the image signal sent from the CCD 4 and stores the image signal in frame units, or converts the image signal in frame units, which will be described later, into luminance (Y) and color difference (UV) signals. A storage area is provided for recording converted image information (hereinafter referred to as YUV image information), YUV image information obtained by converting the resolution of the YUV image information, and function information sent from the control unit 1.

  Here, the image information for one frame sent from the CCD 4 and recorded in the recording unit 12 is immediately read out via the memory control unit 11 and sent to the YUV conversion circuit 14 via the DMA transfer unit 10 and the buffer 13. And converted into YUV image information. The image information for one frame is converted into YUV image information, and then sent to the memory control unit 11 via the buffer 15 and the DMA transfer unit 10 and recorded in the recording unit 12.

Further, the YUV image information recorded in the recording unit 12 is read out via the memory control unit 11 and sent to the resolution conversion circuit 24 via the DMA transfer unit 10 and the buffer 23. The YUV image information sent to the resolution conversion circuit 24 is converted into a data amount suitable for the display data of the display unit 22 to be described later, and is recorded in the recording unit via the buffer 25, the DMA transfer unit 10 and the memory control unit 11. 12 is stored. In addition, when a still image shooting or a moving image shooting is instructed, the YUV image information stored in the recording unit 12 is read out via the memory control unit 11, and the read YUV image information is stored in the DMA. The data is sent to the compression / decompression circuit 17 via the transfer unit 10 and the buffer 16. The sent YUV image information is converted into, for example, JPEG standard format image information in the case of a still image, or motion JPEG or MPEG standard format image information in the case of a moving image, and then transferred to the buffer 18 and DMA transfer. It is sent to the recording medium control unit 19 via the unit 10 and recorded on the recording medium 20.
The recording medium 20 includes a nonvolatile memory or a magneto-optical disk that can be attached to and detached from the digital camera body. The non-volatile memory or magneto-optical disk preferably has a large capacity capable of recording a large number of still images or moving images.

  As for the function information of the digital camera, information such as characters, symbols or icons representing each function such as a mode name and a photographing condition value is recorded in the ROM of the control unit 1 in advance. The function information of the digital camera is once recorded in the recording unit 12 and then sent to the display control circuit 21 described later in detail through the memory control unit 11 and the DMA transfer unit 10. The function information sent to the display control circuit 21 and the subject image converted by the resolution conversion circuit 24 are combined and displayed on the display unit 22.

  The clock circuit 26 measures the current date and time, and the current date and time that has been timed are once recorded in the recording unit 12 and then displayed via the memory control unit 11 and the DMA transfer unit 10. 21. The image is combined with the subject image converted by the resolution conversion circuit 24 and displayed on the display unit 22.

  In the still image or moving image shooting mode, the subject image captured on the CCD 4 is always displayed on the display unit 22 through the display control circuit 21. The display unit 22 is composed of a color liquid crystal, a color organic EL, or the like. In addition, the display unit 22 has display pixels arranged in a matrix in the horizontal and vertical directions, and serves as an electronic viewfinder (monitor display) at the time of shooting by displaying a subject image.

  The display control circuit 21 includes a first DMA interface (I / F) control circuit 30, a second DMA interface (I / F) control circuit 34, a synthesis circuit 37, a code conversion circuit 38, buffers 31, 32, buffers 35 and 36, and a display. A clock signal generation circuit 40 and the like are provided.

  The first DMA interface control circuit 30 sends a DMA transfer request signal to the DMA transfer unit 10, receives a DMA response signal and function information of the digital camera from the DMA transfer unit 10, and sends them to the buffers 31 and 32. Inside the first DMA interface control circuit 30, a memory 30A for recording display position information of function information on the display unit 22 is provided.

The second DMA interface control circuit 34 sends a DMA transfer request signal to the DMA transfer unit 10, and the YUV image information whose resolution is converted by the resolution conversion circuit 24 and recorded in the recording unit 12 via the DMA transfer unit 10. Receive and send to buffers 35 and 36. Inside the second DMA interface control circuit 34, a memory 34A for recording display position information of image information is provided.
The YUV conversion circuit 14, the compression / decompression circuit 17, the resolution conversion circuit 24, and the like include a DMA interface control circuit (not shown) in addition to each buffer.

  The outputs (image information) of the buffers 35 and 36 are sent to the synthesis circuit 37, and the outputs of the buffers 31 and 32 are also sent to the code conversion circuit 38 and converted into YUV image information, and then sent to the synthesis circuit 37. It is synthesized with the image information displayed on the display unit 22. The two buffers 31 and 32 are provided for the first DMA interface (I / F) control circuit 30, and the two buffers 35 and 36 are provided for the second DMA interface (I / F) control circuit 34, respectively. The data of a predetermined burst length sent by the DMA transfer is stored in one buffer, and while the stored data is being read, the next sent data is stored in the other buffer, Immediately after the reading of one buffer is completed, the data stored in the other buffer is immediately read and the next data is stored in one buffer during that time so that the display information transfer delay is not caused. It is to do.

  The display clock signal generation circuit 40 includes a horizontal counter 41 and a vertical counter 42 that count the reference clock signal (φ), and a decoder 43 that decodes data sent from these. The display clock signal extracted by the decoder 43 is sent to each part in the display control circuit 21.

  The clock control unit 51 includes a PLL (Phase Locked Loop), and divides the number of clocks input from the oscillation circuit 52 to output a clock for DMA transfer and for controlling each unit. In this case, the frequency of the output clock (hereinafter sometimes referred to as the active clock frequency) is switched by a control signal from the control unit 1.

Next, the operation of the digital camera of the first embodiment will be described.
FIG. 2 shows a flowchart of active clock frequency change control when DMA transfer is activated.

In a state where the DMA transfer before the processing of FIG. 2 is not activated, the control unit 1 registers the clock frequency S value in a RAM (not shown) inside the control unit 1. In this case, when the digital camera is turned on and the system is initially set, the clock frequency S value after the initial setting may be registered in the ROM in advance.
Here, the clock frequency S value is a value of the number of clocks per unit time, and is a minimum clock frequency value required to continue the operation of the entire system in the driving state of each circuit. The active clock frequency is the current clock frequency oscillated from the clock control unit 51.

Thus, for example, when the shooting mode is set, the subject image captured on the CCD 4 is displayed on the display unit 22, so that the subject image captured on the CCD 4 is stored in the recording unit 12 via the DMA transfer unit 10. 2 is started in order to transfer or receive the image information stored in the recording unit 12 to the YUV conversion circuit 14, the resolution conversion circuit 24, and the display control circuit 21.
When the DMA transfer activation process is started, first, each DMA transfer parameter is selected and set (step S111). Here, the DMA transfer parameter to be set is the number of clocks per unit time required for DMA transfer between circuits via the DMA transfer unit 10 (hereinafter, this value is referred to as clock frequency A1 value, A2 value, A3 Value). For example, if the image data imprinted on the CCD 4 is to be displayed through on the display unit 22 at a frame rate of 30 frames per second, 30 frames of image data (however, one frame is all for the CCD 4 because it is for display). The clock frequency necessary for recording the recording unit 12 on the recording unit 12 is not the pixel data but the image data thinned out by a predetermined amount, and the image data stored in the recording unit 12 is read out and DMA-transferred to the YUV conversion circuit 14 The clock frequency required for the recording is A2, the clock frequency required for recording the YUV image data converted by the YUV conversion circuit 14 on the recording unit 12 is A3, and the YUV image data stored in the recording unit 12 is the resolution conversion circuit 24. The clock frequency required for DMA transfer is A4, which is necessary for DMA transfer between circuits. Frequency value is set.

  The clock frequencies A1, A2, A3, A4,... Are stored in advance in a ROM (not shown) of the control unit 1, and different parameters are set depending on the mode or the shooting state. . For example, in the above-described through display, in addition to the clock frequency described above, the clock frequency A5 for transferring and recording the image data from the resolution conversion circuit 24 to the recording unit 12 and the transferred and recorded image data are sent to the display control circuit 21. The clock frequency A6, the clock frequency A7 for sending camera function information to the display control circuit 21, and the like are set. When the shutter button is operated in this through display state to record a still image, all the pixels of the CCD 4 are instructed. Since the data is sent to the recording unit 12 as one frame of image data, the amount of data per frame is larger than that during through display. However, the recording of still images does not require 30 frames, and may be 1 or 2 frames. Therefore, a clock frequency, for example, A10 for DMA transfer of data for 1 or 2 frames is set. In addition, the clock frequency for DMA transfer from the recording unit 12 to the compression / expansion circuit 17 and the clock frequency A11 for DMA transfer from the compression / expansion circuit 17 to the recording medium 20 that are not DMA-transferred for the through display are set during recording. It is what is done.

  Based on the DMA transfer parameter setting, the control unit 1 adds each of the clock frequency A1, A2, A3,... Required for DMA transfer in the driving state of each circuit, and further, a clock described below. The total value G value is calculated by adding the frequency J value (step S112).

The clock frequency J value is a surplus clock frequency value that allows the DMA transfer to be normally performed in consideration of the bus traffic state due to the difference in the DMA transfer waiting time and the amount of converted data to be transferred. Is set.
Accordingly, in step S112, the lowest frequency required for DMA transfer is calculated as the total value G.

  In the next step S113, the clock frequency S value registered before entering this flowchart is compared with the total value G value calculated in step S112, and the active clock frequency S value determines the operation of the entire system when each DMA is started. It is determined whether or not the value is equal to or lower than the minimum clock frequency G required for continuing.

When it is determined that the active clock frequency S value is smaller than the calculated clock frequency G, that is, the active clock frequency S value is not the minimum clock frequency value (step S113; Yes), the active clock frequency is set to the frequency G. The value of the active clock frequency is changed so as to increase the value (step S114).
After changing the value of the active clock frequency to the clock frequency G value, the value of the active clock frequency S stored in the RAM of the control unit 1 is updated to this clock frequency G value (step S115). After updating to the clock frequency S value, the DMA transfer of each circuit is started (step S116).
After the DMA transfer is activated, the DMA transfer end wait state is entered (step S117), and the DMA transfer ends.

In step S113, when the clock frequency S value is equal to or higher than the necessary minimum clock frequency G value (step S113; No), the clock frequency S value is not changed without changing the active clock frequency value. The DMA transfer of the circuit is started (step S116).
After starting the DMA transfer, the DMA transfer is waited for (step S117), and the DMA transfer ends.

FIG. 3 is a flowchart of DMA transfer end processing, and particularly shows a flow of changing the active clock frequency at the end of DMA transfer.
First, when the DMA transfer end process is started, the control unit 1 performs various processes for DMA transfer end other than the change of the active clock frequency (step S121), and the DMA transfer set in step S111 of FIG. The clock frequency A1 value, A2 value, A3 value, etc., which are parameters are summed up and calculated, and the current active clock frequency value S (if the processing in steps S114 and S115 in FIG. The total value of the clock frequency A1, A2, A3,... Is subtracted from the frequency value S), and the J value is subtracted to calculate the total value G (step S122). ).

  In the next step S123, the total value G obtained in step S122 is compared with the minimum clock frequency required to continue the operation of the entire system after the completion of the DMA transfer. It is determined whether or not the clock frequency is greater than the limit.

If it is determined that the total value G is larger than the minimum clock frequency (step S123; Yes), the active clock frequency is lowered to the minimum clock frequency (step S124), and step S124. Later, the necessary minimum clock frequency value is updated as a new active clock frequency S value (step S125), and the process ends.
When the total value G is the minimum necessary clock frequency value (step S123; No), the active clock frequency value remains as it is, and the active clock frequency value is not updated and ends ( Step S124). Although the total value G cannot be less than the minimum required clock frequency, the active clock frequency is set to the minimum required if it is below the minimum required clock frequency due to some error. The clock frequency may be increased.

  These processes shown in FIGS. 2 and 3 are repeated every time the DMA roll is started and the DMA transfer is stopped.

  From the above, it is possible to optimally switch the DMA transfer between the circuits to the lowest possible clock frequency value within the range in which the transfer is normally performed before starting and / or after the DMA transfer is completed. Furthermore, the data transfer device was used because the value of the active clock frequency can be appropriately switched to the value of the clock frequency required to continue the operation of the entire system while corresponding to the bus traffic state of the data bus. Power consumption can be reduced without impairing the performance of an imaging apparatus such as a digital camera.

  When bus traffic is concentrated, priorities and narrowing down may be set in advance for DMA transfer between circuits. By prioritizing and narrowing down the DMA transfer, it is possible to avoid the concentration of bus traffic while ensuring DMA transfer between important circuits, so that the performance of the imaging apparatus is not impaired while continuing the operation of the entire system. , Power consumption can be reduced.

[Second Embodiment]
A digital camera according to the second embodiment will be described. In the second embodiment, the description of the same parts as in the first embodiment is omitted. The difference from the first embodiment is that a bus occupancy measuring unit is provided in the DMA bus control unit 2.
The bus occupancy measurement unit measures the active clock frequency for a certain period by a counter and calculates the bus occupancy in the DMA transfer unit 10.
Note that the bus occupancy rate measurement unit may be provided in another circuit, or may independently respond with another circuit via the DMA transfer unit 10.

The control unit 1 performs clock frequency control for the entire system. In addition to the program of the first embodiment, the ROM of the control unit 1 stores a program for performing operations (steps S201 to S207) to be described later.
The ROM also maintains the operation of the entire system based on the clock frequency corresponding to the activation state of each circuit after the digital camera is activated and the system is initialized, and is allowed by the DMA transfer unit 10. A predetermined threshold value of an upper limit value (Qmax) and a lower limit value (Qmin) of the bus occupancy that can be set is set, and the predetermined threshold value is read by the control unit 1.

Next, the operation of the digital camera of the second embodiment will be described.
FIG. 4 shows a flowchart of control of the second embodiment.
The bus occupancy rate measurement unit starts activation of the bus occupancy rate measurement counter of the entire DMA transfer unit 10 per unit time based on the clock frequency value during DMA transfer in the driving state of each circuit. (Step S201). Examples of the driving state of each circuit include the operating cycle of the CCD driving circuit 6 and the display unit 22 as a basis for each operation mode.

The bus occupancy rate measuring unit measures the bus occupancy rate, calculates the bus occupancy rate result, and writes it in the provided RAM (step S202). If the measurement of the bus occupancy rate of the bus occupancy rate measuring unit does not end (step S202; N), the measurement is continued as it is, and if the measurement is completed (step S203; Y), the control unit 1 ends. Notice.
After the notification, the control unit 1 reads the bus occupancy rate measurement result (Qrst) from the bus occupancy rate measurement unit (step S203), and sets predetermined threshold values for the upper limit value (Qmax) and lower limit value (Qmin) of the bus occupancy rate. Read from the ROM of the control unit 1 or the like. The predetermined threshold is preferably set in the ROM in advance.

  The control unit 1 controls the clock frequency value corresponding to a predetermined threshold based on the calculated bus occupancy rate result (Qrst) (steps S204 to S207). That is, the control unit 1 switches the value of the clock frequency based on the bus occupancy measurement result (Qrst) read from the bus occupancy measurement unit.

  When the bus occupancy rate measurement result (Qrst) is larger than the upper limit value (Qmax) of the threshold (Qrst> Qmax) (step S204; Y), the control unit 1 changes the value to increase the active clock frequency ( Step S205), the process proceeds to the next step 206. When the bus occupancy rate measurement result (Qrst) is smaller than the upper limit value (Qmax) of the threshold (Qrst <Qmax) (step S204; N), the control unit 1 keeps the value of the active clock frequency as it is, The process proceeds to step 206.

  Further, when the bus occupancy rate measurement result (Qrst) is smaller than the lower limit value (Qmin) (Qrst <Qmin) (step S206; Y), the control unit 1 changes the active clock frequency value so as to decrease ( Step S207), the process proceeds to the next step 208 and ends. When the bus occupancy rate measurement result (Qrst) is larger than the lower limit value (Qmin) (Qrst> Qmin) (step S206; N), the value of the active clock frequency is left as it is, and the processing ends. At this time, the value of the active clock frequency is within a predetermined threshold.

  The control unit 1 repeats these processes at regular intervals to control the value of the active clock frequency (steps S201 to S207).

Based on the above, the actual bus traffic state is measured as the bus occupancy rate measurement result, and the active clock frequency value can be periodically switched to the optimal clock frequency value based on the bus occupancy rate result. The operation of the entire system of the imaging apparatus such as a camera can be stably continued. Further, since the value of the clock frequency can be reduced within a threshold required at the time of DMA transfer in an actual bus traffic state, power consumption can be reduced.
[Third Embodiment]

A digital camera according to the third embodiment will be described. In the second embodiment, the description of the same parts as in the first embodiment is omitted. The difference from the first embodiment is that a clock control unit 51a that further measures the number of clocks of the active clock frequency and sends the result to the control unit 1 is provided.
In addition to the program of the first embodiment, the ROM of the control unit 1 stores a program for raising the value of the active clock frequency when there is no DMA response based on the operation described later, particularly based on the number of clocks.

In the third embodiment, for example, the second DMA interface control circuit 34 of the display control circuit 21 will be described as an example. The second DMA interface control circuit 34 sequentially sends image information B1, B2,... Consisting of, for example, 8 words to the buffers 35, 36.
The clock controller 51a includes a counter that counts the number of clocks. The clock control unit 51 a sends the number of clocks to the control unit 1 via the DMA transfer unit 10. In the operation program, the number of clocks corresponding to the value of the clock frequency between the circuits is set as the allowable time until the writing of image information to the buffers 35 and 36 is started after the DMA transfer request is started. .

Next, the operation of the digital camera of the third embodiment will be described.
FIG. 5 shows a timing chart of the operation of the display unit 22 which is an example of the third embodiment.
The control unit 1 sends image information B1, B2,... For each predetermined amount to the buffers 35 and 36 via the DMA transfer unit 10 and the second DMA interface control circuit 34. The image information B1 is recorded in the buffer 35 before the display timing.

  The image information B1 recorded in the buffer 35 is read (operation time A), sent to the display unit 22 via the synthesis circuit 37, and displayed. At the same time, a DMA transfer request is made to send image information B2 (operation time B), and a DMA response signal (operation time C) and image information B2 are sent in response to this DMA transfer request. This image information B2 is written in the buffer 36 (operation time D).

At the next timing t1, the image information B2 written in the buffer 36 is read out and sent to the display unit 22 via the synthesis circuit 37 (operation time E) and a DMA transfer request is sent to send the next image information B3 ( Operating time F). In response to this DMA transfer request, a DMA response signal (operation time G) and image information B3 are sent and written to the buffer 35 (operation time H).
At the next timing t2, the image information B3 written in the buffer 35 is read out, sent to the display unit 22, and the next image information B4 is written in the buffer 36.

  In this way, the display data is alternately written and / or read by the two buffers 35 and 36, the image information B1, B2,... Is sent to the display unit 22 via the synthesis circuit 37, and the image is displayed on the display unit 22. Display.

Here, simultaneously with asserting the DMA transfer request, the clock control unit 51 starts counting the number of active clocks of the active clock frequency and sends the number of active clocks to the control unit 1.
When the control unit 1 has not received the image information B1 and / or the DMA response after the received active clock count exceeds the clock count X value set correspondingly between the circuits (allowable time elapses) The active clock frequency is increased to a preset clock frequency. Further, after the value of the active clock frequency is increased, the control unit 1 further sets the value of the active clock frequency in advance if the image information B1 has not been sent even after the fixed count number Y (allowable time) has elapsed. Increase the clock frequency to the set value.

For example, if the image information A1 and / or the DMA response is not sent to the control unit 1 after a predetermined number of clocks X value (for example, X = 3) at the clock frequency f0 in FIG. Then, the clock control unit 51 is controlled so that the clock frequency f0 is immediately increased to the clock frequency f1. Further, after a predetermined clock count Y value (for example, Y = 3) has elapsed at the clock frequency f1, if the image information A1 and / or the DMA response is not sent to the control unit 1, the clock frequency f2 is further activated. Increase the clock frequency. In this case, the value of the clock frequency is f0 <f1 <f2.
By sequentially increasing the clock frequency value to f0, f1, f2,..., The write operation time I at timing t2 can be made shorter than the write operation time B at timing t0. At this time, the value of the clock frequency between the circuits required at the time of DMA transfer that can continue the operation of the entire system is set.

As described above, the period of the timings t0, t1, t2,... Is synchronized with the display timing and is fixed, so that the image information can be written and / or read in accordance with these timings. Can be displayed normally.
In addition, the clock frequency value required at the time of DMA transfer is set to a low value in advance, and the clock frequency value is immediately increased according to the number of clocks so that there is no delay in writing data to the buffer and reading data from the buffer. Therefore, the operation of the entire system of the imaging apparatus such as a digital camera can be stably continued and the power consumption can be reduced.

  In addition, since the bus traffic can be managed by the control unit, it is possible to prevent an operation failure due to concentration of access that cannot be predicted more accurately and to ensure a sufficient operation margin, and a stable operation system. Can be built.

1 is a circuit configuration diagram of a digital camera that is an example of an imaging apparatus according to the present invention. FIG. 6 is a control flow diagram of an active clock frequency before starting DMA transfer in the first embodiment. FIG. 6 is a control flow diagram of an active clock frequency after completion of DMA transfer in the first embodiment. FIG. 10 is a control flow diagram of an active clock frequency during DMA transfer in the second embodiment. It is a time chart figure of the DMA transfer in 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control part 2 DMA bus control part 10 DMA transfer part 34 2nd DMA interface control circuit 51 Clock control part

Claims (5)

DMA bus control means for performing DMA transfer control of data between a plurality of circuits sharing a DMA transfer unit;
A data transfer device comprising clock control means for controlling a clock frequency of data transfer in the DMA transfer unit;
A clock number setting means for setting the number of clocks per unit time required for the data transfer between the respective circuits based on the operating state of the data transfer device every time DMA transfer is started ;
A clock frequency setting means for setting the clock frequency of the data transfer in the DMA transfer portion on the basis of the number of clocks sum between each circuit set by the clock count setting means,
A data transfer device comprising:   Further, it comprises frequency storage means for storing the clock frequency value set by the clock frequency setting means, and at the end of data transfer in the DMA transfer section, the clock frequency stored in the frequency storage means is set to operate the entire system. 2. The data transfer apparatus according to claim 1, further comprising low frequency setting means for setting to a low clock frequency required for continuing.   3. The data according to claim 1, wherein the clock frequency set by the clock frequency setting means is a clock frequency that is equal to or greater than a total value of the number of clocks and in a range in which transfer is normally performed. Transfer device.   The clock number data storage means for storing clock number data per unit time necessary for the data transfer between the circuits is further provided. Data transfer device. Imaging apparatus characterized by comprising a data transfer apparatus according to any one of claims 1 to 4.

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