JP4791999B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a wiring pattern in a region where wirings having different pitches are connected. For example, the present invention is applied to a boundary region between a memory cell array region and a memory cell peripheral circuit region in a NAND flash memory. is there.

  Optical lithography is generally used for manufacturing semiconductor devices such as semiconductor memories and microprocessors. In optical lithography, a pattern exposure mask on which a pattern has been formed is irradiated with light, projected onto a photoresist on a semiconductor substrate via an optical system, and the photoresist is exposed to expose the mask pattern onto the semiconductor substrate. Transfer technology.

  Semiconductor devices are being miniaturized for the purpose of high integration and cost reduction. For that purpose, it is first necessary to realize miniaturization of a pattern formed by photolithography.

  In general, the resolution R and the depth of focus DOF in optical lithography are expressed by the following Rayleigh equation.

R = k1 (λ / NA)
DOF = k2 (λ / NA2)
Here, λ is the wavelength of the light source, NA is the aperture ratio, k1 and k2 are constants based on the process and the like.

  As can be seen from the above equation, it is effective to shorten the wavelength of the light source in order to transfer a fine pattern. Conventionally, i-line having a wavelength of 365 nm has been generally used as a light source of an exposure apparatus, but a KrF excimer laser having a wavelength of 248 nm is generally used to form a finer pattern.

  In order to advance further miniaturization, it is necessary to use a light source having a shorter wavelength, to reduce k1 and k2, and to increase the aperture ratio NA (higher NA). Here, although an ArF excimer laser with a wavelength of 193 nm is considered promising as a short wavelength light source, development including an optical system and a photoresist for the ArF excimer laser is difficult, and has yet to be put into practical use. Not in. Although k1 and k2 can be reduced by improving the resist and the process, generally, the limit is about 0.4 to 0.5. In addition, high NA is not practical because it is difficult to process a high NA lens capable of exposing a large area. Moreover, in actual exposure, it is necessary to secure a certain depth of focus. However, as is clear from the Rayleigh equation, as the NA increases, the depth of focus decreases. It is difficult.

  As described above, improvement in resolution is limited only by improvement in wavelength, aperture ratio, and process. Therefore, as a technique for further increasing the resolution, so-called super-resolution techniques such as a method using a halftone phase shift mask and a method using modified illumination for exposure of a mask pattern have come to be used. Here, the super-resolution technique will be briefly described.

  The halftone phase shift mask does not completely block the light even at the line pattern part, but instead of chromium, generally a translucent film with a transmission coefficient of 3 to 10% is formed to transmit the light. Are shifted by 180 degrees. At this time, the resolution is improved by making the light intensity distribution at the boundary between the line pattern and the space pattern steep due to the interference between the light transmitted through the line pattern portion and the light transmitted through the space pattern portion. is there. On the other hand, in a normal mask, the line pattern portion normally blocks light with chromium or the like so that the photoresist is not exposed.

  In the modified illumination method, an aperture that shields the vicinity of the center of the light source is provided to irradiate the mask with only light incident in an oblique direction. When such a modified illumination method is used, any one of the ± first-order lights in the diffracted light is not projected, and the remaining one of the diffracted lights is projected. The resolution can be improved by such a method of forming an image by using two light beams of the zero-order light and the ± first-order light. On the other hand, in the normal illumination method, the light irradiated to the mask from the light source is projected on the semiconductor substrate by projecting three light beams of zero-order light and ± first-order light generated by diffraction. Imaged.

  However, the super-resolution technique as described above is very effective for a dense pattern arranged periodically, but it is difficult to form a sparse pattern at the same time as the dense pattern. In this regard, for example, there are the following problems.

  FIG. 19 shows a general pattern arrangement of a semiconductor memory.

  A peripheral circuit region 2 for driving the memory cell array is arranged so as to surround the memory cell array region 1. The gate lines and metal wirings in the memory cell array region 1 are generally formed by a dense pattern arranged periodically such as a simple line and space (line and space), but the gates in the peripheral circuit region 2 The lines and metal wirings are formed in a pattern that is sparser than the memory cell array region 1. The gate lines and metal wirings in the peripheral circuit region 2 have a certain degree of periodicity, but have a more complicated pattern than the memory cell array region 1. The gate lines and metal wirings in the memory cell array region 1 extend out of the memory cell array region 1 as they are, and are connected to the gate lines and metal wirings in the peripheral circuit region 2 through the connection region 3.

  However, in such a connection region 3 between the memory cell array region 1 and the peripheral circuit region 2, the fine line-and-space pattern in the memory cell array region 1 extends as it is and the periodicity of the pattern Therefore, the resolution and the depth of focus in the connection area 3 are likely to deteriorate. As a result, a desired pattern is not formed, causing a disconnection or a short circuit of the wiring.

  FIG. 20 shows a pattern exposure mask on which a wiring pattern for connecting the memory cell array region 1 and the peripheral circuit region 2 in FIG. 19 is formed.

  In the figure, a wiring pattern having a line width L, a space S between lines, and a pitch (L + S) is formed in the memory cell array region 1, and a wiring pattern having a pitch of 2 × (L + S) is formed in the peripheral circuit region 2. In the connection region 3, a wiring pattern for connecting, for example, an odd-numbered wiring pattern in the memory cell array region 1 to a wiring pattern in the peripheral circuit region 2 is formed. In this case, one end of each of the remaining (even-numbered) wiring patterns in the memory cell array region 1 is terminated on the boundary line with the connection region 3. In addition, the line widths of the wiring patterns in the connection region 3 are changed in two stages, and the respective changed positions are aligned on the same line.

  FIG. 21 shows the result of the simulation of the resist pattern obtained when the resist on the semiconductor substrate is exposed using the pattern exposure mask shown in FIG. Here, the resist pattern is obtained by obtaining a light intensity distribution and showing an equal intensity distribution. The three lines in the resist pattern indicate the light intensity that the wiring dimensions can achieve as intended, and +/- The resist pattern at each of 10% light intensity is shown.

  As the calculation conditions for the above simulation, the line width of the wiring on the semiconductor substrate and the space between the lines are both 0.15 μm on the semiconductor substrate, the light source is a KrF excimer laser with a wavelength λ = 248 nm, the aperture ratio NA = 0.6, coherent The coefficient σ was set to 0.75, and a ring zone covering the central part of the light source (covering two-thirds of the entire light source by area ratio) was used. In addition, a halftone phase shift mask in which the transmittance was 6% and the phase was rotated 180 degrees was used as a pattern exposure mask. Further, in order to check whether the depth of focus is secured, it was assumed that the exposure was performed under a condition shifted by 0.4 μm from the optimum focus.

  However, it can be seen that, among the three simulation results shown in FIG. 21, the line is broken when the line width is the narrowest, that is, when the exposure amount is increased by 10% from the optimum value. That is, in actual exposure, wiring disconnection may occur due to variations in exposure amount, resist sensitivity, and the like, causing malfunction. The reason why the desired pattern is not formed at the part where the periodicity of the wiring is interrupted in this way is that the diffracted light generated at the terminal part of the wiring or the part where the line width of the wiring changes affects the adjacent pattern. is there.

  As described above, even if miniaturization in the memory cell array region is possible by using the super-resolution technique, a desired pattern is formed in the connection region 3 of the wiring between the memory cell array region and the peripheral circuit region as described above. In some cases, the pattern portion of the connection region 3 limits the pitch of the memory cell array, leading to an increase in the chip size of the semiconductor memory.

  As described above, the conventional semiconductor memory has a memory cell array region in which line & space wiring patterns are formed at a fine pitch below the wavelength of the light source of the exposure apparatus, and wiring patterns are formed at a larger pitch than that. In the boundary area with the peripheral circuit area, the resolution and depth of focus are likely to deteriorate due to light interference when forming a wiring pattern using photolithography, and the desired pattern is not formed. There is a problem that is likely to occur.

  The present invention has been made to solve the above problems, and includes a first region in which line and space wiring patterns are formed at a fine pitch P that is equal to or less than the wavelength of a light source of an exposure apparatus, and Suppresses deterioration of resolution and depth of focus when forming a wiring pattern using optical lithography in the boundary region with the second region where the wiring pattern is formed at a large pitch (for example, 2 × P), and wiring with different pitches An object of the present invention is to provide a semiconductor device which can prevent disconnection or short-circuit of a wiring pattern in a connection region and can be highly integrated.

The first semiconductor device according to the present invention includes a semiconductor substrate and a plurality of (n) line patterns made of a conductor having a line width L via a space S between lines in the first region on the semiconductor substrate. The first line & space pattern formed in order and the second region on the semiconductor substrate are n / 2 line patterns made of conductors each having a line width L or more. A second line and space pattern formed so as to repeat through the first line, and a third region existing between the first region and the second region on the semiconductor substrate. & N / 2 line patterns every other & space pattern and n connected to the n / 2 line patterns of the second line & space pattern
A third line & space pattern in which a line pattern made of two conductors is formed, and n / of the first line & space pattern not connected to the second line & space pattern each line pattern 2 is a boundary position between the first region and the first line pattern which terminates at the boundary between the third region, the third region and the second region
A second line pattern that terminates, the first line pattern, and the second line pattern.
A third line pattern that is located between the first and second regions and ends in the third region, and each line pattern of the third line & space pattern includes two adjacent first and third lines . line
Pattern or the second or third line pattern or the third line pattern
The line width changes in the length direction in the third region between the end positions of the lines, so that the line width is larger on the second region side than on the first region side. It is formed.

In the second semiconductor device of the present invention, a plurality of (n) line patterns each made of a conductor are arranged on the semiconductor substrate and the first region on the semiconductor substrate with a pitch P1 through the first inter-line space. In the first, second, third, and fourth line & space patterns formed in order, and n line patterns made of conductors in the second region on the semiconductor substrate are second Between the first region and the second region on the semiconductor substrate, and the fifth and sixth line and space patterns formed so as to repeat at a pitch P2 larger than P1 through the inter-line space. In a third region existing, n connected to a line pattern composed of n conductors of the second line & space pattern and a line pattern composed of n conductors of the fifth line & space pattern. A seventh line & space pattern formed so that a line pattern and a space between lines repeat, and a line pattern consisting of n conductors of the third line & space pattern and the sixth line pattern. A line pattern consisting of n conductors connected to a line pattern consisting of n conductors of the line & space pattern and an eighth line & space pattern formed so that a space between lines is repeated, Each line pattern of the first line & space pattern and the fourth line & space pattern is terminated at a boundary position between the first area and the third area and within the third area, and the seventh pattern Each line pattern of the line & space pattern and the eighth line & space pattern is Is disposed at an angle relative to the longitudinal direction of the pattern region, and the pitch P3 of the portion located obliquely, repeats division P1 <P3 <P2 der, the region of the 3 into two, One of the lines and the space pattern is an area where the line and space pattern is arranged in the oblique direction, and the other one is the line and space pattern which is arranged parallel to the length direction of the pattern of the first area. In the case of a region, the boundary between these two regions extends in an oblique direction with respect to the direction in which the n conductors in the first region are arranged .

  According to the present invention, it is possible to suppress the deterioration of the resolution and the depth of focus when forming a fine wiring pattern using photolithography in the connection region between the regions having different wiring pitches, and the wiring pattern may be disconnected or short-circuited. Thus, a semiconductor device which can reduce the performance and can be highly integrated can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Semiconductor Device Pattern Exposure Mask According to First Embodiment>
FIG. 1 is a plan view showing a part of a mask pattern formed on a semiconductor device pattern exposure mask according to the first embodiment of the present invention. FIG. 2 shows an enlarged view of a part of the mask pattern of FIG.

  The mask pattern shown in FIGS. 1 and 2 is a pattern exposure mask for a semiconductor memory, 11 is a first mask region corresponding to the memory cell array region, 12 is a second mask region corresponding to the peripheral circuit region, 13 Indicates a third mask region corresponding to a boundary region (connection region) between the memory cell array region and the peripheral circuit region. A hatched portion indicates a light shielding portion (light shielding body pattern), and a white background portion indicates a light transmitting portion, which are respectively for transferring a line pattern and a space pattern onto a semiconductor substrate.

  In the first mask region 11, a first line pattern 111, a second line pattern 112, a third line pattern 113, and a fourth line pattern 114 each have a line width L, and an inter-line space S Are arranged in order (wiring pitch is L + S), and a first line & space pattern is formed so that these line patterns 111 to 114 are periodically repeated at least two sets or more.

  In the second mask region 12, a fifth line pattern 121 and a sixth line pattern 122 each having a line width L or more are arranged via a space S between lines (wiring pitch is 2 × (L + S)). And a second line & space pattern is formed in which these line patterns 121 and 122 are arranged so that at least two sets are periodically repeated.

  Each one end side of the first line pattern 111 and the third line pattern 113 of the line patterns 111 to 114 in the first mask region 11 is extended, and the seventh line pattern in the third mask region 13 is extended. It is connected to the fifth line pattern 121 and the sixth line pattern 122 in the second mask region 12 through 131 and the eighth line pattern 132.

  On the other hand, one end side of the second line pattern 112 and the fourth line pattern 114 of the line patterns 111 to 114 in the first mask region 11 is terminated in the third mask region 12. Yes. In this case, the second line pattern 112 is terminated at the boundary position between the first mask region 11 and the third mask region 13, and the fourth line pattern 114 is connected to the third mask region 13 and the second mask region 13. This is extended to the boundary position with the mask region 12 and terminated.

  That is, in the third mask region 13, the seventh line pattern 131 connected to the first line pattern 111 and the fifth line pattern 121 and the eighth line connected to the third line pattern 113 and the sixth line pattern 122 are provided. Are formed, and a third line & space pattern is formed so that at least two sets of the fifth and sixth line patterns are periodically repeated.

  Note that a third mask region and a second mask region (not shown) are also provided on the other end side of the first mask region 11 symmetrically with the third mask region 13 and the second mask region 12 shown in FIG. A mask area exists. The other end sides of the first line pattern 111 and the third line pattern 113 in the first mask region 11 are terminated in a third mask region (not shown). The other end sides of the second line pattern 112 and the fourth line pattern 114 in the first mask region 11 are extended, pass through the third mask region (not shown), and the second mask region (not shown). Connected to line pattern. In this way, all the line patterns 111 to 114 in the first mask region 11 are connected to the second mask region.

  Further, in the third mask region 13, the seventh line pattern 131 has a line width that changes stepwise in the middle of the length direction, and is closer to the fifth line pattern 121 than to the first line pattern 111. Is formed so that the line width is increased stepwise. Similarly, the line width of the eighth line pattern 132 changes stepwise in the length direction in the third mask region 13, and the sixth line pattern 122 side rather than the third line pattern 113 side. Is formed so that the line width is increased stepwise.

  The positions where the line widths of the seventh line pattern 131 and the eighth line pattern 132 change stepwise are S or more in the length direction from the boundary position between the third mask region 13 and the first mask region 11, In addition, the position is L or more in the length direction from the boundary position between the third mask region 13 and the second mask region 12.

  In this example, as a part of the seventh line pattern 131, the first line pattern 111 extends in the pattern length direction to the portion of the distance S into the third mask region 13 while maintaining the line width. At the distance S, the line width of the seventh line pattern 131 is increased. Similarly, as part of the eighth line pattern 132, the third line pattern 113 extends into the third mask region 13 in the pattern length direction up to the distance S while maintaining its line width. In the distance S portion, the line width of the eighth line pattern 132 is increased.

  Further, the fourth line pattern 114 in the first mask region 11 extends with the line width L in parallel with the seventh line pattern 131 and the eighth line pattern 132.

  Here, the characteristics of the semiconductor device pattern exposure mask according to the first embodiment are summarized as follows: (a) a mask substrate in which a line pattern is formed by a light shielding portion and a space pattern is formed by a light transmitting portion; (B) In the first region on the mask substrate, first, second, third, and fourth line patterns each having a line width L are formed so as to be sequentially arranged via the inter-line space S. (C) In the second region on the mask substrate, the fifth and sixth line patterns each having a line width L or more are arranged in order through the inter-line space S or more. A second line and space pattern formed in the above manner; and (d) a third region existing between the first region and the second region on the mask substrate. And a third line pattern formed of a light shield connected to the fifth line pattern and an eighth line pattern formed of a light shield connected to the third line pattern and the sixth line pattern. Line & space pattern. And (e) the second line pattern is terminated at a boundary position between the first region and the third region, and the fourth line pattern includes the third region and the second region. (F) The seventh line pattern has a line width that changes in the middle of the length direction in the third region, and is more than the first line pattern side. The fifth line pattern side is formed so that the line width is thicker. (G) The eighth line pattern has a line width that changes in the middle of the length direction in the third region. The line width on the sixth line pattern side is larger than that on the third line pattern side, and (h) at least two sets of the line and space patterns are respectively provided in the corresponding regions. Arranged to repeat periodically It has been.

  Note that the position where the line widths of the seventh line pattern 131 and the eighth line pattern 132 change stepwise may be larger than S from the boundary position between the third mask region 13 and the first mask region 11. However, if the size is too large, the area occupied by the pattern increases, which increases the cost of the semiconductor device to be manufactured, which is not desirable. Therefore, it is appropriate that the distance of this portion is S.

  In the mask pattern described above, the minimum space on the mask is S, and it is desirable that the minimum space S on the mask is matched with the minimum space S of the line & space pattern. The reason will be described below.

  In the mask manufacturing process, the mask pattern may differ from the desired one due to dust or the like. Therefore, after forming a pattern on the mask, it is necessary to inspect for defects. Since the defect inspection is performed by an inspection apparatus using light such as a laser microscope, the size of the pattern that can be inspected is limited by the wavelength of the light source of the inspection apparatus. In order to perform the defect inspection completely, the dimension of the pattern needs to be a certain large value.

  In a mask for simultaneously forming a memory cell array region and a peripheral circuit region, a pattern with the smallest dimension existing in a certain mask generally corresponds to a pattern in the memory cell array region. Therefore, if the wiring line widths and inter-wiring spaces of all patterns in the mask are matched with the wiring line widths and inter-wiring spaces in the memory cell array region, it is possible to completely inspect defects in the mask. become.

  Further, after forming the gate lines and wirings of the semiconductor memory, the pattern portion corresponding to the space between the lines of the mask is filled later with an interlayer insulating film. At this time, the space between the gate lines and between the wirings is too small. Then, there is a possibility that the interlayer insulating film cannot be embedded in this portion. Then, foreign matter remains in this portion, which may cause a malfunction of the memory. In this way, in order to completely fill the interlayer insulating film, it is desirable that the space for the gate line and the wiring is matched with the minimum space in the memory cell array region.

  In photolithography, reduction projection exposure is generally used, and therefore, the dimension of the mask pattern is 4 times or 5 times the dimension of the resist pattern formed on the semiconductor substrate. That is, for example, the size of a mask for forming a resist pattern of 0.15 μm is 0.6 μm, 0.75 μm, or the like. Hereinafter, for simplification of description, the mask pattern has the same dimensions as the resist pattern.

<Semiconductor Device According to First Embodiment>
FIG. 3 shows a result obtained by optical simulation of a resist pattern obtained by exposing a photoresist on a semiconductor device using the mask pattern of FIG.

  Here, the line width and inter-line space of the line pattern corresponding to the line pattern of the mask are both 0.15 μm on the semiconductor substrate, the light source wavelength λ = 248 nm, KrF excimer laser, aperture ratio NA = 0.6, coherent A halftone phase shift with a coefficient of σ = 0.75, a ring zone that covers the central part of the light source by about two-thirds of the total area of the light source, and a 6% transmittance and 180 ° phase rotation for the shading part. This is calculated when a mask is used.

  In actual exposure, it is necessary to take into account the focus deviation due to the difference in the stage height of the exposure apparatus, the step due to the warpage of the semiconductor substrate, the step on the substrate, etc. The focus deviation is 0.4 μm. It is calculated as.

  Under the above conditions, the light intensity distribution on the semiconductor substrate is obtained by optical simulation, and the distribution of the equal intensity is shown in FIG. 3. The three lines in the figure have the wiring dimensions of 0.15 μm as intended. And the resist pattern at light intensity of +/− 10% from that.

  The resist pattern shown in FIG. 3 is formed corresponding to the mask pattern shown in FIG. 1, and there is no disconnection or short circuit of the wiring, and the line width is extremely narrow or the space is extremely narrow. Also not seen. Compared with the conventional resist pattern shown in FIG. 21, since the distance between the terminal portion of the wiring and the portion where the line width of the wiring changes is appropriately separated, it is affected by the influence of the diffracted light generated in such a portion. It can be seen that defects are less likely to occur in adjacent wiring patterns. Therefore, even when pattern exposure is actually performed on the semiconductor substrate using the mask pattern of FIG. 1, it is expected that a sufficient process margin can be secured and a good wiring pattern can be obtained.

  Here, the characteristics of the pattern of the semiconductor device according to the first embodiment formed using the mask pattern of FIG. 1 are summarized as follows: (a) In each of the first regions on the semiconductor substrate, the line width L is A first line & space pattern formed such that first, second, third, and fourth line patterns made of a conductive material are sequentially arranged via inter-line spaces S, and (b) on a semiconductor substrate In the second region, the second line & space pattern formed so that the fifth and sixth line patterns made of conductors each having a line width L or more are arranged in order via the inter-line spaces S or more, respectively. And (c) a third region existing between the first region and the second region on the semiconductor substrate, and made of a conductor connected to the first line pattern and the fifth line pattern. First And comprises a third line and space pattern eighth line pattern composed of a line pattern and the third conductor and the line pattern connected to the line pattern of the sixth was formed. And (d) the second line pattern is terminated at a boundary position between the first region and the third region, and the fourth line pattern includes the third region and the second region. (E) In the seventh line pattern, the line width changes stepwise in the length direction in the third region, and the first line pattern The fifth line pattern side is formed so that the line width is thicker stepwise than the side, and (f) the eighth line pattern is halfway in the length direction in the third region. The line width is changed stepwise, and the line width is formed to be thicker on the sixth line pattern side than on the third line pattern side, and (g) each line & Space pattern around at least 2 sets in each corresponding area It is arranged so as repeated manner.

<Method for Manufacturing Semiconductor Device According to First Embodiment>
Next, a method for forming a wiring pattern by transferring a pattern to a photoresist on a semiconductor substrate using the mask of FIG. 1 will be briefly described.

  First, a photoresist is applied on a conductor film (metal film or semiconductor film) deposited on a semiconductor substrate, and pattern exposure is performed on the photoresist by photolithography using the mask of FIG. Next, a part of the exposed photoresist is removed, and the exposed portion of the conductor film is removed by etching to perform patterning. At this time, an ordinary illumination method may be used for the exposure step, but a modified illumination method may also be used. It is also possible to use a halftone phase shift mask in which each light shielding portion of the mask of FIG. 1 is changed to a translucent material that changes the phase.

<Modification of Mask, Semiconductor Device, and Manufacturing Method Therefor>
As a modification of the mask according to the first embodiment, an inversion mask in which the light shielding portion and the light transmitting portion in the line & space pattern in the mask according to the first embodiment are reversed may be configured.

  Next, a method for forming a wiring pattern by transferring a pattern to a photoresist on a semiconductor substrate using this inversion mask will be briefly described.

  First, a photoresist is applied on an insulating film on a semiconductor substrate, and pattern exposure is performed on the photoresist by photolithography using the inversion mask. Next, a part of the exposed photoresist is peeled off, and the exposed portion of the insulating film is removed by etching to form a wiring formation groove. Thereafter, a conductor is embedded in the wiring forming groove. At this time, an ordinary illumination method may be used for the exposure step, but a modified illumination method may also be used. It is also possible to use a halftone phase shift mask in which each light shielding portion of the reversal mask is changed to a semitransparent material that changes the phase.

<Mask according to Second Embodiment>
FIG. 4 is a plan view showing a part of a mask pattern formed on a semiconductor device pattern exposure mask according to the second embodiment of the present invention. FIG. 5 shows an enlarged view of a part of the mask pattern shown in FIG.

  The mask pattern shown in FIGS. 4 and 5 is different from the mask pattern according to the first embodiment described above with reference to FIGS. 1 and 2. The position of the line pattern 121 is slightly shifted downward in the drawing, and as a result, the seventh line pattern 131a is bent stepwise in the third mask region 13, and (2) the second In the second mask region 12, the position of the sixth line pattern 122 is slightly shifted upward (the direction opposite to the shift direction of the fifth line pattern 121) (the fifth line pattern 121 and As a result, the eighth line pattern 132a is bent stepwise in the third mask region 13, and the other is the same. The same reference numerals are given.

  That is, in the third mask region 13, the seventh line pattern 131 a has a line width that changes stepwise in the length direction, and is closer to the fifth line pattern 121 a side than the first line pattern 111 side. The line width is formed to be thicker in a step shape. Similarly, in the eighth line pattern 132a, the line width changes stepwise in the length direction in the third mask region 13, and the sixth line pattern 122a side rather than the third line pattern 113 side. Is formed so that the line width is increased stepwise.

  The bending directions of the seventh line pattern 131a and the eighth line pattern 132a are directions close to each other. Further, the line width of the bent portion of the wiring is L. The line width of this portion may be larger than L, but it is not desirable because it leads to an increase in the occupied area, and L is appropriate.

  In addition, the fourth line pattern 114 in the first mask region 11 extends with the line width L parallel to the seventh line pattern 131a and the eighth line pattern 132a. The pitch of the seventh line pattern 131a, the eighth line pattern 132a, and the fourth line pattern 114 is 2 × (L + S), and the space between the lines is S. I do not care.

  The positions at which the line widths of the seventh line pattern 131a and the eighth line pattern 132a are bent stepwise are S in the length direction from the boundary position between the third mask region 13 and the first mask region 11. The position is equal to or more than L (L in this example) in the length direction from the boundary position between the third mask region 13 and the second mask region 12 as described above.

  In this example, the seventh line pattern 131a and the eighth line pattern 132a have a pattern length into the third mask region 13 while maintaining the line width of the first line pattern 111 and the third line pattern 113. It extends in the vertical direction to a distance S, and the line width is widened in this portion.

  The position where the line widths of the seventh line pattern 131a and the eighth line pattern 132a are bent stepwise is larger than S from the boundary position between the third mask region 13 and the first mask region 11. However, if the size is too large, the area occupied by the pattern increases, which increases the cost of the semiconductor device to be manufactured, which is not desirable. Therefore, it is appropriate that the distance of this portion is S.

  In the mask pattern described above, the minimum space on the mask is S, and it is desirable that the minimum space S on the mask is matched with the minimum space S of the line & space pattern. The reason is as described above in the first embodiment.

<Semiconductor Device According to Second Embodiment>
FIG. 6 shows a result obtained by optical simulation of a resist pattern obtained by exposing a photoresist on a semiconductor device using the mask pattern of FIG. In this simulation, the conditions of the light source are the same as those in the first embodiment.

  The resist pattern shown in FIG. 6 is formed corresponding to the mask pattern shown in FIG. 4, and there is no disconnection or short circuit of the wiring, and there is no part where the line width is extremely narrow or the space is extremely narrow. can not see. Therefore, even when pattern exposure is actually performed on a semiconductor substrate, it is expected that a sufficient process margin can be secured and a good wiring pattern can be obtained.

  Note that the method of manufacturing the semiconductor device according to the second embodiment may be performed in accordance with the first embodiment described above, and may be manufactured using the reversal mask of the mask pattern of FIG. is there.

<Mask according to Third Embodiment>
FIG. 7 is a plan view showing a part of a mask pattern formed on a semiconductor device pattern exposure mask according to the third embodiment of the present invention. FIG. 8 shows an enlarged view of a part of the mask pattern of FIG.

  The mask pattern shown in FIGS. 7 and 8 is such that the end position of the fourth line pattern 114 is the seventh line compared to the mask pattern according to the second embodiment described above with reference to FIGS. Since the pattern 131a or the eighth line pattern 132a is closer to the second region 12 than the bent portion of the pattern 131a or the eighth line pattern 132a, and the others are the same, the same reference numerals as those in FIGS.

  In other words, the end position of the fourth line pattern 114 is the boundary position between the third region 13 and the second region 12, and the seventh line is at a position L or more in the length direction from this boundary position. One end side in the line width direction of the pattern 131a and the eighth line pattern 132a is bent in a step shape, and the seventh line pattern 131a and the eighth line pattern 132a are further bent in the length direction from the bent position. The other end side in the line width direction is bent stepwise.

<Semiconductor Device According to Third Embodiment>
FIG. 9 shows a result obtained by optical simulation of a resist pattern obtained by exposing a photoresist on a semiconductor device using the mask pattern of FIG. In this simulation, the conditions of the light source are the same as those in the first embodiment.

  The resist pattern shown in FIG. 9 is formed corresponding to the mask pattern of FIG. 7, and there is no disconnection or short-circuiting of the wiring, and there are portions where the line width is extremely thin or spaces are extremely narrow. can not see. Therefore, even when pattern exposure is actually performed on a semiconductor substrate, it is expected that a sufficient process margin can be secured and a good wiring pattern can be obtained.

  In addition, when the mask of FIG. 7 is used, compared to the case of using the mask of FIG. 4 according to the second embodiment, the diffracted light generated near the terminal portion of the fourth line pattern 113 and the mask Interference with the diffracted light generated near the bent portion of the seventh line pattern 131a and the bent portion of the eighth line pattern 132a can be reduced, and the effect of preventing disconnection or short-circuiting of the wiring can be further enhanced. Can do.

  The semiconductor device manufacturing method according to the third embodiment may be performed according to the first embodiment described above, and can also be manufactured using the reversal mask of the mask pattern of FIG. is there.

<Mask according to Fourth Embodiment>
FIG. 10 is a plan view showing a part of a mask pattern formed on a semiconductor device pattern exposure mask according to the fourth embodiment of the present invention.

  The mask pattern shown in FIG. 10 is different from the mask pattern according to the third embodiment described above with reference to FIGS. 7 and 8, and the fifth line pattern 121b and the sixth line pattern in the second region 12. The line width of 122b changes stepwise at and near the boundary position between the third region 13 and the second region 12, and stepwise in the direction in which the fifth line pattern 121b and the sixth line pattern 122b approach each other. 1 are the same as those in FIG. 1 and FIG.

  In other words, the auxiliary pattern is added to one end side in the line width direction of the fifth line pattern 121b and the sixth line pattern 122b having a large wiring pitch of 2 × (L + S).

<Semiconductor Device According to Fourth Embodiment>
FIG. 11 shows a result obtained by optical simulation of a resist pattern obtained by exposing a photoresist on a semiconductor device using the mask pattern of FIG. In this simulation, the conditions of the light source are the same as those in the first embodiment.

  The resist pattern shown in FIG. 11 is formed corresponding to the mask pattern shown in FIG. 10, and there is no disconnection or short circuit of the wiring, and there are portions where the line width is extremely narrow and spaces are extremely narrow. can not see. Therefore, even when pattern exposure is actually performed on a semiconductor substrate, it is expected that a sufficient process margin can be secured and a good wiring pattern can be obtained.

  Moreover, when the mask of FIG. 10 is used, the fifth line pattern 121b and the sixth line pattern 122b in the second region 12 are compared with the case of using the mask of FIG. 7 according to the third embodiment. The line width of the third region 13 and the second region 12 is widened stepwise at and near the boundary position between the third region 13 and the second region 12, and the diffracted light generated in this vicinity and the end of the fourth line pattern 114 The interference of the generated diffracted light can be reduced, and the effect of preventing the disconnection or short circuit of the wiring can be further enhanced.

  Note that the manufacturing method of the semiconductor device according to the fourth embodiment may be performed according to the first embodiment described above, and can also be manufactured using the reversal mask of the mask pattern of FIG. is there.

<Modification of the first to fourth embodiments>
In the first to fourth embodiments, the first line & space pattern in the first region 11 of the mask is such that line patterns having a line width L or more are arranged in order via the inter-space S. In the second line & space pattern formed in the second region 12, the line pattern having the line width L or more is formed so as to be arranged in order via the inter-space S or more.

  As a modification of the first to fourth embodiments, the first line & space pattern is formed so that the line patterns are arranged in order at a pitch P, and the second line & space pattern is the pitch of the line pattern. Even when they are formed in order of 2 × P or more, substantially the same effect as in the first to fourth embodiments can be obtained.

  Moreover, it is also possible to manufacture using the reversal mask of the mask pattern according to this modification.

<Mask according to Fifth Embodiment>
The mask according to the fifth embodiment is a pattern exposure mask for a NAND flash memory which is a kind of EEPROM.

  Here, the NAND flash memory will be briefly described. An EEPROM, which is a kind of nonvolatile semiconductor memory device, normally uses a MOS structure memory cell (EEPROM cell) in which a floating gate and a control gate are stacked, and is electrically rewritable. A NAND flash memory has an array of NAND cells in which a plurality of EEPROM cells are connected in series, and is suitable for high integration.

  FIG. 12 shows an equivalent circuit by taking out two blocks arranged in the word line direction in the memory cell array of the NAND flash memory.

  Eight EEPROM cells 101 to 108 and 201 to 208 are connected in series to form NAND cells, respectively. The drain side of these NAND cells is connected to the bit line BL1 through the drain side selection transistors 1D and 2D. The source side is connected to the source line SL via the source side selection transistors 1S and 2S.

  A memory cell array is composed of a plurality of blocks each including one drain side select transistor, one NAND cell, and one source side select transistor. Note that the number of EEPROM cells constituting the NAND cell is not limited to eight, and may be any number such as four, sixteen, thirty-two, and the like.

  FIG. 13 shows a plane pattern obtained by taking out three blocks arranged in the word line direction in the memory cell array of the NAND flash memory.

  The control gate electrodes of the NAND cells are connected to the word lines WL1 to WL8, and the word lines WL1 to WL8 are commonly connected to the control gate electrodes of adjacent NAND cells. The gate electrodes of the adjacent drain side select transistors 1D and 2D are commonly connected to the drain side select gate line SG (D), and the gate electrodes of the adjacent source side select transistors 1S and 2S are commonly connected to the source side select gate line. Connected to SG (S).

  FIG. 14 is a plan view showing a part of a mask pattern formed on a semiconductor device pattern exposure mask according to the fifth embodiment of the present invention. FIG. 15 shows an enlarged view of a part of the mask pattern of FIG.

  In the mask patterns shown in FIGS. 14 and 15, 11 is a first mask region corresponding to the memory cell array region of the NAND flash memory, 12 is a second mask region corresponding to the peripheral circuit region, and 13 is a memory cell array region. A third mask region corresponding to a boundary region (connection region) with the peripheral circuit region is shown. A hatched portion indicates a light shielding portion (light shielding body pattern), and a white background portion indicates a light transmitting portion, which are respectively for transferring a line pattern and a space pattern onto a semiconductor substrate.

  In the first mask region 11, a first line pattern 111 to an eighth line pattern 118 each having a line width L are arranged in order via a space S between lines (wiring pitch is L + S), and A first line & space pattern is formed in which at least two sets of the line patterns 111 to 118 are periodically repeated. In this case, the line patterns 111 to 118 correspond to the eight word lines WL1 to WL8 of the NAND cell, and the NAND cell drain-side selection gate is interposed between each set of the line patterns 111 to 118. Line patterns 110 and 119 corresponding to the line SG (D) and the source side selection gate line SG (S) are arranged and formed. One end side of the line pattern 110 corresponding to the drain side selection gate line is extended with the line width and connected to the line pattern 120 in the second mask region 12 through the third mask region 13.

  In the second mask region 12, the ninth line pattern 121 to the twelfth line pattern 124 each having a line width L or more are arranged via the inter-line space S or more (the wiring pitch is 2 × (L + S)). In addition, a second line & space pattern is formed in which the line patterns 121 to 124 are arranged so that at least two sets are periodically repeated. In this case, a line pattern 120 corresponding to the drain-side selection gate line is disposed between each set of the line patterns 121 to 124.

  For example, one end side of even-numbered second, fourth, sixth, and eighth line patterns 112, 114, 116, and 118 among the line patterns 111 to 118 in the first mask region 11 is extended. The line patterns 121 to 124 in the second mask region 12 are connected through the third mask region 13.

  On the other hand, one end side of each of the remaining odd-numbered first, third, fifth, and seventh line patterns 111, 113, 115, and 117 among the line patterns 111 to 118 in the first mask region 11. Are terminated in the third mask region 13. In this case, the first line pattern 111 is terminated at the boundary position between the first mask region 11 and the third mask region 13, and the third line pattern 113 and the seventh line pattern 117 are the lines. The fifth line pattern 115 extends to the boundary position between the third mask region 13 and the second mask region 12 and extends at the intermediate position of the third mask region 13. It is extended and terminated.

  In other words, four line patterns (first, third, fifth, and seventh line patterns 111, 113, 115) that are not connected to the second line & space pattern among the first line & space patterns. 117) terminates at the boundary position between the first region 11 and the third region 13, at the boundary position between the third region 13 and the second region 12, or at any position within the third region 13. In addition, the end position is closer to the second region 12 as it is located at the center of the first line & space pattern arrangement.

  That is, in the third mask region 13, the thirteenth line pattern 131 connected to the second line pattern 112 and the ninth line pattern 121, and the fourteenth line connected to the fourth line pattern 114 and the tenth line pattern 122. Line pattern 132, 15th line pattern 133 connected to 6th line pattern 116 and 11th line pattern 123, and 16th line pattern 134 connected to 8th line pattern 118 and 12th line pattern 124. And the 3rd line & space pattern arrange | positioned so that the said line patterns 131-134 may repeat at least 2 sets or more periodically may be formed. In this case, the third, fifth, and seventh line patterns 111, 113, 115, and 117 in the first mask region 11 are extended into the third mask region 13. The arrangement order of the line patterns is 131, 113, 132, 115, 133, 117, 134. Further, a line pattern 130 corresponding to the drain side selection gate line is disposed between the sets of the line patterns 131 to 134.

  The line patterns 131 to 134 have a line width that changes stepwise in the middle of the length direction in the third region 13 and bends in a step shape, and is second than the first line & space pattern side. The line & space pattern side is formed so that the line width increases stepwise, and the position where the line width changes stepwise is located at the center of the third line & space pattern array The closer to the second region 12 is, the closer it is.

  In this case, the direction in which the thirteenth line pattern 131 bends is in a direction approaching the first line pattern 111, and the length of the bent portion is L or more (L in terms of suppressing the occupied area of the pattern). The position where one end in the line width direction changes stepwise is greater than or equal to S in the length direction from the end position of the first line pattern 111 (in terms of suppressing the occupied area of the pattern). S is suitable).

  The end position of the third line pattern 113 is S or more in the length direction from the position where the other end in the line width direction of the thirteenth line pattern 131 changes stepwise (in terms of suppressing the occupied area of the pattern). S is suitable).

  In addition, the direction in which the fourteenth line pattern 132 is bent is a direction approaching the third line pattern 113, and the length of the bent portion is L or more (from the viewpoint of suppressing the area occupied by the pattern, L is set. The position where one end in the line width direction changes stepwise is greater than or equal to S in the length direction from the end position of the third line pattern 113 (in terms of suppressing the occupied area of the pattern). It is appropriate that

  The end position of the fifth line pattern 115 is at least L in the length direction from the position where the other end in the line width direction of the fourteenth line pattern 132 changes stepwise (in terms of suppressing the occupied area of the pattern). L is suitable).

  The direction in which the fifteenth line pattern 133 bends is a direction approaching the seventh line pattern 117, and the length of the bent portion is not less than L (from the viewpoint of suppressing the area occupied by the pattern, it should be L). The position where one end in the line width direction changes stepwise is greater than or equal to S in the length direction from the end position of the third line pattern 113 (in terms of suppressing the occupied area of the pattern). It is appropriate that That is, the position where the fifteenth line pattern 133 is bent is on the same line as the position where the fourteenth line pattern 132 is bent.

  The end position of the seventh line pattern 117 is S or more in the length direction from the position where the other end in the line width direction of the thirteenth line pattern 131 changes stepwise (in terms of suppressing the occupied area of the pattern). S is suitable). That is, the end position of the seventh line pattern 117 is on the same line as the end position of the third line pattern 113.

  The direction in which the sixteenth line pattern 134 is bent is a direction away from the seventh line pattern 117, and the position where one end in the line width direction changes stepwise is the first line pattern 134. 111 is the position of S or more in the length direction from the terminal position (S is suitable from the point of suppressing the occupied area of the pattern), and the length of the bent portion is L or more (suppressing the occupied area of the pattern) From this point, it is appropriate to set L). That is, the position where the sixteenth line pattern 134 is bent is on the same line as the position where the thirteenth line pattern 131 is bent.

  In the mask pattern described above, the minimum space on the mask is S, and it is desirable that the minimum space S on the mask is matched with the minimum space S of the line & space pattern. The reason is as described above in the first embodiment.

  Note that a third mask region and a second mask region (not shown) are also provided on the other end side of the first mask region 11 symmetrically with the third mask region 13 and the second mask region 12 shown in FIG. A mask area exists. The other end sides of the second, fourth, sixth, and eighth line patterns 112, 114, 116, and 118 in the first mask region 11 are terminated in the third mask region 13 (not shown). .

  The other end sides of the first, third, fifth, and seventh line patterns 111, 113, 115, and 117 in the first mask region 11 are extended so as to pass through the third mask region 13 (not shown). Then, it is connected to the line pattern of the second mask region 12 (not shown). In this way, all line patterns in the first mask region 11 are connected to the second mask region.

<Semiconductor Device According to Fifth Embodiment>
FIG. 16 shows a result obtained by optical simulation of a resist pattern obtained by exposing the photoresist on the NAND flash memory using the mask pattern of FIG. In this simulation, the conditions of the light source are the same as those in the first embodiment.

  The resist pattern shown in FIG. 16 is formed corresponding to the mask pattern shown in FIG. 14, and there is no disconnection or short circuit of the wiring, and there is an extremely narrow line width or an extremely narrow space. can not see. Therefore, even when pattern exposure is actually performed on a semiconductor substrate, it is expected that a sufficient process margin can be secured and a good wiring pattern can be obtained.

  Note that the semiconductor device manufacturing method according to the fifth embodiment may be performed according to the first embodiment described above, and can also be manufactured using the reversal mask of the mask pattern of FIG. is there.

<Mask According to Sixth Embodiment>
FIG. 17 is a plan view showing a part of a mask pattern formed on a semiconductor device pattern exposure mask according to the sixth embodiment of the present invention.

  The mask pattern shown in FIG. 17 is a pattern exposure mask for a NAND flash memory, 11 is a first mask area in the memory cell array of the NAND flash memory, 12 is a second mask area corresponding to the peripheral circuit area, Reference numeral 13 denotes a third mask region corresponding to a boundary region (connection region) between the memory cell array region and the peripheral circuit region.

  In the memory cell array of the NAND type flash memory, as described above with reference to the equivalent circuit shown in FIG. 12, for example, a drain-side selection transistor 1D, a NAND cell in which eight EEPROM cells 101 to 108 are connected in series, A memory cell array is composed of a plurality of blocks each including a combination of the source side select transistors 1S. Here, an area corresponding to four blocks arranged in the bit line direction is shown.

  The first mask region 11 includes a light shielding member for forming word lines WL1 to WL8 of NAND cells of the first block, the second block, the third block, and the fourth block in the memory cell array region. There are at least four (first, second, third, fourth) line & space patterns formed so that eight line patterns 111 to 118 are sequentially arranged at a pitch P1 through a space S between lines. Is arranged.

  In the second mask region 12, fifth and sixth lines & 6 are formed so that eight line patterns 121 to 128 each made of a light shielding element are repeated at a pitch of 2 × P1 or more through a space between lines. Space pattern is arranged.

  In the third mask region 13, the seventh line & space pattern and the eighth line & space pattern are repeated. The seventh line & space pattern includes eight line patterns 111 to 118 of the second line & space pattern in the first mask region 11 and 8 of the fifth line & space pattern in the second mask region 12. The eight line patterns 131 to 138 and the inter-line space pattern, each of which is formed of a light shielding body, are connected to the line patterns 121 to 128, respectively. The eighth line & space pattern is composed of a light shielding body connected to the eight line patterns 111 to 118 of the third line & space pattern and the eight line patterns 121 to 128 of the sixth line & space pattern. Eight line patterns 131 to 138 and an inter-line space pattern are formed to repeat.

  The line patterns 111 to 118 of the first line & space pattern and the fourth line & space pattern in the first mask area 11 are terminated at the boundary position between the first area 11 and the third area 13. Yes.

  Each part of the line patterns 131 to 138 of the seventh line & space pattern and the eighth line & space pattern in the third mask region 13 is in the length direction of the pattern of the first mask region 11. The pitch P2 of the diagonally arranged portions is larger than the pitch P1 of the line patterns 111 to 118 in the first mask region 11, and the line patterns 121 to 12 in the second mask region 12 are arranged. It is smaller than 128 pitch 2 × P1. That is, P1 <P2 <2 × P1.

  The first, second, third, and fourth line & space patterns are arranged so as to periodically repeat at least two or more sets in the first mask region 11, and the fifth and sixth line & space patterns are arranged. Are arranged so as to periodically repeat at least two sets in the second mask region 12, and the seventh and eighth line & space patterns are arranged so as to repeat periodically in at least two sets in the third mask region 13. Has been.

  Note that a third mask region and a second mask (not shown) are also provided on the other end side of the first mask region 11 symmetrically with the third mask region 13 and the second mask region 12 shown in FIG. A mask area exists. The other end sides of the line patterns 111 to 118 (gate lines of the memory cells in the second and third blocks) in the second and third lines and spaces in the first mask region are not shown. Terminated in the third mask region. The other end sides of the line patterns 111 to 118 (gate lines of the memory cells in the first and fourth blocks) in the first and fourth lines and spaces in the first mask region are extended. The line pattern of the second mask region (not shown) is connected through the third mask region (not shown). In this way, all the line patterns 111 to 118 in the first mask region 11 are connected to the second mask region.

  In FIG. 17, 110 is a line pattern corresponding to the drain side select gate line SG (D) of the NAND cell block, and 119 is a line pattern corresponding to the source side select gate line SG (S).

<Semiconductor Device According to Sixth Embodiment>
FIG. 18 shows a result obtained by optical simulation of a resist pattern obtained by exposing the photoresist on the NAND flash memory using the mask pattern of FIG. In this simulation, the conditions of the light source are the same as those in the first embodiment.

  The resist pattern shown in FIG. 18 is formed corresponding to the mask pattern shown in FIG. 17, and there is no disconnection or short-circuiting of the wiring, and there are portions where the line width is extremely narrow or spaces are extremely narrow. can not see. Therefore, even when pattern exposure is actually performed on a semiconductor substrate, it is expected that a sufficient process margin can be secured and a good wiring pattern can be obtained.

  Note that the manufacturing method of the semiconductor device according to the sixth embodiment may be performed according to the first embodiment described above, and can also be manufactured using the reversal mask of the mask pattern of FIG. is there.

The top view which shows a part of mask pattern currently formed in the mask for semiconductor device pattern exposure which concerns on the 1st Embodiment of this invention. FIG. 2 is an enlarged plan view showing a part of the mask pattern of FIG. 1 taken out and enlarged. The figure which shows the result of having calculated | required the resist pattern obtained by exposing the photoresist on a semiconductor device using the mask pattern of FIG. 1 by optical simulation. The top view which shows a part of mask pattern currently formed in the mask for semiconductor device pattern exposure which concerns on the 2nd Embodiment of this invention. FIG. 5 is an enlarged plan view showing a part of the mask pattern in FIG. 4 taken out. The figure which shows the result of having calculated | required the resist pattern obtained by exposing the photoresist on a semiconductor device using the mask pattern of FIG. 4 by optical simulation. The top view which shows a part of mask pattern currently formed in the mask for semiconductor device pattern exposure which concerns on the 3rd Embodiment of this invention. FIG. 8 is an enlarged plan view showing a part of the mask pattern in FIG. The figure which shows the result of having calculated | required the resist pattern obtained by exposing the photoresist on a semiconductor device using the mask pattern of FIG. 7 by optical simulation. The top view which shows a part of mask pattern currently formed in the mask for semiconductor device pattern exposure which concerns on the 4th Embodiment of this invention. The figure which shows the result of having calculated | required the resist pattern obtained by exposing the photoresist on a semiconductor device using the mask pattern of FIG. 10 by optical simulation. The figure which shows the equivalent circuit which takes out 2 blocks arranged in the word line direction in the memory cell array of NAND type flash memory in order to demonstrate the 5th Embodiment of this invention. FIG. 13 is a diagram showing a plane pattern of three blocks arranged in the word line direction in the memory cell array of the NAND flash memory of FIG. 12. The top view which shows a part of mask pattern currently formed in the mask for semiconductor device pattern exposure which concerns on the 5th Embodiment of this invention. FIG. 15 is a plan view showing a part of the mask pattern in FIG. 14 taken out and enlarged. The figure which shows the result of having calculated | required the resist pattern obtained by exposing the photoresist on NAND type flash memory using the mask pattern of FIG. 14 by optical simulation. The top view which shows a part of mask pattern currently formed in the mask for semiconductor device pattern exposure which concerns on the 6th Embodiment of this invention. The figure which shows the result of having calculated | required the resist pattern obtained by exposing to the photoresist on NAND type flash memory by the optical simulation using the mask pattern of FIG. The figure which shows the general pattern arrangement | positioning of a semiconductor memory. FIG. 20 is a diagram showing a pattern exposure mask on which a wiring pattern for connecting the memory cell array region and the peripheral circuit region in FIG. 19 is formed. The figure which shows the result of having calculated | required by the simulation the resist pattern obtained when it exposes to the resist on a semiconductor substrate using the mask for pattern exposure in which the wiring pattern shown in FIG. 20 was formed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... 1st mask area | region, 12 ... 2nd mask area | region, 13 ... 3rd mask area | region, 111-114 ... 1st-4th line pattern, 121 ... 5th line pattern, 122 ... 6th Line pattern, 131 ... seventh line pattern, 132 ... eighth line pattern, L ... line width, S ... space between lines.

Claims (8)

A semiconductor substrate;
In the first region on the semiconductor substrate, a first line and space formed such that a plurality of (n) line patterns made of a conductor having a line width L are arranged in order via inter-line spaces S, respectively. With patterns,
N made of a conductor having a line width L or more in the second region on the semiconductor substrate.
/ A second line & space pattern formed so that two line patterns repeat through a space between lines;
A third region existing between the first region and the second region on the semiconductor substrate, and n / 2 line patterns every other one of the first line and space patterns; A third line & space pattern formed with a line pattern made of n / 2 conductors connected to the n / 2 line patterns of the second line & space pattern;
In each line pattern of the Ren'nara not n / 2 present in the second line and space pattern of the first line and space pattern, the boundary position between the first and third regions
Terminate at the first line pattern to terminate and the boundary position between the third region and the second region.
Between the second line pattern and the first line pattern and the second line pattern
A third line pattern positioned and terminating in the third region , wherein each line pattern of the third line & space pattern includes two adjacent first and third line patterns;
Or the end of the second or third line pattern or the third line pattern.
The line width is changed in the middle of the third region between the positions, and the second region side is formed to be thicker on the second region side than on the first region side. A semiconductor device characterized by comprising: A semiconductor substrate;
In the first region on the semiconductor substrate, a plurality (n) of conductors having a line width L
The first line patterns are formed so that the line patterns are arranged in order via the inter-line spaces S.
Line & space pattern,
N made of a conductor having a line width L or more in the second region on the semiconductor substrate.
/ Second line formed so that two line patterns repeat through the space between lines
With in & space pattern,
A third region existing between the first region and the second region on the semiconductor substrate;
Every other n / 2 line patterns of the first line & space pattern and the first
N / 2 conductive lines connected to the n / 2 line pattern of two line & space patterns
A third line & space pattern formed with a body line pattern,
Of the first line & space pattern, the second line & space pattern
Each n / 2 line pattern that is not connected is a boundary position between the first region and the third region.
A line pattern that terminates and a line that terminates at the boundary between the third region and the second region
Patterns are alternately arranged, and each line pattern of the third line & space pattern is arranged.
In the turn, the line width changes in the middle of the third region in the length direction, and the first region side
Further, the second region side is formed to have a thicker line width.
Semiconductor device . The third line pattern between the first line pattern and the second line pattern
Multiple
The third line pattern includes the first line pattern to the second line pattern.
The end position approaches the second region as it approaches
Each line pattern of the third line & space pattern positioned between the third line patterns is changed from the first line pattern to the second line pattern.
The semiconductor device according to claim 1, wherein a position where the line width changes is equal to or approaching the second region as the distance. In each line pattern of the third line & space pattern, the line width changes stepwise in the length direction in the third region, and the position where the line width changes stepwise is the third position. 3. The position of S in the length direction from a boundary position between the first region and the first region.
The semiconductor device described. 3. The semiconductor device according to claim 1, wherein the first region is a region where a memory cell array is formed, and the second region is a region where a memory cell peripheral circuit is formed. A semiconductor substrate;
In the first region on the semiconductor substrate, a plurality of (n) line patterns each made of a conductor are formed so as to be sequentially arranged at a pitch P1 through a first inter-line space. Third and fourth line & space patterns;
In the second region on the semiconductor substrate, the fifth and sixth lines are formed such that n line patterns each made of a conductor repeat at a pitch P2 larger than P1 through the second inter-line space. & Space pattern,
In a third region existing between the first region and the second region on the semiconductor substrate, a line pattern made of n conductors of the second line & space pattern and the fifth region A line pattern consisting of n conductors connected to a line pattern consisting of n conductors of a line & space pattern, a seventh line & space pattern formed such that a space between lines repeats, and the third A line pattern consisting of n conductors in a line & space pattern and a line pattern consisting of n conductors connected to a line pattern consisting of n conductors in the sixth line & space pattern and a space between lines are repeated. And an eighth line & space pattern formed as follows:
Each line pattern of the first line & space pattern and the fourth line & space pattern is terminated in a boundary position between the first area and the third area and in the third area,
A part of each of the line patterns of the seventh line & space pattern and the eighth line & space pattern is arranged obliquely with respect to the length direction of the pattern of the first region, and obliquely pitch of the portion located P3 is Ri P1 <P3 <P2 der,
The three regions are divided into two, one of which is the region where the line and space pattern is arranged in the oblique direction, and the other is the length of the pattern of the first region. When the region is arranged in the vertical direction, the boundary between these two regions extends obliquely with respect to the direction in which the n conductors in the first region are arranged. Semiconductor device. 7. The semiconductor device according to claim 6, wherein the first region is a region where a memory cell array is formed, and the second region is a region where a memory cell peripheral circuit is formed. The first region is a region where a memory cell array of a NAND flash memory is formed, and the second region is a region where a memory cell peripheral circuit is formed,
The n line patterns of the line & space pattern in the first region include a plurality of memory cells connected in series forming a unit block of the memory cell array and select transistors connected in series so as to sandwich the memory cells. 7. The semiconductor device according to claim 6 , wherein the semiconductor device is connected to each gate of the plurality of memory cells.

Images