JP4322950B2 - Photomask and method of manufacturing semiconductor device using the same - Google Patents

Description

  The present invention relates to a photomask in which an auxiliary pattern is formed adjacent to a pattern, and a method of manufacturing a semiconductor device using the photomask.

  As a method for forming a fine hole pattern with a photomask, in the conventional technique, an auxiliary pattern having the same shape as the main pattern is arranged around the main pattern to improve the resolution (FIG. 1 of Patent Document 1). ). However, consider a case where a photomask having a pattern sequence of minute hole patterns 401 as shown in FIG. When the auxiliary pattern 402 is added to the pattern row shown in FIG. 34, the result becomes as shown in FIG. However, in the mask pattern shown in FIG. 35, the resolution of the hole pattern 401 is insufficient and the lithography margin is small.

In addition, there is a technique for forming an auxiliary pattern adjacent to a pattern having periodicity between adjacent patterns (Patent Document 2). Consider that this auxiliary pattern is formed adjacent to a pattern having no periodicity between adjacent patterns. That is, the auxiliary pattern is arranged adjacent to the short direction of the rectangular pattern. Also in this case, the resolution of the rectangular pattern was insufficient and the lithography margin was small.
Japanese Patent Laid-Open No. 10-239827 Japanese Patent Laid-Open No. 7-140639

  An object of the present invention is to provide a photomask in which an auxiliary pattern is formed adjacent to a pattern in order to improve a lithography margin. Another object of the present invention is to provide a method of manufacturing a semiconductor device using this photomask.

According to an example of the present invention, a photomask on which a pattern for transferring to a substrate using an exposure apparatus is formed has a longitudinal direction surrounded by a light-shielding portion or a semitransparent film and a lateral direction perpendicular to the longitudinal direction. A rectangular main pattern having a periodicity and an auxiliary pattern surrounded by the light-shielding part or the semi-transparent film, and one end part in the longitudinal direction of the main pattern. is arranged near the lateral direction parallel to the length of the main pattern is longer than the length of the short side direction of the main pattern, it comprises a, an auxiliary pattern that is not transferred on the substrate, wherein The length of the auxiliary pattern in the direction parallel to the longitudinal direction of the main pattern (length converted to the dimension when transferred to the substrate) is 50 nm or less .

A method of manufacturing a semiconductor device according to an example of the present invention includes a step of preparing an exposure apparatus for transferring a pattern formed on a photomask to a positive resist film on a semiconductor substrate, and a step of preparing the photomask. The photomask is a main pattern having a longitudinal direction surrounded by a light-shielding portion or a semi-transparent film and a lateral direction perpendicular to the longitudinal direction, and is arranged without periodicity. A main pattern and an auxiliary pattern surrounded by the light-shielding part or the semi-transparent film, disposed near one end in the longitudinal direction of the main pattern, and the length in the direction parallel to the short direction of the main pattern is A step of providing an auxiliary pattern that is longer than the length of the main pattern in the lateral direction and is not transferred onto the substrate; and formed on the photomask using the exposure apparatus. It includes a step of transferring a turn to the positive resist film, and the longitudinal direction parallel to the length of the main pattern (the length in terms of dimensions when transferred to the substrate) of 50nm of the auxiliary pattern It is characterized by the following.

  According to the present invention, the lithography margin can be improved by arranging the auxiliary pattern adjacent to the main pattern.

  Embodiments of the present invention will be described below with reference to the drawings. However, as a matter of course, the present invention is not limited to the embodiments described below.

(First embodiment)
In the present embodiment, an example applied to the case where a photomask of a bit line contact (CB) layer of a NAND flash memory having holes that are continuous in a one-dimensional direction as a part of a pattern is projected and exposed will be described.

  FIG. 1 shows an outline of a NAND flash memory circuit.

  As shown in FIG. 1, each NAND flash memory is configured by connecting nonvolatile semiconductor memory cells M in series, and one end of the NAND flash memory is connected to a selection gate line SG (SG1, SG1 ′) via a selection transistor S. It is connected to the bit line BL. Each memory cell M is connected to a control gate line CG (CG1 to CG4, CG1 '). The other end (not shown) is connected to the common source line via a selection transistor connected to the selection gate line.

  FIG. 2 is a plan view of the NAND flash memory, and FIG. 3 is a cross-sectional view taken along the line II-II ′ of FIG.

  As shown in FIGS. 2 and 3, a p-type well 102 is formed on an n-type Si 101. An n-type diffusion layer 103 is formed in a part of the p-type well 102. The n-type diffusion layer 103 becomes the source and drain of the nonvolatile memory cell M. A tunnel insulating film 104 is formed on the channel region. A floating gate 105 is formed on the tunnel insulating film 104. An inter-gate insulating film 106 is formed on the floating gate 105. A control gate 107 is formed on the inter-gate insulating film 106. In the selection transistor S, a part of the inter-gate insulating film 106 is removed, and the floating gate 105 and the control gate 107 are electrically connected to form a selection gate SG.

  An interlayer insulating film 109 is formed on the Si substrate 101. A bit line contact hole 110 connected to the n-type diffusion layer 103 between the two select transistors S is formed in the interlayer insulating film 109. Bit line contacts 111 are formed in the bit line contact holes 110 and on the interlayer insulating film. A second interlayer insulating film 112 is formed on the bit line contact 111. A via plug 113 is formed in the hole formed in the second interlayer insulating film 112. A bit line 114 connected to the via plug 113 is formed on the second interlayer insulating film 112.

  As shown in FIG. 2, the long side dimension of the bit line plug hole greatly affects the chip size. The shorter the long side dimension of the bit line plug hole, the smaller the chip size, and the chip cost can be reduced. Therefore, it is important to improve the resolution of the bit line contact, control the size, and reduce the long side dimension.

  In the present embodiment, the mask design is performed so that the bit line contact holes having a short side length of 72.5 nm are arranged at a pitch of 145 nm. FIG. 4 is a diagram showing the configuration of the mask according to the first embodiment of the present invention. 4A is a plan view, and FIG. 4B is a cross-sectional view taken along the line IV-IV ′ of FIG. 4A. In addition, the dimension of the photomask shown to this embodiment and each embodiment after this embodiment is the value converted into the dimension when it transfers to a board | substrate.

  As shown in FIG. 4A, three or more hole patterns 201 are arranged along one direction. The size of the hole pattern 201 is a rectangle with a = 50 nm and b = 350 nm square. Auxiliary patterns 202 (202a, 202b) having a width W of 50 nm or less and a resolution limit or less are formed at a distance d of 300 nm in a direction orthogonal to the arrangement direction (one direction) of the hole patterns 201. The length in one direction of the auxiliary pattern is equal to or greater than the length of the hole pattern row, and the long side (longitudinal direction) is substantially parallel to the arrangement direction of the hole patterns. As shown in FIG. 4B, the hole pattern 201 and the auxiliary patterns 202 a and 202 b are formed so as to be surrounded by a semitransparent film 211 formed on the transparent substrate 210. The hole pattern 201 and the auxiliary patterns 202a and 202b may be formed so as to be surrounded by a light shielding film formed on the transparent substrate.

  If the width W of the auxiliary pattern 202 is larger than 0.3 × λ / NA (68 nm in this embodiment) with respect to the numerical aperture NA, the possibility that the auxiliary pattern is transferred is increased, which is not desirable.

  As shown in FIG. 5, it is not preferable that the distance d is less than 0.3 × b with respect to the length b of the hole pattern because it is larger than the target dimension (0.15 μm). Therefore, the distance d is preferably 0.3 × b or more with respect to the length b. If it is larger than 1.5 × b, the depth of focus may be shortened, which is not desirable. Furthermore, it is more preferable that the distance d and the length b have a relationship of 0.5 × b ≦ d ≦ 1.0 × b, which increases the depth of focus. FIG. 5 is a diagram showing the dependency of the depth of focus and the long side dimension on the distance d / length b.

  Suitable illumination differs depending on whether the patterns are sparsely arranged or densely arranged. In the case of bit line contact holes, patterns are densely arranged in the short side direction, but patterns are sparsely arranged in the long side direction. In the case of the photomask having the auxiliary pattern 402 shown in FIG. 18, it is dense in the arrangement direction and the direction perpendicular to the arrangement direction, but sparse in the oblique direction.

  In the mask of this embodiment, by arranging the auxiliary patterns that are not transferred adjacent to each other in the long side direction, the patterns are densely arranged in the oblique direction. As a result, it becomes suitable for illumination conditions when the patterns are densely arranged, and the resolution and the depth of focus can be improved.

  Illumination conditions suitable when the patterns are densely arranged are oblique incidence illumination. The reason why the oblique incidence is suitable for the dense pattern will be described with reference to FIGS. FIG. 6 is a diagram showing the generation and imaging of diffracted light from a dense pattern. FIG. 6A shows the case of vertical illumination, and FIG. 6B shows the case of oblique incidence illumination. As shown in FIG. 6A, in the case of vertical illumination, ± first-order light has an angle larger than the NA of the projection lens, and only zero-order light reaches the wafer. As shown in FIG. 6B, in the case of oblique incidence illumination, an image can be formed on the wafer as long as the zero-order light and the first-order light pass through the projection optical system. Therefore, the limit resolution can be improved with oblique incidence illumination.

  FIG. 7 is a diagram for explaining the principle of improving the depth of focus by oblique incidence illumination. FIG. 7A shows the state of diffraction and image formation of vertical illumination, and FIG. 7B shows the state of diffraction and image formation of oblique incidence illumination. When the pitch P of the mask and the wavelength λ, the angle between the 0th order light and the 1st order light transmitted through the mask are θ, and the numerical aperture NA of the lens, the relationship P = λ / sinθ = λ / NA is established. As shown in FIG. 7, when the mask pitch is the same and the illumination is obliquely incident, the angle of focus between the first-order diffracted light and the zeroth-order diffracted light is small, so that the depth of focus is improved compared to vertical illumination.

  FIG. 8 is a diagram for explaining the principle of resolution improvement by oblique incidence illumination. As shown in FIG. 8, when the pitch becomes dense, θ increases and the resolution improves.

  When the resist was exposed using the mask on which the continuous auxiliary pattern was formed, the resist pattern to be formed was obtained by simulation, and optimum exposure conditions were obtained. In the simulation, first, an aerial image is calculated for the mask pattern. Next, the effect of the resist process is taken in by convolution integration of a Gaussian function (σ = ΔL), and a resist pattern is calculated. The effect of the resist process is obtained in advance by fitting experimental results and simulation results. This time, ΔL = 45 nm.

  The wavelength λ of the illumination light source was 193 nm, and the numerical aperture NA and the illumination optical system aperture (illumination conditions) were changed for comparison. FIG. 9 shows the configuration of the aperture used for the simulation. 9A is normal illumination, FIG. 9B is annular illumination, FIG. 9C is dipole illumination, FIG. 9D is quadrupole illumination, and FIG. 9E is fan second illumination. FIG. 9F shows the aperture of the fourth fan illumination. The numerical aperture NA was set to 0.68, 0.78, or 0.85. Depending on the conditions, in the case of dipole illumination, the diameters of the two openings provided in the aperture may be changed. Similarly, in the case of quadrupole illumination, the size of the opening provided in the aperture may be changed according to conditions. Moreover, although it is 4 rotation symmetry in the figure, 2 rotation symmetry may be sufficient.

  As a result of simulation, the numerical aperture NA was 0.85, and the illumination system aperture was optimal for the second fan illumination. The second fan illumination parameters were set to σ = 0.9, Inner σ = 0.6, θoa1 = 30 [deg], and the openings were arranged so as to be illuminated obliquely with respect to the short side direction of the arrangement direction. . As a result, the resolution of the bit line contact hole was improved, and a continuous hole pattern with a long side dimension of 150 nm at a pitch of 145 nm could be formed. Note that the modified illumination method other than the fan second illumination has a higher margin than the normal illumination, and therefore other modified illumination methods may be used.

  The width of the auxiliary pattern 203 shown in FIG. 10 was increased stepwise from 0 (no auxiliary pattern) until adjacent auxiliary patterns 203 were connected, and lithography simulation was performed. The dimensions of the pattern 201 other than the auxiliary pattern 203 are the same as the pattern shown in FIG.

The illumination condition is fan second illumination, and the numerical aperture NA is 0.85. The simulation result is shown in FIG. Table 1 shows an outline of the simulation results. Table 1 shows the depth of focus when the exposure tolerance is 8%.

  From this, it can be seen that the auxiliary pattern according to the present embodiment has the largest lithography margin.

(Second Embodiment)
FIG. 12 is a diagram showing the configuration of a mask according to the second embodiment of the present invention. FIG. 12A is a plan view of the mask, and FIG. 12B is a cross-sectional view of the XII-XII ′ portion of FIG. This mask is used to form a bit line contact hole in a NAND flash memory.

  As shown in FIG. 12, a hole pattern and first and second auxiliary patterns are formed surrounded by the light shielding film 212. Three or more hole patterns 201 are arranged along one direction. The size of the hole pattern is a rectangle with a = 40 nm and b = 200 nm square. A second auxiliary pattern 222 (222a, 222b) having a width W of 50 nm or less and a resolution limit is formed at a distance d of 300 nm in a direction orthogonal to the arrangement direction (one direction) of the hole patterns 201. . In the second auxiliary pattern 222, the transparent substrate 210 is dug down. As a result, the transmitted light of the second auxiliary pattern 222 and the transmitted light of the hole pattern 201 have a phase difference of 180 degrees. A first auxiliary pattern 223 (223a, 223b) having a width W of 50 nm and a resolution limit or less is provided at a distance d of 300 nm from the second auxiliary pattern 222 in a direction orthogonal to the arrangement direction (one direction). Is formed. The transmitted light of the first auxiliary pattern 223 and the transmitted light of the hole pattern 201 are in phase.

  When exposure was performed under the same illumination conditions as in the first embodiment, a continuous hole pattern with a long side dimension of 130 nm at a pitch of 145 nm could be formed.

(Third embodiment)
In this example, the dimensions of the photomasks shown in FIGS. 4 and 12 were optimized and the long side dimensions were compared. Table 2 shows the dimensions of each optimized photomask.

The illumination conditions were the same as those in the first embodiment, and a long side dimension was obtained by performing a simulation. Table 3 shows long side dimensions of holes formed when the exposure margin is 8% and the depth of focus is 0.2 μm.

  As shown in Table 3, it can be seen that the long side dimension can be shrunk by using a continuous auxiliary pattern, particularly two continuous auxiliary patterns.

(Fourth embodiment)
In the present embodiment, a method for generating mask data having the above-described continuous auxiliary pattern will be described. 13 and 14 are diagrams used for explaining a mask data generation method according to the fourth embodiment of the present invention.

  First, as shown in FIG. 13A, design data is prepared in which the interval between adjacent hole patterns 301 is S and three or more hole patterns are arranged in one direction. Next, as shown in FIG. 13B, a resize process for expanding each hole pattern 301 by S / 2 left and right in the x direction is performed, and adjacent patterns are connected to create a pattern 302. Next, as shown in FIG. 13C, the pattern 303 is generated by performing a resizing process for increasing d (the distance between the main pattern and the auxiliary pattern) + W (the width of the auxiliary pattern) vertically in the y direction. Next, as illustrated in FIG. 13D, a resize process is performed to reduce the size in the Y direction vertically, thereby generating a pattern 304. Next, as shown in FIG. 14E, difference patterns 305a and 305b between the pattern 303 shown in FIG. 13C and the pattern 304 shown in FIG. 13D are extracted. As shown in FIG. 14F, the pattern 301 shown in FIG. 13A and the patterns 305a and 305b shown in FIG. 13E are merged. Through the above processing, a hole pattern having a continuous auxiliary pattern can be designed.

(Fifth embodiment)
In the present embodiment, a method for generating mask data having a continuous auxiliary pattern will be described. 15 and 16 are diagrams used for explaining a mask data generation method according to the fifth embodiment of the present invention.

  First, as shown in FIG. 15A, design data in which the interval between adjacent hole patterns is S and three or more hole patterns (width a) 301 are arranged in one direction is prepared. Next, as shown in FIG. 15B, the pattern 312 is generated by performing a resizing process for increasing d (the distance between the main pattern and the auxiliary pattern) + W (the width of the auxiliary pattern) up and down in the y direction. Next, as illustrated in FIG. 15C, a resize process is performed to reduce the width W in the vertical direction and the pattern 313 is generated. Next, as shown in FIG. 15D, a difference pattern 314 between the pattern 312 shown in FIG. 15B and the pattern 313 shown in FIG. 15C is extracted. Next, as shown in FIG. 16E, resize processing is performed to expand each pattern by S / 2 left and right in the x direction to generate patterns 315a and 315b. As shown in FIG. 16F, the pattern 301 shown in FIG. 16A is merged with the patterns 315a and 315b shown in FIG. Through the above processing, a hole pattern having a continuous auxiliary pattern can be designed.

(Sixth embodiment)
FIG. 17 is a plan view showing a configuration of a phase shift mask according to the sixth embodiment of the present invention. As shown in FIG. 17, the main pattern 501 and the auxiliary patterns 502 (502a, 502b) are formed surrounded by a semi-transparent film 511. The translucent film 511 is formed on a transparent substrate (not shown). The light transmittance of the translucent film is 6%, and the phase of the light transmitted through the translucent film is 180 degrees different from the phase of the light transmitted through the hole pattern 501 and the auxiliary patterns 502a and 502b. This phase shift mask is mounted on an exposure apparatus having an exposure wavelength of λ and a numerical aperture of NA. The phase shift mask preferably transfers the pattern to the substrate with oblique incidence illumination. The main pattern 501 and the auxiliary pattern 502 may be formed surrounded by a light shielding film formed on a transparent substrate.

  The main pattern 501 is adjacent to the main pattern 501, and is arranged without periodicity with respect to the pattern resolved by the exposure apparatus on which the phase shift mask is mounted. The main pattern 501 has a rectangular shape with rounded corners, and has a short direction and a long direction in the x direction and the y direction.

  The auxiliary patterns 502a and 502b are arranged in the vicinity of one end of the main pattern 501 in the longitudinal direction. The auxiliary pattern 502 is not resolved by the exposure apparatus on which the phase shift mask is mounted. The length L in the x direction of the auxiliary pattern 502 is sufficiently longer than the width in the x direction of the main pattern 501.

  If the value obtained by converting the width in the y direction of the auxiliary pattern 502 into a dimension on the substrate is larger than 0.27 × λ / NA or less, the possibility that the auxiliary pattern is transferred is increased, which is not desirable. Here, λ is the exposure wavelength, and NA is the numerical aperture.

ED-Tree analysis was performed on the phase shift mask having the auxiliary pattern. Further, ED-Tree analysis was performed on the phase shift mask shown in FIG. 18 in which only the main pattern 501 was formed. 19 and 20 show the ED-Tree analysis results. FIG. 19 shows an ED-Tree analysis result of the phase shift mask on which the auxiliary pattern shown in FIG. 17 is formed. FIG. 20 shows an ED-Tree analysis result of the phase shift mask in which the auxiliary pattern shown in FIG. 18 is not formed. 19 and 20, L _-20% , L _0% , and L _{+ 20%} indicate that the length in the y-axis direction of the pattern to which the main pattern 501 is transferred is -20%, 0%, The line is + 20%. 19 and 20, S _-10% , S _0% , and S _{+ 10%} indicate that the length in the x-axis direction of the pattern to which the main pattern 501 is transferred is -10%, 0 % And + 10%.

  As shown in FIGS. 19 and 20, when there is an auxiliary pattern, there is little dimensional variation at the time of defocusing a side perpendicular to the hole auxiliary pattern, and the lithography margin can be improved.

  Lithographic margin evaluation was performed using the length L in the x direction of the auxiliary pattern 502 as a parameter. The lithography margin is the depth of focus when the focus margin is 8%. FIG. 21 is a diagram showing a lithography margin result. As shown in FIG. 21, when the length of the auxiliary pattern 502 reaches about 1000 nm, the lithography margin (depth of focus) tends to be saturated.

  For the phase shift mask having the auxiliary pattern 502 and the phase shift mask without the auxiliary pattern, the light intensity distribution on the substrate in the y direction was simulated. FIG. 22 shows the normalized light intensity on the substrate when the phase shift mask having the auxiliary pattern 502 is used. FIG. 23 shows the normalized light intensity on the substrate when a phase shift mask having no auxiliary pattern 502 is used. The normalized light intensity is equal between the phase shift mask on which the auxiliary pattern is formed and the phase shift mask without the auxiliary pattern.

  The light intensity on the substrate when the pattern formed on the phase shift mask was transferred onto the substrate was simulated. The light intensity distribution in the y-axis direction is shown in FIG. FIG. 24 shows the light intensity distribution in the y-axis direction on the substrate of the exposure light transmitted through the phase shift mask. In FIG. 24, peak B is due to the auxiliary pattern. When the light intensity at peak B increases, the pattern is transferred onto the wafer, and the auxiliary pattern width W needs to be optimized.

  A simulation was performed using the auxiliary pattern width W as a parameter, and the ratio of peak A to peak B (B / A) was obtained. The exposure conditions are an exposure wavelength λ of 193 nm and a numerical aperture NA of 0.85. FIG. 25 is a diagram showing the relationship between the ratio (B / A) of the peak A and the peak B and the auxiliary pattern width W. The auxiliary pattern width W is a value converted into a dimension on the substrate. In this case, the auxiliary pattern width W that gives the normalized exposure intensity equivalent to the case where there is no auxiliary pattern is 50 nm.

  The light intensity on the substrate when the pattern formed on the phase shift mask was transferred onto the substrate was simulated. FIG. 26 shows the light intensity distribution in the x-axis direction on the substrate. FIG. 26 shows the light intensity distribution in the x-axis direction on the substrate of the exposure light transmitted through the phase shift mask. There are a peak C and a peak D in the light intensity distribution. Peak C is due to the main pattern. The peak D is considered to be due to the auxiliary pattern. A simulation was performed using the distance d between the main pattern and the auxiliary pattern as a parameter, and the ratio of peak A to peak B (B / A) was obtained. The distance d is a value converted into a dimension on the substrate. FIG. 27 is a diagram illustrating a relationship between the ratio C of the peak C and the peak D (D / C) and the distance d. As shown in FIG. 27, the ratio (D / C) changes according to the distance. Therefore, it can be seen that the optimization of the distance d is necessary. In this embodiment, the distance d between the auxiliary pattern and the main pattern is 100 nm. However, the distance d is not limited to 100 nm and may be 50 nm or more.

(Seventh embodiment)
FIG. 28 is a plan view showing a configuration of a photomask according to the seventh embodiment of the present invention.

  In addition, the dimension of the photomask shown to this embodiment and each embodiment after this embodiment is the value converted into the dimension when it transfers to a board | substrate.

  As shown in FIG. 28, a plurality of line patterns 601 are periodically arranged in the x direction. The L / S pattern LS is configured by the plurality of line patterns 601. Auxiliary patterns 602a and 602b are arranged adjacent to one end side of the line pattern 601 in the y direction. The length in the x direction of the auxiliary patterns 602a and 602b is equal to or longer than the length in the x direction of the L / S pattern. The auxiliary pattern is a pattern that is not transferred onto the substrate even when used in the exposure apparatus used. If the width W in the y direction of the auxiliary patterns 602a and 602b is larger than 0.26 × λ / NA (59 nm in this embodiment) with respect to the numerical aperture NA and the wavelength λ of the exposure light, the auxiliary patterns 602a and 602b Is undesirably increased because of the possibility of transfer to the resist on the substrate. The hole pattern 601 and the auxiliary patterns 602a and 602b are formed of a light shielding film formed on a transparent substrate. The hole pattern 601 and the auxiliary patterns 602a and 602b may be formed of a translucent film formed on a transparent substrate.

  When the L / S pattern LS and the auxiliary patterns 602a and 602b are transferred to the resist film on the substrate and developed, shortening and thinning of the formed line pattern edge can be reduced. As a result, resist pattern collapse during resist pattern formation can be reduced.

  Further, although the auxiliary pattern is arranged adjacent to one end of the line pattern 601 in the y direction, an auxiliary pattern adjacent to the other end of the line pattern 601 in the y direction may be arranged. In addition, although two auxiliary patterns 602a and 602b are arranged, only one auxiliary pattern may be formed, or three or more auxiliary patterns may be arranged. The distance d between the line pattern 601 and the auxiliary pattern 602a is preferably 50 nm or more.

  Next, a method for generating design data with an auxiliary pattern added from design data including an L / S pattern will be described below. FIG. 29 is a flowchart showing a procedure of a design data generation method according to the seventh embodiment of the present invention.

  First, first design data having an L / S pattern LS composed of a plurality of line patterns 601 shown in FIG. 30 is prepared (step ST11). In the pattern corresponding to the first design data, no auxiliary pattern is arranged adjacent to the L / S pattern. Next, a normalized exposure light intensity distribution on the resist film when the L / S pattern is transferred to the resist film by lithography simulation is obtained (step ST12). FIG. 31 shows the normalized exposure light intensity distribution obtained. FIG. 31 shows the normalized exposure light intensity distribution in the x direction.

  An exposure light intensity α at which a target pattern dimension is obtained is obtained from the normalized exposure light intensity (step ST13). Further, an exposure light intensity β that is 20% higher than the exposure light intensity α is obtained (step ST14). The exposure light intensity β corresponds to the upper limit value of the exposure amount margin.

  Next, a plurality of design data (design data group) in which the auxiliary pattern 602 is arranged adjacent to the L / S pattern LS as shown in FIG. 28 is prepared (step ST15). In the pattern corresponding to each design data, the width W in the x direction of the auxiliary pattern and the distance d between the L / S pattern and the auxiliary pattern are changed.

  The normalized exposure light intensity when the pattern corresponding to each design data is transferred to the resist film with the exposure light intensity β is determined by lithography simulation (step ST16). FIG. 32 shows the normalized exposure light intensity distribution obtained. FIG. 32 shows the intensity distribution in the y direction. In FIG. 32, the peak Pa corresponds to the auxiliary pattern 602a, and the peak Pb corresponds to the auxiliary pattern 602b.

  Design data is selected from the obtained plurality of exposure light intensity distributions so that the auxiliary pattern is not transferred to the resist when the pattern is transferred with the exposure light intensity β (step ST17). In the present embodiment, the case where the peaks Pa and Pb are greater than or equal to the exposure light intensity β is set as a condition that the auxiliary pattern is not designed.

  With the above processing, it is possible to design the layout of the auxiliary pattern in the vicinity of the line end of the line pattern that is the main pattern.

(Eighth embodiment)
A method of manufacturing a semiconductor device using the photomask described in the first to third embodiments and the sixth and seventh embodiments will be described. FIG. 33 is a flowchart showing a procedure of a method of manufacturing a semiconductor device according to the eighth embodiment of the present invention.

  Photomask design data having an auxiliary pattern with dimensions corresponding to the exposure apparatus used for pattern transfer is prepared. A photomask is created based on the design data (step ST101). A photomask is stored in the semiconductor device (step ST102).

  For example, a semiconductor substrate on which an interlayer insulating film or the like is formed is prepared. A positive resist film is applied and formed on the semiconductor substrate (step ST103). A semiconductor substrate is stored in an exposure apparatus. In order to form a latent image on the resist film, the pattern formed on the photomask is transferred to the resist film using an exposure apparatus (step ST104). The resist film is developed (step ST105). The interlayer insulating film is etched using the developed resist film as a mask (step ST106). Thereafter, further processing is performed to manufacture a semiconductor device.

  In addition, this invention is not limited to the said embodiment, In the implementation stage, it can change variously in the range which does not deviate from the summary. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.

1 is a diagram schematically showing a circuit of a NAND flash memory according to a first embodiment. 1 is a plan view showing a configuration of a flash memory according to a first embodiment. 1 is a cross-sectional view showing a configuration of a flash memory according to a first embodiment. 1 is a diagram illustrating a schematic configuration of a photomask according to a first embodiment. The figure which shows the space | interval d / length b dependence of a focal depth and a long side dimension. The figure which shows generation | occurrence | production and image formation of the diffracted light from a dense pattern. The figure for demonstrating the principle of the focal depth improvement by an oblique incidence illumination. The figure for demonstrating the principle of the resolution improvement by an oblique incidence illumination. The top view which shows the structure of an aperture (illumination condition). The top view which shows the structure of the photomask used for simulation. The figure which shows the relationship between exposure amount tolerance and a focal depth. The figure which shows the structure of the mask concerning 2nd Embodiment. The figure used for description of the mask data generation method concerning a 4th embodiment. The figure used for description of the mask data generation method concerning a 4th embodiment. The figure used for description of the mask data generation method concerning a 5th embodiment. The figure used for description of the mask data generation method concerning a 5th embodiment. The top view which shows the structure of the phase shift mask in which the auxiliary pattern concerning 6th Embodiment was formed. The top view which shows the structure of the phase shift mask in which the auxiliary pattern is not formed. The figure which shows the ED-Tree analysis result of the phase shift mask shown in FIG. The figure which shows the ED-Tree analysis result of the phase shift mask shown in FIG. The figure which shows the relationship between the depth of focus when the focus margin is 8%, and the length L of the auxiliary pattern. The figure which shows the normalized light intensity on a board | substrate at the time of using the phase shift mask shown in FIG. The figure which shows the normalized light intensity on the board | substrate at the time of using the phase shift mask shown in FIG. The figure which shows the light intensity distribution of the y-axis direction on the board | substrate of the exposure light which permeate | transmitted the phase shift mask shown in FIG. The figure which shows the relationship between ratio (B / A) of peak A and peak B, and auxiliary pattern width W. FIG. The figure which shows the light intensity distribution of the x-axis direction on the board | substrate of the exposure light which permeate | transmitted the phase shift mask. The figure which shows the relationship with the distance d of ratio (D / C) of the peak C and the peak D. FIG. The top view which shows the structure of the photomask concerning 7th Embodiment. 18 is a flowchart illustrating a procedure of a design data generation method according to the seventh embodiment. The figure which shows a line and space pattern. The figure which shows the normalized exposure light intensity distribution on a resist film at the time of transferring an L / S pattern to a resist film. The figure which shows the normalized exposure light intensity when the pattern corresponding to design data is transferred to a resist film with exposure light intensity (beta). The figure which shows the procedure of the manufacturing method of the semiconductor device concerning 8th Embodiment. The top view which shows the pattern row | line | column with which the hole pattern was arranged in multiple numbers along one direction. The figure which shows the pattern which added the auxiliary pattern to the pattern row | line | column shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Substrate, 102 ... Type well, 103 ... Type diffusion layer, 104 ... Tunnel insulating film, 105 ... Floating gate, 106 ... Inter-gate insulating film, 107 ... Control gate, 109 ... Interlayer insulating film, 110 ... Bit line contact hole 111, bit line contact, 112, second interlayer insulating film, 113, via plug, 114, bit line.

Claims (6)

A photomask on which a pattern for transferring to a substrate using an exposure apparatus is formed,
A rectangular main pattern having a longitudinal direction surrounded by a light-shielding part or a semi-transparent film and a short direction perpendicular to the longitudinal direction, the main pattern arranged without periodicity,
The auxiliary pattern is surrounded by the light-shielding portion or the semi-transparent film, and is disposed in the vicinity of one end portion in the longitudinal direction of the main pattern, and the length in the direction parallel to the short direction of the main pattern is the length of the main pattern An auxiliary pattern that is longer than the short-side length and is not transferred onto the substrate;
Comprising a result, the
A length of the auxiliary pattern in a direction parallel to the longitudinal direction of the main pattern (length converted to a dimension when transferred to the substrate) is 50 nm or less .   The photomask according to claim 1, wherein a distance d between the main pattern and the auxiliary pattern is 50 nm or more.   2. The photomask according to claim 1, wherein a length of the auxiliary pattern in a direction parallel to a short direction of the main pattern is 1000 nm or more. Preparing an exposure apparatus for transferring a pattern formed on a photomask to a positive resist film on a semiconductor substrate;
A step of preparing the photomask, wherein the photomask is a main pattern having a longitudinal direction surrounded by a light-shielding portion or a semi-transparent film and a lateral direction perpendicular to the longitudinal direction, and having a periodicity. A main pattern that is not provided, and an auxiliary pattern surrounded by the light-shielding portion or the semi-transparent film, disposed near one end in the longitudinal direction of the main pattern, and the short direction of the main pattern A length in a direction parallel to the main pattern is longer than a length in the short direction of the main pattern, and an auxiliary pattern not transferred onto the substrate; and
Transferring the pattern formed on the photomask to the positive resist film using the exposure apparatus;
Including
The length of the auxiliary pattern in the direction parallel to the longitudinal direction of the main pattern (length converted to the dimension when transferred to the substrate) is 50 nm or less .   5. The method of manufacturing a semiconductor device according to claim 4, wherein the illumination condition of the exposure apparatus is oblique incidence illumination. 5. The method of manufacturing a semiconductor device according to claim 4 , wherein a length of the auxiliary pattern in a direction parallel to a short direction of the main pattern is 1000 nm or more.

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