JP4790336B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including a memory cell that stores data using a difference in threshold voltage.

  Nonvolatile semiconductor memory devices such as flash memories have been developed that can store information by injecting electrons into the floating gate (FG) or by extracting electrons. The flash memory includes a memory cell having a floating gate, a control gate (CG), a source, a drain, and a well (substrate). In the memory cell, the threshold voltage increases when electrons are injected into the floating gate, and the threshold voltage decreases when electrons are extracted from the floating gate.

  In general, the distribution with the lowest threshold voltage is called the erased state of the memory cell, and the threshold voltage distribution higher than the erased state is called the written state of the memory cell. For example, when the memory cell stores 2-bit data, the threshold voltage distribution having the lowest voltage corresponds to the logic level “11”, and this state is called an erased state. Then, the threshold voltage corresponding to the logic levels “10”, “01”, and “00” is obtained by performing the write operation on the memory cell to make the threshold voltage higher than the erase state, and this state is the write state. Called.

  In addition, although the prior art about this invention was demonstrated based on the general technical information which the applicant acquired, the information which should be disclosed as prior art document information before filing in the range which an applicant memorize | stores The applicant does not have

  By the way, in the conventional nonvolatile semiconductor memory device, when the power supply voltage is supplied to the nonvolatile semiconductor memory device, the control gate, the source, the drain and the well of the memory cell are in a standby state where writing and reading are not performed. Is supplied with ground voltage. Even when the power supply voltage is not supplied, in the standby state, the potentials of the control gate, source, drain and well of the memory cell become the ground potential due to natural discharge.

  Therefore, when the conventional nonvolatile semiconductor memory device is in a standby state and the threshold voltage of the memory cell is UV Vth, the potential difference between CG and FG and between FG and well (hereinafter referred to as self-bias). 0V. Here, the UV Vth is a threshold voltage of the memory cell in a state where the charge in the FG has disappeared by irradiating the memory cell with ultraviolet (Ultra Violet), that is, the charge in the FG becomes neutral as a whole. That is.

  On the other hand, when the memory cell is in the erased state or the written state, self-bias is generated by the charge accumulated in the FG. If there is no defect in the ONO film (oxide film-nitride film-oxide film) between CG-FG and the tunnel oxide film between FG-well, there is no problem even if self-bias occurs. However, when data rewrite is repeated on the memory cell, the tunnel oxide film deteriorates due to stress of writing or erasing. Then, a small stress-induced leakage current (hereinafter referred to as SILC (Stress-Induced Leakage Current)) occurs due to self-bias (see, for example, “Ultrathin Silicon Oxide Film Formation and Interface Evaluation Technology” p.131). .

  When SILC occurs, the threshold voltage of the memory cell shifts in the direction of UV Vth due to outflow of electrons from FG or inflow of electrons into FG. When the threshold voltage shift reaches the read voltage, that is, the voltage for determining the logic level of data stored in the memory cell, a DL (Data Loss) defect that changes the memory content of the memory cell occurs, and the nonvolatile semiconductor The data retention characteristics of the storage device deteriorate.

  For example, when the memory cell stores 2-bit data, it corresponds to the threshold voltage center corresponding to each logic level, that is, the threshold voltage distribution corresponding to the logic level “10” and the logic level “01”. When UV Vth is located in the middle of the threshold voltage distribution, there is no significant difference in the likelihood of a DL failure between memory cells storing data of each logic level. However, for example, when UV Vth is closer to the threshold voltage distribution corresponding to the logic level “10” than the logic level “01”, the memory cell storing the data of the logic level “01” has the logic level “01”. Since the self-bias is larger than that of a memory cell that stores 10 ″ data, the amount of SILC is large and a DL defect is likely to occur. Similarly, a memory cell that stores data of logic level “00” has a higher self-bias, a larger threshold voltage shift, and a DL failure than a memory cell that stores data of logic level “11”. . Here, if a DL failure occurs in a memory cell that stores data at any logic level, the entire nonvolatile semiconductor memory device can be used even if a DL failure does not occur in a memory cell that stores data at another logic level. In this case, the data retention characteristic is deteriorated. Therefore, the conventional nonvolatile semiconductor memory device has a problem that the data retention characteristic is deteriorated due to the difference in self-bias of the memory cells storing the data of each logic level.

  Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device that can reduce deterioration of data retention characteristics.

  In order to solve the above problems, a nonvolatile semiconductor memory device according to an aspect of the present invention generates a plurality of memory cells for storing data and a voltage to be supplied to the memory cells using a difference in threshold voltage. A voltage generation unit; and a logic unit that controls the voltage generation unit to generate a predetermined potential difference between at least one of a well, a drain, and a source in a standby state by controlling the voltage generation unit.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device that can reduce deterioration of data retention characteristics.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
The present embodiment relates to a nonvolatile semiconductor memory device in which a control gate of a memory cell is set to a potential other than a ground potential in a standby state.

[Configuration and basic operation]
FIG. 1A is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the first embodiment of the present invention. In the following description, it is assumed that the nonvolatile semiconductor memory device according to the present embodiment is a NOR flash memory and that the memory cell stores 2-bit data.

  Referring to FIG. 1, a nonvolatile semiconductor memory device includes a memory array 1, a logic unit 2, a charge pump circuit 3, an X decoder 4, a Y gate 5, a Y decoder 6, an address buffer 7, An I / O buffer 8, a sense amplifier 9, and a write driver 10 are provided.

  Memory array 1 includes a plurality of memory cells and one or more select gates. The charge pump circuit 3, the X decoder 4, the Y gate 5, and the Y decoder 6 constitute a voltage generation unit 50. The voltage generator 50 generates a voltage based on the control of the logic unit 2 and supplies the generated voltage to the memory cells of the memory array 1.

  An address signal input from the outside is output to the X decoder 4 and the Y decoder 6 via the address pad and the address buffer 7. Data input from the outside is output to the logic unit 2 via the DQ pad and the I / O buffer 8. Data read from the memory array 1 is output to the outside through the Y gate 5, the sense amplifier 9, the I / O buffer 8, and the DQ pad.

  The logic unit 2 outputs a control signal to each circuit based on a command signal input from the outside, and performs control for writing, reading, and erasing the memory cell.

  The charge pump circuit 3 generates a voltage to be supplied to the memory cells of the memory array 1 based on the control of the logic unit 2, and outputs the generated voltage to the X decoder 4, the Y gate 5, and the write driver 10. .

  X decoder 4 decodes the address signal received from address buffer 7 to select a word line, source line and well corresponding to a specific memory cell in memory array 1. X decoder 4 drives the selected word line, source line, and well with the voltage received from charge pump circuit 3.

  The X decoder 4 does not use the voltage received from the charge pump circuit 3 when the word line, the source line or the well corresponding to a specific memory cell is set to the ground potential. A word line, a source line, or a well corresponding to a specific memory cell may be connected. The X decoder 4 can also float a word line, a source line or a well corresponding to a specific memory cell based on the control of the logic unit 2.

  Here, FIG. 1B is a diagram showing the structure of the memory array 1. The control gate of the memory cell is connected to the word line, the drain is connected to the sub bit line, the source is connected to the source line, and the drain of the select gate is connected to the main bit line.

  Referring to FIG. 1A again, Y decoder 6 decodes the address signal received from address buffer 7 to generate a selection signal and outputs it to Y gate 5.

  Y gate 5 selects a main bit line and a sub bit line corresponding to a specific memory cell in memory array 1 represented by a selection signal received from Y decoder 6. Y gate 5 drives the selected main bit line and sub bit line with the voltage received from charge pump circuit 3.

  When the main bit line and the sub bit line corresponding to a specific memory cell are set to the ground potential, the Y gate 5 does not use the voltage received from the charge pump circuit 3, but specifies the node at the ground potential. The main bit line and the sub bit line corresponding to the memory cell may be connected.

  The memory cell to be written and the memory cell to be read are specified by the selection of the word line, source line and well by the X decoder 4 and the selection of the main bit line and sub bit line by the Y gate 5 and Y decoder 6.

  2A to 2C are diagrams showing erase, write, and read operations for the memory cells of the nonvolatile semiconductor memory device according to the first embodiment of the present invention, respectively. FIG. 3 is a diagram showing the threshold voltage of the memory cell when the nonvolatile semiconductor memory device according to the first embodiment of the present invention stores 2-bit data.

  Referring to FIG. 2A, erasing of a memory cell uses FN (Fowler-Nordheim) phenomenon to extract electrons from FG that is a charge storage layer, and the threshold voltage is the distribution with the lowest voltage value, that is, This is done by using the “11” distribution (threshold voltage distribution corresponding to the logic level “11”) shown in FIG.

  Referring to FIG. 2B, writing to the memory cell uses CHE (Channel Hot Electron) phenomenon to inject electrons into FG to gradually increase the threshold voltage, that is, in an erased state. The “11” distribution shown in FIG. 3 is raised to the “10”, “01” and “00” distributions. More specifically, the X decoder 4, the Y gate 5, and the Y decoder 6 use the threshold voltage of the memory cell to be written as the threshold voltage corresponding to the logic level of the data received from the logic unit 2 via the write driver 10. Thus, data is written.

  Referring to FIG. 2C, reading from the memory cell is performed by applying a voltage between threshold voltage distributions corresponding to each logic level, that is, reading voltages 1 to 3 shown in FIG. The sense amplifier 9 determines whether or not current flows between the source and drain of the memory cell.

  Next, the operation in the standby state of the nonvolatile semiconductor memory device according to the first embodiment of the invention will be described.

[Operation]
FIG. 4 is a diagram showing the relationship between the DL lifetime and the voltage supplied to the control gate. Here, the DL lifetime is the time until the nonvolatile semiconductor memory device becomes defective in DL, and is one of the indexes representing data retention characteristics.

  This figure shows a case where UV Vth is closer to the threshold voltage distribution corresponding to the logic level “10” than the logic level “01”. The state of Vg = 0.0 V is a standby state of the conventional nonvolatile semiconductor memory device, that is, a state where the potentials of CG, well, source and drain of the memory cells of the memory array 1 are ground potential. In this state, the memory cell that stores data of the logic level “00” has a shorter DL life than the memory cell that stores data of the logic level “11”. This is because, as described above, the self-bias is different between the memory cell storing the data of the logic level “00” and the memory cell storing the data of the logic level “11”.

  Therefore, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, in the standby state, a positive voltage, for example, 1 V is supplied to the CG of the memory cell of the memory array 1, and the well and source of the memory cell are supplied. And a ground voltage to the drain. Hereinafter, this operation will be described in detail.

  FIG. 5 is a diagram showing an example of the potential relationship of the memory cells in the standby state of the nonvolatile semiconductor memory device according to the first embodiment of the invention.

  FIG. 6 is a diagram showing an example of the potential relationship of the memory array 1 in the standby state of the nonvolatile semiconductor memory device according to the first embodiment of the invention.

  When the nonvolatile semiconductor memory device is in a standby state, the logic unit 2 controls the charge pump circuit 3 and the X decoder 4 to supply a positive voltage to the CG of the memory cells of the memory array 1, and at least the X decoder 4 is controlled to supply the ground voltage to the well and source of the memory cell, and at least the Y gate 5 is controlled to supply the ground voltage to the drain of the memory cell.

  More specifically, when the chip enable signal received from the outside via the I / O buffer 8 indicates disable, the logic unit 2 outputs a control signal indicating a command for generating a positive voltage to the charge pump circuit 3. A control signal representing an instruction for selecting all the word lines, a control signal representing an instruction for deselecting all wells, and a control signal representing an instruction for deselecting all source lines are output to the X decoder 4, A control signal representing an instruction to be all unselected is output to Y decoder 6.

  The charge pump circuit 3 receives a control signal from the logic unit 2, generates a positive voltage, and outputs the positive voltage to the X decoder 4.

  X decoder 4 receives a control signal from logic unit 2 and selects all word lines. X decoder 4 drives all word lines of memory array 1 with a positive voltage received from charge pump circuit 3. The X decoder 4 receives a control signal from the logic unit 2 and deselects all source lines and wells of the memory array 1. The potentials of all the source lines and wells of the memory array 1 that are not selected are set to the ground potential.

  Y decoder 6 receives a control signal from logic unit 2, generates a selection signal indicating that all sub-bit lines of memory array 1 are not selected, and outputs the selection signal to Y gate 5.

  Y gate 5 receives a selection signal indicating non-selection from Y decoder 6 and deselects all sub-bit lines of memory array 1. The potentials of all sub-bit lines of the memory array 1 that are not selected are set to the ground potential. Note that the main bit line connected to the select gate of the memory array 1 may be at the ground potential in the standby state or at a potential other than the ground potential.

  Referring to FIG. 4 again, when the voltage supplied to CG is changed from the ground voltage to 1 V in the standby state as described above, the DL life of the memory cell storing the data of logic level “00” is extended. This is because, in a memory cell having a threshold voltage distribution corresponding to the logic level “00”, a larger number of electrons are injected into the FG than in a state where the charge of the FG is neutral as a whole. This is because SILC occurs in the direction of escaping from the well, source, and drain. However, if the CG potential of the memory cell is changed from the ground potential to 1 V, electrons in the FG gather on the CG side and SILC is reduced. .

  On the other hand, the DL lifetime of the memory cell storing the data of the logic level “11” is shortened. This is because in the memory cell having the threshold voltage distribution corresponding to the logic level “11”, a larger number of electrons are extracted from the FG than in the state where the charge of the FG is neutral as a whole. SILC occurs in the direction in which electrons are injected from FG to FG. However, if the CG potential of the memory cell is changed from the ground potential to 1 V, electrons in the well, source, and drain are attracted in the FG direction, increasing SILC. Because it will be.

  Therefore, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, the DL life of the memory cell storing the data of the logic level “11” is shortened, but the data of the logic level “11” is stored. By extending the lifetime of the logic level “00” having a short lifetime for the memory cell, the DL lifetime of the entire nonvolatile semiconductor memory device can be increased.

  The operation in the standby state of the nonvolatile semiconductor memory device according to the first embodiment of the present invention is not limited to the above. Hereinafter, a case where the potential relationship between the memory cell and the memory array 1 in the standby state is other than the potential relationship shown in FIGS. 5 and 6 will be described.

  Contrary to the case shown in FIG. 4, when the UV Vth is closer to the threshold voltage distribution corresponding to the logical level “01” than the logical level “10”, the logical level “11” in the conventional standby state. A memory cell that stores data has a shorter DL life than a memory cell that stores data of logic level “00”.

  In this case, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, in the standby state, a negative voltage, for example, −1 V is supplied to the CG of the memory cell of the memory array 1, and the well of the memory cell Supply a ground voltage to the source and drain.

  When the voltage supplied to the CG is changed from the ground voltage to −1 V in the standby state, the DL life of the memory cell storing the data of the logic level “00” is shortened. This is because, in a memory cell having a threshold voltage distribution corresponding to the logic level “00”, SILC occurs in the direction in which electrons in the FG pass through the well, source, and drain as described above. This is because when the potential is changed from the ground potential to −1 V, electrons in the FG are attracted in the direction of the well, the source and the drain, and SILC is increased.

  On the other hand, the DL life of the memory cell storing the data of the logic level “11” is extended. This is because, in the memory cell having the threshold voltage distribution corresponding to the logic level “11”, SILC occurs in the direction in which electrons are injected from the well, the source and the drain into the FG as described above. Is changed from the ground potential to −1 V, electrons in the FG gather on the well, source and drain sides, and SILC is reduced.

  Therefore, even when the relationship between the DL lifetimes is opposite to that in FIG. 4, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, the DL lifetime of the memory cell storing the data of the logic level “00” is short. However, by increasing the lifetime of the logic level “11” having a short lifetime for the memory cell storing the data of the logic level “00”, the DL lifetime can be extended in the entire nonvolatile semiconductor memory device.

  The logic unit 2 may have all the memory cells in the memory array 1 in the potential relationship shown in FIG. 5, or only the memory cell corresponding to the data area that requires high data retention characteristics is shown in FIG. It may be a relationship. That is, the memory space of the nonvolatile semiconductor memory device may be divided into a code area for storing a program and a data area for storing data, depending on the usage purpose of the user. In general, the former is less frequently rewritten and requires high data retention characteristics. The latter is frequently rewritten and does not require data retention characteristics that are as high as the code area. Therefore, in this case, the logic unit 2 may have only the potential relationship shown in FIG. 5 for the memory cells corresponding to the code area.

  Further, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, the normal standby state in the conventional nonvolatile semiconductor memory device and the potential relationship as shown in FIGS. It can be set as the structure which selects the standby state of a form. More specifically, the logic unit 2 determines whether to control the charge pump circuit 3, the X decoder 4, the Y gate 5, the Y decoder 6 and the like in the standby state based on an externally input command signal. To do. That is, when the standby state of the present embodiment is selected, the logic unit 2 outputs a control signal representing an instruction for generating a predetermined voltage to the charge pump circuit 3, and sets each location of the memory cell. A control signal indicating an instruction to be selected or not selected is output to each circuit. On the other hand, when the conventional standby state is selected, the logic unit 2 outputs a control signal representing an instruction to stop the operation to the charge pump circuit 3.

  Here, in the standby state of the present embodiment, since all the word lines in the memory array 1 are driven by the positive voltage or the negative voltage received from the charge pump circuit 3, the standby state of the present embodiment is changed to the normal state. In the first reading for the memory cell after returning, it is necessary to set the word line not corresponding to the memory cell to be read to the ground potential, and the reading time increases. Further, in the standby state of the present embodiment, since a voltage other than the ground voltage is supplied to the memory cell, current consumption for compensating for a voltage drop due to a minute leak current flowing through the memory cell, and the charge pump circuit 3 There is current consumption due to the operation of the sensing circuit.

  Therefore, with the configuration in which the normal standby state and the standby state of the present embodiment are selected, when the user places importance on the power consumption in the standby state and the first read time for the memory cell after returning from the standby state, it is normal. When the standby state of the memory cell is selected and the data retention characteristic of the memory cell is emphasized, the standby state of the present embodiment can be selected, and a nonvolatile semiconductor memory device that can flexibly meet the user's application is provided. can do.

  In particular, the present invention can be applied to a mobile phone or the like to which power supply voltage is continuously supplied even in a standby state, thereby easily realizing the standby state of the present embodiment and improving data retention characteristics. it can.

  By the way, the conventional nonvolatile semiconductor memory device has a problem that the data retention characteristic is deteriorated due to the difference in self-bias of the memory cells storing the data of each logic level. However, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, a predetermined potential difference is generated between the CG of the memory cell and the well, drain, and source in the standby state. With such a configuration, the difference in DL lifetime due to the difference in self-bias of the memory cells storing data of each logic level is reduced, and the DL lifetime in the entire nonvolatile semiconductor memory device is extended, that is, data retention. Degradation of characteristics can be reduced.

  In the standby state of the nonvolatile semiconductor memory device according to the first embodiment of the present invention, the word lines, wells, drains, and sources are not connected to the nodes of the peripheral circuit of the memory array 1, and therefore once predetermined If the voltage is supplied, the potential is maintained. Then, it is not necessary to supply a large amount of current in order to maintain the potential, and the current consumption in the standby state is extremely reduced. For example, when the positive voltage is generated by a step-down circuit, the current consumption of the nonvolatile semiconductor memory device can be suppressed to 1 uA or less.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
The present embodiment relates to a nonvolatile semiconductor memory device in which the well, drain, and source of a memory cell are set to a potential other than the ground potential in a standby state. The configuration and basic operation of the nonvolatile semiconductor memory device according to the present embodiment are the same as those of the nonvolatile semiconductor memory device according to the first embodiment.

  Next, the operation in the standby state of the nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described.

[Operation]
In the case shown in FIG. 4, in the nonvolatile semiconductor memory device according to the second embodiment of the present invention, in the standby state, the ground voltage is supplied to the CG of the memory cell of the memory array 1, and the well of the memory cell , Supply a negative voltage, for example -1 V, to the source and drain. Hereinafter, this operation will be described in detail.

  FIG. 7 is a diagram showing an example of the potential relationship of the memory cells in the standby state of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

  FIG. 8 is a diagram showing an example of the potential relationship of the memory array 1 in the standby state of the nonvolatile semiconductor memory device according to the second embodiment of the invention.

  When the nonvolatile semiconductor memory device is in a standby state, the logic unit 2 controls at least the X decoder 4 to supply the ground voltage to the CG of the memory cells of the memory array 1, and the charge pump circuit 3 and the X decoder 4 is supplied to supply a negative voltage to the well and source of the memory cell, and the charge pump circuit 3, Y gate 5 and Y decoder 6 are controlled to supply a negative voltage to the drain of the memory cell.

  More specifically, logic unit 2 outputs a control signal representing a command for generating a negative voltage to charge pump circuit 3 when a chip enable signal received from outside via I / O buffer 8 represents disabled. A control signal representing an instruction for selecting all the word lines, a control signal representing an instruction for deselecting all wells, and a control signal representing an instruction for deselecting all source lines are output to the X decoder 4, A control signal representing an instruction to be all unselected is output to Y decoder 6. When a negative voltage is supplied to the memory cell, the logic of selection and non-selection is reversed, and the selected location becomes the ground potential.

  The charge pump circuit 3 receives a control signal from the logic unit 2, generates a negative voltage, and outputs it to the X decoder 4. Further, the charge pump circuit 3 outputs the generated negative voltage to the Y gate 5 via the write driver 10.

  X decoder 4 receives a control signal from logic unit 2 and selects all word lines. All the word lines of the selected memory array 1 are set to the ground potential. The X decoder 4 receives a control signal from the logic unit 2 and deselects all source lines and wells of the memory array 1. X decoder 4 drives all source lines and wells of memory array 1 with a negative voltage received from charge pump circuit 3.

  Y decoder 6 receives a control signal from logic unit 2, generates a selection signal indicating that all sub-bit lines of memory array 1 are not selected, and outputs the selection signal to Y gate 5.

  Y gate 5 receives a selection signal from Y decoder 6 and drives all sub-bit lines of memory array 1 with the negative voltage received from charge pump circuit 3.

  Here, when the voltage supplied to the well, source, and drain of the memory cell is changed from the ground voltage to -1V in the standby state, the voltage supplied to the CG of the memory cell is changed from the ground voltage to 1V as shown in FIG. Similarly to the case, the DL life of the memory cell storing the data of the logic level “00” is extended. This is because, in the memory cell having the threshold voltage distribution corresponding to the logic level “00”, SILC occurs in the direction in which the electrons in the FG escape to the well, the source and the drain as described above. This is because if the source and drain potentials are changed from the ground potential to -1 V, electrons in the FG gather on the CG side, and SILC is reduced.

  On the other hand, the DL lifetime of the memory cell storing the data of the logic level “11” is shortened. This is because SILC occurs in the direction in which electrons are injected from the well, the source and the drain into the FG in the memory cell having the threshold voltage distribution corresponding to the logic level “11”. This is because if the source and drain potentials are changed from the ground potential to −1 V, the well, source and drain electrons are attracted in the direction of FG, and SILC is increased.

  Therefore, in the nonvolatile semiconductor memory device according to the second embodiment of the present invention, the DL life of the memory cell storing the data of the logic level “11” is shortened, but the data of the logic level “11” is stored. By extending the lifetime of the logic level “00” having a short lifetime for the memory cell, the DL lifetime of the entire nonvolatile semiconductor memory device can be increased.

  The operation in the standby state of the nonvolatile semiconductor memory device according to the second embodiment of the present invention is not limited to the above. Hereinafter, a case where the potential relationship between the memory cell and the memory array 1 in the standby state is other than the potential relationship shown in FIGS. 7 and 8 will be described.

  Contrary to the case shown in FIG. 4, when the UV Vth is closer to the threshold voltage distribution corresponding to the logical level “01” than the logical level “10”, the logical level “11” in the conventional standby state. A memory cell that stores data has a shorter DL life than a memory cell that stores data of logic level “00”.

  In this case, in the nonvolatile semiconductor memory device according to the second embodiment of the present invention, the ground voltage is supplied to the CG of the memory cell of the memory array 1 in the standby state, and the well, source and drain of the memory cell are supplied. Is supplied with a positive voltage, for example, 1V.

  When the voltage supplied to the well, drain, and source is changed from the ground voltage to 1 V in the standby state, the DL life of the memory cell storing the data of the logic level “00” is shortened. This is because, in the memory cell having the threshold voltage distribution corresponding to the logic level “00”, SILC occurs in the direction in which the electrons in the FG escape to the well, the source and the drain as described above. This is because when the source and drain potentials are changed from the ground potential to 1 V, electrons in the FG are attracted toward the well, source and drain, and SILC is increased.

  On the other hand, the DL life of the memory cell storing the data of the logic level “11” is extended. This is because SILC occurs in the direction in which electrons are injected from the well, the source and the drain into the FG in the memory cell having the threshold voltage distribution corresponding to the logic level “11”. This is because if the source and drain potentials are changed from the ground potential to 1 V, electrons in the FG gather on the well, source and drain sides, and SILC is reduced.

  Therefore, even when the relationship between the DL lifetimes is opposite to that in FIG. 4, in the nonvolatile semiconductor memory device according to the second embodiment of the present invention, the DL lifetime of the memory cell storing the data of the logic level “00” is short. However, by increasing the lifetime of the logic level “11” having a short lifetime for the memory cell storing the data of the logic level “00”, the DL lifetime can be extended in the entire nonvolatile semiconductor memory device.

  The logic unit 2 may have all the memory cells of the memory array 1 in the potential relationship shown in FIG. 7, or only the memory cell corresponding to the data area that requires high data retention characteristics is shown in FIG. It may be a relationship.

  Further, the logic unit 2 is configured to supply a voltage other than the ground voltage to the well, drain, and source of the memory cell of the memory array 1 when the nonvolatile semiconductor memory device is in the standby state. It is not a thing.

  The logic unit 2 supplies a voltage other than the ground voltage to any one of the well, drain and source of the memory cell in the standby state, and supplies the ground voltage to the other part of the memory cell. can do. With such a configuration, the capacity load can be reduced. For example, when a voltage other than the ground voltage is supplied only to the drain, if the supply voltage to the drain is within a range where the current due to the forward bias between the drain and the well can be kept small, the current for charging the source and the well Is no longer necessary. In addition, when a voltage other than the ground voltage is supplied only to the drain, even if the supply voltage to the drain is in a range where the current due to the forward bias between the drain and the well cannot be kept small, by floating the well, No current is required to charge the source. In particular, when SILC occurs frequently near the drain, it is equivalent to supplying a voltage other than the ground voltage to all wells, drains, and sources while preventing current consumption for charging other parts of the memory cell. Data retention characteristics can be realized. In the nonvolatile semiconductor memory device according to the first embodiment, a voltage other than the ground voltage is supplied to the gate of the memory cell, and the ground voltage is supplied to the well, drain, and source. This has the effect of reducing current consumption.

  The logic unit 2 supplies a voltage other than the ground voltage to the well of the memory cell and one of the drain and the source in the standby state and supplies the ground voltage to the other part of the memory cell. It can be. With such a configuration, the capacity load can be reduced. For example, when a voltage other than the ground voltage is supplied to the drain and well, no current is required to charge the source.

  Further, in the standby state, if a voltage other than the ground voltage is supplied only to the well, the time until the memory cell is first read after the transition from the standby state to the normal state of the present embodiment, and It can be prevented that the time from the first reading to the memory cell in the normal state until the transition to the standby state of this embodiment becomes long. In the configuration in which a voltage other than the ground voltage is applied to the control gate, drain, or source in the standby state, the control gate, drain is first read out from the memory cell after transition from the standby state to the normal state in the present embodiment. Alternatively, the source potential needs to be changed from the potential in the standby state of this embodiment. However, since the well potential does not affect the threshold voltage of the memory cell, in the configuration in which a voltage other than the ground voltage is supplied only to the well, This is because it is not necessary to change the voltage supplied to the well in this state and in the standby state of the present embodiment.

  Here, since a memory cell of a general flash memory is an NMOS (N-Channel metal oxide semiconductor), if the source or drain has a potential other than the ground potential, the well also has a potential other than the ground potential. In the case of a flash memory in which the cell is a P-MOS, a voltage other than the ground voltage is supplied to any one of the well, drain and source of the memory cell, and the other part of the memory cell is grounded. It can be set as the structure which supplies a voltage.

  As described above, in the nonvolatile semiconductor memory device according to the second embodiment, as in the nonvolatile semiconductor memory device according to the first embodiment, the self-bias of the memory cell storing data of each logic level is reduced. It is possible to reduce the difference in DL lifetime due to the difference and to prolong the DL lifetime in the entire nonvolatile semiconductor memory device, that is, to reduce deterioration of data retention characteristics.

  In the non-volatile semiconductor memory device according to the second embodiment of the present invention, the same voltage other than the ground voltage is supplied to the well, source and drain of the memory cell of the memory array 1 to thereby charge the logic unit 2 and the charge. The processing of the pump circuit 3 and the Y gate 5 can be simplified.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Third Embodiment>
The present embodiment relates to a nonvolatile semiconductor memory device in which CG, well, drain, and source of a memory cell are set to a potential other than the ground potential in a standby state. The configuration and basic operation of the nonvolatile semiconductor memory device according to the present embodiment are the same as those of the nonvolatile semiconductor memory device according to the first embodiment.

  Next, the operation in the standby state of the nonvolatile semiconductor memory device according to the third embodiment of the invention will be described.

[Operation]
In the case shown in FIG. 4, in the nonvolatile semiconductor memory device according to the third embodiment of the present invention, in the standby state, a positive voltage, for example, 1 V is supplied to the CG of the memory cells of the memory array 1, and the memory A negative voltage, for example -1 V, is supplied to the well, source and drain of the cell. Hereinafter, this operation will be described in detail.

  FIG. 9 is a diagram showing an example of the potential relationship of the memory cells in the standby state of the nonvolatile semiconductor memory device according to the third embodiment of the present invention.

  FIG. 10 is a diagram showing an example of the potential relationship of the memory array 1 in the standby state of the nonvolatile semiconductor memory device according to the third embodiment of the invention.

  When the nonvolatile semiconductor memory device is in a standby state, the logic unit 2 controls the charge pump circuit 3 and the X decoder 4 to supply a positive voltage to the CG of the memory cell, and a negative voltage to the well and source of the memory cell. And the charge pump circuit 3, Y gate 5 and Y decoder 6 are controlled to supply a negative voltage to the drain of the memory cell.

  More specifically, when the chip enable signal received from the outside via the I / O buffer 8 indicates disable, the logic unit 2 sends a control signal indicating a command for generating a positive voltage and a negative voltage to the charge pump circuit. 3 and outputs to the X decoder 4 a control signal representing an instruction for selecting all the word lines, a control signal representing an instruction for deselecting all wells, and a control signal representing an instruction for deselecting all source lines. , A control signal representing an instruction for deselecting all drains is output to Y decoder 6.

  The charge pump circuit 3 receives a control signal from the logic unit 2 to generate a positive voltage and a negative voltage, and outputs the positive voltage and the negative voltage to the X decoder 4. Further, the charge pump circuit 3 outputs the generated negative voltage to the Y gate 5 via the write driver 10.

  X decoder 4 receives a control signal from logic unit 2 and selects all word lines. X decoder 4 drives all word lines of memory array 1 with a positive voltage received from charge pump circuit 3. The X decoder 4 receives a control signal from the logic unit 2 and deselects all source lines and wells of the memory array 1. X decoder 4 drives all source lines and wells of memory array 1 with a negative voltage received from charge pump circuit 3.

  Y decoder 6 receives a control signal from logic unit 2, generates a selection signal indicating that all sub-bit lines of memory array 1 are not selected, and outputs the selection signal to Y gate 5.

  Y gate 5 receives a selection signal from Y decoder 6 and drives all sub-bit lines of memory array 1 with the negative voltage received from charge pump circuit 3.

  When the voltage supplied to the CG of the memory cell is changed from the ground voltage to 1V in the standby state, and the voltage supplied to the well, source and drain of the memory cell is changed from the ground voltage to −1V in the standby state, In the memory cell having the threshold voltage distribution corresponding to the level “00”, as described above, electrons in the FG gather on the CG side and SILC is reduced. On the other hand, in the memory cell having the threshold voltage distribution corresponding to the logic level “11”, the well, source and drain electrons are attracted in the direction of FG as described above, and SILC is increased.

  Therefore, in the nonvolatile semiconductor memory device according to the third embodiment of the present invention, the DL life of the memory cell storing the data of the logic level “11” is shortened, but the data of the logic level “11” is stored. By extending the lifetime of the logic level “00” having a short lifetime for the memory cell, the DL lifetime of the entire nonvolatile semiconductor memory device can be increased.

  In contrast to the case shown in FIG. 4, when the UV Vth is closer to the threshold voltage distribution corresponding to the logic level “01” than the logic level “10”, the third embodiment of the present invention is applied. In such a nonvolatile semiconductor memory device, in a standby state, a negative voltage, for example, -1 V is supplied to the CG of the memory cell of the memory array 1, and a positive voltage, for example, 1 V is supplied to the well, source and drain of the memory cell. .

  When the voltage supplied to the CG of the memory cell is changed from the ground voltage to -1V in the standby state, and the voltage supplied to the well, source and drain of the memory cell is changed from the ground voltage to 1V in the standby state, In the memory cell having the threshold voltage distribution corresponding to the level “00”, as described above, electrons in the FG are attracted toward the well, source, and drain, and SILC is increased. On the other hand, in a memory cell having a threshold voltage distribution corresponding to the logic level “11”, electrons in the FG gather on the well, source and drain sides as described above, and SILC is reduced.

  Therefore, even when the relationship between the DL lifetimes is opposite to that in FIG. 4, in the nonvolatile semiconductor memory device according to the third embodiment of the present invention, the DL lifetime of the memory cell storing the data of the logic level “00” is short. However, by increasing the lifetime of the logic level “11” having a short lifetime for the memory cell storing the data of the logic level “00”, the DL lifetime can be extended in the entire nonvolatile semiconductor memory device.

  As described above, in the nonvolatile semiconductor memory device according to the third embodiment, as in the nonvolatile semiconductor memory device according to the first embodiment, the self-bias of the memory cell storing data of each logic level is reduced. It is possible to reduce the difference in DL lifetime due to the difference and to prolong the DL lifetime in the entire nonvolatile semiconductor memory device, that is, to reduce deterioration of data retention characteristics.

[Modification]
The present invention is not limited to the above embodiment, and includes, for example, the following modifications.

(1) Types of Memory The nonvolatile semiconductor memory device according to the embodiment of the present invention has been described on the assumption that it is a NOR flash memory. However, the present invention is not limited to this, and a difference in threshold voltage is used. The present invention can be applied to any nonvolatile memory that stores data. For example, a NAND flash memory and an AG-AND flash memory may be used, and the present invention can also be applied to an NROM (Nitride Read Only Memory) that accumulates charges in an insulating film layer such as a nitride film.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1A is a diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. FIG. 2B is a diagram illustrating a structure of the memory array 1. (A) It is a figure which shows the operation | movement of (a) erase (b) write (c) read-out with respect to the memory cell of the non-volatile semiconductor memory device concerning the 1st Embodiment of this invention. FIG. 3 is a diagram showing a threshold voltage of a memory cell when the nonvolatile semiconductor memory device according to the first embodiment of the present invention stores 2-bit data. It is a figure which shows the relationship between DL lifetime and the voltage supplied to a control gate. FIG. 3 is a diagram showing an example of a potential relationship of memory cells in a standby state of the nonvolatile semiconductor memory device according to the first embodiment of the invention. 3 is a diagram showing an example of a potential relationship of the memory array 1 in a standby state of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a diagram showing an example of a potential relationship of memory cells in a standby state of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. FIG. FIG. 6 is a diagram showing an example of a potential relationship of the memory array 1 in a standby state of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. FIG. 6 is a diagram showing an example of a potential relationship of memory cells in a standby state of a nonvolatile semiconductor memory device according to a third embodiment of the present invention. It is a figure which shows an example of the electric potential relationship of the memory array in the standby state of the non-volatile semiconductor memory device which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Memory array, 2 logic part, 3 charge pump circuit, 4 X decoder, 5 Y gate, 6 Y decoder, 7 address buffer, 8 I / O buffer, 9 sense amplifier, 10 write driver, 50 voltage generation part.

Claims (3)

A non-volatile semiconductor memory device,
A plurality of memory cells for storing data using a difference in threshold voltage are provided ,
The threshold voltage of each of the memory cells is set to be included in any one of a plurality of threshold voltage distributions corresponding to stored data,
The nonvolatile semiconductor memory device further includes:
A voltage generator for generating a voltage to be supplied to the memory cell;
In the standby state, the voltage generator is controlled to supply a voltage between the ground voltage and the lower limit of the threshold voltage distribution of the lowest voltage to the control gate of the memory cell, and the well, drain of the memory cell And a non-volatile semiconductor memory device having a logic unit for supplying the ground voltage to the source. The nonvolatile semiconductor memory device according to claim 1, wherein the logic unit determines whether to control the voltage generation unit in the standby state based on an instruction from the outside. In the standby state, the logic unit controls the voltage generation unit to provide a predetermined amount between a control gate in a part of the plurality of memory cells and at least one of a well, a drain, and a source. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the potential difference between the control gate, the well, the drain, and the source in the memory cells other than the part of the memory cells is the same.

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