JP4790277B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

The present invention relates to a solid-state imaging device and a manufacturing method thereof .

  The CCD solid-state imaging device includes a semiconductor substrate having an imaging region, an insulating layer covering the surface of the semiconductor substrate, a horizontal shift register that transfers charges generated in the imaging region, and a semiconductor substrate at an end of the horizontal shift register. A reset FET having a gate electrode provided on the insulating layer; and a signal reading FET having a gate electrode provided on the insulating layer.

  That is, an insulating layer is interposed between the semiconductor substrate and the gate electrode, and this structure is called a MIS (Metal Insulator Semiconductor) structure. An insulating layer is also interposed between the transfer electrode of the shift register and the semiconductor substrate, and this also constitutes a MIS structure.

Conventionally, a semiconductor oxide layer made of a single material has been used for the insulating layer of the MIS structure. That is, it is a silicon oxide film. On the other hand, an insulating layer having a three-layer structure is also known. This insulating layer is an ONO film. The ONO film is made of SiO ₂ / Si ₃ N ₄ / SiO ₂ and is used for a MONOS (Metal / SiO ₂ / Si ₃ N ₄ / SiO ₂ / Si) structure.

In the ONO film, the etching amount and the oxidation amount of Si ₃ N ₄ can be made sufficiently small when the pattern is formed by etching polysilicon and when the polysilicon is oxidized. That is, the selectivity ratio of RIE (reactive ion etching) of polysilicon and _Si 3 _{N 4} is high, unlike the oxidation rate of the polysilicon and _Si 3 _{N 4} is increased, _Si 3 _{N 4} surface is slightly oxidized Therefore, each oxide film thickness can be made almost constant. Therefore, when the ONO film is used, the potential difference under the polysilicon transfer electrode and the gate electrode which are not simultaneously formed can be made smaller than the potential difference in the case of the silicon oxide film made of a single material.

  Accordingly, in the solid-state imaging device, it is preferable to use an ONO film as the insulating layer.

A solid-state imaging device using an ONO film is described in, for example, Patent Document 1 and Patent Document 2 below.
JP-A-5-206438 JP 2000-138364 A

  However, there is a problem that charges are accumulated inside the ONO film during plasma processing such as etching of wirings and electrodes, and the potential under the gate electrode and transfer electrode of the FET varies. That is, the threshold voltage of the FET varies. Of course, only the insulating layer in the portion where the FET is formed can be formed of a single silicon oxide film, but the potential difference between the electrodes that are not simultaneously formed by the transfer electrode using polysilicon is not reduced.

The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a solid-state imaging device capable of suppressing fluctuations in the threshold voltage of an FET and a manufacturing method thereof.

In order to solve the above-described problems, a solid-state imaging device according to the present invention includes a semiconductor substrate having an imaging region, an insulating layer that covers the surface of the semiconductor substrate, a horizontal shift register that transfers charges generated in the imaging region, A signal having a diffusion layer located in the semiconductor substrate at the end of the horizontal shift register, a reset FET having a gate electrode provided on the insulating layer, and a gate electrode provided on the insulating layer and connected to the diffusion layer a readout FET, comprises a first electrical conductor provided on an insulating layer, and a connection traces between the gate electrode and the first conductor of the reset FET, a first conductor, a reset FET The first conductor is electrically connected to the semiconductor substrate by being electrically separated from the electrode pad by passing through the connection trace inside the electrode pad that gives a reset signal to the gate electrode. Conductor Flown charge, characterized in that it is absorbed in the semiconductor substrate.

  The charges generated in the imaging area are transferred to the diffusion layer via the horizontal shift register. The charge transferred to the diffusion layer is read out through the gate of the signal reading FET, and the diffusion layer is reset by the resetting FET after the charge is read out. Since the gate electrode of the reset FET is connected to the first conductor, the charge accumulated in the insulating layer near the gate electrode has already flowed from the gate electrode to the first conductor for charge absorption. . Since the gate electrode and the first conductor are disconnected, a connection trace remains. Note that although this electric charge is accumulated in the insulating layer during the plasma treatment, it is absorbed by the first conductor, so that potential fluctuations directly under the insulating layer can be suppressed.

Further, the solid-state imaging device includes a second conductor provided on an insulating layer, it is preferable to provide a connection traces between the transfer electrode and the second conductor of the horizontal shift register. That is, the transfer electrode of the horizontal shift register is also formed on the insulating layer, and electric charges are accumulated during plasma processing, and potential fluctuations in the region immediately below the transfer electrode may occur. This electric charge is applied to the second conductor. After being absorbed, the connection wiring between the transfer electrode and the second conductor is cut to leave a connection trace. Although this electric charge is accumulated in the insulating layer during the plasma treatment, it is absorbed by the second conductor, so that potential fluctuations directly under the insulating layer can be suppressed. The transfer electrode here includes a summing gate that is a final clock gate, and an output gate that exists between the diffusion layer and the summing gate and determines the potential of charge transfer to the diffusion layer. As a result, potential fluctuations during charge transfer to the diffusion layer can also be suppressed.

The first conductor is positioned inside the electrode pad that applies a reset signal to the gate electrode of the reset FET . Since the first conductor is connected to the electrode pad before separation, the first conductor can absorb the electric charge, and after that, the first conductor is cut to be located inside the electrode pad. In this case, the total area of the electrode pad, the first conductor, and these connection conductors can be significantly reduced.

  When the insulating layer is formed by sequentially laminating the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer, these constitute an ONO film, and therefore, between the electrodes that are not simultaneously formed by the transfer electrode using polysilicon. The potential difference under the insulating layer can be reduced.

  In addition, when the first or second conductor is electrically connected to the semiconductor substrate, the charge flowing from the gate electrode to the first conductor can be absorbed into the semiconductor substrate, and transfer can be performed. The charge flowing from the electrode to the second conductor can be absorbed in the semiconductor substrate.

  The charge accumulation preventing structure according to the present invention is located in a semiconductor substrate, an FET formed on the semiconductor substrate, an electrode pad for applying a reset signal to the gate electrode of the FET, and electrically separated inside the electrode pad, And a first conductor electrically connected to the semiconductor substrate.

  The first conductor is connected to the electrode pad before separation, and the charge can be absorbed by the first conductor. After the charge absorption, the first conductor is electrically separated from the electrode pad inside the electrode pad. In this case, the total area of the electrode pad, the first conductor, and these connection conductors can be significantly reduced.

The solid-state imaging device manufacturing method according to the present invention includes an insulating layer forming step for forming an insulating layer, a reset FET gate electrode, and a solid-state imaging device manufacturing method for manufacturing the solid-state imaging device described above. A connection step of connecting the first conductor, a plurality of plasma processing steps of disposing a semiconductor substrate in the plasma, and after completion of all the plasma processing steps, the gate electrode of the reset FET and the first conductor Cutting and forming a connection trace .

  According to this manufacturing method, charges are accumulated in the insulating layer in each plasma processing step, and the charges flow from the gate electrode to the first conductor. Since the gate electrode and the first conductor are disconnected after the end of the last plasma treatment step, potential fluctuations immediately below the insulating layer of the gate electrode can be suppressed. The cutting may be performed simultaneously with the plasma treatment process.

  The method for manufacturing the solid-state imaging device includes a connection step of connecting the gate electrode of the reset FET and the first conductor. That is, the gate electrode and the first conductor are connected in advance, and charge flows from the gate electrode to the first conductor.

  When the insulating layer in this manufacturing method is formed by sequentially laminating a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer, these constitute an ONO film, so that they are simultaneously formed with a transfer electrode using polysilicon. The potential difference under the insulating layer between the electrodes that cannot be reduced can be reduced.

  The solid-state imaging device manufacturing method includes a protective layer forming step of forming a protective layer covering the gate electrode of the reset FET and the first conductor, and a light shielding film forming step of forming a light shielding layer on the protective layer. And the formation process of any one of the layers is the plasma treatment process described above. That is, the protective layer formation and the light shielding layer formation can be a plasma treatment process, but when the corresponding plasma treatment process is the final plasma treatment process, this can be the last charge accumulation process, and thus the plasma treatment is completed. Thereafter, the first conductor may be cut from the gate electrode.

According to the solid-state imaging device and the manufacturing method thereof of the present invention, the threshold voltage fluctuation of the reset FET can be suppressed.

  Hereinafter, a solid-state imaging device including the charge accumulation preventing structure according to the embodiment and a manufacturing method will be described. Note that the same reference numerals are used for the same elements, and redundant description is omitted.

  FIG. 1 is a plan view of a solid-state imaging device according to an embodiment.

  The solid-state imaging device 1 includes a semiconductor substrate 2 having an imaging region (vertical shift register) 3, a horizontal shift register 4 that transfers charges generated in the imaging region 3, and an output unit provided at an end of the horizontal shift register 4. And 5. The charges generated in the imaging region 3 are transferred to the horizontal shift register 4 through the vertical shift register and read out through the output unit 5 provided at the end of the horizontal shift register 4.

  FIG. 2 is an enlarged view of the output unit 5.

A floating diffusion layer FD is provided at the end of the horizontal shift register 4 via an output gate electrode OG. The diffusion layer FD is connected to the gate electrode of a field effect transistor (FET) TR for signal reading and is connected to the field effect transistor (FET) Q _R source for resetting. The drain of the signal reading field effect transistor TR is grounded via a resistor Z. When charge is input to the gate electrode, the charge flows from the power supply VDD to the resistor Z via the source, and the resistance Z The potential difference is output as the output voltage VOUT. When a reset signal is input to the reset gate terminal RG after reading the output voltage VOUT from one pixel, charge flows from the reset drain terminal RD to the diffusion layer FD, and the diffusion layer FD is reset.

  FIG. 3 is a diagram illustrating a circuit configuration in the vicinity of the output unit 5.

  First, the surface of the semiconductor substrate 2 is covered with the insulating layer 6. The horizontal shift register 4 includes transfer electrodes T1, T2, T3, T4, and T5 disposed on the insulating layer 6. When a charge transfer clock signal is applied to the terminal P1, a positive potential is applied to the transfer electrodes T1 and T2, and negative charges are accumulated in the semiconductor substrate 2 directly below the transfer electrodes T1 and T2 via the insulating layer 6. By applying a charge transfer clock signal having a phase different from that to the terminal SG, charges are transferred under the insulating layer 6 immediately below the adjacent transfer electrodes T3 and T4. An output gate electrode T5 is provided between the horizontal shift register 4 and the diffusion layer FD, and a constant voltage is applied from the output gate terminal OG as necessary. The output gate terminal OG is a terminal that exists between the diffusion layer and the summing gate and is connected to an output gate that determines the potential for charge transfer to the diffusion layer. In this way, the charges generated in the imaging region 3 are transferred to the diffusion layer FD via the horizontal shift register 4.

The reset gate terminal RG is connected to the first conductor (resistor R ₁ ) via the connection trace RG ′. Further, the terminal SG for applying a clock signal to the transfer electrode is connected to the conductor (resistor) R ₂ via the connection trace SG ′. This terminal SG is a terminal connected to the summing gate which is the final clock gate. The terminal OG is also connected to the conductor (resistor) R ₂ via the connection trace OG ′. Although not shown, the opposite side to which the connection trace RG ′ of the _first conductor (resistance R ₁ ) is connected is connected to the semiconductor substrate 2.

The above-described solid-state imaging device includes a diffusion layer FD located in the semiconductor substrate 2, a reset FET (Q _R ) having a gate electrode provided on the insulating layer 6, and a diffusion layer FD provided on the insulating layer 6. A signal readout FET (TR) having a gate electrode connected to the gate electrode, a charge absorbing first conductor R ₁ provided on the insulating layer 6, a gate electrode of the reset FET (Q _R ), And a connection trace RG ′ with _one conductor R ₁ .

The charge transferred to the diffusion layer FD is read out through the gate of the signal readout FET (TR), and the diffusion layer FD is reset by the reset FET (Q _R ) after the charge is read out. Since the gate electrode of the reset FET (Q _R ) is connected to the _first conductor R ₁ , in the finished product after cutting, the charge accumulated in the insulating layer 6 near the gate electrode is Already flowing from the electrode to the first conductor R ₁ for charge absorption. Since the gate electrode and the first conductor R ₁ is disconnected, so that the connecting traces RG 'remains. Although this electric charge is accumulated in the insulating layer 6 during the plasma processing, it is absorbed by the _first conductor R1, so that potential fluctuations directly under the insulating layer 6 are suppressed.

Further, as described above, the charge-absorbing second conductor R ₂ provided on the insulating layer 6 and the transfer electrodes T 3 and T 4 of the horizontal shift register 4 and the second conductor R ₂ are interposed between the _second conductor R ₂ and the _second conductor R _2. There is a connection trace SG ′. The transfer electrodes T3 and T4 of the horizontal shift register 4 are formed on the insulating layer 6, and charges are accumulated during the plasma processing, and potential fluctuations in the region immediately below the transfer electrodes T3 and T4 may occur. is absorbed in the second conductor R _2, thereafter, the transfer electrodes T3, T4 and the second connecting wire conductor R ₂ is disconnected, the connection traces SG 'remains. Although this electric charge is accumulated in the insulating layer 6 during the plasma processing, it is absorbed by the _second conductor R ₂ , so that potential fluctuations directly under the insulating layer 6 can be suppressed. Although not shown, the opposite side where the connection traces SG ′ and OG ′ of the second conductor R ₂ are connected is connected to the semiconductor substrate 2.

  FIG. 4 is a perspective view of the vicinity of the output unit 5.

  A P-type well layer 22 is formed in the surface region of the N-type substrate of the semiconductor substrate 2, and an N-type well layer 21 is formed in the P-type well layer 22. The surface of the semiconductor substrate 2 is covered with an insulating layer 6. The insulating layer 6 is formed by sequentially laminating a first silicon oxide layer 6a, a silicon nitride layer 6b, and a second silicon oxide layer 6c to form a so-called ONO film, and an electrode that is not formed simultaneously with a transfer electrode using polysilicon. The potential difference under the insulating layer 6 is set small.

On the insulating layer 6, transfer electrodes T1, T2, T3, T4 and an output gate electrode T5 constituting the horizontal shift register 4 are formed. The transfer electrodes T3, T4 are electrically connected to the electrode pad SG. ing. The electrode pad SG is rectangular or circular, but the conductor extending from the electrode pad SG extends to the connection trace SG ′, and a resistance (conductor) R ₂ is continuous with the connection trace SG ′. The output gate electrode T5 is electrically connected to the electrode pad OG. The electrode pad OG is rectangular or circular, but the conductor extending from the electrode pad OG extends to the connection trace OG ′, and the resistance (conductor) R ₂ is continuous with the connection trace OG ′. Although not shown, the opposite side to which the connection trace RG ′ of the _first conductor (resistor R ₁ ) is connected is connected to the semiconductor substrate 2 and the connection trace SG ′ of the _second conductor R _2. And OG ′ are connected to the semiconductor substrate 2 on the opposite side.

On the high-concentration N-type floating diffusion layer FD, an electrode TF is provided through a contact hole of the insulating layer 6, and the electrode TF is connected to the source electrode TS of the reset FET (Q _R ). Yes. In this example, a structure in which the floating diffusion layer FD and the source region S of the reset FET (Q _R ) are separated is illustrated. The source electrode TS is connected to an N-type source region S, and the source region S is connected to an N-type drain region D through a P-type well layer 22. A drain electrode TD is provided on the drain region D via a contact hole, and the drain electrode TD is connected to the electrode pad RD. The gate electrode TG of the reset FET (Q _R ) is formed on the insulating layer 6 and is connected to the electrode pad RG. Although the electrode pads RG is rectangular or circular, conductors extending from the electrode pad RG is 'extends to the connection trace RG' connection traces RG resistor in (conductor) R ₁ are continuous. When a positive voltage is applied to the gate electrode TG, an n-type channel is formed in the P-type well layer 22, the drain region D and the source region S (floating diffusion layer FD) are electrically connected, and the floating diffusion layer The potential of the FD becomes the potential of the reset electrode pad RD (reset).

In the drawing, for clarity of structure, the transistor Q _R for reset, exhibits a type which is separate from the floating diffusion layer FD, which is of the type that share the floating diffusion layer FD as the source region It can also be an FET.

Further, the first conductor R ₁ or the second conductor R ₂ is preferably configured to meander pattern. In this case, the resistance of the conductor per unit area can be increased, and charges can be efficiently absorbed without increasing the flowing current.

  A high-concentration N-type isolation layer 10 is formed around the semiconductor chip. The isolation layer 10 may be a high concentration P-type.

  FIG. 5 is a plan view of the semiconductor wafer 100 on which a plurality of solid-state imaging devices 1 are formed. Dicing lines 11 are provided in a lattice shape on the surface of the semiconductor wafer 100, and the solid-state imaging device 1 is located in each lattice. The dicing line 11 is parallel or perpendicular to the orientation flat OF.

FIG. 6 is an enlarged view of one of the solid-state imaging devices 1 shown in FIG. The imaging region 3 is connected to the horizontal shift register 4 and the output of the horizontal shift register 4 is read out via the output amplifier TR. The floating diffusion layer provided at the output of the horizontal shift register 4, via the reset transistor Q _R, is connected to the electrode pad RG, the first conductor located inside of the electrode pad RG is N-type semiconductor substrate Connected to the isolation layer 10. In this example, an interline transfer type imaging device is shown, and the imaging region 3 is output from a group of a plurality of photodiodes 3a arranged in a matrix and each photodiode 3a arranged in the column direction. It comprises a plurality of vertical shift registers 3b for transferring charges in the vertical direction. The present invention is not limited to this transfer method.

  FIG. 7 is an enlarged view of the electrode pad RG shown in FIG.

The charge accumulation preventing structure of this example includes a semiconductor substrate 2, an FET (Q _R ) formed on the semiconductor substrate 2, an electrode pad RG that applies a reset signal to the gate electrode TG of the FET (Q _R ), and a conductor R _1, first conductor R ₁ is located inside of the electrode pad RG. Since the electrode pad RG is connected to the _first conductor R ₁ before separation, the charge can be absorbed by the _first conductor R ₁ , and after that, by being cut, located inside, but in this case, can be significantly reduced electrode pad RG, the total area of the first conductor R ₁ and these connection conductors. Immediately below the first conductor R _1, located N-type diffusion layer DL, charges flown into the first conductor R ₁ is absorbed in the semiconductor substrate through the diffusion layer DL. Connection traces RG 'is interposed between the first conductor R ₁ and the electrode pad RG.

  The connection trace RG ′ is a trace where an electrode pad is first formed on the substrate surface including the diffusion layer DL, and then a portion of the conductor located around the diffusion layer DL is removed by etching. The conductor is removed after all the plasma processing steps are completed. In the plasma processing step, charges accumulated in the insulating layer immediately below the electrode to which the electrode pad is connected are transferred to the semiconductor substrate 2. Absorbed.

Note that the second conductor R ₂ shown in FIG. 4 can also have the same structure as the first conductor R 1 shown in FIG. 7 and can be electrically connected to the semiconductor substrate 2.

As described above, when the first conductor R ₁ is electrically connected to the semiconductor substrate 2, the charge flowing from the gate electrode TG to the first conductor R ₁ is absorbed into the semiconductor substrate 2. In addition, when the second conductor R ₂ is electrically connected to the semiconductor substrate 2, the charge flowing from the transfer electrode T 5 to the second conductor R ₂ is transferred into the semiconductor substrate 2. Can be absorbed.

  FIG. 8 is a plan view of the signal readout unit of the solid-state imaging device 1 when the floating diffusion layer FD is used as the source region of the reset FET. 9 is a cross-sectional view taken along arrow IX-IX in FIG.

The N type floating diffusion layer FD constitutes the source region of the reset FET (Q _R ), and by applying a positive voltage to the reset gate electrode TG, an N type channel is formed immediately below the gate electrode TG. The drain region D and the floating diffusion layer FD are connected. Note that the width of the N-type well layer 21 (the length in the direction perpendicular to the longitudinal direction of the horizontal shift register 4) is narrow in the vicinity of the floating diffusion layer FD, and the transferred charges are efficiently collected. The

Figure 10 is an electron micrograph of peripheral electrode pads including a first conductor R ₁ and second conductors R _2. FIG. 11 is an enlarged micrograph of the connection trace RG ′.

Wire that was connected to the first conductor R ₁ and the electrode pad RG has been removed, the connection traces RG 'can be observed.

Next, a method for manufacturing the above-described solid-state imaging device 1 will be described. Polysilicon can be used as the material of the first conductor R ₁ and the second conductor R ₂ , but the material of the wiring W 1 that connects the electrode and each conductor is metal (Al or the like). Or polysilicon is listed.

  12 and 13 are views for explaining a manufacturing method in the case where a metal is used as the wiring W1.

First, an insulating layer 6 shown in FIG. 4 on the semiconductor substrate 2, and thereafter, a gate electrode TG and the conductor R ₁ is formed on the insulating layer 6 (a). Gate electrode TG and the conductor _{R 1} is made of polysilicon. Then, covering the gate electrode TG and the conductor _{R 1} insulating layer for passivation in _{(SiO 2) 61 (b)} . Next, a contact hole H1, H2 to the portion where the gate electrode TG and the conductor _{R 1} of the insulating layer 61 is positioned (c). Then, as the gate electrode TG and the conductor R ₁ is connected to form a wiring W1 on the insulating layer 61. An electrode pad RG is formed simultaneously with the metal wiring W1 (d).

Although connection between the gate electrode TG and the conductor R ₁ is important, the electrode pad RG, since it is sufficient to ultimately position connected to the gate electrode TG, the electrode pad RG, the position of the wires W1 The relationship is described differently from that shown in FIG.

Thereafter, the insulating layer 61 and the wiring W1 are covered with a passivation insulating layer (SiO ₂ ) 62 (e). Further, a wiring cutting hole H3 and an electrode pad exposing hole H4 are formed in the insulating layer 62 for passivation (f). Next, the substrate surface is covered with a light shielding metal WS except for the imaging region (g). After the formation of the photoresist RS on the light shielding metal WS, an opening is formed between the upper portion of the wiring cutting hole H3 and the connection between the electrode pad RG and the light shielding metal WS (RIE, plasma). Processing) (h). Finally, dry etching (RIE, plasma processing) is performed from the opening of the photoresist RS to open the light shielding metal WS located above the cut portion, the insulating layer 62 is removed, and then the wiring W1 is cut ( i). Finally, the photoresist RS is removed.

  14 and 15 are diagrams illustrating a manufacturing method in the case where polysilicon is used as the wiring W1.

First, an insulating layer 6 shown in FIG. 4 on the semiconductor substrate 2, and thereafter, to simultaneously form a gate electrode TG and the conductor R ₁ on the insulating layer 6 (a). Gate electrode TG and the conductor R ₁ consists of polysilicon, which are connected to polysilicon as a wiring W1. Then, covering the gate electrode TG and the conductor _{R 1} insulating layer for passivation in _{(SiO 2) 61 (b)} . Next, a contact hole H1 is formed at a location where the gate electrode TG of the insulating layer 61 is located (c). Next, a metal film is formed on the insulating layer 61 so that the wiring W1 ′ and the electrode pad RG are formed on the gate electrode TG (d).

Although connection between the gate electrode TG and the conductor R ₁ is important, the electrode pad RG, since it is sufficient to ultimately position connected to the gate electrode TG, the electrode pad RG, the position of the wires W1 The relationship is described differently from that shown in FIG.

After that, the insulating layer 61 and the wiring W1 ′ are covered with a passivation insulating layer (SiO ₂ ) 62 (e). Further, an electrode pad exposing hole H4 is formed in the passivation insulating layer 62 (f). Next, the substrate surface is covered with a light shielding metal WS except for the imaging region (g). After the formation of the photoresist RS on the light shielding metal WS, an opening is formed between the upper portion of the portion for cutting the wiring of the photoresist RS and the connection portion between the electrode pad RG and the light shielding metal WS. The metal WS is opened by dry etching (RIE, plasma treatment) (h). Thereafter, dry etching is continued from the opening of the photoresist RS to remove the insulating layer 62 located on the cut portion (RIE, plasma treatment), and then the wiring W1 ′, the insulating layer 61, and the wiring W1 are sequentially removed. Cutting (RIE, plasma treatment) (i). Finally, the photoresist RS is peeled off (j).

  Note that the above-described insulating layer, wiring, contact hole, and dry etching are all plasma processing steps.

  That is, when an insulating layer is formed, the insulating layer is deposited by using an insulating layer material as a target material by sputtering and exposing it to a plasma environment. When forming the wiring, the wiring material is deposited by using a wiring material (metal or polysilicon) as a target material by sputtering and exposing it to a plasma environment. Contact holes are formed and dry etching is performed by exposing an exposed surface of an insulator or metal in an etching gas in a plasma environment. The wiring W1 is cut before the final high temperature treatment (900 ° C. or higher).

As described above, the method for manufacturing the solid-state imaging device described above transfers the semiconductor substrate 2 having the imaging region 3, the insulating layer 6 covering the surface of the semiconductor substrate 2, and the charges generated in the imaging region 3. Horizontal shift register 4, diffusion layer FD located in semiconductor substrate 2 at the end of horizontal shift register 4, reset FET (Q _R ) having gate electrode TG provided on insulating layer 6, insulating layer A solid-state imaging device including a signal readout FET (TR) having a gate electrode provided on the gate electrode 6 and connected to the diffusion layer FD, and a first conductor R ₁ for charge absorption provided on the insulating layer 6. In the device manufacturing method, an insulating layer forming step for forming the insulating layer 6 (FIGS. 12B and 14B) and a plurality of plasma processing steps for disposing the semiconductor substrate 2 in the plasma (FIG. 12A ) To (f), FIG. 13 (g), i), FIG. 14 (a) ~ (f) , FIG. 15 (g) ~ (i) ) and, after the completion of all of the plasma treatment process, the first conductor and the gate electrode TG of the reset FET _{R 1} And a step (FIG. 13 (i), FIG. 15 (i)).

According to this manufacturing method, in the plasma treatment step, the charge in the insulating layer are accumulated, the charge flows from the gate electrode TG in the first conductor R _1. After the end of the last of the plasma processing step, to be cut to the conductor R ₁ of the gate electrode TG and the first, it is possible to suppress the potential variation immediately below the insulating layer of the gate electrode TG.

Further, the method of manufacturing the solid state imaging device includes a connection step of connecting the gate electrode TG of the first conductor R ₁ of the reset FET (FIG 12 (d)). That is, the gate electrode TG and the first conductor R ₁ are connected before cutting, and electric charge flows from the gate electrode TG to the first conductor R ₁ .

  The insulating layer 6 in this manufacturing method is formed by sequentially laminating a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer, and below the insulating layer 6 between the electrodes that are not simultaneously formed by the transfer electrode using polysilicon. The potential difference can be reduced.

Further, the method of manufacturing the solid state imaging device, the protective layer forming step of forming a protective layer 61 covering the gate electrode TG of the first conductor R ₁ of the reset FET (FIG. 12 (b), the FIG. 14 (b )) And a light-shielding film forming step (FIG. 13G, FIG. 15G) for forming the light-shielding layer WS on the protective layer, and these forming steps are plasma processing steps. Although the protective layer 61 and the light shielding layer WS are plasma processing steps, when the corresponding plasma processing step is the final plasma processing step, this may be the final charge accumulation processing, and thus the first charge processing is performed after the plasma processing is completed. the conductor R ₁ may be disconnected from the gate electrode TG. In the above example, the cutting process itself constitutes the plasma processing process.

The present invention can be used in a solid-state imaging device and a manufacturing method thereof.

It is a top view of the solid-state imaging device concerning an embodiment. 4 is an enlarged view of an output unit 5. FIG. 3 is a diagram illustrating a circuit configuration in the vicinity of an output unit 5. FIG. 6 is a perspective view of the vicinity of an output unit 5. FIG. 1 is a plan view of a semiconductor wafer 100 on which a plurality of solid-state imaging devices 1 are formed. It is one enlarged view of the solid-state imaging device 1 shown in FIG. FIG. 7 is an enlarged view of the electrode pad RG shown in FIG. 6. It is a top view of the signal reading part of the solid-state imaging device 1 at the time of using the floating diffusion layer FD as a source region of resetting FET. It is IX-IX arrow sectional drawing in FIG. Is a diagram of an electron microscope photograph of peripheral electrode pads including a first conductor R ₁ and second conductors R _2. It is a figure of the enlarged micrograph of connection trace RG '. It is a figure explaining the manufacturing method at the time of using a metal as wiring W1. It is a figure explaining the manufacturing method at the time of using a metal as wiring W1. It is a figure explaining the manufacturing method at the time of using a polysilicon as wiring W1. It is a figure explaining the manufacturing method at the time of using a polysilicon as wiring W1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 2 ... Semiconductor substrate, 3a ... Photodiode, 3 ... Imaging area, 3b ... Vertical shift register, 4 ... Horizontal shift register, 5 ... Output Part, 6b ... silicon nitride layer, 6a ... silicon oxide layer, 6c ... silicon oxide layer, 6 ... insulating layer, 10 ... isolation layer, 11 ... dicing line, 21 ... Well layer, 22 ... well layer, 61 ... protective layer (insulating layer), 62 ... insulating film, 100 ... semiconductor wafer, D ... drain region, DL ... diffusion layer, FD ... floating diffusion layer, OF ... orientation flat, RG '... connection trace, W1 ... wiring.

Claims (5)

In a solid-state imaging device,
A semiconductor substrate having an imaging region;
An insulating layer covering the surface of the semiconductor substrate;
A horizontal shift register for transferring charges generated in the imaging region;
A diffusion layer located in the semiconductor substrate at an end of the horizontal shift register;
A reset FET having a gate electrode provided on the insulating layer;
A signal readout FET having a gate electrode provided on the insulating layer and connected to the diffusion layer;
A first conductor provided on the insulating layer;
A connection trace between the gate electrode of the reset FET and the first conductor;
Equipped with a,
The first conductor is electrically separated from the electrode pad through the connection trace inside the electrode pad that gives a reset signal to the gate electrode of the reset FET ,
The first conductor is electrically connected to the semiconductor substrate, and the charge flowing into the first conductor is absorbed into the semiconductor substrate . A second conductor provided on the insulating layer;
A connection trace between the transfer electrode of the horizontal shift register and the second conductor;
With
The second conductor is electrically connected to the semiconductor substrate;
The solid-state imaging device according to claim 1. The insulating layer, the first silicon oxide layer, the solid-state imaging device according to claim 1 or 2, characterized in that the silicon nitride layer and the second silicon oxide layer are sequentially stacked. In the manufacturing method of the solid-state imaging device for manufacturing the solid-state imaging device of any one of Claims 1-3,
An insulating layer forming step of forming the insulating layer;
A connection step of connecting the gate electrode of the reset FET and the first conductor;
A plurality of plasma processing steps for disposing the semiconductor substrate in plasma;
After the completion of all the plasma processing steps, cutting the gate electrode and the first conductor of the reset FET , forming the connection trace ,
A method for manufacturing a solid-state imaging device. A protective layer forming step of forming a protective layer covering the gate electrode of the reset FET and the first conductor, and a light shielding film forming step of forming a light shielding layer on the protective layer, The method for manufacturing a solid-state imaging device according to claim 4 , wherein the layer forming step is the plasma processing step described above.

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