JP4781909B2

JP4781909B2 - Printed circuit board and manufacturing method thereof, electronic component storage board and manufacturing method thereof

Info

Publication number: JP4781909B2
Application number: JP2006144975A
Authority: JP
Inventors: 佐藤　　茂樹; 保明関; 茂道脇; 孝一神山
Original assignee: Victor Company of Japan Ltd; Meiko Co Ltd
Current assignee: Victor Company of Japan Ltd; Meiko Co Ltd
Priority date: 2006-05-25
Filing date: 2006-05-25
Publication date: 2011-09-28
Anticipated expiration: 2026-05-25
Also published as: JP2007317827A

Description

本発明は、プリント基板及びその製造方法、電子部品収納基板及びその製造方法に関する。 The present invention relates to a printed circuit board and a manufacturing method thereof, an electronic component storage board and a manufacturing method thereof.

近年、電子機器に搭載するプリント基板の高密度化や信号処理の高速化に伴い、電子部品実装面積の削減や発生ノイズの低減を目的として、プリント基板内に電子部品を収納した電子部品収納基板が用いられている。 In recent years, with the increase in the density of printed circuit boards mounted on electronic devices and the speeding up of signal processing, electronic component storage boards in which electronic components are stored in printed circuit boards for the purpose of reducing the mounting area of electronic components and noise generated. Is used.

プリント基板内に収納される電子部品は、通常、市販されている表面実装型のチップ部品であり、チップ抵抗，チップコンデンサ，チップコイル等がある。
このようなチップ部品は、一般的に、長手を有する形状であり、長手方向の両端にそれぞれ電極部を有している。 Electronic components housed in a printed circuit board are usually surface-mounted chip components that are commercially available, and include chip resistors, chip capacitors, chip coils, and the like.
Such a chip component generally has a longitudinal shape, and has electrode portions at both ends in the longitudinal direction.

上述した電子部品収納基板の一例が特許文献１に記載されている。
特開平９−３１２４７８号公報 An example of the electronic component storage board described above is described in Patent Document 1.
JP-A-9-31478

ここで、特許文献１に記載されているような電子部品収納基板を従来例として、図１３を用いて説明する。図１３は、電子部品収納基板の従来例を説明するための模式的断面図であり、（ａ）は第１従来例を、（ｂ）は第２従来例をそれぞれ説明するための模式的断面図である。 Here, an electronic component storage board as described in Patent Document 1 will be described as a conventional example with reference to FIG. FIGS. 13A and 13B are schematic cross-sectional views for explaining a conventional example of an electronic component storage board. FIG. 13A is a schematic cross-sectional view for explaining a first conventional example and FIG. 13B is a schematic cross-sectional view for explaining a second conventional example. FIG.

まず、第１従来例の電子部品収納基板について図１３（ａ）を用いて説明する。
電子部品収納基板２０１は、プリント基板２１０の貫通孔２１１にチップ部品２２０が収納され、プリント基板２１０のランド部２１１ａとチップ部品２２０の電極部２２１ａとが半田２３０ａによって電気的に接続され、プリント基板２１０のランド部２１１ｂとチップ部品２２０の電極部２２１ｂとが半田２３０ｂによって電気的に接続されている。 First, the electronic component storage board of the first conventional example will be described with reference to FIG.
In the electronic component storage substrate 201, the chip component 220 is stored in the through hole 211 of the printed circuit board 210, and the land portion 211a of the printed circuit board 210 and the electrode portion 221a of the chip component 220 are electrically connected by the solder 230a. The land portion 211b of 210 and the electrode portion 221b of the chip component 220 are electrically connected by solder 230b.

しかしながら、この電子部品収納基板２０１に、ＩＣ等の他の電子部品２３５を実装する際、プリント基板２１０の表面２１０ａ，２１０ｂよりも半田２３０ａ，２３０ｂが突出しているので、突出している高さが高いとこの突出した半田２３０ａ，２３０ｂに他の電子部品２３５が当たってしまう。
このため、他の電子部品２３５とプリント基板２１０のランド部２１１ｃ，２１１ｄとを半田２３０ｃによって接続することができないので、他の電子部品２３５を貫通孔２１１及びチップ部品２２０を跨いで実装することが困難になる。
従って、この電子部品収納基板２０１に他の電子部品２３５を実装する場合、チップ部品２２０が収納されている範囲を除いて他の電子部品２３５を実装しなければならないため、電子部品の高密度実装化に対するさらなる改善が望まれる。 However, when another electronic component 235 such as an IC is mounted on the electronic component storage substrate 201, the solder 230a and 230b protrude from the surfaces 210a and 210b of the printed circuit board 210, and thus the protruding height is high. Then, another electronic component 235 hits the protruding solders 230a and 230b.
For this reason, since the other electronic component 235 and the land portions 211c and 211d of the printed circuit board 210 cannot be connected by the solder 230c, the other electronic component 235 can be mounted across the through hole 211 and the chip component 220. It becomes difficult.
Accordingly, when other electronic components 235 are mounted on the electronic component storage board 201, the other electronic components 235 must be mounted except for the range in which the chip components 220 are stored. Further improvement is desired.

また、上述の電子部品収納基板２０１は、チップ部品２２０の電極部２２１ａ，２２１ｂと半田２３０ａ，２３０ｂとがそれぞれ接続面２２２ａ，２２２ｂで接続されているが、接続面２２２ａ，２２２ｂの面積がそれぞれ小さいので、この電子部品収納基板２０１に熱ストレスが与えられた際に、電子部品収納基板２０１の厚さ方向におけるプリント基板２１０とチップ部品２２０との熱膨張係数の差によってこの接続面２２２ａ，２２２ｂに熱応力が生じる。
この熱応力によって、チップ部品２２０の電極部２２１ａ，２２１ｂと半田２３０ａ，２３０ｂとがこの接続面２２２ａ，２２２ｂで剥離する場合がある。
ここで、上述した電子部品収納基板２０１に熱ストレスが与えられた際とは、電子部品収納基板２０１に他の電子部品２３５をリフロー炉等を用いて半田付けする場合や電子部品収納基板２０１に信頼性試験の１つである熱衝撃試験を行った場合等である。 In the electronic component storage board 201 described above, the electrode portions 221a and 221b of the chip component 220 and the solders 230a and 230b are connected by connection surfaces 222a and 222b, respectively, but the areas of the connection surfaces 222a and 222b are small. Therefore, when thermal stress is applied to the electronic component storage board 201, the connection surfaces 222a and 222b are caused by the difference in thermal expansion coefficient between the printed circuit board 210 and the chip component 220 in the thickness direction of the electronic component storage board 201. Thermal stress is generated.
Due to this thermal stress, the electrode portions 221a and 221b of the chip component 220 and the solders 230a and 230b may be peeled off at the connection surfaces 222a and 222b.
Here, when the above-described electronic component storage board 201 is subjected to thermal stress, when the electronic component storage board 201 is soldered with another electronic component 235 using a reflow furnace or the like, For example, a thermal shock test, which is one of reliability tests, is performed.

次に、第２従来例の電子部品収納基板について図１３（ｂ）を用いて説明する。
電子部品収納基板２５１は、プリント基板２６０の貫通孔２６１にチップ部品２２０が収納され、プリント基板２６０のランド部２６１ａとチップ部品２２０の電極部２２１ａとが半田２３０ａによって電気的に接続され、プリント基板２６０のランド部２６１ｂとチップ部品２２０の電極部２２１ｂとが半田２３０ｂによって電気的に接続されている。
この電子部品収納基板２５１は、第１従来例の電子部品収納基板２０１に対して、プリント基板２６０の厚さをチップ部品２２０よりも厚くしているため、プリント基板２６０の表面よりも半田２３０ａ，２３０ｂが突出することを防止できる。 Next, a second conventional example electronic component storage board will be described with reference to FIG.
In the electronic component storage board 251, the chip component 220 is stored in the through hole 261 of the printed circuit board 260, and the land portion 261a of the printed circuit board 260 and the electrode portion 221a of the chip component 220 are electrically connected by the solder 230a. The land portions 261b of 260 and the electrode portions 221b of the chip component 220 are electrically connected by solder 230b.
Since this electronic component storage board 251 is thicker than the chip component 220 with respect to the electronic component storage board 201 of the first conventional example, the solder 230a, Protruding 230b can be prevented.

しかしながら、電子部品収納基板２５１は、半田２３０ａ，２３０ｂとチップ部品２２０の電極部２２１ａ，２２１ｂとの接続面２２２ｃ，２２２ｄの面積がそれぞれ小さいため、この電子部品収納基板２５１に熱ストレスが与えられた際に、半田２３０ａ，２３０ｂとチップ部品２２０の電極部２２１ａ，２２１ｂとがこの接続面２２２ｃ，２２２ｄで剥離する場合がある。 However, since the electronic component storage board 251 has small areas of the connection surfaces 222c and 222d between the solders 230a and 230b and the electrode portions 221a and 221b of the chip component 220, thermal stress is applied to the electronic component storage board 251. At this time, the solders 230a and 230b and the electrode portions 221a and 221b of the chip component 220 may be separated at the connection surfaces 222c and 222d.

そこで、本発明が解決しようとする課題は、電子部品を収納した際に、基板の表面から半田等の導電性材料が突出することを抑制し、また、導電性材料とチップ部品の電極部との接続強度を向上させるプリント基板及びその製造方法を提供することにある。 Therefore, the problem to be solved by the present invention is to suppress the conductive material such as solder from protruding from the surface of the substrate when the electronic component is accommodated, and the conductive material and the electrode part of the chip component. An object of the present invention is to provide a printed circuit board and a method for manufacturing the same, which can improve the connection strength.

また、本発明が解決しようとする課題は、基板の表面から半田等の導電性材料が突出することを抑制し、また、導電性材料とチップ部品の電極部との接続強度を向上させる電子部品収納基板及びその製造方法を提供することにある。 In addition, the problem to be solved by the present invention is to suppress the protruding of a conductive material such as solder from the surface of the substrate, and to improve the connection strength between the conductive material and the electrode part of the chip component. An object of the present invention is to provide a storage substrate and a manufacturing method thereof.

上記の課題を解決するために、本願各発明は次の手段を有する。
１）基板（１５）と、該基板の一面側に形成された第１の凹部（２１）と、前記基板の他面側に、前記第１の凹部と対向して形成された第２の凹部（２２）と、前記第１の凹部の内面を覆う第１の導電層からなる第１のランド部（３６）と、前記第２の凹部の内面を覆う第２の導電層からなる第２のランド部（３７）と、前記第１の凹部及び前記第２の凹部が形成された範囲内において、前記第１の導電層、前記基板及び前記第２の導電層を貫通する貫通孔（３５）と、を有しており、前記貫通孔の内周面は、前記基板を穿つことで形成されたセンター切削面部と、前記第１及び第２の導電層を穿つことで形成されたエンド切削面部とを含むことを特徴とするプリント基板（５０）である。
２）プリント基板の製造方法において、基板（１５）の一面側に、第１の凹部（２１）を形成する第１凹部形成工程と、前記基板の他面側に、前記第１の凹部と対向して第２の凹部（２２）を形成する第２凹部形成工程と、前記第１の凹部及び前記第２の凹部の各内面を覆うように、前記基板の両面に導電層（２６ａ，２６ｂ）をそれぞれ形成する導電層形成工程と、前記基板における前記第１の凹部及び前記第２の凹部が形成された範囲内に、前記基板を貫通する貫通孔（３５）を穿設する貫通孔穿設工程と、を有することを特徴とするプリント基板（５０）の製造方法である。
３）プリント基板の製造方法において、基板（１５）の一面側に、複数の穴（９１ａ〜９１ｍ）が連結されてなる環状の第１の凹部（９１）を形成する第１凹部形成工程と、前記基板の他面側に、前記第１の凹部に対向して、複数の穴（９２ａ〜９２ｍ）が連結されてなる環状の第２の凹部（９２）を形成する第２凹部形成工程と、前記第１の凹部及び前記第２の凹部の各内面を覆うように、前記基板の両面に導電層（２６ａ，２６ｂ）をそれぞれ形成する導電層形成工程と、前記基板における前記第１の凹部及び前記第２の凹部が形成された範囲内に、前記第１の凹部及び前記第２の凹部がそれぞれ開口縁となるように、前記基板を貫通する貫通孔（９５）を穿設する貫通孔穿設工程と、を有することを特徴とするプリント基板（１００）の製造方法である。
４）１）項記載のプリント基板と、長手を有すると共に該長手の両端にそれぞれ電極部（６２ａ，６２ｂ）を有し、前記長手の方向が前記貫通孔の軸方向となるように前記貫通孔に収納された電子部品（６０）と、前記第１のランド部と該第１のランド部側の前記電極部とを電気的に接続する第１の接続部と、前記第２のランド部と該第２のランド部側の前記電極部とを電気的に接続する第２の接続部と、を有することを特徴とする電子部品収納基板（７０）である。
５）２）又は３）項記載のプリント基板の製造方法により得られたプリント基板の前記貫通孔に、長手を有すると共に該長手の両端にそれぞれ電極部（６２ａ，６２ｂ）を有する電子部品（６０）を、前記長手の方向が前記貫通孔の軸方向となるように挿入する挿入工程と、前記第１の凹部に形成された導電層からなる第１のランド部と該第１のランド部側の前記電極部とを電気的に接続するように、前記第１の凹部に導電性材料（６８ａ）を供給する第１接続工程と、前記第２の凹部に形成された導電層からなる第２のランド部と該第２のランド部側の前記電極部とを電気的に接続するように、前記第２の凹部に導電性材料（６８ｂ）を供給する第２接続工程と、を有することを特徴とする電子部品収納基板（７０）の製造方法である。 In order to solve the above problems, each invention of the present application has the following means.
1) A substrate (15), a first recess (21) formed on one surface of the substrate, and a second recess formed on the other surface of the substrate so as to face the first recess. (22) and, before Symbol first land portion of a first conductive layer covering the inner surface of the first recess (36), a second of a second conductive layer covering the inner surface of the second recess And a through hole (35) that penetrates the first conductive layer, the substrate, and the second conductive layer within a range where the first concave portion and the second concave portion are formed. ) and it has to have a inner peripheral surface of the through hole, and a center cutting surface formed by drilling the substrate, end cutting formed by drilling said first and second conductive layers It is a printed circuit board (50) characterized by including a surface part .
2) In the method for manufacturing a printed circuit board, a first recess forming step of forming a first recess (21) on one surface side of the substrate (15), and facing the first recess on the other surface side of the substrate A second recess forming step of forming the second recess (22), and conductive layers (26a, 26b) on both surfaces of the substrate so as to cover the inner surfaces of the first recess and the second recess. And forming a through hole for forming a through hole (35) penetrating the substrate within a range where the first recess and the second recess are formed in the substrate. A process for producing a printed circuit board (50).
3) In the printed circuit board manufacturing method, a first recess forming step of forming an annular first recess (91) formed by connecting a plurality of holes (91a to 91m) on one surface side of the substrate (15); A second recess forming step of forming an annular second recess (92) formed by connecting a plurality of holes (92a to 92m) on the other surface side of the substrate so as to face the first recess; A conductive layer forming step of forming conductive layers (26a, 26b) on both surfaces of the substrate so as to cover respective inner surfaces of the first recess and the second recess, and the first recess and the Through-hole drilling for forming a through-hole (95) that penetrates the substrate so that the first recess and the second recess each have an opening edge within the range where the second recess is formed. A printed circuit board (100) characterized by comprising: It is a manufacturing method.
4) The printed circuit board according to 1), having a length and electrode portions (62a, 62b) at both ends of the length, and the through hole so that the longitudinal direction is the axial direction of the through hole. An electronic component (60) housed in the first land portion, a first connection portion that electrically connects the first land portion and the electrode portion on the first land portion side, and the second land portion. An electronic component storage board (70), comprising: a second connection portion that electrically connects the electrode portion on the second land portion side.
The through hole of the printed circuit board obtained by 5) 2) or 3) A method of manufacturing a printed circuit board according to claim, the electronic component having an electrode portion, respectively (62a, 62b) at both ends of the long hand and having a longitudinal (60 ) In such a manner that the longitudinal direction is the axial direction of the through hole, and a first land portion made of a conductive layer formed in the first recess and the first land portion side A first connection step of supplying a conductive material (68a) to the first recess so as to electrically connect the electrode portion of the second electrode, and a second layer comprising a conductive layer formed in the second recess . A second connection step of supplying a conductive material (68b) to the second recess so as to electrically connect the land portion of the second land portion and the electrode portion on the second land portion side. It is a manufacturing method of the electronic component storage board (70) characterized.

本発明によれば、特に、基板に凹部を形成し、この凹部の内面を覆う導電層を形成し、凹部が形成された範囲内に基板を貫通する貫通孔を形成し、この貫通孔に電子部品を挿入し、電子部品の電極と導電層とを凹部を埋めるように形成された半田によって電気的に接続することによって、電子部品収納基板の表面から半田等の導電性材料が突出することを抑制し、導電性材料とチップ部品の電極部との接続強度が向上するという効果を奏する。 According to the present invention, in particular, a concave portion is formed in the substrate, a conductive layer covering the inner surface of the concave portion is formed, a through hole penetrating the substrate is formed in a range where the concave portion is formed, and an electron is formed in the through hole. By inserting the component and electrically connecting the electrode of the electronic component and the conductive layer with solder formed so as to fill the recess, the conductive material such as solder protrudes from the surface of the electronic component storage board. This produces an effect that the connection strength between the conductive material and the electrode part of the chip component is improved.

本発明の実施の形態を、好ましい実施例により図１〜図１２を用いて説明する。
本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法を、第１実施例及び第２実施例として以下に説明する。
図１〜図８は、本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第１実施例におけるＡ１工程〜Ａ８工程をそれぞれ説明するための模式的断面図である。
図９〜図１２は、本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第２実施例におけるＢ１工程〜Ｂ４工程をそれぞれ説明するための模式的断面図である。 The preferred embodiments of the present invention will be described with reference to FIGS.
A printed circuit board and a manufacturing method thereof, an electronic component storage board and a manufacturing method thereof according to the present invention will be described below as a first embodiment and a second embodiment.
FIGS. 1-8 is typical sectional drawing for demonstrating each A1 process-A8 process in 1st Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method.
FIGS. 9-12 is typical sectional drawing for demonstrating the B1 process-B4 process in 2nd Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method, respectively.

＜第１実施例＞
まず、第１実施例をＡ１工程〜Ａ８工程として図１〜図８を用いて説明する。
第１実施例において、チップ部品を収納可能なプリント基板５０は以下に説明するＡ１工程〜Ａ５工程により作製することができ、このプリント基板５０にチップ部品６０が収納された電子部品収納基板７０はプリント基板５０にさらにＡ６工程〜Ａ８工程を施すことにより作製することができる。
また、大判のコア材にＡ１工程〜Ａ５工程を行った後にこのコア材を分断することによって複数のプリント基板５０を得るが、図１〜図５では、説明をわかりやすくするために工程の始めから単体のプリント基板５０を示すこととする。 <First embodiment>
First, the first embodiment will be described as steps A1 to A8 with reference to FIGS.
In the first embodiment, the printed circuit board 50 capable of storing chip components can be manufactured by processes A1 to A5 described below. An electronic component storage board 70 in which the chip components 60 are stored in the printed circuit board 50 is as follows. The printed circuit board 50 can be manufactured by further performing steps A6 to A8.
In addition, a plurality of printed circuit boards 50 are obtained by dividing the core material after performing steps A1 to A5 on the large-sized core material. In FIGS. A single printed circuit board 50 is shown.

（Ａ１工程）［図１参照］
まず、コア材２の両面に銅箔３ａ，３ｂが貼り合わされた、所謂、両面銅貼り板（単に、両面板という場合もある）１を準備する。
第１実施例では、コア材２の厚さｔ２を０．５ｍｍ、銅箔３ａ，３ｂの厚さをそれぞれ１８μｍとした。コア材２は、ガラスクロスにエポキシ樹脂を含浸させたものであり、図１では、ガラスクロスを破線で模式的に表している。 (Step A1) [See FIG. 1]
First, a so-called double-sided copper-clad plate (sometimes simply referred to as a double-sided plate) 1 in which copper foils 3a and 3b are bonded to both surfaces of a core material 2 is prepared.
In the first example, the thickness t2 of the core material 2 was 0.5 mm, and the thicknesses of the copper foils 3a and 3b were each 18 μm. The core material 2 is obtained by impregnating a glass cloth with an epoxy resin. In FIG. 1, the glass cloth is schematically represented by a broken line.

次に、両面銅貼り板１の所定位置に、両面銅貼り板１を厚さ方向に貫通する貫通孔５を穿設する。この貫通孔５は、ドリル加工やレーザ加工等により穿設することができる。第１実施例では、ドリル加工により、その直径が０．２ｍｍとなるように貫通孔５を穿設した。 Next, a through hole 5 that penetrates the double-sided copper-clad plate 1 in the thickness direction is formed at a predetermined position of the double-sided copper-clad plate 1. The through hole 5 can be drilled by drilling, laser processing, or the like. In the first embodiment, the through-hole 5 was drilled so that the diameter was 0.2 mm by drilling.

（Ａ２工程）［図２参照］
銅箔３ａ，３ｂの各表面及び貫通孔５の内面に、例えば銅からなる第１めっき層７ａ，７ｂを形成する。この第１めっき層７ａ，７ｂは、例えば、無電解銅めっきを行った後さらに電解銅めっきを行うことで形成することができる。
内面が第１めっき層７ａ，７ｂで覆われた貫通孔５をＩＶＨ（Interstitial Via Hole）１０と称す。 (Process A2) [Refer to FIG. 2]
First plating layers 7 a and 7 b made of, for example, copper are formed on each surface of the copper foils 3 a and 3 b and the inner surface of the through hole 5. The first plating layers 7a and 7b can be formed, for example, by performing electroless copper plating after performing electroless copper plating.
The through hole 5 whose inner surface is covered with the first plating layers 7 a and 7 b is referred to as an IVH (Interstitial Via Hole) 10.

次に、ＩＶＨ１０の内部に充填材９を充填する。
詳しくは、充填材９である孔埋め用インクを、例えばスクリーン印刷法により、ＩＶＨ１０の内部に充填させた後に硬化させる。その後、第１めっき層７ａ，７ｂの各表面より突出して硬化した余分なインクを、例えばバフ研磨により除去することによって、充填材９が充填された後の両面銅貼り板１の各表面を略平坦な面にする。
孔埋め用インクとしては市販の孔埋め用インクを使用することができ、孔埋め用インクを充填する他の充填方法としてロールコート法等を用いることができる。 Next, the filler 9 is filled into the IVH 10.
Specifically, the hole filling ink which is the filler 9 is filled into the IVH 10 by, for example, screen printing, and then cured. Thereafter, excess ink that protrudes and hardens from each surface of the first plating layers 7a and 7b is removed by, for example, buffing, so that each surface of the double-sided copper-clad plate 1 after filling with the filler 9 is substantially omitted. Make the surface flat.
As the hole-filling ink, a commercially available hole-filling ink can be used, and a roll coating method or the like can be used as another filling method for filling the hole-filling ink.

（Ａ３工程）［図３参照］
フォトリソ法により、第１めっき層７ａ及び銅箔３ａを選択的にエッチングして第１配線層１１を形成し、また、第１めっき層７ｂ及び銅箔３ｂを選択的にエッチングして第２配線層１２を形成する。
この第１配線層１１及び第２配線層１２は、ＩＶＨ１０によって互いに電気的に接続されている。第１配線層１１の厚さｔ１１及び第２配線層１２の厚さｔ１２はそれぞれ３０μｍである。 (Step A3) [Refer to FIG. 3]
The first plating layer 7a and the copper foil 3a are selectively etched by the photolithography method to form the first wiring layer 11, and the first plating layer 7b and the copper foil 3b are selectively etched to form the second wiring. Layer 12 is formed.
The first wiring layer 11 and the second wiring layer 12 are electrically connected to each other by the IVH 10. The thickness t11 of the first wiring layer 11 and the thickness t12 of the second wiring layer 12 are each 30 μm.

次に、第１配線層１１及び第２配線層１２をそれぞれ覆うように、両面銅貼り板１の両面に第１絶縁層１７及び第２絶縁層１８を形成する。
第１絶縁層１７の厚さｔ１７（第１配線層１１の表面上の厚さ）及び第２絶縁層１８の厚さｔ１８（第２配線層１２の表面上の厚さ）はそれぞれ６０μｍである。
上述の工程を経た両面銅貼り板１を両面配線板１５と称す。 Next, the 1st insulating layer 17 and the 2nd insulating layer 18 are formed in both surfaces of the double-sided copper-clad board 1 so that the 1st wiring layer 11 and the 2nd wiring layer 12 may be covered, respectively.
The thickness t17 (thickness on the surface of the first wiring layer 11) of the first insulating layer 17 and the thickness t18 (thickness on the surface of the second wiring layer 12) of the second insulating layer 18 are each 60 μm. .
The double-sided copper-clad board 1 that has undergone the above-described steps is referred to as a double-sided wiring board 15.

（Ａ４工程）［図４参照］
両面配線板１５の一面１５ａ側に、円錐状の凹み部２１をドリル加工により形成する。また、両面配線板１５の他面１５ｂ側に、その中心が凹み部２１の中心と略一致する円錐状の凹み部２２をドリル加工により形成する。
第１実施例では、凹み部２１，２２の開口角度θ２１，θ２２がそれぞれ１２０°になるように、先端部の角度が１２０°であるドリルを用いた。
凹み部２１，２２の開口径Ｒ２１，Ｒ２２はそれぞれ０．７ｍｍである。 (Step A4) [Refer to FIG. 4]
A conical recess 21 is formed on one side 15a of the double-sided wiring board 15 by drilling. Further, a conical recess 22 whose center substantially coincides with the center of the recess 21 is formed on the other surface 15b side of the double-sided wiring board 15 by drilling.
In the first embodiment, a drill having a tip portion angle of 120 ° was used so that the opening angles θ21 and θ22 of the recess portions 21 and 22 were 120 °, respectively.
The opening diameters R21 and R22 of the recesses 21 and 22 are 0.7 mm, respectively.

次に、第１絶縁層１７の所定位置にレーザ加工を行って第１配線層１１が露出するように有底穴２３を形成し、第２絶縁層１８の所定位置にレーザ加工を行って第２配線層１２が露出するように有底穴２４を形成する。
有底穴２３，２４の開口径はそれぞれ９０μｍである。 Next, laser processing is performed at a predetermined position of the first insulating layer 17 to form a bottomed hole 23 so that the first wiring layer 11 is exposed, and laser processing is performed at a predetermined position of the second insulating layer 18 to perform first processing. The bottomed hole 24 is formed so that the two wiring layers 12 are exposed.
Each of the bottomed holes 23 and 24 has an opening diameter of 90 μm.

その後、凹み部２１，２２及び有底穴２３，２４の各内面を覆うように、第１絶縁層１７及び第２絶縁層１８の各表面に、例えば銅からなる第２めっき層２６ａ，２６ｂを形成する。この第２めっき層２６ａ，２６ｂは、例えば、無電解銅めっきを行った後さらに電解銅めっきを行うことで形成することができる。
内面が第２めっき層２６ａ，２６ｂで覆われた有底穴２３及び有底穴２４をＬＶＨ（Laser Via Hole）２８及びＬＶＨ２９と称す。 Thereafter, second plating layers 26 a and 26 b made of, for example, copper are formed on the surfaces of the first insulating layer 17 and the second insulating layer 18 so as to cover the inner surfaces of the recessed portions 21 and 22 and the bottomed holes 23 and 24. Form. The second plating layers 26a and 26b can be formed, for example, by performing electroless copper plating after performing electroless copper plating.
The bottomed hole 23 and the bottomed hole 24 whose inner surfaces are covered with the second plating layers 26a and 26b are referred to as LVH (Laser Via Hole) 28 and LVH29.

ところで、Ａ４工程では、凹み部２１，２２を形成した後に有底穴２３，２４を形成したが、これに限定されるものではなく、有底穴２３，２４を形成した後に凹み部２１，２２を形成するようにしてもよい。 In the A4 process, the bottomed holes 23 and 24 are formed after the recesses 21 and 22 are formed. However, the present invention is not limited to this, and the recesses 21 and 22 are formed after the bottomed holes 23 and 24 are formed. May be formed.

（Ａ５工程）［図５参照］
フォトリソ法により、第２めっき層２６ａを選択的にエッチングして第３配線層３１とし、また、第２めっき層２６ｂを選択的にエッチングして第４配線層３２とする。
第１実施例では、第３配線層３１及び第４配線層３２の厚さをそれぞれ２０μｍとした。 (Step A5) [Refer to FIG. 5]
By the photolithography method, the second plating layer 26a is selectively etched to form the third wiring layer 31, and the second plating layer 26b is selectively etched to form the fourth wiring layer 32.
In the first embodiment, the thicknesses of the third wiring layer 31 and the fourth wiring layer 32 are each 20 μm.

次に、凹み部２１，２２の各中心を通って両面配線板１５を貫通する貫通孔３５をドリル加工により形成する。この貫通孔３５は、後述するチップ部品６０を収納するための収納部３５となる。
第１実施例では、貫通孔（収納部）３５の孔径Ｒ３５を０．３６ｍｍとした。 Next, the through-hole 35 which penetrates the double-sided wiring board 15 through each center of the dent parts 21 and 22 is formed by drilling. The through hole 35 serves as a storage portion 35 for storing a chip component 60 described later.
In the first embodiment, the hole diameter R35 of the through hole (housing portion) 35 is set to 0.36 mm.

第３配線層３１において、凹み部２１の内面をリング状に覆う範囲を第１ランド部３６と称す。
また、第４配線層３２において、凹み部２２の内面をリング状に覆う範囲を第２ランド部３７と称す。 In the third wiring layer 31, a range covering the inner surface of the recessed portion 21 in a ring shape is referred to as a first land portion 36.
Further, in the fourth wiring layer 32, a range covering the inner surface of the recessed portion 22 in a ring shape is referred to as a second land portion 37.

さらに、両面配線板１５の両面に、所定の開口部４１ａ，４１ｂを有するソルダーレジスト４０ａ，４０ｂを形成する。
第１実施例では、感光性を有する液状またはインク状のソルダーレジストをスクリーン印刷法を用いて両面配線板１５の両面に塗布して乾燥させた後、フォトリソ法を用いて、第３配線層３１が露出してなる開口部４１ａを有するソルダーレジスト４０ａを形成し、また、第４配線層３２が露出してなる開口部４１ｂを有するソルダーレジスト４０ｂを形成した。 Further, solder resists 40a and 40b having predetermined openings 41a and 41b are formed on both surfaces of the double-sided wiring board 15.
In the first embodiment, a liquid or ink-like solder resist having photosensitivity is applied to both surfaces of the double-sided wiring board 15 using a screen printing method and dried, and then the third wiring layer 31 is used using a photolithographic method. The solder resist 40a having the opening 41a formed by exposing the fourth wiring layer 32 was formed, and the solder resist 40b having the opening 41b formed by exposing the fourth wiring layer 32 was formed.

ところで、Ａ５工程では、まず第３配線層３１及び第４配線層３２を形成し、次に貫通孔３５を形成し、その後ソルダーレジスト４０ａ，４０ｂを形成したがこれに限定されるものではない。
例えば、第３配線層３１及び第４配線層３２、ソルダーレジスト４０ａ，４０ｂ、貫通孔３５の順に形成してもよい。 By the way, in the A5 process, first, the third wiring layer 31 and the fourth wiring layer 32 are formed, then the through hole 35 is formed, and then the solder resists 40 a and 40 b are formed. Absent.
For example, the third wiring layer 31 and the fourth wiring layer 32, a solder resist 40 a, 40 b, but it may also be formed in this order through hole 35.

上述したＡ１工程〜Ａ５工程により、後述するチップ部品６０を収納可能な収納部３５を有するプリント基板５０を得る。 The printed circuit board 50 having the storage portion 35 that can store a chip component 60 to be described later is obtained by the above-described steps A1 to A5.

次に、上述したプリント基板５０の収納部３５に後述するチップ部品６０が収納された電子部品収納基板７０について説明する。 Next, an electronic component storage board 70 in which a chip component 60 described later is stored in the storage portion 35 of the printed circuit board 50 described above will be described.

（Ａ６工程）［図６参照］
まず、上述したプリント基板５０の収納部３５に収納する電子部品であるチップ部品を準備する。このようなチップ部品として、チップ抵抗，チップコンデンサ，及びチップコイル等の受動部品がある。 (Step A6) [Refer to FIG. 6]
First, a chip component which is an electronic component stored in the storage unit 35 of the printed circuit board 50 described above is prepared. Such chip components include passive components such as chip resistors, chip capacitors, and chip coils.

ここで、上述したプリント基板５０の収納部３５に収納するチップ部品について図６を用いて説明する。
チップ部品は、その形状から、一般的に、図６（ａ）に示すような角形チップ部品６０と、図６（ｂ）に示すような円筒形チップ部品６５とに分類することができる。 Here, the chip components housed in the housing portion 35 of the printed circuit board 50 described above will be described with reference to FIG.
The chip parts can be generally classified into square chip parts 60 as shown in FIG. 6A and cylindrical chip parts 65 as shown in FIG.

まず、角形チップ部品６０について説明する。
図６（ａ）に示すように、角形チップ部品６０は、主の構成材料がセラミックである本体部６１と、主の構成材料がＳｎ（スズ）である電極部６２ａ，６２ｂとにより構成されている。
ここで、図６（ａ）において、本体部６１の長手方向の各端面を端面６１ａ，６１ｂ、上側の面を表(おもて)面６１ｃ、下側の面を裏面６１ｄと称することとする。
電極部６２ａは、本体部６１の端面６１ａを覆うように表面６１ｃから裏面６１ｄに跨って形成されており、電極部６２ｂは、端面６１ｂを覆うように表面６１ｃから裏面６１ｄに跨って形成されている。 First, the square chip component 60 will be described.
As shown in FIG. 6A, the rectangular chip component 60 includes a main body portion 61 whose main constituent material is ceramic, and electrode portions 62a and 62b whose main constituent material is Sn (tin). Yes.
Here, in FIG. 6A, the end surfaces 61a and 61b in the longitudinal direction of the main body 61 are referred to as end surfaces 61a and 61b, the upper surface is referred to as a front surface 61c, and the lower surface is referred to as a back surface 61d. .
The electrode portion 62a is formed from the front surface 61c to the back surface 61d so as to cover the end surface 61a of the main body 61, and the electrode portion 62b is formed from the front surface 61c to the back surface 61d so as to cover the end surface 61b. Yes.

次に、円筒形チップ部品６５について説明する。
図６（ｂ）に示すように、円筒形チップ部品６５は、主の構成材料がセラミックである本体部６６と、主の構成材料がＳｎ（スズ）である電極部６７ａ，６７ｂとにより構成されている。
ここで、図６（ｂ）において、本体部６６の長手方向の各端面を端面６６ａ，６６ｂ、周方向の面を側面６６ｃと称することとする。
電極部６７ａは、本体部６６の端面６６ａを覆うように側面６６ｃに跨って形成されており、電極部６７ｂは、端面６６ｂを覆うように側面６６ｃに跨って形成されている。 Next, the cylindrical chip component 65 will be described.
As shown in FIG. 6B, the cylindrical chip component 65 includes a main body portion 66 whose main constituent material is ceramic and electrode portions 67a and 67b whose main constituent material is Sn (tin). ing.
Here, in FIG. 6B, the end surfaces in the longitudinal direction of the main body 66 are referred to as end surfaces 66a and 66b, and the circumferential surfaces are referred to as side surfaces 66c.
The electrode portion 67a is formed over the side surface 66c so as to cover the end surface 66a of the main body 66, and the electrode portion 67b is formed over the side surface 66c so as to cover the end surface 66b.

第１実施例では、プリント基板５０の収納部３５に収納されるチップ部品として、図６（ａ）に示す角形チップ部品６０を用いることとした。
第１実施例で用いる角形チップ部品６０は、長さＬ６０が０．６ｍｍ，幅Ｗ６０が０．３ｍｍ，厚さｔ６０が０．３ｍｍである。即ち、角形チップ部品６０の対角長Ｘ６０は約０．４２ｍｍである。 In the first embodiment, the rectangular chip component 60 shown in FIG. 6A is used as the chip component stored in the storage portion 35 of the printed circuit board 50.
The rectangular chip component 60 used in the first embodiment has a length L60 of 0.6 mm, a width W60 of 0.3 mm, and a thickness t60 of 0.3 mm. That is, the diagonal length X60 of the square chip component 60 is about 0.42 mm.

（Ａ７工程）［図７］
プリント基板５０の収納部３５に角形チップ部品６０を挿入する。
収納部３５の孔径Ｒ３５（０．３６ｍｍ）が角形チップ部品６０の対角長Ｘ６０（約０．４２ｍｍ）よりも小さいので、挿入された角形チップ部品６０は収納部３５に強嵌合させる。
なお、図７中の挿入図Ａ１は、第１ランド部３６近傍を図７における上側から見たときの平面図であり、挿入図Ｂ１は、第２ランド部３７近傍を図７における下側から見たときの平面図である。 (Step A7) [FIG. 7]
The square chip component 60 is inserted into the storage portion 35 of the printed circuit board 50.
Since the hole diameter R35 (0.36 mm) of the storage part 35 is smaller than the diagonal length X60 (about 0.42 mm) of the square chip part 60, the inserted square chip part 60 is strongly fitted into the storage part 35.
7 is a plan view when the vicinity of the first land portion 36 is viewed from the upper side in FIG. 7, and the insertion diagram B1 is the vicinity of the second land portion 37 from the lower side in FIG. It is a top view when seen.

第１実施例では、収納部３５の孔径Ｒ３５を０．３６ｍｍとし、角形チップ部品６０の対角長Ｘ６０を約０．４２ｍｍとしたがこれに限定されるものではなく、発明者らが鋭意実験した結果、チップ部品６０の対角長Ｘ６０と収納部３５の孔径Ｒ３５との差（Ｘ６０−Ｒ３５）が４０〜８０μｍの範囲内になるように設定することにより、チップ部品６０を破損させることなく収納部３５に強嵌合させることができることを見出した。 In the first embodiment, the hole diameter R35 of the storage portion 35 is set to 0.36 mm, and the diagonal length X60 of the square chip component 60 is set to about 0.42 mm. However, the present invention is not limited to this, and the inventors have conducted extensive experiments. As a result, by setting the difference (X60−R35) between the diagonal length X60 of the chip component 60 and the hole diameter R35 of the storage portion 35 to be in the range of 40 to 80 μm, the chip component 60 is not damaged. It has been found that the housing portion 35 can be strongly fitted.

（Ａ８工程）［図８］
図８（ａ）に示すように、プリント基板５０の第１ランド部３６とチップ部品６０の電極部６２ａとを半田６８ａによって電気的に接続し、また、第２ランド部３７と電極部６２ｂとを半田６８ｂによって電気的に接続することにより、第３配線層３１と第４配線層３２とがこのチップ部品６０を介して電気的に接続されてなる電子部品収納基板７０を得る。
なお、図８（ａ）中の挿入図Ａ２は、第１ランド部３６近傍を図８（ａ）における上側から見たときの平面図であり、挿入図Ｂ２は、第２ランド部３７近傍を図８（ａ）における下側から見たときの平面図である。 (Process A8) [FIG. 8]
As shown in FIG. 8A, the first land portion 36 of the printed circuit board 50 and the electrode portion 62a of the chip component 60 are electrically connected by solder 68a, and the second land portion 37 and the electrode portion 62b are electrically connected. Are electrically connected by the solder 68b to obtain the electronic component housing substrate 70 in which the third wiring layer 31 and the fourth wiring layer 32 are electrically connected through the chip component 60.
In addition, inset A2 in FIG. 8A is a plan view when the vicinity of the first land portion 36 is viewed from above in FIG. 8A, and inset B2 shows the vicinity of the second land portion 37. It is a top view when it sees from the lower side in Fig.8 (a).

電子部品収納基板７０において、半田６８ａはプリント基板５０の凹み部２１を埋めるように形成されるので、この半田６８ａが電子部品収納基板７０の表面からの突出することを抑制して、プリント基板５０の第１ランド部３６とチップ部品６０の電極部６２ａとを電気的に接続することができる。
同様に、半田６８ｂはプリント基板５０の凹み部２２を埋めるように形成されるので、この半田６８ｂが電子部品収納基板７０の表面からの突出することを抑制して、プリント基板５０の第２ランド部３７とチップ部品６０の電極部６２ｂとを電気的に接続することができる。 In the electronic component storage board 70, the solder 68 a is formed so as to fill the recess 21 of the printed board 50. Therefore, the solder 68 a is prevented from protruding from the surface of the electronic component storage board 70, and the printed board 50. The first land portion 36 and the electrode portion 62a of the chip component 60 can be electrically connected.
Similarly, since the solder 68b is formed so as to fill the recess 22 of the printed board 50, the solder 68b is prevented from protruding from the surface of the electronic component storage board 70, and the second land of the printed board 50 is suppressed. The part 37 and the electrode part 62b of the chip component 60 can be electrically connected.

従って、図８（ｂ）に示すように、この電子部品収納基板７０に他の電子部品８０，８１を実装する際、他の電子部品８０，８１がこの半田６８ａ，６８ｂに当たらないので、収納部３５及びチップ部品６０を跨いで他の電子部品８０，８１を実装することが可能となる。 Therefore, as shown in FIG. 8B, when other electronic components 80 and 81 are mounted on the electronic component storage board 70, the other electronic components 80 and 81 do not hit the solder 68a and 68b. Other electronic components 80 and 81 can be mounted across the part 35 and the chip component 60.

また、電子部品収納基板７０において、半田６８ａは、チップ部品６０（図６参照）の本体部６１の表面６１ｃから裏面６１ｄに亘って電極部６２ａと接続するため、電極部６２ａと半田６８ａとの接続面積を従来よりも大きくすることができると共に、アンカー効果により、電極部６２ａと半田６８ａとの接続強度を従来よりも大きくすることができる。
同様に、半田６８ｂは、チップ部品６０の本体部６１の表面６１ｃから裏面６１ｄに亘って電極部６２ｂと接続するため、電極部６２ｂと半田６８ｂとの接続面積を従来よりも大きくすることができると共に、アンカー効果により、電極部６２ｂと半田６８ｂとの接続強度を従来よりも大きくすることができる。 Further, in the electronic component storage substrate 70, the solder 68a is connected to the electrode portion 62a from the front surface 61c to the back surface 61d of the main body portion 61 of the chip component 60 (see FIG. 6), and therefore the electrode portion 62a and the solder 68a are connected. The connection area can be made larger than before, and the connection strength between the electrode portion 62a and the solder 68a can be made larger than before due to the anchor effect.
Similarly, since the solder 68b is connected to the electrode portion 62b from the front surface 61c to the back surface 61d of the main body portion 61 of the chip component 60, the connection area between the electrode portion 62b and the solder 68b can be made larger than before. At the same time, the connection strength between the electrode portion 62b and the solder 68b can be increased by the anchor effect.

従って、上述した電子部品収納基板７０に熱ストレスを与えた場合、例えば、電子部品収納基板７０に他の電子部品をリフロー炉等を用いて半田付けする場合や電子部品収納基板７０に信頼性試験の１つである熱衝撃試験を行った場合に、チップ部品６０の電極部６２ａと半田６８ａとの接続面における剥離を防止することができ、また、電極部６２ｂと半田６８ｂとの接続面における剥離を防止することができる。 Therefore, when a thermal stress is applied to the electronic component storage board 70 described above, for example, when another electronic component is soldered to the electronic component storage board 70 using a reflow furnace or the like, or the electronic component storage board 70 is subjected to a reliability test. When the thermal shock test, which is one of the above, is performed, it is possible to prevent peeling at the connection surface between the electrode portion 62a and the solder 68a of the chip component 60, and at the connection surface between the electrode portion 62b and the solder 68b. Peeling can be prevented.

また、電子部品収納基板７０において、半田付けの際の半田の表面張力によって、半田６８ａ，６８ｂが収納部３５とチップ部品６０との隙間に入り込まないので、この隙間を樹脂等で充填しなくてもよい。 Also, in the electronic component storage board 70, the solder 68a and 68b do not enter the gap between the storage portion 35 and the chip component 60 due to the surface tension of the solder during soldering. Also good.

＜第２実施例＞
次に、第２実施例をＢ１工程〜Ｂ４工程として図９〜図１２を用いて説明する。
第２実施例は、第１実施例に対して、収納部の特に凹み部の形状及びその形成方法が異なる。
なお、第１実施例と同じ構成部には同じ符号を付す。 <Second embodiment>
Next, a second embodiment will be described as steps B1 to B4 with reference to FIGS.
The second embodiment is different from the first embodiment in the shape of the storage portion, particularly the recess, and the method of forming the recess.
In addition, the same code | symbol is attached | subjected to the same structure part as 1st Example.

（Ｂ１工程）［図９参照］
まず、上述した第１実施例のＡ１工程〜Ａ２工程と同様の工程を行った後、フォトリソ法により、第１めっき層７ａ及び銅箔３ａを選択的にエッチングして第１配線層１１を形成し、また、第１めっき層７ｂ及び銅箔３ｂを選択的にエッチングして第２配線層１２を形成する。
この第１配線層１１及び第２配線層１２は、ＩＶＨ１０によって互いに電気的に接続されている。第１配線層１１の厚さｔ１１及び第２配線層１２の厚さｔ１２はそれぞれ３０μｍである。
また、第１配線層１１は、後述する有底穴９１ａ，９１ｂ，９１ｃ，９１ｄ，９１ｅ，９１ｆ，９１ｇ，９１ｈ，９１ｉ，９１ｊ，９１ｋ，９１ｍを形成するためのパッド部１１ａを有しており、第２配線層１２は、パッド部１１ａと対応する位置に、後述する有底穴９２ａ，９２ｂ，９２ｃ，９２ｄ，９２ｅ，９２ｆ，９２ｇ，９２ｈ，９２ｉ，９２ｊ，９２ｋ，９２ｍを形成するためのパッド部１２ａを有している。 (Step B1) [Refer to FIG. 9]
First, after performing the same steps as the steps A1 to A2 of the first embodiment described above, the first wiring layer 11 is formed by selectively etching the first plating layer 7a and the copper foil 3a by photolithography. In addition, the first wiring layer 12 is formed by selectively etching the first plating layer 7b and the copper foil 3b.
The first wiring layer 11 and the second wiring layer 12 are electrically connected to each other by the IVH 10. The thickness t11 of the first wiring layer 11 and the thickness t12 of the second wiring layer 12 are each 30 μm.
The first wiring layer 11 has a pad portion 11a for forming bottomed holes 91a, 91b, 91c, 91d, 91e, 91f, 91g, 91h, 91i, 91j, 91k, 91m, which will be described later. The second wiring layer 12 is for forming bottom holes 92a, 92b, 92c, 92d, 92e, 92f, 92g, 92h, 92i, 92j, 92k, 92m, which will be described later, at positions corresponding to the pad portion 11a. It has a pad portion 12a.

次に、第１配線層１１及び第２配線層１２をそれぞれ覆うように、両面銅貼り板１の両面に第１絶縁層１７及び第２絶縁層１８を形成する。
第１絶縁層１７の厚さｔ１７（第１配線層１１の表面上の厚さ）及び第２絶縁層１８の厚さｔ１８（第２配線層１２の表面上の厚さ）はそれぞれ６０μｍである。
上述の工程を経た両面銅貼り板１を両面配線板９０と称す。 Next, the 1st insulating layer 17 and the 2nd insulating layer 18 are formed in both surfaces of the double-sided copper-clad board 1 so that the 1st wiring layer 11 and the 2nd wiring layer 12 may be covered, respectively.
The thickness t17 (thickness on the surface of the first wiring layer 11) of the first insulating layer 17 and the thickness t18 (thickness on the surface of the second wiring layer 12) of the second insulating layer 18 are each 60 μm. .
The double-sided copper-clad board 1 that has undergone the above-described steps is referred to as a double-sided wiring board 90.

（Ｂ２工程）［図１０］
第１絶縁層１７におけるパッド部１１ａが形成されている範囲に、環状に所定の間隔でレーザ加工を行い、複数の有底穴９１ａ，９１ｂ，９１ｃ，９１ｄ，９１ｅ，９１ｆ，９１ｇ，９１ｈ，９１ｉ，９１ｊ，９１ｋ，９１ｍが環状に連結してなる凹み部９１を形成する。
同様に、第２絶縁層１８におけるパッド部１１ｂが形成されている範囲に、環状に所定の間隔でレーザ加工を行い、複数の有底穴９２ａ，９２ｂ，９２ｃ，９２ｄ，９２ｅ，９２ｆ，９２ｇ，９２ｈ，９２ｉ，９２ｊ，９２ｋ，９２ｍが環状に連結してなる凹み部９２を形成する。
なお、図１０中の挿入図Ａ３は、凹み部９１近傍を図１０における上側から見たときの平面図であり、挿入図Ｂ３は、凹み部９２近傍を図１０における下側から見たときの平面図である。 (Process B2) [FIG. 10]
Laser processing is performed annularly at a predetermined interval in a range where the pad portion 11a is formed in the first insulating layer 17, and a plurality of bottomed holes 91a, 91b, 91c, 91d, 91e, 91f, 91g, 91h, 91i are formed. , 91j, 91k, 91m are formed in a recess 91 formed in an annular shape.
Similarly, laser processing is performed annularly at a predetermined interval in the range where the pad portion 11b is formed in the second insulating layer 18, and a plurality of bottomed holes 92a, 92b, 92c, 92d, 92e, 92f, 92g, 92h, 92i, 92j, 92k, and 92m form a recess 92 formed by connecting them in an annular shape.
In addition, inset A3 in FIG. 10 is a plan view when the vicinity of the recess 91 is viewed from the upper side in FIG. 10, and the inset B3 is when the vicinity of the recess 92 is viewed from the lower side in FIG. It is a top view.

次に、第１絶縁層１７の所定位置にレーザ加工を行って第１配線層１１が露出するように有底穴２３を形成し、第２絶縁層１８の所定位置にレーザ加工を行って第２配線層１２が露出するように有底穴２４を形成する。 Next, laser processing is performed at a predetermined position of the first insulating layer 17 to form a bottomed hole 23 so that the first wiring layer 11 is exposed, and laser processing is performed at a predetermined position of the second insulating layer 18 to perform first processing. The bottomed hole 24 is formed so that the two wiring layers 12 are exposed.

各有底穴９１ａ，９１ｂ，９１ｃ，９１ｄ，９１ｅ，９１ｆ，９１ｇ，９１ｈ，９１ｉ，９１ｊ，９１ｋ，９１ｍ，９２ａ，９２ｂ，９２ｃ，９２ｄ，９２ｅ，９２ｆ，９２ｇ，９２ｈ，９２ｉ，９２ｊ，９２ｋ，９２ｍ，２３，２４は、開口している側の直径Ｒａが約９０μｍであり、底面側の直径Ｒｂが約８０μｍである。即ち、上述の凹み部９１，９２は、深さ方向にそれぞれテーパ形状を有している。 Each bottomed hole 91a, 91b, 91c, 91d, 91e, 91f, 91g, 91h, 91i, 91j, 91k, 91m, 92a, 92b, 92c, 92d, 92e, 92f, 92g, 92h, 92i, 92j, 92k, In 92m, 23, and 24, the diameter Ra on the open side is about 90 μm, and the diameter Rb on the bottom side is about 80 μm. That is, the above-mentioned dent parts 91 and 92 each have a taper shape in the depth direction.

また、有底穴９１ａ，９１ｂ，９１ｃ，９１ｄ，９１ｅ，９１ｆ，９１ｇ，９１ｈ，９１ｉ，９１ｊ，９１ｋ，９１ｍの各中心を通る凹み部９１の直径Ｒ９１は０．３６ｍｍであり、有底穴９２ａ，９２ｂ，９２ｃ，９２ｄ，９２ｅ，９２ｆ，９２ｇ，９２ｈ，９２ｉ，９２ｊ，９２ｋ，９２ｍの各中心を通る凹み部９２の直径Ｒ９２は０．３６ｍｍである。 Moreover, the diameter R91 of the recessed part 91 which passes through each center of bottomed hole 91a, 91b, 91c, 91d, 91e, 91f, 91g, 91h, 91i, 91j, 91k, 91m is 0.36 mm, and bottomed hole 92a , 92b, 92c, 92d, 92e, 92f, 92g, 92h, 92i, 92j, 92k, and 92m, the diameter R92 of the recess 92 that passes through each center is 0.36 mm.

その後、凹み部９１，９２及び有底穴２３，２４の各内面を覆うように、第１絶縁層１７及び第２絶縁層１８の各表面に、例えば銅からなる第２めっき層２６ａ，２６ｂを形成する。この第２めっき層２６ａ，２６ｂは、例えば、無電解銅めっきを行った後さらに電解銅めっきを行うことで形成することができる。
内面が第２めっき層２６ａ，２６ｂで覆われた有底穴２３及び有底穴２４をＬＶＨ（Laser Via Hole）２８及びＬＶＨ２９と称す。 Thereafter, second plating layers 26a and 26b made of, for example, copper are formed on the surfaces of the first insulating layer 17 and the second insulating layer 18 so as to cover the inner surfaces of the recessed portions 91 and 92 and the bottomed holes 23 and 24, respectively. Form. The second plating layers 26a and 26b can be formed, for example, by performing electroless copper plating after performing electroless copper plating.
The bottomed hole 23 and the bottomed hole 24 whose inner surfaces are covered with the second plating layers 26a and 26b are referred to as LVH (Laser Via Hole) 28 and LVH29.

ところで、Ｂ２工程では、凹み部９１，９２を形成した後に有底穴２３，２４を形成したが、これに限定されるものではなく、有底穴２３，２４を形成した後に凹み部９１，９２を形成するようにしてもよい。 By the way, in the B2 process, the bottomed holes 23 and 24 are formed after the recessed portions 91 and 92 are formed. However, the present invention is not limited to this, and the recessed portions 91 and 92 are formed after the bottomed holes 23 and 24 are formed. May be formed.

（Ｂ３工程）［図１１］
フォトリソ法により、第２めっき層２６ａを選択的にエッチングして第３配線層３１とし、また、第２めっき層２６ｂを選択的にエッチングして第４配線層３２とする。
第２実施例では、第３配線層３１及び第４配線層３２の厚さをそれぞれ２０μｍとした。
なお、図１１中の挿入図Ａ４は、第１ランド部９６近傍を図１１における上側から見たときの平面図であり、挿入図Ｂ４は、第２ランド部９７近傍を図１１における下側から見たときの平面図である。 (Step B3) [FIG. 11]
By the photolithography method, the second plating layer 26a is selectively etched to form the third wiring layer 31, and the second plating layer 26b is selectively etched to form the fourth wiring layer 32.
In the second embodiment, the thickness of each of the third wiring layer 31 and the fourth wiring layer 32 is 20 μm.
In addition, inset A4 in FIG. 11 is a plan view when the vicinity of the first land portion 96 is viewed from the upper side in FIG. 11, and inset B4 is the vicinity of the second land portion 97 from the lower side in FIG. It is a top view when seen.

次に、凹み部９１及び凹み部９２の各中心を通って有底穴９１ａ，９１ｂ，９１ｃ，９１ｄ，９１ｅ，９１ｆ，９１ｇ，９１ｈ，９１ｉ，９１ｊ，９１ｋ，９１ｍ及び有底穴９２ａ，９２ｂ，９２ｃ，９２ｄ，９２ｅ，９２ｆ，９２ｇ，９２ｈ，９２ｉ，９２ｊ，９２ｋ，９２ｍをそれぞれ分断するように、両面配線板９０を貫通する貫通孔９５をドリル加工により形成する。この貫通孔９５は、チップ部品６０を収納するための収納部９５となる。
貫通孔（収納部）９５の孔径Ｒ９５は０．３６ｍｍである。 Next, bottomed holes 91a, 91b, 91c, 91d, 91e, 91f, 91g, 91h, 91i, 91j, 91k, 91m and bottomed holes 92a, 92b, through the centers of the recessed portion 91 and the recessed portion 92, A through-hole 95 that penetrates the double-sided wiring board 90 is formed by drilling so as to divide 92c, 92d, 92e, 92f, 92g, 92h, 92i, 92j, 92k, and 92m. The through hole 95 serves as a storage portion 95 for storing the chip component 60.
The hole diameter R95 of the through hole (storage part) 95 is 0.36 mm.

第３配線層３１において、凹み部９１の内面をリング状に覆う範囲を第１ランド部９６と称す。
また、第４配線層３２において、凹み部９２の内面をリング状に覆う範囲を第２ランド部９７と称す。 In the third wiring layer 31, a range covering the inner surface of the recessed portion 91 in a ring shape is referred to as a first land portion 96.
Further, in the fourth wiring layer 32, a range covering the inner surface of the recessed portion 92 in a ring shape is referred to as a second land portion 97.

その後、両面配線板９０の両面に、所定の開口部４１ａ，４１ｂを有するソルダーレジスト４０ａ，４０ｂを形成する。
第２実施例では、感光性を有する液状またはインク状のソルダーレジストをスクリーン印刷法を用いて両面配線板９０の両面に塗布して乾燥させた後、フォトリソ法を用いて、第３配線層３１が露出してなる開口部４１ａを有するソルダーレジスト４０ａを形成し、また、第４配線層３２が露出してなる開口部４１ｂを有するソルダーレジスト４０ｂを形成した。 Thereafter, solder resists 40a and 40b having predetermined openings 41a and 41b are formed on both surfaces of the double-sided wiring board 90, respectively.
In the second embodiment, a liquid or ink-like solder resist having photosensitivity is applied to both surfaces of the double-sided wiring board 90 using a screen printing method and dried, and then the third wiring layer 31 is used using a photolithographic method. The solder resist 40a having the opening 41a formed by exposing the fourth wiring layer 32 was formed, and the solder resist 40b having the opening 41b formed by exposing the fourth wiring layer 32 was formed.

ところで、Ｂ３工程では、まず第３配線層３１及び第４配線層３２を形成し、次に貫通孔９５を形成し、その後ソルダーレジスト４０ａ，４０ｂを形成したがこれに限定されるものではない。
例えば、第３配線層３１及び第４配線層３２、ソルダーレジスト４０ａ，４０ｂ、貫通孔９５の順に形成してもよい。 By the way, in the B3 process, first, the third wiring layer 31 and the fourth wiring layer 32 are formed, then the through hole 95 is formed, and then the solder resists 40 a and 40 b are formed. However, the present invention is not limited to this. Absent.
For example, the third wiring layer 31 and the fourth wiring layer 32, a solder resist 40 a, 40 b, but it may also be formed in this order through hole 95.

上述したＢ１工程〜Ｂ３工程により、チップ部品６０を収納可能な収納部９５を有するプリント基板１００を得る。 The printed circuit board 100 having the storage portion 95 that can store the chip component 60 is obtained by the above-described steps B1 to B3.

（Ｂ４工程）［図１２］
上述したプリント基板１００に、第１実施例のＡ６工程〜Ａ８工程と同様の工程を行うことにより、図１２（ａ）に示すように、チップ部品６０が収納された電子部品収納基板１２０を得る。
図１２（ａ）中の挿入図Ａ５は、第１ランド部９６近傍を図１２（ａ）における上側から見たときの平面図であり、挿入図Ｂ５は、第２ランド部９７近傍を図１２（ａ）における下側から見たときの平面図である。 (Process B4) [FIG. 12]
By performing the same steps as the steps A6 to A8 of the first embodiment on the printed circuit board 100 described above, as shown in FIG. 12A, an electronic component storage substrate 120 in which the chip component 60 is stored is obtained. .
An inset A5 in FIG. 12A is a plan view when the vicinity of the first land portion 96 is viewed from the upper side in FIG. 12A, and the inset B5 in the vicinity of the second land portion 97 is FIG. It is a top view when it sees from the lower side in (a).

電子部品収納基板１２０において、半田６８ａはプリント基板１００の凹み部９１を埋めるように形成されるので、この半田６８ａが電子部品収納基板１２０の表面からの突出することを抑制して、プリント基板１００の第１ランド部９６とチップ部品６０の電極部６２ａとを電気的に接続することができる。
同様に、半田６８ｂはプリント基板１００の凹み部９２を埋めるように形成されるので、この半田６８ｂが電子部品収納基板１２０の表面からの突出することを抑制して、プリント基板１００の第２ランド部９７とチップ部品６０の電極部６２ｂとを電気的に接続することができる。 In the electronic component storage board 120, the solder 68 a is formed so as to fill the recessed portion 91 of the printed circuit board 100, so that the solder 68 a is prevented from protruding from the surface of the electronic component storage board 120, and the printed circuit board 100. The first land portion 96 and the electrode portion 62a of the chip component 60 can be electrically connected.
Similarly, since the solder 68b is formed so as to fill the recessed portion 92 of the printed circuit board 100, the solder 68b is prevented from protruding from the surface of the electronic component housing board 120, and the second land of the printed circuit board 100 is suppressed. The part 97 and the electrode part 62b of the chip component 60 can be electrically connected.

従って、図１２（ｂ）に示すように、この電子部品収納基板１２０に他の電子部品８０，８１を実装する際、他の電子部品８０，８１がこの半田６８ａ，６８ｂに当たらないので、収納部９５及びチップ部品６０を跨いで他の電子部品８０，８１を実装することが可能となる。 Accordingly, as shown in FIG. 12B, when other electronic components 80, 81 are mounted on the electronic component storage board 120, the other electronic components 80, 81 do not hit the solder 68a, 68b. Other electronic components 80 and 81 can be mounted across the part 95 and the chip component 60.

また、電子部品収納基板１２０において、半田６８ａは、チップ部品６０（図６参照）の本体部６１の表面６１ｃから裏面６１ｄに亘って電極部６２ａと接続するため、電極部６２ａと半田６８ａとの接続面積を従来よりも大きくすることができると共に、アンカー効果により、電極部６２ａと半田６８ａとの接続強度を従来よりも大きくすることができる。
同様に、半田６８ｂは、チップ部品６０の本体部６１の表面６１ｃから裏面６１ｄに亘って電極部６２ｂと接続するため、電極部６２ｂと半田６８ｂとの接続面積を従来よりも大きくすることができると共に、アンカー効果により、電極部６２ｂと半田６８ｂとの接続強度を従来よりも大きくすることができる。 Further, in the electronic component storage substrate 120, the solder 68a is connected to the electrode portion 62a from the front surface 61c to the back surface 61d of the main body portion 61 of the chip component 60 (see FIG. 6), and therefore the electrode portion 62a and the solder 68a are connected. The connection area can be made larger than before, and the connection strength between the electrode portion 62a and the solder 68a can be made larger than before due to the anchor effect.
Similarly, since the solder 68b is connected to the electrode portion 62b from the front surface 61c to the back surface 61d of the main body portion 61 of the chip component 60, the connection area between the electrode portion 62b and the solder 68b can be made larger than before. At the same time, the connection strength between the electrode portion 62b and the solder 68b can be increased by the anchor effect.

従って、上述した電子部品収納基板１２０に熱ストレスを与えた場合、例えば、電子部品収納基板１２０に他の電子部品をリフロー炉等を用いて半田付けする場合や電子部品収納基板１２０に信頼性試験の１つである熱衝撃試験を行った場合に、チップ部品６０の電極部６２ａと半田６８ａとの接続面における剥離を防止することができ、また、電極部６２ｂと半田６８ｂとの接続面における剥離を防止することができる。 Accordingly, when thermal stress is applied to the electronic component storage board 120 described above, for example, when another electronic component is soldered to the electronic component storage board 120 using a reflow furnace or the like, or a reliability test is performed on the electronic component storage board 120. When the thermal shock test, which is one of the above, is performed, it is possible to prevent peeling at the connection surface between the electrode portion 62a and the solder 68a of the chip component 60, and at the connection surface between the electrode portion 62b and the solder 68b. Peeling can be prevented.

また、電子部品収納基板１２０は、第１実施例の電子部品収納基板７０に対して、プリント基板１００の第１ランド部９６と半田６８ａとの接続面積をより大きくすることができるので、電子部品収納基板７０よりも第１ランド部９６と半田６８ａとの接続強度をさらに大きくすることができる。
同様に、電子部品収納基板１２０は、第１実施例の電子部品収納基板７０に対して、プリント基板１００の第２ランド部９７と半田６８ｂとの接続面積をより大きくすることができるので、電子部品収納基板７０よりも第２ランド部９７と半田６８ｂとの接続強度をさらに大きくすることができる。 Further, the electronic component storage board 120 can increase the connection area between the first land portion 96 of the printed circuit board 100 and the solder 68a with respect to the electronic component storage board 70 of the first embodiment. The connection strength between the first land portion 96 and the solder 68a can be further increased as compared with the storage substrate 70.
Similarly, the electronic component storage board 120 can increase the connection area between the second land portion 97 of the printed circuit board 100 and the solder 68b with respect to the electronic component storage board 70 of the first embodiment. The connection strength between the second land portion 97 and the solder 68b can be further increased as compared with the component storage board 70.

なお、電子部品収納基板１２０において、半田付けの際の半田の表面張力によって、半田６８ａ，６８ｂが収納部９５とチップ部品６０との隙間に入り込まないので、この隙間を樹脂等で充填しなくてもよい。 In the electronic component storage board 120, the solder 68a and 68b do not enter the gap between the storage portion 95 and the chip component 60 due to the surface tension of the solder during soldering. Also good.

本発明の実施例は、上述した構成及び手順に限定されるものではなく、本発明の要旨を逸脱しない範囲において変形例としてもよいのは言うまでもない。 The embodiment of the present invention is not limited to the configuration and procedure described above, and it goes without saying that modifications may be made without departing from the scope of the present invention.

例えば、第１実施例において、Ａ１工程〜Ａ５工程により作製したプリント基板５０が複数面付けされた大判の状態でＡ６工程〜Ａ８工程を行った後、分断することによって複数の電子部品収納基板７０を得るようにしてもよいし、Ａ１工程〜Ａ５工程を行った後に、この大判状態の基板を分断して単体のプリント基板５０を複数得た後、単体のプリント基板５０それぞれにＡ６工程〜Ａ８工程を行って複数の電子部品収納基板７０を得るようにしてもよい。
分断後の全てのプリント基板５０を所定の検査基準に基づいて検査して良品のプリント基板５０を選別し、この良品のプリント基板５０のみにＡ６工程〜Ａ８工程を行うことによって、チップ部品等の部材のロスを低減できると共に、生産性を向上させることができるため、生産コストを低減することができる。 For example, in the first embodiment, after the A6 process to the A8 process are performed in a large state in which a plurality of printed circuit boards 50 manufactured by the A1 process to the A5 process are applied, a plurality of electronic component storage boards 70 are divided. Alternatively, after performing steps A1 to A5, the large-sized substrate is divided to obtain a plurality of single printed circuit boards 50, and then each of the single printed circuit boards 50 is subjected to steps A6 to A8. You may make it obtain the some electronic component storage board | substrate 70 by performing a process.
All the printed boards 50 after the division are inspected based on a predetermined inspection standard, and the non-defective printed boards 50 are selected, and the A6 process to the A8 process are performed only on the non-defective printed boards 50 to Since the loss of members can be reduced and the productivity can be improved, the production cost can be reduced.

また、第２実施例において、Ｂ１工程〜Ｂ３工程により作製したプリント基板１００が複数面付けされた大判の状態でＢ４工程を行った後、分断することによって複数の電子部品収納基板１２０を得るようにしてもよいし、Ｂ１工程〜Ｂ３工程を行った後に、この大判状態の基板を分断して単体のプリント基板１００を複数得た後、単体のプリント基板１００それぞれにＢ４工程を行って複数の電子部品収納基板１２０を得るようにしてもよい。
分断後の全てのプリント基板１００を所定の検査基準に基づいて検査して良品のプリント基板１００を選別し、この良品のプリント基板１００のみにＢ４工程を行うことによって、チップ部品等の部材のロスを低減できると共に、生産性を向上させることができるため、生産コストを低減することができる。 Further, in the second embodiment, after the B4 step is performed in a large state in which a plurality of printed circuit boards 100 manufactured by the B1 step to the B3 step are attached, a plurality of electronic component storage substrates 120 are obtained by dividing. Alternatively, after performing the B1 process to the B3 process, the large-sized substrate is divided to obtain a plurality of single printed circuit boards 100, and then a plurality of single printed circuit boards 100 are subjected to the B4 process. The electronic component storage board 120 may be obtained.
All the printed circuit boards 100 after the division are inspected based on a predetermined inspection standard, and the non-defective printed circuit boards 100 are selected, and the B4 process is performed only on the non-defective printed circuit boards 100, so that the loss of members such as chip parts is lost. Can be reduced, and the productivity can be improved, so that the production cost can be reduced.

また、第１実施例及び第２実施例では、プリント基板５０の収納部３５及びプリント基板１００の収納部９５にそれぞれ収納されるチップ部品として、図６（ａ）に示すような角形チップ部品６０を用いたが、これに限定されるものではなく、例えば、図６（ｂ）に示すような円筒形チップ部品６５を用いることもできる。 In the first and second embodiments, the rectangular chip component 60 as shown in FIG. 6A is used as the chip component stored in the storage unit 35 of the printed circuit board 50 and the storage unit 95 of the printed circuit board 100, respectively. However, the present invention is not limited to this. For example, a cylindrical chip component 65 as shown in FIG. 6B can also be used.

また、第１実施例及び第２実施例では、プリント基板５０のランド部３６，３７とチップ部品６０の電極部６２ａ，６２ｂとを半田６８ａ，６８ｂによって電気的に接続し、プリント基板１００のランド部９６，９７とチップ部品６０の電極部６２ａ，６２ｂとを半田６８ａ，６８ｂによって電気的に接続したが、これに限定されるものではなく、例えば、半田の代わりに銅ペースト等のペースト状またはインク状の導電性樹脂をランド部に塗布して硬化させることによって、プリント基板５０及び１００の各ランド部とチップ部品６０の各電極部とを電気的に接続するようにしてもよい。
導電性樹脂は、印刷法やディスペンス法等の周知の塗布方法によって塗布することができる。 In the first and second embodiments, the land portions 36 and 37 of the printed circuit board 50 and the electrode portions 62a and 62b of the chip component 60 are electrically connected by the solders 68a and 68b. The parts 96 and 97 and the electrode parts 62a and 62b of the chip component 60 are electrically connected by the solders 68a and 68b. However, the present invention is not limited to this. For example, instead of the solder, The land portions of the printed circuit boards 50 and 100 and the electrode portions of the chip component 60 may be electrically connected by applying an ink-like conductive resin to the land portions and curing.
The conductive resin can be applied by a known application method such as a printing method or a dispensing method.

本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第１実施例におけるＡ１工程を説明するための模式的断面図である。It is typical sectional drawing for demonstrating the A1 process in 1st Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第１実施例におけるＡ２工程を説明するための模式的断面図である。It is typical sectional drawing for demonstrating A2 process in 1st Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第１実施例におけるＡ３工程を説明するための模式的断面図である。It is typical sectional drawing for demonstrating A3 process in 1st Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第１実施例におけるＡ４工程を説明するための模式的断面図である。It is typical sectional drawing for demonstrating A4 process in 1st Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第１実施例におけるＡ５工程を説明するための模式的断面図である。It is typical sectional drawing for demonstrating A5 process in 1st Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第１実施例におけるＡ６工程を説明するための斜視図である。It is a perspective view for demonstrating A6 process in 1st Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第１実施例におけるＡ７工程を説明するための模式的断面図及び平面図である。It is typical sectional drawing and top view for demonstrating A7 process in 1st Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第１実施例におけるＡ８工程を説明するための模式的断面図及び平面図である。It is typical sectional drawing and top view for demonstrating A8 process in 1st Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第２実施例におけるＢ１工程を説明するための模式的断面図である。It is typical sectional drawing for demonstrating B1 process in 2nd Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第２実施例におけるＢ２工程を説明するための模式的断面図及び平面図である。It is typical sectional drawing and top view for demonstrating B2 process in 2nd Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第２実施例におけるＢ３工程を説明するための模式的断面図及び平面図である。It is typical sectional drawing and a top view for demonstrating B3 process in 2nd Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 本発明のプリント基板及びその製造方法、電子部品収納基板及びその製造方法の第２実施例におけるＢ４工程を説明するための模式的断面図及び平面図である。It is typical sectional drawing and a top view for demonstrating B4 process in 2nd Example of the printed circuit board of this invention, its manufacturing method, an electronic component storage board, and its manufacturing method. 電子部品収納基板の従来例を説明するための模式的断面図である。It is typical sectional drawing for demonstrating the prior art example of an electronic component storage board | substrate.

Explanation of symbols

１両面銅貼り板、２コア材、３ａ，３ｂ銅箔、５貫通孔、７ａ，７ｂ，２６ａ，２６ｂめっき層、９充填材、１０ＩＶＨ、１１，１２，３１，３２配線層、１７，１８絶縁層、１５両面配線板、１５ａ，１５ｂ面、２１，２２凹み部、２３，２４有底穴、２８，２９ＬＶＨ、３５収納部（貫通孔）、３６，３７ランド部、４０ａ，４０ｂソルダーレジスト、４１ａ，４１ｂ開口部、５０プリント基板、６０，６５チップ部品、６１，６６本体部、６１ａ，６１ｂ，６１ｃ，６１ｄ，６６ａ，６６ｂ，６６ｃ面、６２ａ，６２ｂ，６７ａ，６７ｂ電極部、６８ａ，６８ｂ半田、７０電子部品収納基板、ｔ２，ｔ１１，ｔ１２，ｔ１７，ｔ１８，ｔ６０厚さ、 θ２１，θ２２開口角度、Ｒ２１，Ｒ２２開口径、Ｒ３５孔径、Ｌ６０長さ、Ｗ６０幅、Ｘ６０対角長 DESCRIPTION OF SYMBOLS 1 Double-sided copper paste board, 2 Core material, 3a, 3b Copper foil, 5 Through-hole, 7a, 7b, 26a, 26b Plating layer, 9 Filling material, 10 IVH, 11, 12, 31, 32 Wiring layer, 17, 18 Insulating layer, 15 double-sided wiring board, 15a and 15b faces, 21 and 22 recessed parts, 23 and 24 bottomed holes, 28 and 29 LVH, 35 storage parts (through holes), 36 and 37 land parts, 40a and 40b solder resist , 41a, 41b opening, 50 printed circuit board, 60, 65 chip parts, 61, 66 body, 61a, 61b, 61c, 61d, 66a, 66b, 66c surface, 62a, 62b, 67a, 67b electrode part, 68a, 68b solder, 70 electronic component storage board, t2, t11, t12, t17, t18, t60 thickness, θ21, 22 the opening angle, R21, R22 opening diameter, R35 pore size, L60 length, W60 width, X60 diagonal length

Claims

A substrate,
A first recess formed on one side of the substrate;
A second recess formed on the other surface of the substrate so as to face the first recess ;
A first land portion of a first conductive layer covering the inner surface of the front Symbol first recess,
A second land portion comprising a second conductive layer covering the inner surface of the second recess;
A through hole penetrating the first conductive layer, the substrate and the second conductive layer within a range where the first concave portion and the second concave portion are formed;
And have a,
The inner peripheral surface of the through hole includes a center cutting surface portion formed by punching the substrate and an end cutting surface portion formed by punching the first and second conductive layers. Printed circuit board characterized by

In the method for manufacturing a printed circuit board,
A first recess forming step of forming a first recess on one side of the substrate;
A second recess forming step of forming a second recess facing the first recess on the other surface side of the substrate;
A conductive layer forming step of forming conductive layers on both sides of the substrate so as to cover each inner surface of the first recess and the second recess,
A through-hole drilling step of drilling a through-hole penetrating the substrate in a range where the first recess and the second recess are formed in the substrate;
A printed circuit board manufacturing method comprising:

In the method for manufacturing a printed circuit board,
A first recess forming step of forming an annular first recess formed by connecting a plurality of holes on one surface side of the substrate;
A second recess forming step for forming an annular second recess formed by connecting a plurality of holes on the other surface side of the substrate so as to face the first recess;
A conductive layer forming step of forming conductive layers on both sides of the substrate so as to cover each inner surface of the first recess and the second recess,
A through-hole penetrating the substrate is provided in the range where the first recess and the second recess are formed in the substrate so that the first recess and the second recess each have an opening edge. A through hole drilling step for drilling; and
A printed circuit board manufacturing method comprising:

The printed circuit board according to claim 1;
An electronic component that has a length and has electrode portions at both ends of the length, and is housed in the through hole so that the longitudinal direction is the axial direction of the through hole;
A first connection portion that electrically connects the first land portion and the electrode portion on the first land portion side;
A second connecting portion for electrically connecting the second land portion and the electrode portion on the second land portion side;
An electronic component storage board comprising:

In the through hole of the printed circuit board obtained by the production method of the printed circuit board according to claim 2 or 3, the electronic components each having electrodes at both ends of the long hand and having a longitudinal, direction of the longitudinal said through An insertion step of inserting so as to be in the axial direction of the hole;
A conductive material is applied to the first recess so as to electrically connect the first land portion made of a conductive layer formed in the first recess and the electrode portion on the first land portion side. Supplying a first connection step;
The conductive material is provided in the second recess so as to electrically connect a second land portion made of a conductive layer formed in the second recess and the electrode portion on the second land portion side. A second connection step for supplying
The manufacturing method of the electronic component storage board | substrate characterized by having.