JP4775813B2 - Receiver IC - Google Patents

Description

  The present invention relates to a receiving IC used in a radio timepiece or the like that amplifies a received signal, detects it, and outputs a binarized signal.

  Conventionally, a time signal used in a radio timepiece or the like is formed by amplifying, detecting, and binarizing a standard radio signal received by an antenna. For this reason, in the radio wave clock receiver IC, before the detection circuit, an amplifier such as an AGC (Auto Gain Control) amplifier (AMP) composed of an amplifier circuit and a fixed gain amplifier (PostAMP) composed of the amplifier circuit. And place. Further, since the carrier wave of the signal for the radio clock is a single frequency with high accuracy (for example, 40 kHz or 60 kHz for the radio clock received radio wave provided by the Communications Research Laboratory in Japan) For this purpose, a crystal filter is generally inserted between the AGC amplifier and the fixed gain amplifier.

  FIG. 7 shows a configuration of a receiving IC in which a receiving circuit used in a conventional radio timepiece or the like is formed. A radio wave having a frequency of 40 kHz or 60 kHz received from the receiving antenna is converted into a voltage signal at the antenna end and amplified by the AGC amplifier 101. The amplified signal is filtered by a filter to remove noise. An external crystal filter 102 is used as the filter. The signal filtered by the filter is further amplified by the Post amplifier 104. The amplified signal is rectified by a rectifier, filtered by a low-pass filter (LPF), and then binarized by a comparator and output from the receiving IC. A time signal is formed from the binarized signal. In FIG. 7, the crystal filter 102 is represented by an equivalent circuit composed of a series circuit to which a coil L, a capacitor C1 and a resistor R are connected, and an equivalent parallel capacitor C0. The equivalent parallel capacitance C0 is unique to the crystal filter and causes noise of high frequency components passing through the AGC amplifier to pass therethrough. In order to remove the high frequency component noise, a capacitor (Cc) 103 for canceling the high frequency component noise is inserted between the negative phase output terminal of the AGC amplifier 101 and the input terminal of the Post amplifier 104. An input resistance (Rin) 106 added to a power source 105 is connected to the Post amplifier 104.

In the cited document 1, the gain of the differential amplifier circuit at a desired frequency can be increased with a low current and a small occupied area, which is very useful for amplification of reception of radio waves having a single carrier frequency such as a radio clock. A useful amplifier circuit is disclosed (see FIG. 1 of cited document 1). The differential amplifier circuit disclosed herein is a differential amplifier circuit having a pair of transistors and a pair of loads provided on the output end side of the pair of transistors, at a desired frequency as a load of the differential amplifier circuit. It has a configuration in which a pair of capacitors as impedances that determine the gain, a pair of current sources that cancel the bias current of the differential amplifier circuit, and a pair of high resistances that determine the output bias voltage are added in parallel. ing.
JP 2004-64262 A

Conventionally, a cancel capacitor (Cc) for canceling high-frequency component noise due to the above-described equivalent parallel capacitor (C0) of the crystal filter is provided in the receiving IC. However, the equivalent parallel capacitance of the crystal filter often varies depending on the shape and size of the crystal. For this reason, when a crystal filter is attached to the receiving IC, some of the receiving ICs may use a crystal filter that does not match the built-in canceling capacity. In such a case, the high frequency noise canceling effect is not good, and the post amplifier 104 amplifies the high frequency noise, so that the ratio of the received signal and noise is deteriorated, which hinders the improvement of the reception sensitivity as a radio clock. There are many.
The present invention has been made under such circumstances, and provides a receiver IC that enhances the cancellation effect of high-frequency noise by configuring the built-in cancellation capacitor so as to match the equivalent parallel capacitance of the crystal filter.

According to one aspect of the receiving IC of the present invention, a first amplifier for amplifying a received signal, and noise of the received signal amplified by the first amplifier are connected to a positive phase output terminal of the first amplifier. A second amplifier that amplifies the received signal from which noise has been removed after being removed by the crystal filter, a negative phase output terminal of the first amplifier, and an input terminal of the second amplifier; A cancel capacitor for canceling noise passing through the equivalent parallel capacitor, wherein the cancel capacitor is connected to a reverse phase output terminal of the first amplifier, and a plurality of series circuits in which a buffer and a capacitor are connected in series are connected in parallel. A first parallel circuit having a capacitance value different from each other, and a first decoder for selecting the capacitance, wherein the crystal filter includes the first amplifier of the first amplifier. A series circuit in which a buffer and a crystal filter element are connected in series, connected to the positive phase output terminal, and a plurality of parallel circuits connected in parallel, and the crystal filter elements have different equivalent parallel capacitances; A second decoder for selecting the crystal filter element, the second decoder selects one combination of the buffer and the crystal filter element, and the first decoder selects the selected The cancel capacitance value is switched by selecting a combination of the buffer and the capacitor corresponding to the crystal filter element. A rectifier that rectifies the received signal amplified by the second amplifier, a low-pass filter that filters the received signal rectified by the rectifier, and a comparator that binarizes the received signal filtered by the low-pass filter May be further provided. The input resistor inserted into the bias power source applied to the second amplifier may be a variable resistor whose resistance value can be controlled.

  The present invention improves the reception sensitivity by controlling the capacitance value of the cancellation capacitor, thereby enhancing the cancellation effect of high-frequency noise that cannot pass through the crystal filter and passes therethrough.

  Hereinafter, embodiments of the invention will be described with reference to examples.

First, Embodiment 1 will be described with reference to FIGS.
FIG. 1 is a schematic block diagram of a receiving IC used in a radio clock or the like that externally attaches an antenna and a crystal filter, amplifies a received signal, detects it, and outputs a binarized signal. FIG. FIG. 3 is a partial circuit diagram showing a detailed structure of the canceling capacitor shown in FIG. 2, and FIG. 4 is a frequency characteristic for explaining the filtering characteristics of the crystal filter. FIG.

  As shown in FIG. 1, a time signal used for a radio timepiece or the like is formed by amplifying a signal received by an antenna 2, detecting it, and binarizing it. For this reason, the radio clock receiver IC 1 is provided with an amplifier 11 such as an AGC amplifier constituted by an amplifier circuit and a fixed gain amplifier (Post amplifier) 14 constituted by an amplifier circuit before the detection circuit. Yes. In the receiving IC 1, a radio wave having a frequency of 40 kHz or 60 kHz received from the antenna 2 is converted into a voltage signal at the antenna end and amplified by the AGC amplifier 11. The amplified signal is filtered to remove noise. An external crystal filter 12 is used as the filter.

  The crystal filter 12 used in this embodiment is composed of three crystal filters 12a, 12b, and 12c connected in parallel, and filters signals having frequencies of 40 kHz, 60 kHz, and 77.5 kHz, respectively. Each crystal filter is provided with a switch 18, and is configured to select a desired signal frequency by switching the switch 18. The crystal filter 12 is connected to the positive phase output terminal of the AGC amplifier 11 and is connected to the input terminal of the Post amplifier 14. The signal filtered by the crystal filter 12 is amplified by the Post amplifier 14. The amplified signal is rectified by a rectifier 17 and then filtered by a low-pass filter (LPF) 19. Thereafter, the filtered signal is binarized by the comparator 20 and output. A time signal is formed from the binarized signal.

  In FIG. 2, the crystal filter 12 is shown as an equivalent circuit composed of a series circuit to which a coil L, a capacitor C1 and a resistor R are connected, and an equivalent parallel capacitor C0. The equivalent parallel capacitance C0 is unique to the crystal filter and causes high-frequency noise that passes through the AGC amplifier to pass through (see FIG. 4). This high-frequency component noise is generated in a high-frequency region of about 1 MHz or more. In order to remove this high-frequency component noise, the high-frequency component noise is canceled between the negative phase output terminal of the AGC amplifier 11 and the input terminal of the Post amplifier 14. A variable canceling capacity (Cc) 13 is inserted. Further, a power supply 15 for applying a bias voltage to the Post amplifier 14 is connected to the Post amplifier 14, and an input resistor (RIN) 16 is connected to the power supply 15.

  The feature of this embodiment is that the capacitance value of the cancel capacitor (Cc) 13 is made variable. That is, in this embodiment, the canceling capacitor provided in the receiving IC 1 is composed of a plurality of capacitors having different capacitance values and switch circuits provided in each of these capacitors, so that the switch circuit can be controlled from the outside. It is configured.

FIG. 3 illustrates the configuration of the cancel capacity in detail.
In FIG. 3, the cancel capacitor (Cc) 13 includes a capacitor 13a (Cc01, Cc02, Cc03, Cc04), a buffer 13b, and a decoder 13c. For example, four types of capacitors 13a, 0.7 pF (Cc01), 0.9 pF (Cc02), 1.1 pF (Cc03), and 1.3 pF (Cc04) are built in the receiving IC. Each capacitor is connected to the decoder 13c via the buffer 13b. Then, any one of the four capacitance values is selected by the input signals cc1 and cc2 of the decoder 13c.
Similarly, the frequency of the crystal filter 12 is selected by the switch 18. The switch 18 includes a buffer 18a and a decoder 18b, and one of the three frequency values is selected by input signals XOA and XOB of the decoder 18b.

  As described above, the cancel capacitor (Cc) that is incorporated in the receiver IC and cancels the high-frequency component noise that passes through the equivalent parallel capacitor (C0) of the crystal filter has a variable structure that can control the capacitance value. Even if the prepared crystal filter has an equivalent parallel capacitance (C0) having a value slightly different from the expected value, it can be controlled to the optimum capacitance. As a result, the effect of canceling high-frequency noise is improved, leading to an improvement in reception sensitivity as a radio timepiece.

Next, Example 2 will be described with reference to FIG.
FIG. 5 shows a cancellation for canceling high-frequency component noise transmitted through an equivalent parallel capacitance of a crystal filter externally attached to a receiving IC used for a radio wave clock or the like that amplifies and detects a received signal and outputs a binarized signal. It is a partial circuit diagram which shows the detailed structure of a capacity | capacitance and a crystal filter. The receiving IC of this embodiment is characterized in that the input resistance connected to the Post amplifier is variable.

  A time signal used for a radio timepiece or the like is formed by amplifying, detecting, and binarizing a signal received by an antenna. For this reason, in the radio wave clock receiver IC, an amplifier 21 such as an AGC amplifier composed of an amplifier circuit and a fixed gain amplifier (Post amplifier) 24 composed of an amplifier circuit are arranged before the detection circuit. Yes. In this receiving IC, a radio wave having a frequency of 40 kHz or 60 kHz received from the antenna is converted into a voltage signal at the antenna end and amplified by the AGC amplifier 21. The amplified signal is filtered by a filtering filter to remove noise. An external crystal filter 22 is used as the filter.

The crystal filter 22 used in this embodiment is composed of three crystal filters connected in parallel, and filters signals with frequencies of 40 kHz, 60 kHz, and 77.5 kHz, respectively. Each crystal filter is provided with a switch 28, and is configured to select a desired signal frequency by switching the switch 28. The crystal filter 22 is connected to the positive phase output terminal of the AGC amplifier 21 and is connected to the input terminal of the Post amplifier 24.
The signal filtered by the crystal filter 22 is amplified by the Post amplifier 24. The amplified signal is rectified by a rectifier and then filtered by a low pass filter (LPF). Thereafter, the filtered signal is binarized by a comparator and output. A time signal is formed from the binarized signal.

The equivalent parallel capacitance C0 of the quartz filter 22 is unique to the quartz filter and causes high frequency component noise passing through the AGC amplifier to pass therethrough. In order to remove the high frequency component noise, a cancel capacitor (Cc) 23 for canceling the high frequency component noise is inserted between the negative phase output terminal of the AGC amplifier 21 and the input terminal of the Post amplifier 24. Further, a power source 25 for applying a bias voltage to the Post amplifier 24 is connected to the Post amplifier 24, and an input resistor (RIN) 26 is connected to the power source 25.
The feature of this embodiment is that the capacitance value of the cancel capacitor (Cc) 23 is made variable and the resistance value of the input resistor 26 is made variable. That is, in this embodiment, the cancel capacitor provided in the receiving IC is composed of a plurality of capacitors having different capacitance values and switch circuits provided in each of these capacitors, so that the switch circuit can be controlled from the outside. It is configured. The input resistance provided in the receiving IC is composed of a plurality of resistors having different resistance values and switches provided in each of these resistors, and the switches are configured to be controlled from the outside.

  FIG. 5 illustrates in detail the configuration of the input resistor and the cancel capacitor. In the figure, an input resistor (RIN) 26 comprises a resistor 26a (R1, R2, R3, R4), a switch 26b and a decoder 26c. For example, four types of input resistors 26, 25 kΩ (R1), 50 kΩ (R2), 100 kΩ (R3), and 200 kΩ (R4), are built in the receiving IC. Each resistance of the input resistor 26 is connected to the decoder 26c via the switch 26b. Then, any one of the four resistance values is selected by the input signals RI1 and RI2 of the decoder 26c.

  The Q value (f0 / fB) of the crystal filter depends on the resistance value of the input resistor (RIN) 26 connected to the Post amplifier 24. The Q value of the crystal filter is expressed by the ratio between the resonance frequency (f0) (for example, 40 kHz) of the crystal filter and the frequency pass band (fB) (for example, about 3 to 5 Hz), and the sharpness of the resonance frequency of the frequency characteristic. Represents. If the frequency pass band is large, the Q value becomes small, and if the Q value is small, a lot of noise from the AGC amplifier is passed. Therefore, the Q value should be as large as possible. For this purpose, it is necessary to reduce the input resistance 26 (RIN). Further, the gain (G (XI)) of the signal that passes through the crystal filter and is input to the Post amplifier is represented by RIN / (CI + RIN). CI is the intrinsic impedance of the crystal. When G (XI) is large, the signal input to the Post amplifier is large. Therefore, as the input resistance 26 (RIN) is increased, more signals can be passed.

  As described above, by appropriately adjusting the variable structure input resistance (RIN) and selecting the optimum value of the frequency passband (fB) and the gain (G (XI)) of the signal input to the Post amplifier, When a crystal filter is externally attached to a predetermined receiving IC, it is possible to expect a further improvement in reception sensitivity by preventing loss of radio signal regardless of the characteristics of the external crystal filter.

  The present invention is not limited to the above embodiment. In the above embodiment, the cancel capacitors provided in the receiving IC 1 are connected in parallel with capacitors having different capacitance values (see FIG. 3). However, the capacitors having the same capacitance values are connected in parallel, and the switching circuit is intermittently connected. The capacity value of the cancel capacity may be controlled.

In the above embodiment, the canceling capacitor provided in the receiving IC 1 has a plurality of capacitors connected in parallel (see FIG. 3), which are connected in series, and are connected between both terminals of each of the capacitors connected in series. A switch circuit can be connected in parallel with the capacity of the capacitor, and the capacitance value of the cancel capacity can be controlled by the switching circuit being intermittent.
FIG. 6 explains the configuration of the cancel capacitors connected in series in detail.
The cancel capacitor (Cc) 13 'includes a capacitor 13'a (Cc01, Cc02, Cc03, Cc04), a buffer (BUF) 13'b, and a switch 13c (SEL1 to SEL4). The four capacitors 13 ′ a are connected in series between the negative phase output terminal of the AGC amplifier 11 and the input terminal of the Post amplifier 14, and each capacitor is connected between both terminals of each of the cancel capacitors 13 ′ connected in series. A switch 13'c is connected in parallel, and the capacitance value of the cancel capacitor is controlled by the switching circuit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of a receiving IC used in a radio-controlled timepiece or the like that amplifies a received signal and detects and outputs a binarized signal according to Embodiment 1 of the present invention. The circuit diagram which shows the structure of the part of the amplifier of FIG. 1, and a crystal filter. FIG. 3 is a partial circuit diagram showing a detailed structure of a cancel capacitor for canceling high-frequency component noise that passes through an equivalent parallel capacitor of the crystal filter of FIG. 2 and a crystal filter. The frequency characteristic figure explaining the filtering characteristic of a crystal filter. FIG. 7 is a partial circuit diagram showing a detailed structure of a cancel capacitor for canceling high-frequency component noise that passes through an equivalent parallel capacitor of a crystal filter according to Embodiment 2 of the present invention, an input resistance connected to a Post amplifier, and a crystal filter. FIG. 4 is a partial circuit diagram of a receiving IC for explaining an example in which a parallel connection canceling capacitor mounted on the receiving IC of FIG. 3 is replaced with a series connecting canceling capacitor. The schematic block diagram of the receiving IC in which the receiving circuit used for the conventional radio timepiece etc. was formed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Reception IC 2 ... Antenna 11, 21 ... AGC amplifier (1st amplifier)
12, 12a, 12b, 12c, 22 ... Crystal filter 13, 13 ', 23 ... Cancel capacitance (Cc)
13a, 13'a ... Capacity (Cc01, Cc02, Cc03, Cc04)
13b, 13'b ... buffer 13c ... decoder 13'c ... switch 14, 24 ... Post amplifier (second amplifier)
15, 25 ... Power supply 16, 26 ... Input resistance (RIN)
DESCRIPTION OF SYMBOLS 17 ... Rectifier 18 ... Crystal filter switch 18a ... Buffer 18b ... Decoder 19 ... Low pass filter (LPF) 20 ... Comparator 26a ... Resistance (R1, R2, R3, R4) )
26b: Input resistance switch 26c: Decoder

Claims (3)

The first amplifier that amplifies the received signal and the noise of the received signal amplified by the first amplifier are removed by the crystal filter connected to the positive phase output terminal of the first amplifier, and then the noise is removed. The second amplifier that amplifies the received signal, the negative-phase output terminal of the first amplifier, and the input terminal of the second amplifier, and cancels noise that passes through the equivalent parallel capacitance of the crystal filter. A cancellation capacitor, and the cancellation capacitor is connected to a reverse phase output terminal of the first amplifier, and a plurality of series circuits in which a buffer and a capacitor are connected in series are connected in parallel. A first parallel circuit having a value and a first decoder for selecting the capacitance, wherein the crystal filter is connected to the positive phase output terminal of the first amplifier, A series circuit in which a buffer and a crystal filter element are connected in series is connected in parallel, a second parallel circuit in which the crystal filter elements have different equivalent parallel capacitances, and a second that selects the crystal filter element A combination of the buffer and the crystal filter element is selected by the second decoder, and the buffer corresponding to the selected crystal filter element is selected by the first decoder. A receiving IC, wherein a canceling capacity value is switched by selecting a combination with the capacity. A rectifier that rectifies the received signal amplified by the second amplifier, a low-pass filter that filters the received signal rectified by the rectifier, and a comparator that binarizes the received signal filtered by the low-pass filter The receiving IC according to claim 1, further comprising: 3. The input resistor inserted into the bias power source applied to the second amplifier is a variable resistor capable of controlling a resistance value. 4. Receiving IC.

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