JP4769936B2 - Information processing system with memory controller - Google Patents

Description

  The present invention relates to a memory controller, and more particularly to a high-speed read access technique for a memory device.

  DRAM (dynamic random access memory) is widely used as a main storage device in recent computer systems in order to realize a large-scale storage capacity at a low cost. Data reading from the DRAM is performed by designating a row address and a column address, and a bank address in the case of a multi-bank DRAM. Specifically, the row in the memory cell array bank designated by the bank address and the row address is activated, and the data designated by the column address is read out from the data included in the activated row. Since so-called destructive reading is performed in the DRAM, it is necessary to perform precharge after data reading. For this reason, the memory access speed of the DRAM is relatively slow.

  In the era when the processing speed of the CPU (central processing unit) was relatively slow, the slow memory access speed of the DRAM was not a problem. However, in recent years, the processing speed of the CPU has been dramatically improved, and so-called memory walls, in which the memory access speed of the DRAM cannot catch up with the processing speed of the CPU, have become a problem. Therefore, how to increase the memory access speed of DRAM is an important issue. In particular, high-speed read access is required for applications such as main memory databases and large-scale numerical calculations.

As a conventional high-speed memory access method, static column mode, nibble mode, burst mode, page mode, EDO (extended data out), and the like are known. Further, a fixed stride transfer method has been proposed in which data belonging to one row in a memory cell array is read with a fixed stride (see, for example, Non-Patent Document 1).
Lixin Zhang et al., "The Impulse Memory Controller", IEEE Trans. Computers, 50 (11): 1117-1132, 2001

  The conventional memory access method has the following problems. First, (1) since the memory access speed is slower than the processing speed of the CPU, the CPU stops until the data arrives each time data is accessed. (2) Discontinuous data access is inefficient due to cache line-oriented data access, and unnecessary data must be read along with necessary data to satisfy the cache line. Time is wasted for reading data. Further, (3) it is necessary to give a large amount of physical addresses to the memory device in order to obtain a small amount of data, the amount of information read out is smaller than the amount of information required for addressing, and data reading is inefficient. That is the point.

  When considering an application such as a main memory database, conditional branch processing is often performed on data stored in a memory device based on the result of a simple comparison operation such as a selection operation or a join operation. In other words, the calculation result is important, and the data to be compared is not very important in many cases. Even in such a case, (4) it is wasteful of bus resources and CPU resources to read data from the memory device over time and perform simple calculations with a high-speed and expensive CPU.

  If the memory modules are multiplexed like a vector computer or the like, the above problems will be solved, but this is not preferable because it increases the cost. In view of the above problems, an object of the present invention is to increase the read access speed of a memory device without performing multiplexing of memory modules.

  Means taken by the present invention to solve the above problems is a memory controller that receives information indicating whether or not each data of a predetermined bit length belonging to a row related to read access is read and stores the information. And a column address generation unit that generates a column address of data that needs to be read with reference to information stored in the storage unit, and the row address and the generation related to the read access to the memory device It is assumed that output control of data specified by the specified column address is performed.

  According to the present invention, since a column address of data to be read is generated inside the memory controller, it is not necessary to specify a large amount of physical addresses in the memory controller every time data is read, and the amount of input data related to read access is reduced. Reduced. In addition, only desired data in a row related to read access is output, and unnecessary data is not read out. This speeds up the read access of the memory device.

  Preferably, the memory controller includes a calculation unit that performs a specified calculation between given calculation target data and the specified data, and is generated by the calculation unit when a predetermined command is given. The output data shall be output.

  According to the present invention, since the arithmetic unit performs an operation on the data stored in the memory device, the load on the CPU or the like that should perform the operation is reduced.

  More preferably, the calculation unit performs a specified comparison operation between the calculation target data and the specified data, and based on a result of the comparison calculation, the predetermined bit belonging to the row related to the read access. Information indicating whether each piece of long data satisfies a predetermined condition is generated.

According to the present invention, even when the amount of data that needs to be read is large, the output data related to read access has a fixed length, and thus the amount of output data is reduced. This speeds up the read access of the memory device .

  Further, according to the present invention, the information processing system generates the memory controller and the information as described above, and the memory controller includes the first information accompanied by the generated information and a row address related to the read access. And a processing device that selectively gives one of a read request command and a second read request command with a row address and a column address related to read access. Then, it is assumed that the processing device selects the first and second read request commands in accordance with the density state of the data to be read in the row related to the read access. In addition, the memory controller has a column address selector that selects one of the column address given from the processing device and the column address generated by the column address generation unit, and a command given from the processing device, And a control unit for controlling the selection operation of the column address selector.

  Preferably, the memory controller includes a calculation unit that performs a calculation instructed by the processing device between given calculation target data and data output from the memory device, and is output from the calculation unit. And an output selector for selectively outputting either the data output from the memory device or the data output from the memory device. In addition, the control unit controls the selection operation of the output selector according to a command given from the processing device.

More preferably, the processing device instructs the arithmetic unit to perform a comparison operation. In addition, the arithmetic unit performs the comparison operation between the operation target data and the data output from the memory device, and performs a row related to the read access based on a result of the comparison operation. It is assumed that information indicating whether each of the data having a predetermined bit length belonging to the above satisfies a predetermined condition is generated .

  As described above, according to the present invention, regarding the data reading from the memory device, the data amount to be input to the memory controller and the data amount output from the memory device are reduced. This speeds up the read access of the memory device without particularly multiplexing the memory modules.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 shows a part of the configuration of a memory system including a memory controller and a general DRAM according to the first embodiment of the present invention. The memory controller 1A according to the present embodiment includes a storage unit 10, a column address generation unit 20, a column address selector 30, and a control unit 40. FIG. 1 shows only components necessary for explanation of read access.

  The storage unit 10 receives and stores a bitmap BMin that is information indicating whether or not each of data having a predetermined bit length belonging to a row related to read access is necessary. In the bit map BMin, for each piece of data having a predetermined bit length belonging to one row in the memory cell array 110, a bit that is required to be read is represented by bit "1", and a data that does not need to be read is represented by bit "0". Good. For example, when data is read in units of 32 bit words, the predetermined bit length is “32”, and if one row in the memory cell array 110 includes 4 kbytes (= 1024 words) of data, The amount of information of BMin is 1 kbit (= 32 words).

  The column address generation unit 20 refers to the bitmap BMin stored in the storage unit 10 and generates a column address of data that needs to be read. Specifically, the column address generation unit 20 generates a column address of data (word) corresponding to the bit “1” in the bitmap BMin.

The column address selector 30 selects one of a column address in an address ADDR given from a CPU (not shown) or the like, and a column address generated by the column address generation unit 20, and selects the selected column address C as a column address. Provide to buffer 120. The row address R in the address ADDR is given to the row address buffer 130, and the column address and the row address stored in the column address buffer 120 and the row address buffer 130 are decoded by the column decoder 140 and the row decoder 150, respectively. Desired data is amplified by the sense amplifier 160 and output from the output buffer 170 to the CPU or the like as data Dout.

  The control unit 40 controls the column address generation unit 20 and the column address selector 30. Specifically, the control unit 40 instructs the column address generation unit 20 to generate a column address when the read request command CMD issued by the CPU is an instruction requesting data specified by the bitmap BMin. At the same time, it instructs the column address selector 30 to select the column address generated by the column address generator 20. When receiving a normal read request command, the control unit 40 instructs the column address selector 30 to select a column address in the address ADDR.

Next, read access according to the present invention (hereinafter referred to as “bitmap access”) will be described with reference to the timing chart of FIG. First, after the row corresponding to the row address R is activated, the column addresses Ca, Cb, Cc, Cd, Ce , and Cf generated by the column address generation unit 20 are sequentially specified in synchronization with the clock CLK. Data Da, Db, Dc, Dd, De, and Df corresponding to these column addresses Ca to Cf are sequentially read in synchronization with the clock CLK. Thus, in the bitmap access, the column addresses Ca to Cf are generated inside the memory controller, and this point is different from the memory access in the conventional page mode. That is, in the page mode, a column address is given from the CPU to the memory controller every time in order to designate individual column addresses. In bitmap access, once a row address and a bitmap are given to the memory controller, The memory controller generates a column address, and the DRAM receiving it actively reads out desired data and outputs it to the CPU.

  FIG. 3 shows a configuration of an information processing system preferable for realizing bitmap access. The information processing system shown in FIG. 3 includes a memory controller 1A according to the present embodiment and a CPU 2 as a processing device.

  When performing bitmap access, the CPU 2 issues a read request command for bitmap access and gives the memory controller 1A a row address and a bitmap related to the read access. Normally, the CPU has a built-in cache memory, and cache line-oriented read access is possible. However, the CPU 2 further includes a FIFO (temporarily storing a data output from the memory device 100). first-in first-out) 3. The reason why the FIFO 3 is provided is that non-continuous data may be read in bitmap access, and a cache memory that assumes data continuity is not suitable. By providing the FIFO 3, the CPU 2 can fetch the data Dout read from the memory device 100 at an arbitrary timing regardless of whether or not the cache line is satisfied.

  In addition, by using a part of the cache memory having an N-way configuration in the actual CPU as a FIFO, it is possible to install the FIFO inside the CPU without significantly changing the circuit configuration and without particularly increasing the circuit scale. Can be realized. In addition, even without a FIFO, it is possible to perform processing by the cache memory by clarifying data discontinuity points by inserting bits indicating discontinuity into data obtained by bitmap access. It is.

  By the way, the bit map access has the effect of speeding up the reading of the non-contiguous data in the memory device, but it is more overhead than the normal memory access in that a relatively large bit map is given to the memory device at the time of the read request. Becomes larger. Therefore, when reading several pieces of data belonging to one row in the memory cell array, normal memory access is faster than bitmap access.

  FIG. 4 is a graph comparing time required for normal access and bitmap access (BMA). The horizontal axis p indicates the ratio of the total number of data related to the read request to the total number of data belonging to one row in the memory cell array, and the vertical axis T indicates the required number of cycles of the CPU. As described above, since bitmap access has a large overhead, when p is near zero, the required time is longer than that of normal access. However, since the read request command is issued only once, the required time increases linearly as p increases. On the other hand, normal access takes less time than bitmap access when p is near zero, but the number of read requests from the CPU also increases as the amount of data related to read requests increases. Therefore, the required time increases rapidly as p increases, and the required time becomes longer than bitmap access beyond a certain branch point. Therefore, in order to minimize the time required for read access, in FIG. 3, it is preferable that the CPU 2 switches the read request command in accordance with the density state of the data to be read in the row related to the read access. Specifically, the CPU 2 issues a normal read request command when it is determined that normal access is advantageous, and issues a read request command related to bitmap access when it is determined that bitmap access is advantageous.

  Note that the above branch point varies depending on the configuration of the information processing system, but can be uniquely identified from the cache capacity, the bitmap transfer speed, and the like. In addition, when the data to be read can be accessed with a fixed stride, read access by the above-described fixed stride transfer method may be selected.

(Second Embodiment)
FIG. 5 shows a part of the configuration of a memory system including a memory controller and a general DRAM according to the second embodiment of the present invention. The memory system 1B according to the present embodiment has a configuration in which a calculation unit 50 and an output selector 60 are further added to the memory controller 1A of FIG. In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals.

  The calculation unit 50 performs calculation between the calculation target data Dop given from a CPU (not shown) and the data Dout output from the output buffer 170 using an operator θ instructed by the CPU or the like, and the calculation result As data Dout2. The operations performed by the operation unit 50 include arithmetic operations (for example, addition, subtraction, division, and multiplication), logical operations (for example, logical sum, logical product, and exclusive logical sum), and comparison operations. (For example, “=”, “<”, “>”, “≦”, “≧”, “≠”, etc.).

  The output selector 60 selects one of the data Dout and the data Dout2, and outputs it as data DT to a CPU or the like. The selection operation of the output selector 60 is controlled by the control unit 40. Specifically, the control unit 40 instructs the output selector 60 to select the data Dout2 in the case of bitmap access, while instructing to select the data Dout in the case of normal read access. To do.

  When considering conditional branch processing in a main memory database or the like, the data itself stored in the memory device is not so important, and it is often sufficient to obtain the result of the comparison operation. Therefore, in particular, a case where a comparison operation is performed by the operation unit 50 will be considered. In this case, the operation unit 50 compares the operation target data Dop and the data Dout, and based on the result of the comparison, whether each of the data having a predetermined bit length belonging to the row related to the read access satisfies a predetermined condition. A bit map (hereinafter referred to as “bit map BMout” in order to distinguish it from the bit map BMin) is generated. Such a calculation unit 50 can be realized by a comparator array. Whether or not the data Dout satisfies a predetermined condition is given as a result of performing a comparison operation with the operator θ on the operation target data Dop and the data Dout. For example, when “=” is specified as the operator θ, the bit corresponding to the data Dout in the bitmap BMout is, for example, “1” if the operation target data Dop and the data Dout are equal, and “0” if they are not equal. "

  Since the bitmap BMout indicates whether or not a predetermined condition is satisfied for each of the data having a predetermined bit length belonging to the row related to the read access, the information amount thereof is the same as that of the bitmap BMin. For example, when data is read in units of 32 bit words, the predetermined bit length is “32”, and if one row in the memory cell array 110 includes 4 kbytes (= 1024 words) of data, The information amount of BMout is 1 k bits (= 32 words), which is the same as that of the bitmap BMin. That is, the amount of information in the bitmap BMout is constant even when there is a lot of data to be read, and the amount of output data is reduced.

  As described above, according to the present embodiment, since the memory controller performs relatively simple operations such as arithmetic operations, logical operations, and comparison operations on the data stored in the memory device, the CPU does not need to perform these simple operations. Therefore, time can be allocated to other processes. In particular, only the result of the comparison operation is transmitted to the CPU by performing the comparison operation by the memory controller and outputting the bitmap BMout. As a result, data required only for the comparison operation is not sent from the memory device to the CPU, and the bus resources can be used for other data transfers accordingly. That is, the performance of the entire system is improved.

FIG. 6 shows a configuration of an information processing system including the memory controller according to the present embodiment. In the information processing system of FIG. 6, the FIFO 3 is provided inside the memory controller 1B. As described above, the FIFO 3 is not necessarily provided inside the CPU 2. Note that the CPU 2 may receive the data DT from the FIFO 3, or may fetch the data into the cache line as in the conventional case.

  As described above, the embodiment of the present invention has been described by taking the DRAM memory controller as an example, but the present invention is not limited to this. That is, the memory controller and the read access method according to the present invention include not only a semiconductor memory device represented by a DRAM but also a memory having an approximately cell array structure such as a magnetoresistive memory device (MRAM) and a ferroelectric memory device (FeRAM). Applicable to devices in general.

  Since the memory controller and the information processing system according to the present invention enable high-speed read access, they are useful in application fields such as a main memory database, large-scale numerical calculation, and stream data processing.

1 is a configuration diagram of a memory system including a memory controller according to a first embodiment. 3 is a timing chart relating to read access by the memory controller of FIG. 1. It is a block diagram of the information processing system provided with the memory controller of FIG. It is the graph which compared the required time concerning normal access and bitmap access. It is a block diagram of the memory system provided with the memory controller which concerns on 2nd Embodiment. It is a block diagram of the information processing system provided with the memory controller of FIG.

1A, 1B Memory controller 2 CPU (Processor)
3 FIFO
DESCRIPTION OF SYMBOLS 10 Storage part 20 Column address generation part 30 Column address selector 40 Control part 50 Calculation part 60 Output selector

Claims (3)

Receives information indicating whether or not each piece of data having a predetermined bit length belonging to a row related to read access is necessary, and refers to the information stored in the storage unit that stores the information and the data that needs to be read. A memory controller that controls the output of data specified by the row address related to the read access and the generated column address ;
The information is generated, and the memory controller receives a first read request command with the generated information and a row address related to read access, and a second read request command with a row address and column address related to read access. A processing device that selectively gives one of them,
The processing device performs selection of the first and second read request commands in accordance with a density state of data to be read in a row related to the read access.
The memory controller is
A column address selector for selecting either a column address given from the processing device or a column address generated by the column address generation unit;
An information processing system comprising: a control unit that controls a selection operation of the column address selector according to a command given from the processing device. In the information processing system according to claim 1,
The memory controller is
A calculation unit that performs a calculation instructed by the processing device between given calculation target data and data output from the memory device;
An output selector that selectively outputs any one of the data output from the arithmetic unit and the data output from the memory device;
The information processing system, wherein the control unit controls a selection operation of the output selector in accordance with a command given from the processing device. In the information processing system according to claim 2,
The processing device instructs the arithmetic unit to perform a comparison operation,
The operation unit performs the comparison operation between the operation target data and the data output from the memory device, and based on a result of the comparison operation, data having a predetermined bit length belonging to the row related to the read access An information processing system for generating information indicating whether or not each satisfies a predetermined condition.

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