JP4767264B2 - High voltage semiconductor device - Google Patents

Description

  The present invention relates to a high voltage semiconductor device, and more particularly to a high voltage semiconductor device in which a current conduction state and a current interruption state are realized by a voltage of a control electrode.

  Hereinafter, the structure and operation of a conventional high voltage semiconductor device will be described with reference to FIGS. FIG. 40 is a partial cross-sectional view showing a first example of a conventional high voltage semiconductor device.

Referring to FIG. 40, n ⁻ layer 2 is formed on the main surface of p type semiconductor substrate 1. An n ⁺ buried diffusion region 8 is formed at the boundary between the n ⁻ layer 2 and the p-type semiconductor substrate 1. A p diffusion region 7 is formed so as to penetrate n ⁻ layer 2 in the depth direction and reach the main surface of p type semiconductor substrate 1. A p-channel MOS transistor 14 is formed on the surface of the n − layer 2. The p-channel MOS transistor 14 includes a p ⁻ diffusion region 5, a p ⁺ diffusion region 3, and a gate electrode (control electrode) 9.

An n ⁺ diffusion region 4 is formed adjacent to the p ⁺ diffusion region 3. In addition, n diffusion region 4 a is formed so as to surround p ⁺ diffusion region 3 and n ⁺ diffusion region 4. Source electrode 11 is formed so as to be in contact with both n ⁺ diffusion region 4 and p ⁺ diffusion region 3. Source electrode 11 extends on gate electrode 9 and p ⁻ diffusion region 5 with oxide film 10 interposed therebetween. A p ⁺ diffusion region 6 is formed so as to be continuous with one end of p ⁻ diffusion region 5. A drain electrode 12 is formed on the surface of the p ⁺ diffusion region 6. On the other hand, a substrate electrode (back surface electrode) 13 is formed on the back surface of the p-type semiconductor substrate 1.

  Next, the operation of the high voltage semiconductor device shown in FIG. 40 will be described with reference to FIGS. First, the off operation will be described with reference to FIGS. 41 and 42. 41 and 42 are diagrams showing stepwise the state of the depletion layer during the off operation of the high voltage semiconductor device shown in FIG.

First, referring to FIGS. 41 and 42, the potential of drain electrode 12 and substrate electrode 13 is set to 0 V, and a positive potential (+ Vcc) is applied to gate electrode 9 and source electrode 11. Thereby, mainly, a pn junction B at the interface between the n ⁻ layer 2 and the p-type semiconductor substrate 1, a pn junction A at the interface between the n ⁻ layer 2 and the p diffusion region 7, and the n ⁻ layer 2 A depletion layer extends from the pn junction C at the interface with the p ⁻ diffusion region 5.

At this time, the depletion layer extending from the pn junction A becomes easier to extend than usual due to the influence of the depletion layer extending from the pn junction B. For this reason, the electric field in the vicinity of the pn junction A is kept at a relatively small value. This effect, the concentration and the p-type semiconductor substrate 1, n ^- and impurity concentration of the n type contained in the layer 2, n ^- is achieved by optimizing the thickness of the layer 2, generally RESURF (REduced SURface Field) It is called an effect.

On the other hand, since the depletion layer extending from the pn junction C has a low concentration in the p − diffusion region 5, the p ⁻ diffusion region 5 is depleted at the same time as extending to the n ⁻ layer 2 side. The gate electrode 9 and the source electrode 11 formed so as to overlap the p ⁻ diffusion region 5 form a two-stage field plate. Thereby, depletion of p ⁻ diffusion region 5 is promoted, and the electric field in the vicinity of gate electrode 9 of pn junction C is relaxed.

When the conditions of each element are optimized, a higher positive potential can be applied. Finally, the breakdown voltage is determined by the junction between n ⁺ buried diffusion region 8 and p-type semiconductor substrate 1. At this time, the n ⁻ layer 2 and the p ⁻ diffusion region 5 are almost depleted. In this way, the off state can be maintained.

Next, the on operation will be described with reference to FIG. FIG. 43 is a diagram showing an on state of the conventional high voltage semiconductor device shown in FIG. Referring to FIG. 43, the potential of gate electrode 9 is lowered with respect to the potential of source electrode 11. As a result, the surface of the n ⁻ layer 2 immediately below the gate electrode 9 is inverted to the p-type. Thereby, a hole current flows from p ⁺ diffusion region 3 through p ⁻ diffusion region 5 to p ⁺ diffusion region 6 as indicated by an arrow in FIG. Thereby, the ON state is realized. Most of the resistance of the device in the on state is the resistance value of the p ⁻ diffusion region 5. Therefore, in order to reduce the resistance of the device in the on state, it is effective to reduce the resistance of the p ⁻ diffusion region 5. However, in order to ensure a high breakdown voltage, the p ⁻ diffusion region 5 needs to be substantially depleted in the off state. Therefore, the p-type impurity concentration contained in p ⁻ diffusion region 5 naturally has an upper limit (optimum value).

Next, a second example of a conventional high voltage semiconductor device will be described with reference to FIGS. FIG. 44 is a partial cross-sectional view showing a conventional high voltage semiconductor device in the second example. Referring to FIG. 44, the high voltage semiconductor device in the first example shown in FIG. 40 is different in whether n ⁺ diffusion region 15 is formed in p ⁺ diffusion region 6 or not. Other structures are the same as those of the high voltage semiconductor device shown in FIG.

  Next, the operation of the high voltage semiconductor device shown in FIG. 44 will be described with reference to FIGS. 45 and 46 are diagrams showing stepwise the state of the depletion layer during the off operation of the high voltage semiconductor device shown in FIG. Since the off operation is the same as that of the high voltage semiconductor device in the first example shown in FIG. 40, the description is omitted.

  Next, the on operation of the high voltage semiconductor device according to the second example will be described with reference to FIG. FIG. 47 is a diagram showing an on state of the high breakdown voltage semiconductor device according to the second example.

Referring to FIG. 47, the potential of gate electrode 9 is lowered with respect to source electrode 11. As a result, the surface of the n ⁻ layer 2 immediately below the gate electrode 9 is inverted to the p-type. As a result, hole current 37 b flows from p ⁺ diffusion region 3 through p ⁻ diffusion region 5 to p ⁺ diffusion region 6. In response to this, an electron current 37 a flows from the n ⁺ diffusion region 15 into the p ⁻ diffusion region 5 and the n ⁻ layer 2. Thereby, a high accumulation state of electrons and holes is realized, and conductivity modulation is caused. As a result, an on state is realized. That is, the high breakdown voltage semiconductor device in the second example operates as a p-channel IGBT.

  FIG. 48 is a bird's-eye view showing the overall structure of the high voltage semiconductor device in the second example.

  Next, a third example of a conventional high voltage semiconductor device will be described with reference to FIGS. FIG. 49 is a partial sectional view showing a high voltage semiconductor device according to the third example.

Referring to FIG. 49, buried oxide film 17 is formed on the surface of semiconductor substrate 16. An n ⁻ layer 2 is formed on buried oxide film 17. In addition, trench 22 is formed at a predetermined position of n ⁻ layer 2. An oxide film 18 is formed on the inner surface of the trench 22. A polysilicon layer 19 is embedded in the oxide film 18. The other structure is the same as that of the high voltage semiconductor device in the first example shown in FIG.

Next, the operation of the high voltage semiconductor device according to the third example will be described with reference to FIGS. 50 and 51 are diagrams showing stepwise the state of the depletion layer during the off operation of the high breakdown voltage semiconductor device according to the third example. Referring to these drawings, as in the case of the high breakdown voltage semiconductor device in the first example, the potential of the drain electrode 12 and the substrate electrode 13 is set to 0 V, and the gate electrode 9 and the source electrode 11 have a positive potential ( + V) is applied. As a result, a depletion layer mainly extends from the pn junction at the interface between p ⁻ diffusion region 5 and n ⁻ layer 2 and the pn junction at the interface between p ⁺ diffusion region 6 and n ⁻ layer 2.

At the same time, the depletion layer starts to extend from the interface between the n ⁻ layer 2 and the buried oxide film 17. This contributes to electric field relaxation. As a result, the aforementioned RESURF effect is obtained. The RESURF effect is described in, for example, S. Merchant et al. “Realization of high breakdown voltage (> 700 V) in thin SOI devices” Proc. Of 3rd ISPSD, pp. 31-35 , 1991 . The on operation of the high voltage semiconductor device in the third example is shown in FIG. 52. Since the on operation is the same as that of the high voltage semiconductor device in the first example, description thereof is omitted.

  Next, a fourth example of a conventional high voltage semiconductor device will be described with reference to FIGS. FIG. 53 is a partial sectional view showing a fourth example of a conventional high voltage semiconductor device.

Referring to FIG. 53, in the high breakdown voltage semiconductor device according to the fourth example, p ⁺ diffusion region 3 and p diffusion region 3a are formed in n ⁻ layer 2, and the surface of p ⁺ diffusion region 3 is formed. An n ⁺ diffusion region 4 is formed. An n ⁺ diffusion region 15 is formed at a distance from the p ⁺ diffusion region 3. Then, gate electrode 9 is formed on p diffusion region 3a located between n ⁺ diffusion region 4 and n ⁻ layer 2 with oxide film 10 interposed. Further, the source electrode 11 is formed in contact with the surfaces of both the p ⁺ diffusion region 3 and the n + diffusion region 4. Next, drain electrode 12 is formed in contact with the surface of n ⁺ diffusion region 15. Next, the operation of the high voltage semiconductor device in the fourth example will be described with reference to FIGS. 54 and 55. FIG. 54 is a diagram showing the state of the depletion layer during the off operation of the high breakdown voltage semiconductor device according to the fourth example.

Referring to FIG. 54, the potentials of source electrode 11, gate electrode 9 and substrate electrode 13 are set to 0 V, and a positive potential (+ Vcc) is applied to drain electrode 12. Thereby, the depletion layer mainly extends from the pn junction A at the interface between the p diffusion region 3 a and the n ⁻ layer 2. At the same time, the depletion layer also extends from the interface B between the n ⁻ layer 2 and the buried oxide film 17. Thereby, the elongation of the depletion layer is promoted, and the depletion layer further expands. That is, the RESURF effect is obtained. As a result, the breakdown voltage of the device is increased.

Next, the on operation will be described. FIG. 55 is a diagram showing an on state of the high breakdown voltage semiconductor device according to the fourth example. Referring to FIG. 55, the potential of source electrode 11 and substrate electrode 13 is set to 0 V, the potential of gate electrode 9 is raised with respect to source electrode 11, and a positive potential (+ Vcc) is applied to drain electrode 12. As a result, the surface of the p ⁺ diffusion region 3 immediately below the gate electrode 9 is inverted to n-type, and an inversion region 38 is formed. Thereby, electrons reach n ⁻ layer 2 and n ⁺ diffusion region 15 from n ⁺ diffusion region 4 through inversion region 38. As a result, an on operation is realized.

In the conventional high voltage semiconductor devices in the first to third examples, the resistance value of the p ⁻ diffusion region 5 is a factor that substantially determines the resistance value of the high voltage semiconductor device during the on-operation. Therefore, a reduction in resistance of the p ⁻ diffusion region 5 is desired. For this purpose, a method of increasing the concentration of the p-type impurity contained in the p ⁻ diffusion region 5 is generally considered. However, this suppresses the growth of the depletion layer in the p ⁻ diffusion region 5. As a result, there is a problem that the electric field in the depletion layer is easily increased and the breakdown voltage of the high breakdown voltage semiconductor device is lowered.

In the conventional high voltage semiconductor device in the fourth example, the resistance value of the n ⁻ layer 2 is a factor that determines the resistance value of the high voltage semiconductor device during the on-operation. Therefore, it is desired to reduce the resistance of the n ⁻ layer 2. As a technique for this, a technique for increasing the n-type impurity concentration contained in the n ⁻ layer 2 can be considered as in the above case. However, in this case as well, as in the first to third examples described above, there is a problem that the expansion of the depletion layer in the n ⁻ layer 2 is suppressed and the breakdown voltage of the high breakdown voltage semiconductor device is deteriorated. Arise.

  As described above, in the conventional high withstand voltage semiconductor device, it is difficult to realize both the reduction of the resistance value of the device during the on operation and the increase of the withstand voltage of the device during the off operation.

  The present invention has been made to solve the above-described problems. An object of the present invention is to provide a high breakdown voltage semiconductor device that can reduce the resistance value of a device during an on operation without substantially reducing the breakdown voltage of the device during an off operation.

The high breakdown voltage semiconductor device according to the present invention includes a semiconductor substrate having a main surface, a first conductivity type semiconductor layer, a second conductivity type first impurity diffusion region, and a first conductivity type second and third. An impurity diffusion region, a gate electrode, and a source and drain electrode. The semiconductor layer is formed on the main surface of the semiconductor substrate via a buried oxide film . The first impurity diffusion region is formed on the surface of the semiconductor layer. The second impurity diffusion region is formed on the surface of the first impurity diffusion region. The third impurity diffusion region is formed on the surface of the semiconductor layer at a distance from the first impurity diffusion region. The gate electrode is formed on the surface of the first impurity diffusion region located between the second and third impurity diffusion regions with an insulating layer interposed. The source electrode is formed in contact with both the surface of the second impurity diffusion region and the surface of the first impurity diffusion region adjacent to the second impurity diffusion region. The drain electrode is formed in contact with the surface of the third impurity diffusion region. Then, the fourth impurity diffusion region of the second conductivity type is formed in the direction from the first impurity diffusion region to the third impurity diffusion region in the bottom region of the semiconductor layer located between the first and third impurity diffusion regions. A plurality of are formed.

In the high breakdown voltage semiconductor device of the present invention , the fourth impurity diffusion region is formed in the bottom region of the semiconductor layer adjacent to the main surface of the semiconductor substrate. By forming the fourth impurity diffusion region, it is possible to promote the extension of the depletion layer extending from the junction between the semiconductor substrate and the semiconductor layer. As a result, the breakdown voltage of the high breakdown voltage semiconductor device during the off operation can be improved. Further, even when an increased impurity concentration of the first conductivity type included in the semi-conductor layer, it is possible to maintain a high breakdown voltage of the high-voltage semiconductor device. As a result, it is possible to reduce the resistance value of the high voltage semiconductor device during the on operation.

Embodiments of the present invention will be described below with reference to FIGS.
(Embodiment 1)
FIG. 1 is a partial sectional view showing Embodiment 1 of the present invention. More specifically, an embodiment in which the present invention is applied to a p-channel MOS device is shown. Referring to FIG. 1, n ⁻ layer 2 is formed on the main surface of p-type semiconductor substrate 1. A p diffusion region 7 is formed to reach p type semiconductor substrate 1 through n ⁻ layer 2. A p-channel MOS transistor 14 is formed on the surface of n ⁻ layer 2. This p-channel MOS transistor 14 includes p ⁻ diffusion region 5, p ⁺ diffusion region 3, and gate electrode 9. Gate electrode 9 is formed on the surface of n ⁻ layer 2 located between p ⁻ diffusion region 5 and p ⁺ diffusion region 3 with oxide film 10 interposed.

An n ⁺ diffusion region 4 is formed adjacent to the p ⁺ diffusion region 3. Further, p ⁺ diffusion region 6 is formed so as to be continuous with one end of p ⁻ diffusion region 5. A drain electrode 12 is formed in contact with the surface of the p ⁺ diffusion region 6, and a source electrode 11 is formed in contact with the surface of the p ⁺ diffusion region 3 and the surface of the n ⁺ diffusion region 4. As shown in FIG. 1, source electrode 11 extends on gate electrode 9 and on p ⁻ diffusion region 5.

Then, p diffusion region 20 is formed so as to reach n ⁻ layer 2 from within p ⁻ diffusion region 5. Since the overall configuration of the high voltage semiconductor device shown in FIG. 1 is substantially the same as that of the conventional high voltage semiconductor device shown in FIG. 48, p diffusion region 20 has a ring-like planar structure.

Here, the p diffusion region 20 will be described in more detail. The p-type impurity concentration contained in the p diffusion region 20 (in this specification, “impurity concentration” means the impurity peak concentration) is 10 times the p-type impurity concentration contained in the p ⁻ diffusion region 5. It is preferably about 100 times or more. Further, it is preferable that a plurality of p diffusion regions 20 are provided at intervals in the longitudinal direction of the p ⁻ diffusion region 5. As described above, a plurality of p diffusion regions 20 are provided in the p ⁻ diffusion region 5 with an interval therebetween, thereby promoting the extension of the depletion layer in the horizontal direction during the off operation of the high breakdown voltage semiconductor device.

  FIG. 2 shows the state of the depletion layer during the off operation of the high voltage semiconductor device according to the first embodiment. In FIG. 2, reference numeral 21 denotes a depletion layer end. Referring to FIG. 2, the potential of substrate electrode 13 and drain electrode 12 is set to 0 V, and a positive potential (+ V) is applied to gate electrode 9 and source electrode 11. Thereby, a depletion layer extends from the pn junctions A, B, and C.

Particularly in the vicinity of the surface of the n ⁻ layer 2, the presence of the ring-shaped p diffusion region 20 promotes the extension of the depletion layer in the horizontal direction. Although the undepleted region 30 is left in a part of the p + diffusion region 6 and the p diffusion region 20, the depletion layer is sufficiently expanded in the n ⁻ layer 2. Thereby, the electric field strength in the depletion layer is relaxed, and the same effect as the RESURF effect is obtained. The structure corresponding to the ring-shaped p diffusion region 20 is called Floating Field Rings and has an effect of promoting the elongation of the depletion layer. This is described, for example, in BJ Balign “Modern Power Devices” 1987, pp . 92-99 .

  Next, the on operation of the high voltage semiconductor device in the first embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 3A is a diagram showing a state during the on-operation of the high voltage semiconductor device shown in FIG. FIG. 3B is a diagram showing a state at the time of an on operation of the conventional high voltage semiconductor device.

First, referring to FIG. 3A, in the ON state of the high breakdown voltage semiconductor device, the potential of the drain electrode 12 and the substrate electrode (not shown) is set to 0 V, and a positive potential (+ Vcc) is applied to the source electrode 11. This is realized by lowering the potential of the gate electrode 9 with respect to the source electrode 11. Then, the surface of the n ⁻ layer 2 immediately below the gate electrode 9 is inverted to the p-type, and a current flows from the source electrode 11 to the drain electrode 12.

  Here, the resistance components of the p- diffusion region 5 are RA1, RA2... RAm, the resistance components of the p diffusion region 20 are RB1, RB2. On the other hand, as shown in FIG. 3B, the resistance components of the p @-diffusion region 5 at the position corresponding to the p diffusion region 20 in the conventional example are denoted by RC1, RC2,... RCn.

Then, assuming that the total resistance of p ⁻ diffusion region 5 and p diffusion region 20 in the first embodiment is Rtot (N) and the total resistance of p ⁻ diffusion region 5 in the conventional example is Rtot (O), It is expressed as follows.

  The value of Rtot (O) −Rtot (N) is expressed as follows.

Here, since the p-type impurity concentration contained in the p diffusion region 20 is higher than the p-type impurity concentration contained in the p ⁻ diffusion region 5 as described above, the relationship of RBi> RCi is established.

  As a result, the following relational expression is obtained.

  As described above, by providing the p diffusion region 20, it is possible to reduce the resistance value of the high voltage semiconductor device during the on-operation.

In view of the above contents, it is considered that the resistance value of the high-breakdown-voltage semiconductor device can be further effectively reduced by increasing the concentration uniformly throughout the entire p ⁻ diffusion region 5. . Therefore, the inventors of the present application have studied a technique for uniformly increasing the concentration over the entire p ⁻ diffusion region 5. The results will be described below.

FIG. 4 is a diagram showing the result of computer simulation on the change in breakdown voltage of the high breakdown voltage semiconductor device with respect to the surface concentration of p ⁻ diffusion region 5. By controlling the conditions corresponding to the p-type semiconductor substrate 1, two models having a breakdown voltage of 450 V and 600 V, respectively, in the absence of the p ⁻ diffusion region 5 were verified. As shown in FIG. 4, all show a tendency that the pressure resistance decreases as the surface concentration increases. In the state where the concentration reached 1E17 cm ⁻³ , it can be seen that the withstand voltage is reduced to about 150 V regardless of the initial design conditions.

Here, in consideration of the above contents, the case where the p ⁻ diffusion region 5 is uniformly concentrated and the case where the p diffusion region 20 is provided as in the first embodiment will be compared. FIGS. 5A to 5C show the state of the depletion layer when a positive potential (+ V1 <+ V2 <+ V3) is sequentially applied to a high breakdown voltage semiconductor device having the p diffusion region 24 that is uniformly highly concentrated. FIG. FIG. 6 is a diagram showing the state of the depletion layer when the positive potentials + V1, + V2, and + V3 are sequentially applied to the high voltage semiconductor device of the first embodiment.

  First, referring to FIG. 5A, a depletion layer starts to extend from the pn junctions A, B, and C by applying a positive potential + V1. When a higher potential is applied, the depletion layer extends toward the source electrode 11 as shown in FIGS. 5B and 5C. However, since the p diffusion region 24 is uniformly high in concentration, the degree of extension of the depletion layer gradually decreases as the source electrode 11 is approached. Then, as shown in FIG. 5C, an electrolytic concentration point 32 is generated, and avalanche breakdown is caused.

On the other hand, in the high withstand voltage semiconductor device according to the first embodiment of the present invention, the depletion layer is smoothly directed toward the source electrode 11 as the high voltage is sequentially applied, as sequentially shown in FIGS. It spreads. This is because the p − diffusion region 5 exists between the p diffusion regions 20. As shown in FIGS. 6B and 6C, when the depletion layer extends, an undepleted region 30 remains in the p diffusion region 20, but p ⁻ diffusion occurs at a position adjacent to the p diffusion region 20. Since the region 5 exists, extension of the depletion layer is promoted. That is, since the p ⁻ diffusion region 5 exists between the p diffusion regions 20, the depletion layer continues to grow while the p ⁻ diffusion region 5 is completely depleted. As a result, the depletion layer can be sufficiently expanded, and the breakdown voltage of the high breakdown voltage semiconductor device during the off operation can be improved.

  As described above, in the high voltage semiconductor device according to the first embodiment, the resistance value of the high voltage semiconductor device during the on operation can be reduced without reducing the voltage resistance of the high voltage semiconductor device during the off operation. It becomes.

(Embodiment 2)
Next, Embodiment 2 of the present invention will be described with reference to FIGS. FIG. 7 is a partial sectional view showing a high voltage semiconductor device according to the second embodiment of the present invention.

Referring to FIG. 7, the difference from the high voltage semiconductor device shown in FIG. 1 is whether or not n ⁺ buried diffusion region 8 is formed. Other configurations are the same as those of the high voltage semiconductor device shown in FIG.

As described above, by providing the n ⁺ buried diffusion region 8, the following effects can be obtained. FIG. 8 is a diagram showing the state of the depletion layer during the off operation of the high voltage semiconductor device shown in FIG. By providing n ⁺ buried diffusion region 8 as described above, depletion occurs in n ⁻ layer 2 located between n ⁺ buried diffusion region 8 and p ⁺ diffusion region 3 as shown in FIG. It is possible to prevent the layer from spreading. As a result, the depletion layer extends into the p-type semiconductor substrate 1 located under the n ⁺ buried diffusion region 8. At this time, since the p-type semiconductor substrate 1 has a low concentration and a large thickness, the depletion layer can be sufficiently extended. As a result, the breakdown voltage of the high breakdown voltage semiconductor device during the off operation can be further improved.

(Embodiment 3)
Next, Embodiment 3 of the present invention will be described with reference to FIG. 9 and FIG. FIG. 9 is a partial cross-sectional view showing a high voltage semiconductor device according to Embodiment 3 of the present invention.

Referring to FIG. 9, in the high breakdown voltage semiconductor device according to the third embodiment, buried oxide film 17 is formed on the surface of semiconductor substrate 16, and n ⁻ layer 2 is formed on the surface of buried oxide film 17. Is done. That is, a high voltage semiconductor device having an SOI (Semiconductor On Insulator) structure is shown. A trench 22 is provided so as to penetrate n ⁻ layer 2, and oxide film 18 and polysilicon layer 19 are buried in trench 22. Other structures are the same as those of the high voltage semiconductor device of the first embodiment shown in FIG.

FIG. 10 shows the state of the depletion layer during the off operation of the high breakdown voltage semiconductor device according to the third embodiment. As shown in FIG. 10, the depletion layer extends sufficiently in the n ⁻ layer 2 while leaving the undepleted region 30. Also in this case, the presence of the p diffusion region 20 and the p ⁻ diffusion region 5 promotes the horizontal extension of the depletion layer. Thereby, the RESURF effect is effectively exhibited, and the breakdown voltage during the off operation is improved. Note that the same effect as in the first embodiment can be obtained with respect to the ON operation.

(Embodiment 4)
Next, Embodiment 4 will be described with reference to FIGS. FIG. 11 is a partial cross-sectional perspective view showing a high voltage semiconductor device according to Embodiment 4 of the present invention.

Referring to FIG. 11, p diffusion region 23 containing p-type impurities having a concentration equal to or higher than the p-type impurity concentration contained in p ⁻ diffusion region 5 is formed, and n ⁻ diffusion region is formed on the surface of p diffusion region 23. 2a is provided. An n ⁺ diffusion region 15 is formed on the surface of the p ⁺ diffusion region 6. Other structures are almost the same as those of the high voltage semiconductor device shown in FIG.

As described above, by providing the n ⁻ diffusion region 2 a on the surface of the p diffusion region 23, regions in which modulation is caused by electron injection are formed above and below the p diffusion region 23 during the ON operation. Thereby, the modulation efficiency can be improved, and the switching operation speed can be increased.

FIG. 12 shows a part of a cross section taken along line XII-XII in FIG. Referring to FIG. 12, p diffusion region 23 has a gap 31 on its side. By having the gap 31, it is possible to form a region in which modulation is caused not only on the top and bottom of the p diffusion region 23 but also on the left and right. Thereby, the modulation efficiency can be further improved. Note that the n ⁻ diffusion region 2 a and the n ⁻ layer 2 are connected by the gap 31.

  Next, the off operation of the high voltage semiconductor device according to the fourth embodiment will be described with reference to FIG. FIG. 13 is a diagram illustrating the state of the depletion layer during the off operation of the high breakdown voltage semiconductor device according to the fourth embodiment.

  Referring to FIG. 13, a predetermined voltage is applied under the same voltage application conditions as in the first embodiment. As a result, the depletion layer begins to extend from the pn junctions A, B, C, and D. In particular, the depletion layer extending from the pn junctions C and D grows so as to sandwich the p diffusion region 23 from above and below the p diffusion region 23 as indicated by an arrow 25 in FIG. Thereby, depletion of the p diffusion region 23 can be promoted, and the RESURF effect can be effectively expressed. Thereby, the breakdown voltage of the high breakdown voltage semiconductor device during the off operation can be improved.

In addition, since the depletion of the p diffusion region 23 is further promoted as described above, the p type impurity concentration of the p diffusion region 23 can be made higher than the p type impurity concentration of the p ⁻ diffusion region 5. It becomes. Thereby, it is possible to reduce the resistance value of the high voltage semiconductor device during the on-operation.

(Embodiment 5)
Next, Embodiment 5 of the present invention will be described with reference to FIGS. FIG. 14 is a partial cross sectional view showing a high voltage semiconductor device according to Embodiment 5 of the present invention. More specifically, an embodiment in which the present invention is applied to an IGBT is shown. Referring to FIG. 14, the difference between the high voltage semiconductor device in the fifth embodiment and the high voltage semiconductor device shown in FIG. 11 is whether or not n ⁺ buried diffusion region 8 is formed.

By providing this n ⁺ buried diffusion region 8, as shown in FIG. 15, the depletion layer can be expanded in the p-type semiconductor substrate 1 located under the n ⁺ buried diffusion region 8 during the off operation. Become. Thereby, the breakdown voltage of the high breakdown voltage semiconductor device can be further improved as in the case of the second embodiment.

(Embodiment 6)
Next, Embodiment 6 of the present invention will be described with reference to FIGS. FIG. 16 is a partial sectional view showing a high voltage semiconductor device according to the sixth embodiment of the present invention.

Referring to FIG. 16, n ⁻ layer 2 is formed on the surface of p type semiconductor substrate 16 with a buried oxide film 17 interposed. A trench 22 is provided so as to penetrate the n ⁻ layer 2, and an oxide film 18 and a polysilicon layer 19 are buried in the trench 22. Other structures are the same as those of the high voltage semiconductor device shown in FIG.

Also in the case of the high breakdown voltage semiconductor device according to the sixth embodiment, the depletion layer can be sufficiently expanded in n ⁻ layer 2 as shown in FIG. Thereby, the same effect as in the case of the above-described fourth embodiment can be obtained.

(Embodiment 7)
Next, Embodiment 7 of the present invention will be described with reference to FIGS. FIG. 18 is a cross sectional view showing a high voltage semiconductor device according to Embodiment 7 of the present invention. More specifically, an embodiment in which the present invention is applied to an n-channel MOS device is shown.

Referring to FIG. 18, a buried oxide film 17 is formed on the surface of the semiconductor substrate 16. An n ⁻ layer 2 is formed on buried oxide film 17. An n channel MOS transistor 14 a is formed on the surface of n ⁻ layer 2. This n-channel MOS transistor 14 a is composed of an n ⁺ diffusion region 4, a gate electrode 9, and an n ⁻ layer 2. A p diffusion region 3a is formed in n ⁻ layer 2.

N ⁺ diffusion region 15a is formed at a distance from p diffusion region 3a. The drain electrode 12 is formed in contact with the surface of the n ⁺ diffusion region 15a, and the source electrode 11 is formed in contact with the surface of the p diffusion region 3a and the surface of the n ⁺ diffusion region 4.

A trench 22 is formed so as to pass through n ⁻ layer 2 and reach buried oxide film 17, and oxide film 18 and polysilicon layer 19 are buried in trench 22. Then, a p diffusion region 26 is formed in the bottom region of n ⁻ layer 2 located between p diffusion region 3 a and n ⁺ diffusion region 15 a in the vicinity of buried oxide film 17.

  As shown in FIG. 18, a plurality of p diffusion regions 26 may be provided at intervals, but adjacent p diffusion regions 26 are connected by, for example, a p-type low concentration region. It may be. Further, the p-type impurity concentration contained in the p diffusion region 26 may be equal to or higher than the p-type impurity concentration contained in the p diffusion region 3a. Preferably, the p-type impurity concentration contained in the p diffusion region 26 is about 10 to 100 times the p-type impurity concentration contained in the p diffusion region 3a.

  The reason why the breakdown voltage of the high breakdown voltage semiconductor device during the off operation can be improved by forming the p diffusion region 26 as described above will be described below. FIG. 19 is a diagram showing the state of the depletion layer during the off operation of the high breakdown voltage semiconductor device according to the seventh embodiment. As shown in FIG. 19, in order to turn off the high breakdown voltage semiconductor device according to the seventh embodiment, the potentials of the source electrode 11, the gate electrode 9 and the substrate electrode 13 are set to 0 V, and the drain electrode 12 has a positive potential ( + V) is applied. As a result, the depletion layer begins to extend from the pn junction A and the interface E.

Here, as shown in FIG. 19, the p diffusion region 26 is provided at the bottom of the n ⁻ layer 2 located between the p diffusion region 3a and the n ⁺ diffusion region 15a, so that the p diffusion region 26 is depleted. It will have the function of promoting the horizontal spread of the layer. Further, by providing a plurality of p diffusion regions 26 toward the bottom region of the n ⁻ layer 2 located immediately below the drain electrode 12, the function of further promoting the horizontal extension of the depletion layer becomes excellent. .

  Thereby, the extension of the depletion layer in the horizontal direction is promoted, and the RESURF effect is effectively expressed. As a result, the breakdown voltage of the high breakdown voltage semiconductor device during the off operation can be improved. In addition, by providing the p diffusion region 26, it is possible to expand a range in which a certain breakdown voltage can be maintained for various parameters related to the breakdown voltage determination.

FIG. 20 is a diagram showing a change in breakdown voltage of the high breakdown voltage semiconductor device with respect to the specific resistance of the n ⁻ layer 2. In FIG. 20, the characteristic of the conventional example is shown by a solid line. As shown in FIG. 20, after showing a slight increase tendency with a decrease in the specific resistance of the n ⁻ layer 2, the breakdown voltage rapidly decreases.

This trend is explained, for example, in “High isolation voltage of SOI isolation structure” electronic device Semiconductor Power Conversion Joint Study Group EDD-92-106 (SPC-92-72) pp.1-6, 1992 , This is caused by electric field concentration due to the suppression of the depletion layer in the horizontal direction. On the other hand, by providing the p diffusion region 26, the characteristics as shown by the dotted line in FIG. That is, the region where the breakdown voltage can be maintained on the low specific resistance side is expanded. As a result, the n ⁻ layer 2 can be made to have a lower specific resistance than before to reduce the element resistance and maintain a high breakdown voltage.

FIG. 21 shows a change in breakdown voltage of the high breakdown voltage semiconductor device with respect to the buried oxide film thickness. In FIG. 21, the solid line indicates the characteristics of the conventional example. Although the breakdown voltage increases as the buried oxide film thickness increases, there is a tendency that the breakdown voltage rapidly decreases when the buried oxide film thickness reaches a certain value. This tendency is caused by the suppression of the depletion layer extending from the interface E in FIG. 19 into the n ⁻ layer 2. On the other hand, by forming the p diffusion region 26, the characteristic changes as shown by the dotted line in FIG. That is, even when the thickness of the buried oxide film 17 is greater than a certain value, it is possible to maintain a high breakdown voltage. Accordingly, it is possible to design an element with a margin for the thickness and specific resistance of the n ⁻ layer 2, and it is easy to manufacture the element in consideration of reduction in resistance of the element and increase in switching speed.

(Embodiment 8)
Next, an eighth embodiment of the present invention will be described with reference to FIGS. FIG. 22 is a partial cross sectional view showing a high voltage semiconductor device according to the eighth embodiment of the present invention. Referring to FIG. 22, the high voltage semiconductor device shown in FIG. 18 is different in that n diffusion region 23a is formed in the bottom region of n ⁻ layer 2 located immediately under n ⁺ diffusion region 15a. . Other structures are the same as those of the high voltage semiconductor device shown in FIG.

  As described above, the following effects can be obtained by forming the n diffusion region 23a. The effect will be described with reference to FIG. FIG. 23 is a diagram showing the state of the depletion layer during the off operation of the high voltage semiconductor device shown in FIG.

  Referring to FIG. 23, the off state is realized under the same conditions as in the seventh embodiment. As shown in FIG. 23, when a predetermined potential is applied to each electrode, the depletion layer starts to extend from the pn junction A and the interface E. Further, the presence of the p diffusion region 26 promotes the extension of the depletion layer in the horizontal direction. Thereby, the RESURF effect is effectively expressed.

At this time, various parameters such as dimensions are controlled so that the electrolytic concentration point 32 comes to the interface E located in the n diffusion region 23a. As a result, the characteristics shown by the alternate long and short dash line in FIG. 21 are obtained. This reflects the effect of increased avalanche breakdown electrolysis strength. For example, “High-voltage output device structure for trench isolation SOI power IC” by Yasuhara et al. 68, pp. 69-74, 1992 . By adopting such a structure, it is possible to further increase the breakdown voltage of the element as compared with the case of the seventh embodiment.

(Embodiment 9)
Next, Embodiment 9 of the present invention will be described with reference to FIGS. 24 and 25. FIG. FIG. 24 is a partial cross-sectional view showing a high voltage semiconductor device according to Embodiment 9 of the present invention.

Referring to FIG. 24, in the ninth embodiment, p diffusion region 26 is formed away from the interface between buried oxide film 17 and n ⁻ layer 2. Other structures are the same as those of the high voltage semiconductor device shown in FIG.

  Even when the p diffusion region 26 is formed as described above, the same effect as in the case of the seventh embodiment can be obtained. FIG. 25 shows the state of the depletion layer during the off operation of the high breakdown voltage semiconductor device according to the ninth embodiment shown in FIG. As shown in FIG. 25, the depletion layer can be sufficiently expanded in the horizontal direction, and the RESURF effect can be effectively expressed.

(Embodiment 10)
Next, Embodiment 10 of the present invention will be described with reference to FIG. FIG. 26 is a partial sectional view showing a high voltage semiconductor device according to the tenth embodiment of the present invention. More specifically, an embodiment in which the idea of the present invention is applied to a p-channel EST is shown.

Referring to FIG. 26, n ⁻ layer 2 is formed on the surface of semiconductor substrate 16 with a buried oxide film 17 interposed. A p ⁻ diffusion region 27 is formed on the surface of n ⁻ layer 2. On the surface of the p ⁻ diffusion region 27, n diffusion regions 28a and 28b and an n ⁺ diffusion region 39 are provided with a space therebetween. An n ⁺ diffusion region 40 and a p ⁺ diffusion region 29a are formed on the surface of the n diffusion region 28a.

Source electrode 11a is formed so as to be in contact with both n ⁺ diffusion region 40 and p ⁺ diffusion region 29a, and source electrode 11b is formed in contact with p ⁺ diffusion region 29b. Gate electrode 9 is formed on the surface of p ⁻ diffusion region 27 located between n diffusion region 28a and n diffusion region 28b with oxide film 10 interposed. Further, the drain electrode 12 is formed in contact with the surface of the n ⁺ diffusion region 39.

In such a configuration, p ⁺ diffusion region 33 is provided in p ⁻ diffusion region 27 located between n diffusion region 28 b and n + diffusion region 39. The p-type impurity concentration contained in the p ⁺ diffusion region 33 is preferably about 10 to 100 times or more the p-type impurity concentration contained in the p ⁻ diffusion region 27. Further, it is preferable that a plurality of p ⁺ diffusion regions 33 are provided at intervals.

Thereby, as in the case of the first to third embodiments, it is possible to effectively promote the spread of the depletion layer in the horizontal direction during the off operation. Further, since the p ⁺ diffusion region 33 has a relatively higher concentration than the p ⁻ diffusion region 27, it is possible to reduce the resistance of the current path during the on operation. Thereby, the element resistance can be reduced.

(Embodiment 11)
Next, Embodiment 11 of the present invention will be described with reference to FIG. FIG. 11 is a cross sectional view showing a high voltage semiconductor device according to an eleventh embodiment of the present invention. Referring to FIG. 27, a high voltage semiconductor device in the eleventh embodiment, structural differences between the high voltage semiconductor device according to the tenth embodiment shown in FIG. 26, n ⁺ diffusion region 41 is p ⁺ diffusion It is formed instead of the region 29b. Other structures are the same as those of the high breakdown voltage semiconductor device according to the tenth embodiment.

  That is, the eleventh embodiment shows a high breakdown voltage semiconductor device when the idea of the present invention is applied to a p-channel BRT. In this case, the same effect as in the case of the tenth embodiment can be obtained.

Next, a modified example of the p diffusion region 20 will be described with reference to FIGS. 28 to 32.
<First Modification>
First, a first modification will be described with reference to FIG. FIG. 28 is a partially enlarged cross-sectional view showing a first modification of p diffusion region 20. Referring to FIG. 28, p diffusion regions 20a and p ⁻ diffusion regions 5a are alternately arranged, and the respective diffusion depths are substantially equal. In the case of such a structure, substantially the same effect as that shown in FIG. 1 can be obtained.

<Second Modification>
Next, a second modification will be described with reference to FIG. FIG. 29 is a partially enlarged sectional view showing a second modification of p diffusion region 20.

Referring to FIG. 29, the diffusion depth of p diffusion region 20b is formed to be shallower than the diffusion depth of p ⁻ diffusion region 5b. Thereby, it is possible to further promote the spread of the depletion layer in the horizontal direction than in the case shown in FIG.

<Third Modification>
Next, a third modification of the p diffusion region 20 will be described with reference to FIG. FIG. 30 is a partially enlarged cross-sectional view showing a third modification of p diffusion region 20.

Referring to FIG. 30, instead of p diffusion region 20 shown in FIG. 1, polysilicon layer 34 into which p-type impurities are introduced at a high concentration may be formed on the surface of n ⁻ layer 2. . At this time, a plurality of p ⁻ layers 5 c are formed on the surface of the n ⁻ layer 2 at intervals, and adjacent p ⁻ diffusion regions 5 c are electrically connected by the polysilicon layer 34. Even with such a structure, substantially the same effect as that shown in FIG. 1 can be obtained. In the case of the present modification, the concentration of the polysilicon layer 34 can be made extremely high, and the device resistance during the on operation can be further reduced as compared with the case of the first embodiment shown in FIG. It becomes.

<Fourth modification>
Next, a fourth modification of the p diffusion region 20 will be described with reference to FIG. FIG. 31 is a partially enlarged sectional view showing a fourth modification of p diffusion region 20.

Referring to FIG. 31, in the present modification, a plurality of p diffusion regions 20c are provided at intervals on the surface of p ⁻ diffusion region 5d. Even in the case of such a structure, the same effect as in the case of the first embodiment shown in FIG. 1 can be obtained.

<Fifth Modification>
Next, a fifth modification of the p diffusion region 20 will be described with reference to FIG. FIG. 32 is a partial enlarged cross-sectional view showing a fifth modification of p diffusion region 20.

Referring to FIG. 32, in the present modification, polysilicon layer 34a is formed on the surface of n ⁻ layer 2 with insulating layer 35 interposed. A p ⁺ diffusion region 36 is formed so as to surround the contact portion between polysilicon layer 34a and p ⁻ diffusion region 5e. Other structures are the same as those in the third modified example. In the case of this modification, substantially the same effect as in the case of the third modification can be obtained.

Next, a method for manufacturing polysilicon layer 34a and p ⁻ diffusion region 5e in FIG. 32 will be described with reference to FIGS.

First, the first manufacturing method will be described with reference to FIGS. Referring to FIG. 33, an insulating layer 35 made of a silicon oxide film or the like is deposited on the surface of n ⁻ layer 2 by CVD or the like. Then, after patterning the insulating layer 35 into a predetermined shape, a poly-type impurity introduced at a high concentration of p-type impurities by using a CVD method or the like so as to cover the insulating layer 35 and the surface of the n ⁻ layer 2. A silicon layer 34a is formed.

Next, referring to FIG. 34, p-type impurities are diffused from the polysilicon layer 34a to the surface of the n ⁻ layer 2 by performing heat treatment or the like on the polysilicon layer 34a. Thereby, p ⁻ diffusion regions 5e are formed at intervals.

Next, as shown in FIG. 35, the polysilicon layer 34a is patterned into a predetermined shape. Through the above steps, polysilicon layer 34a and p ⁻ diffusion region 5e shown in FIG. 32 are formed.

Next, a second manufacturing method of the polysilicon layer 34a and the p ⁻ diffusion region 5e will be described with reference to FIGS. First, referring to FIG. 36, after forming the insulating layer 35 through the same process as in the first method, boron ions (on the surface of the n ⁻ layer 2 are formed using this insulating layer 35 as a mask. A p-type impurity such as B @ +) is selectively implanted. Then, by performing a diffusion process on the implanted p-type impurities, p ⁻ diffusion regions 5e are formed at intervals as shown in FIG.

Next, as shown in FIG. 38, a polysilicon layer 34a is formed through the same steps as in the first method. Then, heat treatment is performed on polysilicon layer 34a to form p ⁺ diffusion regions 36 on the surface of p ⁻ diffusion region 5e, as shown in FIG. Through the above steps, polysilicon layer 34a and p ⁻ diffusion region 5e shown in FIG. 32 are formed. Thereafter, gate electrode 9, p ⁺ diffusion regions 3 and 6, oxide film 10, source / drain electrodes 11 and 12 are formed.

  Note that the first to fifth modifications described above are applicable not only to the first embodiment but also to all other p-channel devices. In addition, it should be considered that the embodiment disclosed this time is illustrative and not restrictive in all respects. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a partial cross-sectional view showing a high voltage semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view showing a state of a depletion layer during an off operation of the high voltage semiconductor device shown in FIG. 1. (A) is a figure which shows the resistance component at the time of ON operation of the high voltage | pressure-resistant semiconductor device shown by FIG. (B) is a figure which shows the resistance component at the time of ON operation | movement of the high voltage | pressure-resistant semiconductor device in a prior art example. It is a figure which shows the relationship between the surface concentration of a p <-> diffusion area | region, and a proof pressure. (A)-(c) is a figure which shows the state of the depletion layer at the time of OFF operation | movement at the time of making p diffusion area | region 24 high concentration uniformly. (A)-(c) is a figure which shows the state of the depletion layer at the time of OFF operation | movement of the high voltage | pressure-resistant semiconductor device shown by FIG. 1 in steps. It is a fragmentary sectional view which shows the high voltage semiconductor device in Embodiment 2 of this invention. It is a figure which shows the state of the depletion layer at the time of OFF operation | movement of the high voltage | pressure-resistant semiconductor device shown by FIG. It is a fragmentary sectional view which shows the high voltage semiconductor device in Embodiment 3 of this invention. FIG. 10 is a diagram showing a state of a depletion layer during an off operation of the high breakdown voltage semiconductor device shown in FIG. 9. It is a perspective view which shows the high voltage semiconductor device in Embodiment 4 of this invention. It is a fragmentary sectional view which follows the XII-XII line | wire in FIG. FIG. 12 is a diagram illustrating a state of a depletion layer during an off operation of the high breakdown voltage semiconductor device illustrated in FIG. 11. It is a fragmentary sectional view which shows the high voltage semiconductor device in Embodiment 5 of this invention. FIG. 15 is a diagram showing a state of a depletion layer during an off operation of the high breakdown voltage semiconductor device shown in FIG. 14. It is a fragmentary sectional view which shows the high voltage semiconductor device in Embodiment 6 of this invention. FIG. 17 is a diagram showing a state of a depletion layer during an off operation of the high breakdown voltage semiconductor device shown in FIG. 16. It is a fragmentary sectional view which shows the high voltage semiconductor device in Embodiment 7 of this invention. It is a figure which shows the state of the depletion layer at the time of OFF operation | movement of the high voltage semiconductor device shown by FIG. It is a figure which shows the relationship between the specific resistance of an n < ^- > layer, and the proof pressure of a high voltage | pressure-resistant semiconductor device. It is a figure which shows the relationship between a buried oxide film thickness and the proof pressure of a high voltage | pressure-resistant semiconductor device. It is a fragmentary sectional view which shows the high voltage semiconductor device in Embodiment 8 of this invention. FIG. 23 is a diagram showing a state of a depletion layer during an off operation of the high breakdown voltage semiconductor device shown in FIG. 22. It is a fragmentary sectional view which shows the high voltage semiconductor device in Embodiment 9 of this invention. FIG. 25 is a diagram showing a state of a depletion layer during an off operation of the high breakdown voltage semiconductor device shown in FIG. 24. It is a fragmentary sectional view which shows the high voltage semiconductor device in Embodiment 10 of this invention. It is a fragmentary sectional view which shows the high voltage semiconductor device in Embodiment 11 of this invention. FIG. 6 is a cross-sectional view showing a first modification of the structure of p diffusion region 20 according to the present invention. It is sectional drawing which shows the 2nd modification of the structure of the p diffusion area | region 20 which concerns on this invention. It is sectional drawing which shows the 3rd modification of the structure of the p diffusion area | region 20 which concerns on this invention. It is sectional drawing which shows the 4th modification of the structure of the p diffusion area | region 20 which concerns on this invention. It is sectional drawing which shows the 5th modification of the structure of the p diffusion area | region 20 which concerns on this invention. FIG. 33 is a cross-sectional view showing a first step of a first method of forming polysilicon layer 34a and p ⁻ diffusion region 5e shown in FIG. 32. FIG. 33 is a cross-sectional view showing a second step of the first method for forming polysilicon layer 34a and p ⁻ diffusion region 5e shown in FIG. 32. FIG. 33 is a cross-sectional view showing a third step of the first method for forming polysilicon layer 34a and p ⁻ diffusion region 5e shown in FIG. 32. FIG. 33 is a cross-sectional view showing a first step of a second method of forming polysilicon layer 34a and p ⁻ diffusion region 5e shown in FIG. 32. FIG. 33 is a cross-sectional view showing a second step of the second method of forming polysilicon layer 34a and p ⁻ diffusion region 5e shown in FIG. 32. FIG. 33 is a cross-sectional view showing a third step of the second method of forming polysilicon layer 34a and p ⁻ diffusion region 5e shown in FIG. 32. FIG. 33 is a cross-sectional view showing a fourth step of the second method of forming polysilicon layer 34a and p ⁻ diffusion region 5e shown in FIG. 32. It is a fragmentary sectional view showing the 1st example of the conventional high voltage semiconductor device. FIG. 41 is a diagram showing a state of a depletion layer during an off operation of the conventional high voltage semiconductor device shown in FIG. 40. FIG. 41 is a diagram showing a state of a depletion layer during an off operation of the high voltage semiconductor device shown in FIG. 40. FIG. 41 is a diagram showing an on operation of the high breakdown voltage semiconductor device shown in FIG. 40. It is a fragmentary sectional view showing the 2nd example of the conventional high voltage semiconductor device. FIG. 45 is a diagram showing a state of a depletion layer during an off operation of the conventional high voltage semiconductor device shown in FIG. 44. FIG. 45 is a diagram showing a state of a depletion layer during an off operation of the high voltage semiconductor device shown in FIG. 44. FIG. 45 is a diagram showing an on operation of the high breakdown voltage semiconductor device shown in FIG. 44. FIG. 45 is a bird's eye view showing the overall configuration of the high voltage semiconductor device shown in FIG. 44. It is a fragmentary sectional view showing the 3rd example of the conventional high voltage semiconductor device. It is a figure which shows the state of the depletion layer at the time of OFF operation | movement of the conventional high voltage | pressure-resistant semiconductor device shown by FIG. FIG. 50 is a diagram showing a state of a depletion layer during an off operation of the high breakdown voltage semiconductor device shown in FIG. 49. FIG. 50 is a diagram showing an on operation of the high breakdown voltage semiconductor device shown in FIG. 49. It is a fragmentary sectional view showing the 4th example of the conventional high voltage semiconductor device. FIG. 54 is a diagram showing a state of a depletion layer during an off operation of the conventional high voltage semiconductor device shown in FIG. 53. FIG. 54 is a diagram showing an off operation of the high breakdown voltage semiconductor device shown in FIG. 53.

Explanation of symbols

1 p-type semiconductor substrate, 2 n− layer, 7, 20, 24, 26, 33 p diffusion region, 23a n diffusion region, 5, 27 p ⁻ diffusion region, 8 n ⁺ buried diffusion region, 9 gate electrode, 10 Oxide film, 11 source electrode, 12 drain electrode, 13 substrate electrode, 16 semiconductor substrate, 17 buried oxide film, 21 depletion layer edge, 30 undepleted region, 31 gap, 32 electrolytic concentration point, 34, 34a polysilicon layer 35 Insulating layer.

Claims (3)

A semiconductor substrate having a main surface;
A first conductivity type semiconductor layer formed on the main surface of the semiconductor substrate via a buried oxide film ;
A first impurity diffusion region of a second conductivity type formed on the surface of the semiconductor layer;
A second impurity diffusion region of the first conductivity type formed on the surface of the first impurity diffusion region;
A third impurity diffusion region of a first conductivity type formed on the surface of the semiconductor layer at a distance from the first impurity diffusion region;
A gate electrode formed on the surface of the first impurity diffusion region located between the second and third impurity diffusion regions with an insulating layer interposed therebetween;
A source electrode formed in contact with both the surface of the second impurity diffusion region and the surface of the first impurity diffusion region adjacent to the second impurity diffusion region;
A drain electrode formed in contact with the surface of the third impurity diffusion region;
With
In the bottom region of the semiconductor layer located between the first and third impurity diffusion regions , a plurality of second conductivity type second layers are formed in the direction from the first impurity diffusion region to the third impurity diffusion region . A high breakdown voltage semiconductor device in which four impurity diffusion regions are formed.   2. The high withstand voltage semiconductor device according to claim 1, wherein the fourth impurity diffusion region is disposed at a distance from each other toward a bottom region of the semiconductor layer located immediately below the third impurity diffusion region.   A fifth impurity diffusion region of the first conductivity type is formed at a distance from the fourth impurity diffusion region in the bottom region of the semiconductor layer located immediately below the third impurity diffusion region. The high voltage semiconductor device according to claim 1 or 2.

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