JP4767160B2 - チップ部品の搭載方法 - Google Patents
チップ部品の搭載方法 Download PDFInfo
- Publication number
- JP4767160B2 JP4767160B2 JP2006346989A JP2006346989A JP4767160B2 JP 4767160 B2 JP4767160 B2 JP 4767160B2 JP 2006346989 A JP2006346989 A JP 2006346989A JP 2006346989 A JP2006346989 A JP 2006346989A JP 4767160 B2 JP4767160 B2 JP 4767160B2
- Authority
- JP
- Japan
- Prior art keywords
- chip component
- solder
- conductor film
- component mounting
- chip part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Description
2・・・支持基体
3・・・チップ部品搭載用導体膜
3a・・・固定領域
3b・・・ガイド領域
4・・・半田
Claims (1)
- 下面に導体膜が形成された四角形状のチップ部品を準備するとともに、前記チップ部品を搭載し固定する四角形状の固定領域および該固定領域の一辺の両端からそれぞれ引き出されたガイド領域を有するチップ部品搭載用導体膜が上面に形成された支持基体を準備する第1工程と、
前記チップ部品搭載用導体膜の上面に半田を配置する第2工程と、
前記チップ部品を、下面の一辺側の両端を前記チップ部品搭載用導体膜の前記ガイド領域に前記半田を介して載せるように前記支持基体上に配置する第3工程と、
前記半田を加熱して溶融させて溶融した前記半田によって前記チップ部品を前記チップ部品搭載用導体膜の前記ガイド領域から前記固定領域上に移動させ、しかる後に、前記半田を冷却して固化させて前記チップ部品搭載用導体膜上に前記チップ部品を接合する第4工程とを含むチップ部品の搭載方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006346989A JP4767160B2 (ja) | 2006-12-25 | 2006-12-25 | チップ部品の搭載方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006346989A JP4767160B2 (ja) | 2006-12-25 | 2006-12-25 | チップ部品の搭載方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008159830A JP2008159830A (ja) | 2008-07-10 |
JP4767160B2 true JP4767160B2 (ja) | 2011-09-07 |
Family
ID=39660414
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006346989A Expired - Fee Related JP4767160B2 (ja) | 2006-12-25 | 2006-12-25 | チップ部品の搭載方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4767160B2 (ja) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3110170B2 (ja) * | 1992-09-02 | 2000-11-20 | 第一高周波工業株式会社 | 板状体のろう接方法 |
JP2002223062A (ja) * | 2001-01-26 | 2002-08-09 | Toyo Commun Equip Co Ltd | プリント配線基板のパッド形状 |
JP2003151998A (ja) * | 2001-11-16 | 2003-05-23 | Denso Corp | 半導体装置の製造方法 |
JP4747281B2 (ja) * | 2006-03-29 | 2011-08-17 | 三菱マテリアル株式会社 | Au−Sn合金はんだペーストを用いた基板と素子の接合方法 |
-
2006
- 2006-12-25 JP JP2006346989A patent/JP4767160B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008159830A (ja) | 2008-07-10 |
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