JP4760058B2 - Memory element and memory - Google Patents

Description

  The present invention relates to a storage element and a memory, and is suitable for use in a nonvolatile memory.

In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.
However, since DRAM is a volatile memory in which information disappears when the power is turned off, a nonvolatile memory in which information does not disappear is desired.

  As a nonvolatile memory that is expected to be promising in the future, a resistance change type memory such as a phase change memory or an RRAM (see, for example, Non-Patent Document 1) has been proposed.

  Among these, the phase change memory uses a crystal-amorphous phase change for recording and holding information, and recording is performed by applying voltage pulses of the same polarity and different magnitudes.

In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

I.G.Baek et al., International Electron Devices Meeting (IEDM) Technical Digest 2004, 2004, p. 587-590

  However, the phase change memory has a complicated structure because a heating mechanism is required to record information using heat.

  In order to solve the above-described problem, the present invention provides a memory element that can form a nonvolatile memory with a relatively simple structure and a memory including the memory element.

The memory element of the present invention includes an oxide layer mainly composed of an oxide of at least one element selected from Zr and Hf, and a conductive nitride composed of ZrN or HfN in the lower and upper layers of the oxide layer, respectively. The layers are laminated.
The memory of the present invention includes the memory element of the present invention, and includes a voltage applying unit for applying a voltage to the memory element in the stacking direction of the stacked film of the memory element. Information is recorded in the memory element by applying a voltage to the element to change the resistance value of the memory element.

According to the above configuration of the memory element of the present invention, ZrN or HfN is formed on the oxide layer mainly composed of an oxide of at least one element selected from Zr and Hf, and the lower layer and the upper layer of the oxide layer, respectively. When the conductive nitride layer made of is laminated, the resistance value of the memory element changes irreversibly by applying a voltage in the stacking direction of the stacked film of the memory element. By utilizing this change in resistance value, it is possible to record information in the storage element and hold the recorded information.
In addition, since the memory element has a configuration including an oxide layer and a conductive nitride layer as an upper layer and a lower layer, the configuration is relatively simple and the memory element can be easily miniaturized.

  According to the configuration of the memory of the present invention described above, the memory element of the present invention is provided, and voltage applying means for applying a voltage to the memory element in the stacking direction of the stacked film of the memory element is provided. Since the structure is such that information is recorded in the memory element by applying a voltage to the memory element by applying means and changing the resistance value of the memory element, the memory element has a relatively simple structure and can be easily miniaturized. And a voltage applying means. A nonvolatile memory is configured. Thereby, the configuration of the nonvolatile memory can be simplified.

According to the above-described present invention, it is possible to make the memory element relatively simple with a relatively simple structure, so that memory cells composed of the memory element are densely integrated to constitute a nonvolatile memory. It becomes possible.
Therefore, according to the present invention, the non-volatile memory can be reduced in size and the storage capacity can be increased.

  First, an outline of the present invention will be described prior to description of specific embodiments of the present invention.

In the memory element of the present invention, a conductive nitride layer made of ZrN or HfN is formed on the lower and upper layers of an oxide layer mainly composed of an oxide of at least one element selected from Zr and Hf, respectively. It is configured by stacking.
By configuring the memory element in this manner, the resistance value of the memory element is changed by applying a voltage to the memory element, and the changed state (resistance value) can be held.
By utilizing this fact, binary information can be recorded and held in the storage element in a recording state where the resistance value of the storage element is low and a recording state where the resistance value of the storage element is high.

The memory of the present invention includes the memory element of the present invention, and includes a voltage applying unit for applying a voltage to the memory element in the stacking direction of the stacked film of the memory element. Information is recorded in the memory element by applying a voltage to the element to change the resistance value of the memory element.
Examples of the voltage application means include an electrode connected to the memory element, a wiring connected to the electrode, and a power supply unit (power supply circuit or the like) that generates a voltage to be applied.
And each memory cell is comprised by the memory element of the said invention, and a large memory capacity non-volatile memory can be comprised by providing many memory cells and comprising a memory.

In the memory element of the present invention, more preferably, the oxide layer is constituted by a plurality of oxide layers, and the conductivity of each oxide layer is different.
With such a configuration, the stacked film of the memory element has a vertically asymmetric configuration, so that the resistance value varies greatly depending on the recording state. Thereby, it becomes easy to read the information recorded in the storage element.
To vary the conductivity of a plurality of oxide layers, for example, B in at least part of the oxide layer of the plurality of oxide layers, Mn, Fe, Co, Ni , Ru, Re, Mg, Ca, At least one element selected from Y may be added, and the presence or absence of the additional element or the type or amount of the added element may be different.

  Furthermore, in the memory element of the present invention, when at least one element selected from Mg, Ca, and Y is added to the oxide layer, the crystal structure of the oxide is stabilized and oxygen easily moves. Thereby, the operating voltage can be lowered.

The conductive nitride layer may be formed by sputtering or the like using a nitride target, or may be formed in nitrogen using a metal target, or a nitrogen plasma after forming a metal film. The metal film may be nitrided.
Similarly, the oxide layer may be formed by sputtering using an oxide target, may be formed in oxygen using a metal target, or may be formed by oxygen plasma after forming a metal film. The metal film may be oxidized.

Subsequently, specific embodiments of the present invention will be described.
FIG. 1 shows a schematic configuration diagram (cross-sectional view) of an embodiment of a memory element of the present invention.
The memory element 10 is formed by laminating an electrode film 11 serving as a lower electrode, a first nitride layer 12, an oxide layer 13, a second nitride layer 14, and an electrode film 15 serving as an upper electrode.

  Conventionally known electrode materials can be used as the material of the electrode film 11 serving as the lower electrode and the electrode film 15 serving as the upper electrode. For example, Ta can be used.

As a material of the first nitride layer 12 and the second nitride layer 14, a conductive nitride composed of at least one element selected from Ti, Zr, Hf, and Ta and nitrogen described above is used.
As a result, a current can flow through the first nitride layer 12 and the second nitride layer 14.
The oxide layer 13 is composed mainly of an oxide of one or more elements selected from Zr and Hf described above.

By forming a laminated film in which the first nitride layer 12, the oxide layer 13, and the second nitride layer 14 are laminated, the resistance value of the memory element 10 changes in accordance with the voltage applied to the laminated film. In addition, the resistance value after the change can be held.
Accordingly, binary information can be recorded and held in the storage element 10 in a recording state in which the resistance value of the storage element 10 is low and a recording state in which the resistance value of the storage element 10 is high.

  In addition, at least one element selected from Mg, Ca, and Y may be added to the oxide layer 13. By adding these elements, the crystal structure of the oxide is stabilized, and oxygen is added. Since it becomes easy to move, the operating voltage of the memory element 10 can be lowered.

  The storage element 10 of this embodiment can be operated as follows to store information.

A voltage (positive voltage or negative voltage) is applied from the outside to the electrode film 11 serving as the lower electrode and the electrode film 15 serving as the upper electrode. Thereby, the resistance value between the two electrode films 11 and 15 changes. For example, the resistance value changes from a high state to a low state, or the resistance value changes from a low state to a high state.
Thereafter, when the applied voltage is removed, the resistance value is maintained in a changed state.
This makes it possible to record information.

Further, by applying a reverse polarity voltage to the memory element, the resistance value can be changed back to the original state.
Also at this time, when the applied voltage is removed, the resistance value is maintained in the original state.

By repeating such a process, information can be repeatedly recorded in the memory element 10.
For example, if a high resistance value is associated with “0” information and a low resistance value is associated with “1” information, “0” and “1” information may be repeatedly recorded. it can.

In addition, a memory can be formed using the memory element 10 of this embodiment.
That is, a memory (storage device) can be configured by configuring a memory cell by the storage element 10 and arranging the memory cell in, for example, a column or matrix.
For each memory element 10, a wiring connected to the electrode film 11 side of the lower electrode and a wiring connected to the electrode film 15 side of the upper electrode are provided, and each memory is stored near the intersection of these wirings, for example. The element 10 may be disposed.
By selecting a wiring through which a current is applied by applying a voltage, a memory cell to be recorded can be selected, and a current can be passed through the memory element 10 of the memory cell to record information.

  According to the configuration of the memory element 10 of the present embodiment described above, the oxide layer 13 composed mainly of an oxide of one or more elements selected from Zr and Hf, the lower layer of the oxide layer 13, and First nitride layer 12 and second nitride layer using conductive nitride (consisting of at least one element selected from Ti, Zr, Hf, and Ta and nitrogen) provided in each upper layer 14, the resistance value of the memory element 10 is changed by applying a voltage in the stacking direction of the stacked film of the memory element 10. By utilizing this change in resistance value, it is possible to record information in the storage element and hold the recorded information.

Further, according to the configuration of the memory element 10 of the present embodiment, the memory element 10 is configured with a relatively simple stacked structure of the first nitride layer 12, the oxide layer 13, and the second nitride layer 14. be able to. Furthermore, since information is recorded by applying a voltage, a heating mechanism such as a phase change memory is not required.
Thereby, since the structure of the memory element 10 can be simplified, even if the memory element 10 is miniaturized, it is easy to record information and hold recorded information.
Therefore, by configuring the memory using the memory element 10 of the present embodiment described above, it is possible to reduce the size of the memory or increase the storage capacity with the same size.

  In the above-described embodiment, the oxide layer 13 is a single layer. However, in the present invention, the oxide layer may be formed of a plurality of oxide layers having different conductivity. The case is shown below.

FIG. 2 shows a schematic configuration diagram (cross-sectional view) of a memory element according to another embodiment of the present invention.
In the memory element 20, the oxide layer 13 is composed of a stack of a first oxide layer 13A and a second oxide layer 13B.
The first oxide layer 13A and the second oxide layer 13B have different conductivity.
Specifically, for example, at least one element selected from B, Mn, Fe, Co, Ni, Ru, and Re is added to each oxide layer 13A, 13B, and the first oxide layer 13A and the first oxide layer 13A The second oxide layer 13B is different in the presence or absence of the additive element or the type or amount of the element to be added.
This makes it easy to read information recorded in the storage element 20.

  Other configurations are the same as those of the memory element 10 of the previous embodiment shown in FIG.

In addition, a memory can be formed using the memory element 20 of this embodiment.
That is, a memory (storage device) can be configured by configuring a memory cell by the storage element 20 and arranging the memory cell in, for example, a column or matrix.
For each memory element 20, a wiring connected to the electrode film 11 side of the lower electrode and a wiring connected to the electrode film 15 side of the upper electrode are provided. For example, each memory is located near the intersection of these wirings. The element 20 may be disposed.
Then, by selecting a wiring through which a current is applied by applying a voltage, a memory cell to be recorded can be selected, and a current can be passed through the storage element 20 of the memory cell to record information.

According to the configuration of the memory element 20 of the present embodiment, similarly to the memory element 10 of the previous embodiment shown in FIG. 1, the memory element 20 can be stored by applying a voltage in the stacking direction of the stacked film of the memory element 20. The resistance value of the element 20 changes. By utilizing this change in resistance value, it is possible to record information in the storage element and hold the recorded information.
In addition, the storage element 20 can be configured with a relatively simple stacked structure of the first nitride layer 12, the oxide layer 13, and the second nitride layer 14, and information is recorded by applying a voltage. Since a heating mechanism such as a phase change memory is not required, the configuration of the memory element 20 can be simplified. Thereby, even if the memory element 20 is miniaturized, it becomes easy to record information and hold the recorded information.
Therefore, by configuring the memory using the memory element 20 of this embodiment described above, it is possible to reduce the size of the memory and increase the storage capacity with the same size.

  Further, according to the configuration of the memory element 20 of the present embodiment, the oxide layer 13 is formed of a stack of the first oxide layer 13A and the second oxide layer 13B having different conductivity, so that the memory element 20 Since the stacked structure is asymmetrical in the vertical direction, it becomes easy to read information recorded in the storage element 20.

  In each of the above-described embodiments, the oxide layer 13 has a single layer or a two-layer structure, but the oxide layer may have a laminated structure of three or more layers and the upper and lower conductivity may be asymmetric.

(Example)
Subsequently, the memory element of the present invention was actually fabricated and the characteristics were examined.

First, the memory element 10 having the configuration shown in FIG. 1 was actually manufactured using the following materials and film thicknesses for each layer.
That is, a Ta film having a film thickness of 10 nm is formed as the electrode film 11 serving as an underlayer / lower electrode, and a ZrN film having a film thickness of 20 nm is formed thereon as the first nitride layer 12, and the film thickness is formed thereon. After forming a metal Zr film having a thickness of 5 nm, an oxidation process was performed in oxygen plasma to form an oxide layer 13. Further, a ZrN film having a thickness of 20 nm was formed as the second nitride layer 14, and a Ta film having a thickness of 10 nm was formed thereon as the electrode film 15 serving as the upper electrode.
The ZrN film was formed by reactive sputtering in nitrogen gas using a metal Zr target.
In this way, the memory element 10 shown in FIG. 1 was manufactured and used as a sample of the memory element.
Then, a sample of the storage element (Example 1) in which the oxidation treatment time in the oxygen plasma of Zr was 60 seconds and a sample of the storage element (Comparative Example) in which the oxidation treatment time was 120 seconds were produced.

For each of the manufactured samples, the current flowing through the memory element was measured while changing the voltage to be applied, and the current-voltage (IV) characteristics of the memory element were examined.
FIG. 3A shows the IV characteristics of the sample (Example 1) in which the plasma oxidation treatment time of Zr is 60 seconds, and FIG. 3B shows the IV characteristics of the sample (Comparative Example) in which the plasma oxidation time is 120 seconds. Show.

In FIG. 3A, hysteresis is seen in the IV characteristic, and it can be confirmed that the device functions as a memory.
Specifically, the resistance value changes between applied voltages 2 V and 3 V, the resistance value changes from a low resistance value to a high resistance value on the + applied voltage side, and the resistance value on the − applied voltage side. The resistance value changes from a high state to a low resistance state.

On the other hand, in FIG. 3B, the non-linearity of the IV characteristic is seen, and the resistance value changes with the applied voltage, but the change is reversible and no hysteresis appears. That is, it turns out that it does not function as a memory.
Therefore, it can be seen that, in order to make it possible to hold information in the memory element, it is necessary to prevent excessive oxidation when the oxide layer is formed. Note that when an oxide layer is directly formed by a direct sputtering method or the like, it is assumed that the oxide layer functions as a memory.

Next, the characteristics of the oxide layer and electrode layer were varied and the characteristics were examined.
First, in the configuration of the memory element 10 illustrated in FIG. 1, a sample of the memory element was manufactured using the oxide layer 13 as a material obtained by adding various elements to a Zr oxide.
Specifically, the oxide layer 13 is formed by adding Y alone, Y and B, Y and Ru, Y and Re, Y and Mn, Y and Fe, Y and Co, and Y and Ni to the Zr oxide, respectively. Thus, samples of the memory element (sample numbers 1 to 9) were produced. Note that the oxide layer was formed by forming a metal layer (alloy layer of Zr and an additive element) having a thickness of 5 nm and then oxidizing in oxygen plasma for 60 seconds.

And the voltage of 0.1V was applied to the memory element, and the sheet resistance value of the memory element of each sample was measured.
Table 1 shows the composition of the oxide layer of each sample and the sheet resistance value of the memory element as measurement results. In the composition of the oxide layer in Table 1, the subscript indicates atomic% of elements other than oxygen.

From Table 1, the sheet resistance value varies depending on the type and amount of the additive element, and takes a value of 1.2 to 25 × 10 ⁴ Ω / μm ² .
It can also be seen that the resistance value is lower when other elements are added than when Y alone is added.
Furthermore, when comparing Zr ₉₅ Y ₃ B ₂ + O (sample number 2) and Zr ₉₃ Y ₃ B ₄ + O (sample number 3), the latter with a larger amount of boron B added has a lower resistance value. You can see that

Next, in the configuration of the storage element 10 shown in FIG. 1 and the configuration of the storage element 20 shown in FIG. 2, the materials of the nitride layers 12 and 14 and the materials of the oxide layers 13, 13A, and 13B are changed. Thus, samples of the memory elements (sample numbers 10 to 17) were produced. The sample number 10 is the configuration of the memory element 10 shown in FIG. 1, the sample numbers 11 to 16 are the configuration of the memory element 20 shown in FIG. 2, and the sample number 17 is not shown, but the oxide layer has a three-layer structure. This is the configuration.
In each sample, the thickness of the nitride layers 12 and 14 was 20 nm. The oxide layers 13, 13A and 13B were subjected to plasma oxidation treatment for 60 seconds after the metal layer was formed.

For each sample of the memory element, the IV characteristics were measured by changing the voltage applied to the memory element.
Then, from the curve obtained the I-V characteristic was measured, the minimum voltage (recording voltage) V _C of the recording of information can be, the resistance value of the high-resistance recording state (R _H) and the low-resistance recording state The ratio (R _H / R _L ) to the resistance value (R _L ) was determined.
Table 2 shows the layer structure of the memory element of each sample and the ratio R _H / R _{L of} the recording voltage V _c and the resistance value. In Table 2, the thickness of the oxide layer indicates the thickness of the metal layer before oxidation.

From Table 2, with the structure of the oxide layer the resistivity of two different layers, an oxide layer as compared with the case of a single layer (Sample No. 10), it is possible to lower the recording voltage V _c It can be seen that the resistance ratio R _H / _{RL, that} is, the rate of change in resistance also increases.

Further, Sample No. 17 as a three-layer structure of the oxide layer 13, and the upper and lower layers constituting the asymmetric, the recording voltage V _c is relatively small and the resistance change rate is larger than the other samples.

Sample No. 16 in which the lower first oxide layer 13A is made of a material containing Hf oxide as a main component and Fe added thereto is the recording voltage as in the other samples mainly containing Zr oxide. V _c is relatively small and the resistance change rate is large.

The sample number 12 and the sample number 13 are the same except for the thickness of the lower first oxide layer 13A.
Recording voltage V _c is towards the first oxide layer 13A is thin sample No. 13 is small, which is good.
On the other hand, the rate of change in resistance is greater for Sample No. 12 where the first oxide layer 13A is thicker and better.

  The present invention is not limited to the above-described embodiments and examples, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (cross-sectional view) of an embodiment of a memory element of the present invention. It is a schematic block diagram (sectional drawing) of other embodiment of the memory element of this invention. It is a figure which shows the difference in the current-voltage characteristic by the manufacturing conditions of the laminated film in the memory element of FIG. A is a current-voltage characteristic of a sample in which the oxidation treatment time of the oxide layer is 60 seconds. B is a current-voltage characteristic of a sample in which the oxidation time of the oxide layer is 120 seconds.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,20 Memory element, 11, 15 Electrode film | membrane, 12 1st nitride layer, 13 Oxide layer, 13A 1st oxide layer, 13B 2nd oxide layer, 14 2nd nitride layer

Claims (4)

An oxide layer mainly composed of an oxide of at least one element selected from Zr and Hf;
A storage element in which a conductive nitride layer made of ZrN or HfN is laminated on a lower layer and an upper layer of the oxide layer, respectively. The oxide layer is composed of a stack of a plurality of oxide layers having different conductivity , and at least one of the plurality of oxide layers includes B, Mn, Fe, Co, Ni, Ru, Re, Mg, Ca, 2. The memory element according to claim 1, wherein at least one element selected from Y is added, and the conductivity of the plurality of oxide layers varies depending on the type or amount of the added element. The oxide layer is a single oxide layer made of ZrYO or an oxide in which at least one element selected from B, Mn, Fe, Co, Ni, Ru, and Re is added to ZrYO. Item 2. The memory element according to Item 1. It has a memory element given in any 1 paragraph of Claims 1-3 ,
A voltage applying means for applying a voltage to the storage element in the stacking direction of the stacked film of the storage element;
A memory in which information is recorded in the memory element by applying a voltage to the memory element by the voltage applying means and changing a resistance value of the memory element.

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