JP4759368B2 - Semiconductor integrated circuit design method - Google Patents

Description

The present invention relates to a method for designing a semiconductor integrated circuit.

In a conventional method for designing a semiconductor integrated circuit such as an LSI, a delay variation due to a voltage drop amount is included in a library, and a method of keeping the maximum voltage drop amount within a guaranteed value of the library by optimizing power supply wiring is general.
It has been pointed out that such a semiconductor integrated circuit design method is designed with a margin because the entire chip has a voltage drop defined by the maximum voltage drop amount.
For this reason, logic cell sizing and buffer insertion during timing optimization become excessive, and there are problems such as an increase in the number of gates during layout and an increase in chip size.
Patent Document 1 discloses a technique that does not use logic cell sizing or buffer insertion when timing is improved.
Japanese Patent Application Laid-Open No. 2003-228867 has an invention that improves timing by changing a power supply voltage, but has a disadvantage that a power supply wiring having a different power supply voltage has to be performed in advance, and the problem of an increase in chip size cannot be avoided. .
Therefore, in order to avoid the above-mentioned problems, a plurality of libraries having different maximum voltage drop amounts have been prepared in recent years, and a design method that reflects the voltage drop amount of each logic cell has been proposed. For example, an accurate delay calculation can be performed from a library suitable for the voltage drop amount of each logic cell, and an excessive margin design can be avoided.
Further, the above design method has a feature that if the amount of voltage drop can be reduced, the delay of the logic cell becomes faster and the timing convergence is improved.
As a method of improving the timing convergence by improving the voltage drop amount, there is Patent Document 2.
JP 2003-345845 A JP 2000-99554 A

However, although Patent Document 2 logically reduces power consumption and suppresses the voltage drop amount of the entire circuit to improve timing convergence, it can logically reduce power consumption. Otherwise, there is a drawback that the voltage drop cannot be suppressed and the timing cannot be converged.
Therefore, the present invention has been made in view of the above points, and provides a semiconductor integrated circuit design method capable of improving timing convergence even in a circuit that cannot logically reduce power consumption. For the purpose.

In order to achieve the above object, a first aspect of the present invention is a semiconductor integrated circuit design method executed by a design apparatus for designing a layout of a semiconductor integrated circuit, the entire semiconductor chip or each logic cell. A voltage drop amount analyzing step for analyzing the voltage drop amount of the battery, and performing a static timing analysis in consideration of the voltage drop amount, and analyzing the timing convergence of the critical path of the logic cell based on the obtained timing information A static timing analysis step; a first determination step for determining whether timing improvement is possible by reducing the voltage drop amount when the result of the static timing analysis step is a timing violation; and the voltage When the timing can be improved by reducing the amount of descent, it is determined whether the timing can be improved by changing the arrangement position. When it is determined that the timing can be improved by changing the arrangement position in the second determination step to be performed and the determination step, the logic cell included in the critical path is relocated to a position where the voltage drop amount is small. And an arrangement changing step.
The invention according to claim 2 has a step of strengthening a power line of a logic cell included in the critical path when it is determined in the second determination step that the timing cannot be improved by changing the arrangement position. It is characterized by.
According to a third aspect of the present invention, in the first determination step, an allowable arrival time is an arrival time in consideration of a voltage drop amount to each logic cell of the critical path extracted in the static timing analysis step. And whether it is between the arrival time without voltage drop amount or not.
According to a fourth aspect of the present invention, in the second determining step, whether or not the arrangement position can be easily changed is determined on the basis of the ease of movement of the logic cell that is digitized.
In the invention according to claim 5, the ease of movement is obtained by dividing the number of logic cells having a voltage drop amount exceeding the average voltage drop amount of the logic cells included in the entire chip or the critical path by the total number of critical paths. It is calculated based on a value.
According to a sixth aspect of the present invention, when the start point and the end point of the logic cell are flip-flops, the amount of voltage drop due to the movement of the logic cell is improved based on the voltage drop amount of the start point and end point of the logic cell. It is characterized by selecting or improving the amount of voltage drop by strengthening the power source.

According to the present invention, an increase in the number of gates due to layout timing improvement can be minimized, and a semiconductor integrated circuit having an optimum layout can be designed .

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a design flow of a semiconductor integrated circuit as an embodiment of the present invention.
In a design apparatus for designing a semiconductor integrated circuit, first, design rules, a library, a net list, and timing constraints are read (S1, S2). Next, a floor plan is executed to determine the chip size and hard macro placement position (S3). Thereafter, an allowable voltage drop value is set or an allowable voltage drop value described in the library is automatically acquired, and the read netlist is analyzed to determine the power supply wiring (S4).
Next, logic cell placement processing is performed as step S5. In the logic cell placement process, placement is performed in consideration of the voltage drop amount.
As the placement processing in step S5, first, in step S5-1, initial placement is performed considering only the timing convergence and the wiring congestion degree.
Next, in step S5-2, voltage drop analysis is performed to obtain voltage drop amount information for the entire chip and voltage drop amount information for each logic cell. The voltage drop information on the entire chip and the voltage drop information on each logic cell can be input from the outside.
Next, in step S5-3, STA (static timing analysis) capable of considering the voltage drop amount is performed to obtain timing information, and a critical path is recognized from this timing information. Note that the critical path may be recognized by inputting timing information from the outside.
In step S5-4, the logic cell arrangement information obtained in step S5-1, the voltage drop information of the entire chip obtained by the voltage drop analysis in step S5-2, and the voltage drop of each logic cell. Based on the information and the critical path information obtained by the STA in step S5-3, a detailed arrangement process for preferentially arranging the critical path at a position where the voltage drop amount is small is performed.
Here, the arrangement process of step S5 described so far will be described in more detail.
First, the initial arrangement in step S5-1 and the voltage drop analysis in step S5-2 are necessary to perform the STA in step S5-3. As described above, it is not necessary to input voltage drop amount information and timing information of the entire chip and each logic cell from the outside.
FIG. 2 shows the voltage drop analysis result of step S5-2.
In FIG. 2, the voltage drop amount at the center of the chip is the largest, and the voltage drop amount decreases toward the outside.
FIG. 3 shows the arrangement of logic cells (A, B, C, D, E) included in the critical path extracted from the STA implementation result in step S5-3, and the voltage drop analysis result obtained in step S5-2. FIG.
Since the initial arrangement in step S5-1 is not an arrangement that takes the voltage drop amount into consideration, it can be seen that the critical path has been arranged at a position where the voltage drop amount is large.

Next, the detailed arrangement process in step S5-4 in consideration of the voltage drop amount will be described with reference to FIG.
In this case, first, the chip is divided into regions of a certain size. Next, the average voltage drop amount in each region is obtained. Thereafter, a value obtained by dividing the maximum voltage drop amount by some amount is obtained, and compared with the average voltage drop amount of each region, a range in which the voltage drop amount falls is determined to group each region. For example, when the maximum voltage drop is 10 mV, AA group (0 to 2.5 mV), BB group (2.6 to 5.0 mV), CC group (5.1 to 7.5 mV) in 2.5 mV increments. And divided into four ranges of DD groups (7.6 to 10 mV), and grouping is performed according to which range each region is. In this case, the AA group is the group having the smallest voltage drop amount, and the DD group is the group having the largest voltage drop amount.
Next, the logic cells (A, B, C, D) included in the critical path extracted from the STA implementation result of step S5-3 are arranged. First, the logic cells included in the critical path are temporarily placed at the optimum coordinates obtained from the timing and the degree of convergence of the wiring. At this time, the logic cell A sets the temporary arrangement position as the position a.
Next, an area included in the small group with the smallest voltage drop amount from the position a is searched. In order to maintain the initial placement timing and wiring convergence to some extent, a search is performed within a certain range. For this range, a value given as an initial value may be used or input from the outside. In addition, the initial value may be summed with the SLACK value obtained from the timing analysis of this path so that the critical path timing is severer so that the movement can be performed in a range where the influence on the timing is small.
The closest region in the group with the lowest voltage drop included in this range is defined as region a.
Next, the area a of all the logic cells placed in the area a is obtained. Next, an area b obtained by adding the area a to the area a is obtained. If the area b is smaller than the area a (area c), the cell a is moved into the area a. When the area b exceeds the area a, the area b included in the group with the smallest voltage drop amount next to the position a is searched. This process is performed for all the logic cells included in the critical path.
Thereby, a critical path can be arranged in an area where the voltage drop is the smallest. By performing this process until all the logic cells are arranged, it is possible to perform detailed arrangement in which the critical path is preferentially arranged at a position where the voltage drop amount is small.

FIG. 4 shows a result of preferentially arranging critical path logic cells (A ′, B ′, C ′, D ′, E) at positions where the voltage drop amount is small by the detailed arrangement (S5-4) of this embodiment. Indicates.
In this way, by placing the critical path preferentially at a position where the voltage drop amount is small, the influence of delay variation due to the voltage drop amount is reduced, the timing convergence is improved, and the timing in the timing optimization processing described later is performed. Improvements can be facilitated.
As another arrangement method in consideration of the voltage drop amount, it has been found that the voltage drop amount is generally the largest at the center of the chip. Therefore, it is possible to perform detailed arrangement so that the critical path is not arranged at the center of the chip.
After performing the arrangement processing in step S5 as described above, CTS (clock tree synthesis) is performed in step S6 shown in FIG. 1, and timing optimization processing is performed in subsequent step S7.
As the timing optimization process in step S7, first, in step S7-1, a voltage drop analysis is performed. In this voltage drop analysis, in addition to the analysis of the entire chip, the voltage drop amount of each logic cell is also analyzed. Next, in step S7-2, STA (static timing analysis) is performed (S7-2). The critical path is recognized from the timing information of this STA.
In subsequent step S7-3, it is confirmed whether the timing of the entire circuit has converged. If it is confirmed that all the timings are satisfied ("Y" in S7-3), the process proceeds to step S8. The next process is signal wiring.

On the other hand, if a negative result is obtained in step S7-3, that is, if a timing violation occurs, in step S7-4, the voltage drop amount of the entire chip, each logic cell included in the critical path where the timing violation occurred It is determined whether the timing can be improved by reducing the voltage drop amount from the voltage drop amount and the logic cell arrangement position information.
If it is determined that the timing violation can be eliminated by reducing the voltage drop amount (“Y” in S7-4), the arrangement position can be changed to a position with a smaller voltage drop amount in step S7-5. Judge whether or not. If the arrangement position can be changed to a position where the amount of voltage drop is smaller (“Y” in S7-5), the arrangement is changed to a position where the amount of voltage drop is small in step S7-6. . This improves the timing.
In step S7-5, if the arrangement position cannot be changed to a position where the amount of voltage drop is smaller (“N” in S7-5), the power supply wiring is strengthened in step S7-7. This improves the timing.
If the timing cannot be improved even if the voltage drop amount is reduced in step S7-4 ("N" in S7-4), the cell sizing of the path causing the timing violation in step S7-8. And timing improvement by a known technique such as buffer insertion. In addition, when the process of step S7-6, S7-7, S7-8 is performed, it returns to step S7-1 and it is made to confirm whether the timing has converged in step S7-3.
If timing violations occur in a plurality of paths, the timing optimization process in step S7 is performed for each path.

Here, the timing optimization processing in step S7 will be described in detail.
First, FIG. 5 shows the voltage drop analysis result of the entire chip in the voltage drop analysis of step S7-1. In this case, the amount of voltage drop at the center of the chip is the largest, and the amount of voltage drop becomes smaller toward the outside. The voltage drop analysis result of the entire chip shown in FIG. 5 is the same as that shown in FIG.
FIG. 6 shows the arrangement position of the logic cells (A → B → C → D → E) in the critical path obtained as a result of the STA that can consider the voltage drop of each logic cell in step S7-1. It is the figure matched with the map.
In this case, there is almost no voltage drop at the position where the logic cell A and the logic cell E are arranged, and the logic cell B has a small voltage drop amount, so that the delay variation due to the voltage drop is a level that can be ignored. Conceivable.
On the other hand, since the logic cell C is arranged at a position in the amount of voltage drop, it is affected by delay variation due to the voltage drop. Since the logic cell D is arranged at a position where the amount of voltage drop is large, the logic cell D is greatly affected by delay variation due to the voltage drop.
FIG. 7 is a diagram showing the delay of the logic cells constituting the critical path.
The logic cell A and the logic cell E are flip-flops, and the logic cells C, D, and E are the same buffer cell. As a result of performing the STA that can consider the voltage drop amount of each logic cell, the logic cell C that is hardly affected by the voltage drop has a delay of 1 ns, but is arranged at a position in the voltage drop amount. It takes 3 ns for the logic cell D and 5 ns for the logic cell E arranged at a position where the voltage drop amount is large. Actually, the delay of the flip-flops of the logic cells A and E must be taken into consideration, but it is omitted for convenience of explanation. The clock cycle of this circuit is 8 ns.
Next, in step S7-3, it is determined whether the circuit timing has converged.
The total delay of the critical paths (A to E) is 9 ns, but the clock cycle is 8 ns. That is, in the case shown in FIG. 7, the timing has not converged. Therefore, in this case, the process proceeds to step S7-4, and in step S7-4, it is determined whether or not convergence is possible by improving the voltage drop amount.

Here, an example of a method for determining whether the timing can be converged by improving the voltage drop amount is shown.
FIG. 8 is a graph of the arrival time to each logical cell (A → B → C → D → E) of the critical path extracted in the STA.
The range in which the timing can be improved by improving the voltage drop amount is from the arrival time T1 considering the voltage drop amount of each logic cell to the arrival time T2 without the voltage drop amount.
In this example, since the allowable arrival time T3 is between the arrival time T1 to the logic cell E in consideration of the voltage drop amount and the arrival time T2 without the voltage drop amount, the improvement of the timing due to the improvement of the voltage drop amount is achieved. It can be judged that it is possible.
Next, the process of determining whether or not the timing can be improved by changing the arrangement position when the timing can be improved by improving the voltage drop amount (S7-5) will be described.
In order to effectively improve the timing by changing the arrangement position, it is necessary to easily change the arrangement position. Therefore, the ease of movement of the logic cell can be used as a criterion.
First, the ease of movement of the logic cell is defined as follows.
Ease of movement of logic cells = (number of logic cells having a voltage drop exceeding the average voltage drop of the entire chip / total number of critical paths)
In the above calculation formula, when determining the mobility of the logic cell, the average voltage drop amount of the entire chip is used as a reference, but the average voltage drop amount of the logic cell included in the critical path may be used as a reference.
FIG. 9 is a graph showing the voltage drop amount of each logic cell in the critical path and the average voltage drop amount of the entire chip obtained as a result of STA.
Logic cells having a voltage drop amount exceeding the average voltage drop amount of the entire chip in the critical path are two logic cells C and D, and the total number of logic cells included in the critical path is five. In this case, the ease of movement of the logic cell is 0.4 from the above formula.

On the other hand, in FIG. 10, the number of logic cells (cells A, B, C, E) having a voltage drop amount equal to or greater than the average voltage drop amount is 4 cells, and the mobility of the logic cells is 0.8.
In the above example, for example, when it is determined that the ease of movement of the logic cell is 0.5 or less and the timing can be improved by reducing the voltage drop amount, the critical path shown in FIG. 9 is determined to be able to improve the timing by changing the arrangement position. The critical path in FIG. 10 can be determined to be unable to improve the timing by changing the arrangement position. Note that the reference value (0.5 in the above example) for determining that the timing can be improved by reducing the voltage drop amount may be a different value. As another method, there is a method that pays attention to the voltage drop amount at the start point and end point of the critical path. In general, the start and end points of logic cells are often flip-flops. The flip-flop has a clock terminal, and a buffer tree that suppresses the skew in the CTS processing in step S6 is often extended.
By moving the flip-flop, the SKEW suppressed in the CTS process in step S6 is destroyed. For this reason, when the voltage drop amount at the start and end points of the logic cell is small, the voltage drop amount improvement is selected by moving the logic cell. When the voltage drop amount at the logic cell at the start and end points of the logic cell is large, the power supply is strengthened. Select to improve the voltage drop.

As a timing improvement method, there are two methods, a timing improvement method by changing the arrangement to a position where the amount of voltage drop is small, and a timing improvement method by strengthening the power source. It is selected by the process of -5.
Examples of improvements are shown below.
First, an example of timing improvement by changing the arrangement to a position where the voltage drop amount is small will be described.
In this case, first, the logic cell to be moved is recognized.
The logic cell to be moved is a logic cell having a voltage drop amount greater than the average voltage drop amount.
For example, in FIG. 9 described above, logic cells having a voltage drop amount greater than the average voltage drop amount are logic cells C and D. Therefore, it can be recognized that the logic cells whose arrangement is changed are C and D. After the identification of the logic cell to be arranged is completed, the arrangement is changed.
Next, processing for changing the arrangement of the logic cells D will be described with reference to FIG.
First, a straight line L1 (broken line in the figure) connecting the logic cells A and E that are the start point and the end point is drawn. This straight line may be a straight line connecting cells before and after the logic cell to be moved other than the straight line connecting the start point and the end point.
Next, a straight line L2 perpendicular to this straight line is drawn from the logic cell D whose arrangement is to be changed.
Next, the logic cell D is moved a certain distance in a straight line direction perpendicular to the start point and the end point. After moving a certain distance, check the voltage drop at that position. As the distance and the number of times of movement, those given as initial values may be used, or values externally input may be used. Further, the calculation may be performed based on the distance from the logic cell to be moved (logic cell D in this example) to the straight line connecting the start point and the end point. Furthermore, it is moved again by a certain distance in the same direction, and the amount of voltage drop at that position is confirmed. This movement is executed the number of times designated by the initial value or the number of times externally input, and the position with the lowest voltage drop is specified.
In order not to increase the total wiring length of the critical path, it is preferable that the movement range is up to twice the distance from the logic cell D to the straight line connecting the start point and the end point. When the cells in this range are moved, the total wiring length tends to be short.

Next, the cell D ′ is moved to a position where the specified voltage drop amount is the lowest. This process is performed for all the logic cells recognized as the logic cells to be moved.
FIG. 12 shows a layout after the layout of the logic cells C and D is changed.
The logic cells C and D before the change were greatly affected by the delay variation due to the voltage drop, but moved to a position where the voltage drop amount at a level where the delay variation due to the voltage drop amount can be ignored is small. Thereby, the amount of voltage drop can be reduced and timing can be improved.
FIG. 13 shows a delay value based on the STA result after the arrangement change of the circuit after the arrangement improvement and the logic cells C ′ and D ′. Since the voltage drop amount of the logic cells C ′ and D ′ has changed small, the cell delay is 1 ns. The delay of the logic cells A, B, and E does not change. Since the clock cycle of the circuit is not changed from 8 ns, the timing of 5 ns is MET.
In this way, by rearranging the arrangement position of the logic cell affected by the delay variation due to the voltage drop amount to a position where the voltage drop amount is small, the delay of the logic cell can be reduced and the timing violation can be eliminated. it can. Thereby, in step S7-3, it is confirmed that the timing has converged, and the process proceeds to the next step S8.

Next, the timing improvement method by power supply reinforcement will be described.
FIG. 14 shows the voltage drop analysis result after the power supply wiring is strengthened and the arrangement of critical paths. The voltage drop map and the voltage drop map are changed by strengthening the power supply around the logic cells C and D that are greatly affected by the delay variation due to the voltage drop amount. As a method for strengthening the power source, a known technique is used.
FIG. 15 is a diagram showing the delay value of the logic cell of the circuit after the power supply wiring enhancement and the STA result after the power enhancement. The logic cells A, B, C, and E have no change in delay because the amount of voltage drop does not change. The logic cell D has a reduced voltage drop due to the strengthening of the power supply around the logic cell D, and the voltage drop is in the middle position. Therefore, the delay of the logic cell is 3 ns. Since the circuit clock period 8 ns does not change, the 1 ns timing is MET. By strengthening the power supply wiring of the logic cell and reducing the voltage drop amount of the logic cell included in the timing violation path, the delay of the logic cell is reduced and the timing violation can be solved. Thereby, in step S7-3, it is confirmed that the timing has converged, and the process proceeds to the next step S8.
As described above, in this embodiment, focusing on the voltage drop amount of the critical path, the timing convergence is improved by controlling the voltage drop amount of the critical path, and the optimal number of gates due to the improvement of the layout timing is suppressed as much as possible. A semiconductor integrated circuit can be designed according to the layout. Therefore, if a semiconductor integrated circuit is manufactured by using the semiconductor integrated circuit design method of this embodiment, a semiconductor integrated circuit that can improve timing convergence even in a circuit that cannot logically reduce power consumption. Can be manufactured.

It is the figure which showed the design flow of the semiconductor integrated circuit as embodiment of this invention. It is the figure which showed the analysis result of the voltage drop. It is the figure which showed the example of arrangement | positioning of a critical path. It is the figure which showed the example of arrangement | positioning after the improvement of a critical path. It is the figure which showed the analysis result of the voltage drop. It is the figure which showed the example of arrangement | positioning of a critical path. FIG. 5 is a diagram showing delay of logic cells constituting a critical path. It is explanatory drawing of the delay which can be improved by reduction of a voltage drop. It is the graph which showed the voltage drop amount of each logic cell, and the average voltage drop amount. It is the graph which showed the voltage drop amount of each logic cell, and the average voltage drop amount. It is explanatory drawing of the movement method of each logic cell. It is the figure which showed the arrangement | positioning after the movement of each logic cell. FIG. 5 is a diagram showing delay of logic cells constituting a critical path. It is a figure explaining the example of improvement by power supply reinforcement. FIG. 5 is a diagram showing delay of logic cells constituting a critical path.

Explanation of symbols

  A, B, C, D, E ... logic cells

Claims (6)

A design method of a semiconductor integrated circuit executed by a design apparatus for designing a layout of a semiconductor integrated circuit,
A voltage drop analysis step for analyzing the voltage drop of the whole semiconductor chip or each logic cell;
Static timing analysis in consideration of the amount of voltage drop, static timing analysis step of analyzing the timing convergence of the critical path of the logic cell based on the obtained timing information;
A first determination step of determining whether or not timing improvement by reducing the voltage drop amount is possible when the result of the static timing analysis step is a timing violation;
A second determination step of determining whether or not the timing can be improved by changing the arrangement position when the timing can be improved by reducing the voltage drop amount;
An arrangement changing step for changing the arrangement of the logic cells included in the critical path to a position where the amount of voltage drop is small when it is determined that the timing can be improved by changing the arrangement position in the determining step;
A method for designing a semiconductor integrated circuit , comprising: 2. The method according to claim 1, further comprising a step of strengthening a power supply line of a logic cell included in the critical path when it is determined in the second determination step that the timing cannot be improved by changing the arrangement position. A method for designing a semiconductor integrated circuit. In the first determination step, an allowable arrival time is between an arrival time in consideration of a voltage drop amount to each logic cell in the critical path extracted in the static timing analysis step and an arrival time without a voltage drop amount. 3. The method of designing a semiconductor integrated circuit according to claim 1, wherein the determination is made based on whether or not the semiconductor integrated circuit is present . 4. The determination according to claim 1, wherein in the second determination step, determination is made on the basis of ease of movement of the logic cell, which is a numerical value as to whether or not the arrangement position can be easily changed. 5. Design method of semiconductor integrated circuit. The ease of movement is calculated based on a value obtained by dividing the number of logic cells having a voltage drop amount exceeding the average voltage drop amount of logic cells included in the entire chip or the critical path by the total number of critical paths. The method of designing a semiconductor integrated circuit according to claim 4. When the start point and end point of the logic cell are flip-flops, the improvement of the voltage drop amount due to the movement of the logic cell is selected based on the voltage drop amount of the start point and end point of the logic cell, or the voltage drop amount due to power strengthening 2. The method of designing a semiconductor integrated circuit according to claim 1, wherein the improvement is selected.