JP2000099554A - Logic block arranging method, delay library and delay time calculating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve operation timing while a power voltage drop phenomenon by a wiring resistor is considered and to reduce power consumption. SOLUTION: In a power voltage map generation process ST01, a power voltage map showing the distribution of operation power voltage owing to the wiring position of a power wiring in a cell arrangement area is generated. In an initial arrangement deciding process ST02 a cell is initialized for outline arrangement 1, a pad cell is arranged at the peripheral edge part of a chip, and a cell except for the pad cell in the center of the chip, for example. In an operation timing improvement process ST03, the operation timing of the respective cells, which considers the drop of power voltage is improved. In a cell group dividing process ST06 a cell group is divided. The improvement processing of timing and the reduction processing of power consumption are repeated for the prescribed number of times and the cells are minutely arranged in a minute arrangement process ST07.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of arranging functional blocks or logical blocks composed of logical cells, a method of creating a delay library, and a method of calculating a delay time in a layout design of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, as is called the system-on-silicon era, a semiconductor LSI chip with a higher degree of integration has been developed as a system is built on one chip, and the number of steps required for LSI design has increased. Is going on.

[0003] The layout design is no exception.
Since man-hours and processing time are increasing exponentially, laying out the entire circuit at once requires enormous time and labor.

As a layout design method of a semiconductor LSI chip, there are a gate array method, a sea of gate method, a standard cell method, and the like. Each of these methods is based on NA
A method of arranging an LSI chip by arranging basic logic cells such as ND and OR and composite cells combining them on an LSI substrate in an array and wiring between terminals provided in each cell according to a predetermined circuit connection It is. In these methods, design automation has been advanced, and various design support systems (CAD systems) have been developed.

A basic procedure for designing an LSI using the present system will be described.

1) A logic cell is arranged in a virtual chip area (cell arrangement).

2) A rough wiring path on the chip is determined (schematic wiring).

3) Wiring between all nets is determined based on the schematic wiring so as to satisfy a specific design rule (detailed wiring).

Here, a net is a set of terminals of cells which must be connected to an equal potential. For example, when designing an LSI using the building block method, first, a floor plan for determining in which area functional blocks are to be arranged for the entire chip is often performed. At this time, the functional blocks that are not laid out are arranged, and the pins are arranged to determine the positions of the external terminals (floating external terminals) with which these functional blocks perform input / output with the outside.

[0010] Advances in semiconductor LSI manufacturing technology have led to the design of semiconductor LSIs using a design rule of less than 0.5 μm, which is called deep submicron today. As a result, the wiring delay becomes larger than the gate delay in the relationship between the wiring delay and the gate delay occupying the signal transmission time in the circuit, that is, the signal delay time (hereinafter simply referred to as delay time). It is an indispensable task to consider wiring delay in the design. In order to solve this problem, a semiconductor LSI is designed while considering a delay time. Such a design method is called a timing-driven design method.

Hereinafter, the basic principle of the timing driven design method will be briefly described. Generally, many semiconductor LSIs are designed as synchronous circuits. This synchronous circuit can be modeled as a set of synchronous elements such as flip-flops and a set of combinational circuits connecting the synchronous elements. At this time, the clock cycle time T of the circuit
_clk is _Tclk ≧ max ( _Thold + _TDQ + _Tdelay +
T _skew ). Here, T _hold is the setup / hold time of the synchronous element, T _DQ is the delay time from signal input to signal output inside the synchronous element, T _delay is the delay time of the combinational circuit, and T _skew is the clock _skew .

Further, the delay time T _delay is a _delay between gates (a delay from a fan-in of one gate to a fan-in of another gate connected to the one gate) T _d.
Can be modeled by the sum of That is, it can be formulated as T _d = T _intrinsic + T _load + T _wire + T _priv . Here, T _intrinsic is a gate delay independent of the wiring load, T _load is a gate delay relating to the entire wiring load (sum of wiring capacitance and input pin capacitance),
_wire is a wiring delay that depends on the wiring shape and the like, and _Tpriv is a delay that depends on the waveform _blunting of the preceding stage.

[0013] The model is further simplified to include three terms excluding the wiring delay T _wire depending on the wiring shape, ie, T
_{If intrinsic} , T _load and T _priv are put as the gate delay T _gate , then T _d = T _gate + T _wire .

Thus, the timing driven design is
This is a method of designing by estimating a gate delay and a wiring delay based on the modeling described above. In addition,
For details, see Proceedings of the 27th Design Automation Conference Minutes, 1990, pp. 573-579 (Proc. Of the 2
7th Design Automation Conference, 1990, pp.573-57
9) ”or“ The 31st Design Automation Conference Minutes, 1994, pp. 327-332 (Proc. Of the
31st Design Automation Conference, 1994, pp.327-3
32)).

Next, the basic concept “slack” used in the timing driven design method will be described.

The slack value (slack (x)) is a timing constraint (delay value constraint) of a signal path, a signal net, and the like.
For a value indicating the margin is defined as _{slack (x) = T r (} x) -T a (x). Here, T _r (x) represents the arrival time required by design for the circuit x (element, signal path, etc.),
_a (x) is the time when it actually arrived at the circuit x (determined on the layout diagram). Therefore, when T _a (x) is larger than T _r (x), that is, when slack (x) is negative, it means that a timing violation has occurred.

The timing-driven design method shortens the wiring until all slack values become positive to improve operation timing. For details, see “The 22nd Design Automation Conference Minutes, 1985, pp. 124-130 (Pr.
oc. of the 22nd Design Automation Conference, 198
5, pp. 124-130) ".

On the other hand, a method of arranging logical blocks in consideration of a delay time is called a timing-driven arranging method.
PROUD Law, Proceedings of the 25th Design Automation Conference Minutes, 1988, pp. 318-323 (Proc. Of
the 25th Design Automation Conference, 1988, pp.3
18-323) "and the RITUAL method" I Triple E Transactions on Circuits and Systems, 1992, pp. 825-840 (Proc. IEEE Tra
nsactions on circuits and systems, 1992, pp.825-84
0) ", the Gordian method," I Triple E Transactions on Computer Aided Design, 1991, pp. 356-365 (Proc. IEEE Tra
nsactions on computer Aided Design, 1991, pp.356-3
65) ”has been proposed.

These methods are high-speed algorithms which have been recently announced in many ways and combine a minimum cut method and a mathematical programming technique. These methods are also one of the high-speed solutions, and a quadratic expression as shown in the following expression (1) is used as the evaluation function. Φ (x) = (xt × B × x + yt × B × y) / 2 + ct × x + dt × y (1) Here, the matrix x and the matrix y are the coordinate positions of the module (logical block). Represents a vector, matrix ct and matrix d
t represents the transpose of the vector with respect to the coordinate position of the fixed module, and the matrices xt and yt are the matrices x and y
Represents the respective transposed matrices. Further, matrix B
Is a Laplace matrix in which the connection relations of modules are weighted, and the operation timing (cost weighting) is controlled by being reflected in the matrix B.

Solving the quadratic equation shown in equation (1) (nonlinear programming) is a technique that is often used recently because the calculation cost is smaller than solving the linear equation (linear programming). However, it has been reported that the placement result of a semiconductor LSI chip is better when the evaluation function is a linear expression,
Focusing on this, there has been reported a method of improving equation (1) and using a pseudo-quadratic equation using the concept of a spring constant (Gor
Dian method, Proceedings of the 28th Design Automation Conference Minutes, 1991, pp. 427-432 (Proc. of t
he 28th Design Automation Conference, 1991, pp.427
-432) ").

The outline of this arrangement algorithm is as follows. 1) The one-dimensional arrangement is obtained by using the equation (1) alternately on the X axis and the Y axis. And 3) repeating 1) and 2) an appropriate number of times for each divided arrangement area.

This is shown in FIGS. 12 (a) to 12 (c). As shown in FIG. 12A, the semiconductor layer chip 101
In the upper center, a plurality of modules 1 including logic cells and the like
02 are arranged so as to overlap as an initial arrangement. Here, first, a one-dimensional arrangement is obtained using the evaluation result of Expression (1), and the arrangement area is divided using a first straight line 103A parallel to the X axis. Next, as shown in FIG. 12B, a one-dimensional arrangement is obtained in each of the divided areas, and the arrangement area is divided again using a second straight line 103B parallel to the Y axis. Next, as shown in FIG. 12C, a one-dimensional arrangement is obtained in each of the divided areas, and an arrangement area is formed using a third straight line 103C and a fourth straight line 103D which are respectively parallel to the X axis. Divide further. In this way, the division of the area by the straight line parallel to the X axis or the Y axis is alternately repeated to obtain the final module arrangement shown in FIG.

Incidentally, semiconductor LSI chips are required to be designed not only for high-speed operation but also for low power consumption. A CMOS circuit, which is a circuit method widely used in a semiconductor LSI chip, has a feature that a current with low power consumption can be obtained because current flows only during operation. However, power consumption continues to increase despite CMOS circuits.

The power consumption P of the CMOS circuit in the semiconductor LSI chip is given by the following equation (2).

[0025] _{P = K p × (CL ×} V s × V dd + I SC × Δt SC × V dd) × f CLK + (I DC + I LEAK) × V dd = K p × f CLK × CL × V s × V _dd + K _p × f _CLK × I _SC × Δt _SC × V _dd + I _DC × V _dd + I _LEAK × V _dd (2) where K _p represents a switching (transition) probability and C
L represents load capacitance, V _s represents signal amplitude, and V _dd
Represents a power supply voltage, I _SC represents an average value of a through current, ΔT _SC represents a through current generation time during which a through current flows, f _CLK represents a clock frequency, and I _DC represents a DC current of a differential amplifier or the like. And I _LEAK represents a leak current.

In equation (2), the first term represents the power required for charging and discharging the load, and the second term represents the power due to the through current flowing during switching.

The third term is a general CM except for a sense amplifier and an analog circuit of a memory through which a DC current flows.
The term can be ignored in the OS circuit, and the fourth term hardly flows in the CMOS circuit unless the threshold voltage of the transistor is extremely reduced. As a result, in the CMOS circuit, the third and fourth terms can be ignored, so that the power consumption P can be approximated as follows.

[0028] _{P = K p × f CLK ×} CL × V s × V dd + K p × f CLK × I SC × Δt SC × V dd ... (3) expression of the power P (3), each designed Commonly used in the process.

[0029] To reduce power consumption, the toggle count (K _p × f _CLK), the load capacitance CL, the signal amplitude V _s, the power supply voltage V _dd, or through current generation requires that time be reduced Delta] t _SC It is.

An arrangement method for lowering power consumption has also been proposed. A typical example is the Pcube method “European
Minutes of the Design Automation Conference, 1993, pp. 72-77 (Proc. Of the European Design Autom
ation Conference, 1993, pp.72-77). This is basically the PROUD method, RITUAL method and Go
This is almost the same method as the rdian method, but the matrix B shown in equation (1) is slightly different. That is, the transition probabilities are used for the elements of the matrix B, whereby an arrangement in which the wiring of a module having a high transition probability is shortened can be realized.

There is also research from another viewpoint of low power consumption. This is a post-layout optimization method for performing further optimization once the layout has been completed.
The basic technologies are gate resizing (reduction of gate size), optimization by buffer insertion, etc., and PNO method (Pla
cement based Net Optimization).

The outline of the algorithm is as follows: 1) Execute timing-driven placement; 2) Minimize the gate size of all cells; 3) Detect delay paths that have caused timing violations;
The operation timing is improved by using the O method.

According to reports, it is about 1/4 compared to before optimization.
Power consumption can be reduced.

Further, the semiconductor LSI of the deep submicron era where the current amount of the semiconductor LSI rapidly increases beyond the electric power amount
In the case of SI, there is a problem in that the operation speed of cells or the like is reduced due to disconnection due to electromigration or a voltage drop due to power supply wiring resistance in the LSI power supply wiring.

Conventionally, as a technique for accurately estimating a power supply voltage drop, a method of solving a power supply wiring network using an equivalent circuit model of a resistor and a current source network has been proposed. The power supply wiring network is treated as a resistance network, and the cell or transistor is treated as a current source. Related known examples include the XPOWER method (“Latest ASIC Design Technology '94”, published by Nikkei BP, pages 87-92) or “The 29th Design Automation Conference Minutes, 1992, pages 524-529 (Proc.
of the 29th Design Automation Conference, 1992, p
p.524-529) ".

[0036]

As described above,
In a semiconductor LSI in the deep submicron era, a power supply voltage drop due to wiring resistance cannot be ignored.

However, the delay calculation model used for the automatic layout and wiring in the conventional layout design assumes that the power supply voltage is uniformly supplied to each functional block or logic cell. Therefore, there is a high possibility that discrepancies with the case where the delay time is calculated by performing a strict simulation of the power supply voltage drop after the layout design is performed, and a situation in which the design needs to be redone may occur.

In order to reduce power consumption during layout design, the Pcube method has been proposed as an arrangement for reducing power consumption, but has the following problems. That is, since the transition probability is directly evaluated by a quadratic function, it is effective for shortening the wiring length, but is insufficient in terms of power consumption. For example, there is a problem that power consumption of a net having a high transition probability is excessively evaluated.

The PNO method also has the following problem. That is, since the driving capability of the cell is optimized in the post layout, the optimization of the load capacitance related to the wiring is not performed. Specifically, although the load capacitance CL with respect to the pin capacitance shown in the above equation (3) is reduced, the reduction in the load capacitance CL due to the shortened wiring length is ignored.
The through current generation time Δt _SC increases.

A first object of the present invention is to solve the above-mentioned conventional problems and to improve the operation timing while considering the power supply voltage drop phenomenon due to the wiring resistance when designing the layout of a semiconductor integrated circuit. It is a second object to reduce power consumption.

[0041]

A first logical block arrangement method according to the present invention achieves the first and second objects and employs a timing-driven arrangement method in which the operating frequency is a constraint. The present invention is directed to a method of arranging a plurality of logic blocks including functional blocks or logic cells constituting a semiconductor integrated circuit in an arranging area. A power supply voltage map creating step of creating a power supply voltage map representing a voltage distribution; an initial arrangement determining step of determining an initial arrangement of a plurality of logic blocks; and a delay for each of the plurality of logic blocks based on the voltage values of the power supply voltage map. By calculating the time and rearranging the plurality of logical blocks so as to reduce the calculated delay time, each of the plurality of logical blocks is An operation timing improvement step for improving the operation timing, and calculating the power consumption for each of a plurality of logic blocks based on the voltage value of the power supply voltage map, and the driving capability of the output side of the logic block so that the calculated power consumption value is reduced. A power consumption reducing step of reducing the power consumption of each of the plurality of logical blocks, and dividing the rearranged plurality of logical blocks so as to include each of the plurality of logical blocks. Generating a divided block group, and an iterative step of sequentially repeating an operation timing improvement step, a power consumption reduction step, and a block group generation step for each block of the plurality of block groups,
And a detailed arrangement step of rearranging the rearranged plurality of logical blocks so that they do not overlap each other and satisfy operation timing.

According to the first logic block arranging method, before arranging the logic block, a power supply voltage map representing the distribution of the operating power supply voltage for each logic block due to the wiring position of the power supply wiring in the arrangement area is created. Therefore, in the operation timing improvement step, the voltage drop phenomenon is reflected in the delay time calculated for each logic block based on the voltage value shown in the power supply voltage map. Further, in the power consumption reduction step, the power consumption is calculated for each logical block based on the voltage value represented in the power supply voltage map. Therefore, the calculated power consumption also depends on the wiring position of the power supply wiring in the placement area. The voltage drop phenomenon is reflected.

In the first logical block arranging method, the operation timing improving step includes the steps of:
A delay time calculating step of calculating a delay time based on a power supply voltage value depending on a position where each is arranged; and a tentative arrangement step of tentatively arranging a plurality of logical blocks based on the calculated delay time. Delay value excess net extraction for extracting a net exceeding a delay constraint value regulated by a constraint condition among a plurality of nets composed of a set of input / output terminals connected to equipotentials in a plurality of logic blocks based on the delay time. And a relocation step of relocating a logical block having a net exceeding the delay constraint value among the plurality of logic blocks so that the logical block falls within the delay constraint value.

In the first logic block arrangement method, the power consumption reduction step calculates, for each of the plurality of logic blocks, a transition probability that the potential of the output pin of each logic block transitions from high to low or from low to high. A transition probability calculating step, a power consumption calculating step of calculating power consumption based on a power supply voltage value depending on a position where each of the plurality of logic blocks is disposed, and an equipotential in the plurality of logic blocks. After extracting a net that does not exceed the delay constraint value regulated by the constraint condition from a plurality of nets composed of a set of input / output terminals, the calculated power consumption values are arranged in descending order, and the arranged power consumption values are arranged in descending order. A logic block corresponding to each of the power consumption values is selected, and the selected logic block is a logic block having a lower driving capability than the logic block. And a logical block exchange step of exchanging so as not to exceed the delay constraint value.

A second logic block arranging method according to the present invention achieves the first object, and uses a timing-driven arranging method with an operating frequency as a constraint condition to configure a functional block constituting a semiconductor integrated circuit. Or, based on a logical block arrangement method of arranging a plurality of logical blocks composed of logical cells, an initial arrangement determining step of determining an initial arrangement of a plurality of logical blocks, and, for each of the plurality of logical blocks, at a position where each is arranged. A delay time calculating step of calculating a delay time based on a dependent power supply voltage value, a provisional arrangement step of temporarily arranging a plurality of logical blocks based on the calculated delay time; Of multiple nets consisting of a set of input / output terminals connected to equipotentials in the logic block of A delay value excess net extracting step of extracting a net, and a relocation step of relocating a logical block having a net exceeding a delay constraint value among a plurality of logical blocks so that the logical block falls within the delay constraint value. And

According to the second logic block arrangement method, the delay time is calculated for each of the plurality of logic blocks based on the power supply voltage value depending on the position where each of the logic blocks is arranged. The time reflects the voltage drop phenomenon. Further, since a logical block having a net exceeding the delay constraint value is rearranged so as to be within the delay constraint value, an operation timing violation can be eliminated.

A third logic block layout method according to the present invention achieves the first and second objects, and configures a semiconductor integrated circuit by using a timing-driven layout method with operating frequency as a constraint. A logical block arranging method for arranging a plurality of logical blocks composed of functional blocks or logical cells to be performed, and an initial arrangement determining step of deciding an initial arrangement of the plurality of logical blocks; A transition probability calculating step of calculating a transition probability that the potential of the output pin has a transition from high to low or from low to high, and, for each of a plurality of logic blocks, consuming based on a power supply voltage value depending on a position where each is arranged. A power consumption calculation step of calculating power; and a plurality of nets each including a set of input / output terminals connected to equipotentials in a plurality of logic blocks. After extracting a net that does not exceed the delay constraint value regulated by the constraint condition, the calculated power consumption values are arranged in descending order, and the logic blocks respectively corresponding to the power consumption values are arranged in descending order of the arranged power consumption values. And a logic block exchange step of exchanging the selected logic block with a logic block having a smaller driving capability than the logic block so as not to exceed the delay constraint value.

According to the third logic block arranging method, the power consumption is calculated for each logic block based on the power supply voltage value depending on the position where each logic block is arranged. , The voltage drop phenomenon caused by the wiring position of the power supply wiring is reflected. Furthermore, after extracting nets that do not exceed the delay constraint value, the calculated power consumption values are arranged in descending order, and the logic blocks respectively corresponding to the power consumption values are selected from the side with the higher power consumption value of the extracted nets, Since the selected logic block is replaced with a logic block having a smaller driving capability than the logic block within a range not exceeding the delay constraint value, power consumption can be reduced without causing an operation timing violation.

The delay library according to the present invention comprises the first
The delay library for calculating the delay time for each of a plurality of logic blocks in the timing design of a semiconductor integrated circuit composed of a plurality of logic blocks consisting of functional blocks or logic cells,
A delay calculation function including a slope value of an input signal waveform, an output load capacitance value, and a power supply voltage value is provided.

According to the delay library creating method of the present invention, a delay calculation function including a slope value of an input signal waveform, an output load capacitance value and a power supply voltage value is generated. , The power supply voltage drop is reflected in the delay time output from the function.

A delay time calculating method according to the present invention achieves the first object, and comprises a plurality of logic blocks in a timing design of a semiconductor integrated circuit constituted by a plurality of logic blocks including functional blocks or logic cells. Assuming a delay time calculation method that calculates the delay time for each
When using an unregistered logical block whose operating power supply voltage value that guarantees the operation of the logical block is not registered in the library among the plurality of logical blocks, the first power supply that is larger than the operating power supply voltage value of the unregistered logical block A library preparing step of preparing a first library that guarantees operation with a voltage value and a second library that guarantees operation with a second power supply voltage value smaller than the operation power supply voltage value of the unregistered logic block; The first library is used to determine a first delay time of an unregistered logical block, and the second library is used to determine a second delay time of an unregistered logical block.
A delay time calculating step of calculating a delay time at an operating power supply voltage of an unregistered logic block from the delay time and the second delay time.

According to the delay time calculating method of the present invention, the first library of the unregistered logic block is used by using the first library which guarantees the operation at the first power supply voltage value larger than the operation power supply voltage value of the unregistered logic block. And the second delay time of the unregistered logic block is obtained by using a second library smaller than the operating power supply voltage value of the unregistered logic block, and the first delay time and the second delay time are obtained. In order to calculate the delay time in the operation power supply voltage of the unregistered logic block from, even if there is no library corresponding to the operation power supply voltage value that guarantees the operation of the logic block,
The delay time of the logic block at a desired operating power supply voltage can be obtained.

[0053]

(First Embodiment) A first embodiment of the present invention.
An embodiment will be described with reference to the drawings.

1 to 3 are explanatory diagrams of a logic block arrangement method according to the first embodiment of the present invention. FIG. 1 shows a schematic flow chart, and FIG. 2 shows a cell arrangement area and a standard cell arrangement area. FIG. 3 shows an equivalent circuit, and FIG. 3 shows a power supply voltage map of a cell arrangement region. Here, standard cells are treated as logical blocks.

As shown in FIG. 1, the cell arranging process employs a two-stage configuration of a general arrangement 1 and a detailed arrangement ST07. The overall strategy for cell placement is a PROUD, RITUAL, or Gord method that combines a minimal cut method and a mathematical programming technique.
This is the same as the ian method, and performs hierarchical processing as shown in FIG.

First, in a power supply voltage map preparing step ST01, a power supply voltage map representing a distribution of operating power supply voltages due to a wiring position or a structure of a power supply wiring in a cell arrangement region is prepared. Therefore, the power supply voltage distribution reflects the amount of voltage drop for each wiring position. Specifically, a method of creating a power supply voltage map of a semiconductor LSI and a cell arrangement region of the LSI will be described with reference to FIGS. FIG.
In (a), reference numeral 11 denotes one of blocks obtained by dividing a cell arrangement region on an LSI into a plurality. The block 11 is provided with four cell columns 12 and each cell column 12
The power supply line 13 is disposed on one side in the longitudinal direction of the device, and the ground line 14 is disposed on the other side. When the block 11 having such wiring is represented as a resistor and a current source network in the same manner as in the XPOWER method or the like, FIG.
Is obtained. As shown in FIG.
Each cell of each cell column 12 becomes a current source flowing through the ground line, and is solved by the circuit network to each node N _ij (1 ≦ i, j
It is an integer of ≦ 5. The power supply voltage drop can be evaluated by obtaining the voltage value of ()).

It is assumed that each cell row 12 is divided into four slots 15 for the block 11 shown in FIG. 3A, and that a uniform voltage value is applied to each of the slots 15. 16 shown in FIG. 3 (b) represents the power supply voltage map, slots 15 of a circle shown in FIG. 3 (a) corresponds to the slot S ₁₁ shown in FIG. 3 (b). Slot S
The voltage value V ₁₁ at ₁₁ expressed as v (S _11).

In this embodiment, the slot 1
5 is obtained by dividing the block 11 into 16 parts (the cell row 12 is divided into four parts). However, the present invention is not limited to this. When the difference between the voltage values of the adjacent nodes N _ij falls within a predetermined value, these nodes N
There is also a method of defining _ij as one region.

Next, an initial arrangement determination step ST0 shown in FIG.
2, a plurality of cells (cell group) for the schematic arrangement 1
Is performed. The arrangement position of the cell group may be appropriate,
Generally, the pad cells are arranged at the periphery of the chip, and the other cells are arranged at the center of the chip.

Here, a power supply voltage map creation step ST01
And the order of the initial arrangement determination step ST02 may be interchanged. Therefore, first, the power supply voltage map creation step ST
When performing 01, random arrangement is performed, or
A power supply voltage map is created by setting an appropriate current source. On the other hand, when the initial placement determination step ST02 is performed first, a power supply voltage map may be created based on the information on the initial cell placement.

Next, in the operation timing improvement step ST03, the operation timing of each cell is improved in consideration of the power supply voltage drop. Specifically, a delay calculation is performed on the current cell arrangement position using the power supply voltage map 16 shown in FIG. 3B to calculate the delay time of each cell. At this time, since no wiring has been performed, there is no wiring route, but this is defined as a star-connected net model (star-connected net
model), and the placement of each cell is improved by using a timing-driven placement method based on the calculated delay time.

Next, in the power consumption reduction step ST04, the power consumption is determined by taking the power supply voltage drop into consideration, thereby reducing the power consumption. Specifically, the power consumption values obtained for each cell are arranged in descending order of the power consumption value, and the logic blocks corresponding to the power consumption values are selected. The selected logic block is replaced with a cell or a functional block having a smaller driving capability than the selected logic block, which is registered in the cell library, within a range where no timing violation occurs. Thus, an effect of reducing power consumption equivalent to the method of reducing power consumption by the PNO method can be expected.

The power supply voltage map may be updated at the end of the operation timing improvement step ST03 or at the end of the power consumption reduction step ST04. This is because there is a possibility that the state of the power supply voltage will be different through the operation timing improvement step ST03 or the power consumption reduction step ST04.

Next, after performing the operation timing improvement step ST03 and the power consumption reduction step ST04 in one layer,
In the division determination step ST05, a plurality of cells (cell groups)
It is determined whether or not to divide. If the predetermined number of divisions is not reached, in a cell group division step ST06 as a next division block group generation step, division into a plurality of block groups having a plurality of cells is performed using the method shown in FIG.
On the other hand, if the predetermined number of divisions is reached,
Proceed to T07. Note that the number of divisions may be repeated, for example, until the number of cells in one divided area (slot) is within several.

Next, after completing the cell group dividing step ST06, the operation timing improving step ST is performed for each divided area.
The process is repeated again from 03.

When it is determined in the division determination step ST05 that the division has been completed, in the detailed arrangement step ST07, the cells are arranged so that the cells do not overlap and the operation timing is satisfied. The arrangement method may be appropriate, and for example, the Pcube method may be used.

As described above, according to the present embodiment, the power supply voltage map 16 representing the voltage distribution depending on the position of the power supply wiring in the placement area is created in advance. As a result, it is possible to realize a cell arrangement method that reflects the power supply voltage drop phenomenon due to the wiring resistance for each slot in detail, and is timing-driven and capable of reducing power consumption. Thus, in the cell arrangement based on timing, the cell arrangement can be performed under conditions closer to the actual LSI chip, and as a result, a timing error can be prevented. For this reason, rework of the design can be eliminated, and man-hours can be reduced.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 4 to 6 are explanatory diagrams of a logic block arranging method according to the second embodiment of the present invention. FIG. 4 shows a schematic flowchart, FIG. 5 shows a virtual wiring model, and FIG. Represents a logical block connection configuration (= slack graph) for explaining slack. FIG. 4 is also a specific example of the operation timing improvement step ST03 of the logic block arrangement method according to the first embodiment.

First, as shown in FIG.
At T31, for example, the cell arrangement area is divided into a plurality of slots, and the delay time of each cell is calculated using the power supply voltage map for each slot. However, the arrangement position of each cell uses the current hierarchy, and if it is the first hierarchy, the initial arrangement is used. Further, at this stage, the cells are not wired, and there is no wiring path. Therefore, the wiring of the cells is assumed using a star net model.

FIG. 5A shows a star net model. Assume that cells 21 to 24 are arranged as shown in FIG. Also, the pin p _1o of the output side cell 21,
The pin p _2i of the input side cell 22 and the pin p _{3i of the} input side cell 23
The pin p _4i of the input cell 24 belongs to the net 25. As described above, the star-shaped net model is an RC (resistance / capacity) network model that assumes that the center of gravity 25a of a pin belonging to the net 25 is a branch point of the net 25, and FIG. An RC network model corresponding to the star net model of FIG.

In FIG. 5B, the distance from the center of gravity 25b to the pin n (where n is an integer of 1 to 4) is X.
_Assuming L _xn in the direction and L _yn in the Y direction, the resistance R _n and the capacitance C _n can be expressed by the following equations (4) and (5). Note that n = 1 corresponds to the cell 21, n = 2 corresponds to the cell 22, n = 3 corresponds to the cell 23, and n = 4 corresponds to the cell 24.

[0073] _{R n = r x × L xn} + r y × L yn ... (4) C n = c x × L xn + c y × L yn ... (5) where, r _x, r _y are X and Y represents the sheet resistance of the wiring in the direction, c _x, c _y represents the wiring capacitance per unit area in the X and Y directions, the output resistance of the pin p _1o R _s, pin p _2i, p _3i, p _{Assuming that} the input pin capacitances of _4i are C _2i , C _3i and C _4i , respectively, an RC network as shown in FIG. 5B is formed. Further, the calculation method of the delay calculation may be appropriate, and for example, the Elmore method may be used (“Journal of Applied Physics, 1948, pp. 55-63 (Journal of Applied
Physics, 1984, pp.55-63 ").

Next, a temporary cell placement step ST32 shown in FIG.
, Cells are provisionally arranged using a timing-driven arrangement method. That is, mathematical programming and Gordian
The same pseudo quadratic programming as the method is used. We also introduce the concept of slack for timing driven strategies.

Hereinafter, the basic concept of slack will be described with reference to FIG. FIG. 6A is a slack graph showing a part of a circuit including a logic module M _n (where n = 1 to 9) as a logic block.
In FIG. 6 (a), 31 represents a logical module M _n, undirected represents a connection relation between the logic modules M _n, an integer d _n which is written in the logic module M _n represents a module delay value , W _n written on undirected branches
Represents a wiring delay value.

The signal is transmitted from the primary input P _im to the primary output P _om (where m = 1, 2, 3
And ), And the path constraint delay value here is 25.

Next, an actual path delay (cumulative delay) value in this circuit is obtained. The path delay value is determined by determining the longest delay time among the delay times required to reach an arbitrary vertex. For example, the path delay value to the module M _1, since the time required from the primary input P _i1 to the module M ₁ is zero, taking the sum of the module delay value 3, the delay value until the module M ₁ Is the path delay value (a ₁ ) = 0 + 3 = 3.

Similarly, the delay value from the primary input P _i2 to the module M ₂ is the path delay value (a ₂ )
= 0 + 2 = 2, and the path delay value (a ₃ ) from the primary input _{Pi 3} to the module M ₃ = 0 + 4 = 4.

Next, a path delay value from the primary input P _i1 or the primary input P _i2 to the module M ₄ is obtained. Since 2 paths of up module M ₁ ~ module M ₄ to the modules M ₂ ~ module M ₄ are present, the path delay value to the module M ₁ ~ module M _4, the wiring delay value of 5 in the module M ₄ since the delay value is 2, the path delay value to the module M ₁ ~ module M ₄ is 3 + 5 + 2 = 10.

On the other hand, since the path delay values of the modules M ₂ to M ₄ are 9 and the delay value of the module M ₄ is 2, the path delay values of the modules M ₂ to M ₄ are obtained. Is 2 + 9 + 2 = 13. Accordingly, since the path delay value to the module M ₄ is that the maximum of the delay value that reaches the module M _4, path delay value to the module _{M 4 (a 4) = max} ( module M ₁ ~ module M ₄ , The path delay value from module M ₂ to module M ₄ ) = max (3 + 5 + 2, 2 + 9 + 2) = 13.

[0081] Similarly, the path delay value to the module _{M 5 (a 5) = max} ( path delay value to the module M ₁ ~ module M _5, module M ₂ ~ module path delay value to the M _5, module M ₃ path delay value of up to ~ module _{M 5) = max (3 +} 7 + 3, 2 + 5 + 3, 4 + 10 + 3) = 17 , and the path delay value to the module _{M 6 (a 6) = max} ( path delay from module M _2-module M ₆ value, the module M ₃ ~ path delay value to the module _{M 6) = max (2 +} 9 + 1, 4 + 5 + 1) = 12.

[0082] In addition, the path delay value to the module _{M 7 (a 7) = max} ( path delay value to the module M ₁ ~ module M _7, a path delay value to the modules M ₄ ~ module M _7, the module M ₅ ~ module path delay value to the _{M 7) = max (3 +} 7 + 1, 13 + 11 + 1, 17 + 6 + 1) = 25 , and the path delay value to the module _{M 8 (a 8) = max} ( path delay value to the modules M ₃ ~ module M _8, path delay value to the modules M ₅ ~ module M _8, the path delay value to the modules M ₄ ~ module _{M 8) = max (4 +} 10 + 1, 13 + 11 + 1, 17 + 5 + 1) = 25 , and the path delay value to the module M ₉ (a ₉ ) = Max (path delay value from module M ₄ to module M ₉ , from module M ₅ to module M ₉₎ , The path delay value from module M ₆ to module M ₉ ) = max (13 + 11 + 2, 17 + 8 + 2, 12 + 5 + 2) = 27.

[0083] From the foregoing, since the path constraints delay value is 25, sla in the primary output P _om
ck ( _Pom ) becomes slack ( _Po1 ) = 25-25 = 0 slack ( _Po2 ) = 25-25 = 0 slack ( _Po3 ) = 25-27 = -2, respectively.

As described above, since the slack (P _o3 ) takes the minimum value, the critical path is changed to the module M ₃ → M ₅
→ the M _9. In addition, the slack value is negative,
This means that a timing violation has occurred. To eliminate this timing violation modules M ₃ ~ module M to ₅ wiring, or modules M ₅ ~ module M
It can be seen that any of the wires up to ₉ must be shortened.

Returning to the description of the flow of FIG.

Next, in a timing violation net extraction step ST33 shown in FIG. 4, a net in which a timing violation has occurred with respect to the temporary placement result in the cell temporary placement step ST32 is extracted. The extraction method is as described above, and can be easily and reliably obtained by using a slack graph as shown in FIG.

Next, in the provisional arrangement improvement step ST34,
The number of nets having a timing violation is reduced by moving the cell having the timing violation to shorten the wiring length of the net. For example, in order to improve timing in the module M ₃ → module M ₅ → module M ₉ which is a critical path shown in FIG.
It is sufficient to reduce the wiring length of at least one of the net including the module M ₃ → the module M ₅ and the net including the module M ₅ → the module M ₉ . For example, among the modules M ₃ and the module M _5, better to reduce the module towards the output drive capability is small is efficient. that is,
This is because if the module has a higher driving capability, the wiring length is not reduced, that is, even if the wiring length is long, the delay time is not increased.

By the way, the Laplace matrix B given by weighting the connection relations of modules (cells) shown in equation (1)
The operation timing of the module can also be improved by appropriately changing.

Further, it is assumed that a plurality of cells are provisionally arranged on the same line as shown in FIG. Among the plurality of cells, the cell 41, the cell 42, and the cell 43 are, for example,
It is assumed that it belongs to the net 45 so as to straddle the cut line 44 for generating a slot. In this case, as shown in FIG.
Cell 43 and cut line 4
4 is replaced with a cell 46 located on the cell 42 side.

As described above, the provisional arrangement improvement step ST34 is
Consideration is also given to preventing a timing violation net from being processed across divided regions such as a plurality of slots. Generally, the pseudo quadratic programming method considers the minimum cut in order to promote the reduction of the wiring length, but it is still strictly insufficient.

Further, timing violation net extraction step S
After repeating the T33 and the provisional placement improvement step ST34 a predetermined number of times or until further improvement is not expected, the process ends.

As described above, according to the present embodiment, since the delay time of a cell or a net is calculated based on the power supply voltage map for each slot, the power supply voltage drop phenomenon due to the power supply wiring resistance is reflected for each slot. A timing driven placement method can be realized. Thus, in the cell arrangement based on timing, the cell arrangement can be performed under conditions closer to the actual LSI chip, and as a result, a timing error can be prevented.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 8 shows a schematic flow of a logical block arranging method according to the third embodiment of the present invention. FIG. 8 is also a specific example of the power consumption reduction step ST04 of the logic block arrangement method according to the first embodiment.

First, as shown in FIG. 8, in a transition probability calculating step ST41, a transition probability of a signal in which a signal potential of a net transitions from high to low or from low to high is calculated for each net of a cell. This is nothing but to seek switching (transition) probability K _p in equation (3). The transition probability K _p may be determined in a suitable manner, for example, “I Triple E Transactions on Computer Aid Design, 1990, pp. 439-45.
0 (Proc. IEEE Transactions on computer Aided Desi
gn, 1990, pp. 439-450) ”.

FIG. 9 is a graph showing the transition probability of a net included in the logic circuit shown in FIG.
1 shows the calculation results. In FIG. 9, FIG.
The description of the same components as those shown in FIG. The transition probability s _j in FIG. 9 is the output pin p _j of the module M _n (where,
j is a positive integer. ) Is the transition probability. here,
The transition probabilities of the primary inputs P _im are all set to 0.5.

Next, a power consumption calculating step ST4 shown in FIG.
In step 2, the power consumption of each module (cell) reflected by the power supply voltage drop is calculated using the power supply voltage map 16. The calculation formula uses equation (3), and the wiring net model is
The star net model shown in FIG. 5 is used. This allows
More accurate calculation of power consumption becomes possible.

Next, in a low drive capacity cell replacement step ST43, a high power consumption cell and a low drive capacity cell are replaced in order to reduce excess power consumption. This has the effect of reducing the second term in equation (3). Specifically, among the cells obtained in the power consumption calculation step ST42, the cells are sorted in descending order of the power consumption value, and cells having a predetermined ratio from cells having a large power consumption and having no timing violation have been generated. And replaces the selected cell with a low-driving-capacity cell in the range registered in the cell library that has a lower driving capability than the selected cell and does not cause a timing violation. in this way,
Since the high power consumption cell is replaced with a low driving capacity cell, that is, a low power consumption cell, the power consumption of the circuit can be reduced.

Here, when a series of processes as shown in the first embodiment are performed hierarchically, the ratio of selecting the high power consumption cells is reduced as the hierarchical division progresses. This is to prevent an increase in the number of nets that cause a timing violation because the operation timing is delayed if the cells are excessively replaced with cells with low driving capability.

As described above, according to this embodiment, since the power consumption of each cell is calculated based on the power supply voltage map for each slot, the power supply voltage drop phenomenon due to the power supply wiring resistance is reflected for each slot. Thus, a module (cell) arranging method with low power consumption can be realized. Thus, in the cell arrangement based on timing, the cell arrangement can be performed under conditions closer to the actual LSI chip, and as a result, a timing error can be prevented.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 10A shows a logical block for explaining a method of creating a delay library according to the fourth embodiment of the present invention. FIG. 10B shows a delay calculation function of a delay library described using ALF (Advanced Library Format) which is a library description language.
4 shows a function program for calculating the delay time of the buffer 51 having the input pin in and the output pin out shown in FIG.

As shown in FIG. 10B, the present delay calculation function program uses the template (TE
In the std_delay_3D section of “MPLATE),“ slewrate ”is used as a delay value table.
(Slope value of input signal waveform) "," capacitanc
e (output load capacitance value) "and" voltage (power supply voltage value) "are defined respectively.

In the vector section in the latter half of the program, the delay value itself is defined in the delay table 53.

The feature of this embodiment is that the voltage definition statement 52 is described, and the delay time of the buffer 51 is expressed by using three parameters of the slope value of the input signal waveform, the output load capacitance value, and the power supply voltage value. Therefore, "table" of the vector section is expressed as a three-dimensional table.

For example, "slewrate tabl"
e ”is 1 and“ capacitance table ”
Is 2 and the "voltage table" is 3, the index # 3 is referenced and a delay value of 0.2 is output.

As described above, according to the present embodiment, a delay library including a desired power supply voltage fluctuation can be created, so that a delay time of a logic block in which a power supply voltage drop phenomenon is considered can be calculated.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.

FIG. 11 shows the basic concept of the delay time calculating method according to the fifth embodiment of the present invention.

[0110] In this embodiment, the delay calculation function for calculating a delay time of the logic blocks, a function represented by parameters and gradient values T _s of the (input signal) waveform and the load capacitance CL.

First, as shown in FIG. 11, predetermined power supply voltage values are different from each other (where n is a positive integer).
It is assumed that a number of delay libraries LIB _{1 to} LIB _n are prepared. Here, the power supply is a delay value to be determined voltage value v _i
(Where, i is i = 1,2, ..., n- 1) a, the power supply voltage v _i is, v ₂ <and the relation of v _i <v _3.

Therefore, here, the first power supply voltage value v ₂
It will select the corresponding delay library LIB ₂ and the delay library LIB ₃ corresponding to the second power supply voltage value v ₃ and.

Next, as shown by the first three-dimensional coordinates 61, the first delay time T ₁ determined from the slope value T _s1 of the parameter waveform and the load capacitance CL ₁ using the delay library LIB ₂ is calculated. Ask.

Similarly, as shown in the second three-dimensional coordinates 62, the second delay time T ₂ determined from the slope value T _s1 of the parameter waveform and the load capacitance CL ₁ using the delay library LIB ₃ is calculated. Ask. The delay time T _{i at a} desired power supply voltage value v _i is expressed by the following equation (6).

[0115] _{T i = (T 1 -T 2} ) × (v i -v 2) / (v 3 -v 2) + T 2 ... (6) which is a first power supply voltage v ₂ and the second Power supply voltage value v
Means linear interpolation for ₃ . The reason why linear interpolation is possible is that the delay time is almost proportional to the power supply voltage unless the voltage is reduced.

As described above, according to the present embodiment, even if a delay library expressing a desired power supply voltage fluctuation cannot be prepared, at least the operation of the logic block is performed with a power supply voltage value smaller than the desired power supply voltage value. Is provided, and a second delay library that guarantees the operation of the logic block with a power supply voltage value larger than a desired power supply voltage value is easily and easily obtained by the equation (6). The delay time in the desired power supply voltage operation can be reliably calculated.

[0117]

According to the first logic block arranging method of the present invention, the power supply voltage map representing the distribution of the operating power supply voltage for each logic block is prepared before the logic block is arranged. The delay time calculated for each logic block based on the voltage value shown in (1) reflects the voltage drop. In addition, since the power consumption is calculated for each logical block based on the voltage value represented in the power supply voltage map, the calculated power consumption also reflects the voltage drop caused by the wiring position of the power supply wiring in the placement area. . Thereby, in the cell arrangement by timing driven,
Since the cells can be arranged under conditions closer to the actual semiconductor LSI chip, timing errors can be prevented as a result. For this reason, rework of the design can be eliminated, and man-hours can be reduced.

According to the second logic block arranging method of the present invention, the delay time is calculated based on the power supply voltage value depending on the position of each logic block. Indicates the voltage drop. Further, for a logical block having a net exceeding the delay constraint value, the logical block is rearranged so as to be within the delay constraint value, so that an operation timing violation can be eliminated. As a result, in the cell arrangement based on timing, the cell arrangement can be performed under conditions closer to the actual semiconductor LSI chip. As a result, timing errors can be prevented.

According to the third logic block arranging method of the present invention, the power consumption is calculated based on the power supply voltage value depending on the position where each logic block is arranged. The voltage drop caused by the wiring position of the power supply wiring in the arrangement area is reflected. Furthermore, after extracting the nets that do not exceed the delay constraint value, the calculated power consumption values are arranged in descending order, and the logical blocks corresponding to the power consumption values are selected from the side with the higher power consumption value of the extracted nets, Since the selected logic block is replaced with a logic block having a lower driving capability than the logic block within a range not exceeding the delay constraint value, power consumption can be reduced without causing an operation timing violation. In addition, in the cell arrangement based on timing, the cell arrangement can be performed under conditions closer to the actual semiconductor LSI chip.

According to the method for creating a delay library of the present invention, a delay calculation function including a slope value of an input signal waveform, an output load capacitance value, and a power supply voltage value is generated. If the power supply voltage drop amount is included in the delay calculation function, the delay time output from the delay calculation function reflects the power supply voltage drop and is output. Thus, when the present delay library is used, in the cell arrangement based on timing, the cell arrangement can be performed under conditions closer to the actual semiconductor LSI chip.

According to the delay time calculating method of the present invention, even when the library corresponding to the operation power supply voltage value for guaranteeing the operation of the logic block does not exist, the power supply voltage value is smaller than the desired power supply voltage value. A first library;
If a second library having a power supply voltage value larger than the desired power supply voltage value is prepared, the delay time of the logic block at the desired operation power supply voltage can be obtained.

[Brief description of the drawings]

FIG. 1 is a flowchart of a logical block arrangement method according to a first embodiment of the present invention.

FIG. 2A is a plan view showing a standard cell arrangement area for explaining a logic block arrangement method according to the first embodiment of the present invention. (B) is an equivalent circuit diagram of (a).

FIG. 3A is a plan view showing a standard cell arrangement area for describing a logic block arrangement method according to the first embodiment of the present invention. (B) is a power supply voltage map diagram in the logic block arrangement method according to the first embodiment of the present invention.

FIG. 4 is a flowchart of a logical block arrangement method according to a second embodiment of the present invention.

FIG. 5A is a circuit diagram showing a star net model for explaining a logical block arrangement method according to a second embodiment of the present invention. (B) is an RC network model diagram of (a).

FIGS. 6A and 6B are circuit diagrams for explaining slack in the logical block arrangement method according to the second embodiment of the present invention.

FIGS. 7A and 7B are cell layout diagrams showing a logical block layout method according to a second embodiment of the present invention.

FIG. 8 is a flowchart of a logical block arrangement method according to a third embodiment of the present invention.

FIG. 9 is a circuit diagram for explaining a transition probability of a net in a logical block arrangement method according to a second embodiment of the present invention.

FIG. 10A is a circuit diagram illustrating a buffer for explaining a method of creating a delay library according to a fourth embodiment of the present invention. (B) is a program diagram showing a delay calculation function used for the buffer delay library shown in (a).

FIG. 11 is a conceptual diagram illustrating a delay time calculation method according to a fifth embodiment of the present invention.

FIG. 12 is a plan view showing how a plurality of cells are arranged in an arrangement area.

[Explanation of symbols]

 1 Schematic arrangement ST01 Power supply voltage map creation step ST02 Initial arrangement determination step ST03 Operation timing improvement step ST04 Power consumption reduction step ST05 Division determination step ST06 Cell group division step (divided block group generation step) ST07 Detailed arrangement step ST31 Delay calculation step ST32 cell Temporary Placement Step ST33 Timing Violation Net Extraction Step ST34 Temporary Placement Improvement Step ST41 Transition Probability Calculation Step ST42 Power Consumption Calculation Step ST43 Low Drivability Cell Exchange Step 11 Block 12 Cell Row 13 Power Line 14 Ground Line 15 Slot 16 Power Supply Voltage Map 21 Cell 22 cell 23 cell 24 cell 25 net 25a center of gravity position 25b center of gravity position 31 logic module 41 cell 42 cell 43 cell 44 cut line 45 net 46 cell 51 buffer 2 Voltage definition statement 53 delay table 61 first three-dimensional coordinates 62 second three-dimensional coordinate

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 15/60 658A 668K 668Q H01L 21/82 C 1006 Matsushita Electric Industrial Co., Ltd. (72) Inventor Masaaki Hirata 1006 Oji Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (7)

[Claims] 1. A logic block arranging method for arranging a plurality of logic blocks including functional blocks or logic cells constituting a semiconductor integrated circuit in an arranging area by using a timing-driven arranging method with an operating frequency as a constraint. A power supply voltage map creating step of creating a power supply voltage map representing a distribution of operation power supply voltages for each of the logic blocks in the placement area due to a wiring position of a power supply wiring; and determining an initial placement of the plurality of logic blocks. An initial arrangement determination step, calculating a delay time for each of the plurality of logic blocks based on the voltage value of the power supply voltage map, and rearranging the plurality of logic blocks so that the calculated delay time is reduced. An operation timing improvement step of improving each operation timing of the plurality of logic blocks; and the power supply voltage map. The power consumption is calculated for each of the plurality of logic blocks based on the voltage value, and the driving capability on the output side of the logic block is reduced so that the calculated power consumption value is reduced, so that each power consumption of the plurality of logic blocks is reduced. A power consumption reduction step of reducing power; a divided block group generation step of dividing the rearranged plurality of logical blocks so as to include a plurality of logical blocks to generate a plurality of divided block groups; For each of the plurality of divided block groups, a repetition step of sequentially repeating the operation timing improvement step, the power consumption reduction step and the divided block group generation step, and the operation timing of the rearranged plurality of logical blocks so that they do not overlap each other. And a detailed arranging step of rearranging the logical block so as to satisfy the condition. 2. The operation timing improvement step includes: for each of the plurality of logic blocks, a delay time calculation step of calculating a delay time based on a power supply voltage value depending on a position where each of the plurality of logic blocks is arranged; A tentative placement step of tentatively arranging the plurality of logic blocks based on the calculated delay time, and a plurality of nets comprising a set of input / output terminals connected to the same potential in the plurality of logic blocks based on the calculated delay time. A delay value excess net extracting step of extracting a net exceeding a delay constraint value regulated by the constraint condition, and a logic block having a net exceeding the delay constraint value among the plurality of logic blocks. 2. The method according to claim 1, further comprising the step of rearranging a logical block so as to be within the delay constraint value. 3. A transition probability calculation step of calculating, for each of the plurality of logic blocks, a transition probability of a potential of an output pin of each logic block transitioning from high to low or from low to high. A power consumption calculation step of calculating power consumption based on a power supply voltage value depending on a position where each of the plurality of logic blocks is arranged; and an input / output terminal connected to an equipotential in the plurality of logic blocks. After extracting a net that does not exceed the delay constraint value regulated by the constraint condition from among a plurality of nets consisting of a set of power consumption values, the calculated power consumption values are arranged in descending order, and the power consumption values are arranged in descending order of the arranged power consumption values. Selecting a logic block corresponding to each power value, and selecting the selected logic block with a logic block having a lower driving capability than the logic block and the delay constraint. 2. A logical block arranging method according to claim 1, further comprising a logical block exchanging step of exchanging the logical block so as not to exceed the value. 4. A logic block arranging method for arranging a plurality of function blocks or a plurality of logic blocks composed of logic cells constituting a semiconductor integrated circuit by using a timing-driven arranging method with an operating frequency as a constraint. An initial arrangement determining step of determining an initial arrangement of the logical blocks, and a delay time calculating step of calculating a delay time based on a power supply voltage value depending on a position where each of the plurality of logical blocks is arranged. A tentative placement step of tentatively arranging the plurality of logic blocks based on the calculated delay time; and a plurality of sets of input / output terminals connected to equipotentials in the plurality of logic blocks based on the calculated delay time. A delay value excess net extraction step of extracting a net exceeding a delay constraint value regulated by the constraint condition out of the nets; Out of the logical blocks having a net exceeding the delay constraint value, the logic block further comprises a rearrangement step of rearranging the logical block so as to be within the delay constraint value. Block placement method. 5. A logic block arranging method for arranging a plurality of functional blocks or a plurality of logic blocks including logic cells constituting a semiconductor integrated circuit by using a timing-driven arranging method using an operating frequency as a constraint. An initial arrangement determining step of determining an initial arrangement of the logical blocks, and a transition probability of calculating, for each of the plurality of logical blocks, a transition probability that a potential of an output pin of each logical block transitions from high to low or from low to high. A calculating step; a power consumption calculating step of calculating, for each of the plurality of logic blocks, a power consumption based on a power supply voltage value dependent on a position where each of the plurality of logic blocks is arranged; From a plurality of nets consisting of a set of input / output terminals, extract nets that do not exceed the delay constraint value regulated by the constraint conditions After that, the calculated power consumption values are arranged in descending order, and the logical blocks corresponding to the power consumption values are selected in descending order of the arranged power consumption values, and the selected logical block has a higher driving capability than the logical block. A method of arranging logical blocks, comprising: a logical block exchanging step of exchanging a small logical block so as not to exceed the delay constraint value. 6. A delay library for calculating a delay time for each of a plurality of logic blocks in a timing design of a semiconductor integrated circuit constituted by a plurality of logic blocks including function blocks or logic cells, comprising: A delay calculation function comprising a delay calculation function that includes a slope value, an output load capacitance value, and a power supply voltage value as input values. 7. A delay time calculation method for calculating a delay time for each of a plurality of logic blocks in a timing design of a semiconductor integrated circuit constituted by a plurality of logic blocks including functional blocks or logic cells, wherein When using an unregistered logical block whose operating power supply voltage value that guarantees the operation of the logical block is not registered in the library, a first power supply voltage larger than the operating power supply voltage value of the unregistered logical block A library preparing step of preparing a first library that guarantees operation with a value and a second library that guarantees operation with a second power supply voltage value smaller than the operation power supply voltage value of the unregistered logical block; Using a first library to determine a first delay time of the unregistered logical block, and using the second library A delay time calculating step of calculating a second delay time of the unregistered logic block and calculating a delay time at an operating power supply voltage of the unregistered logic block from the first delay time and the second delay time. A delay time calculation method, characterized in that: