JP4558612B2 - Layout design method for semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a layout design method for a semiconductor integrated circuit that performs cell placement and inter-cell wiring.

  Currently, a chip (LSI, large scale integration) development sequence starts with, for example, market research, and designs specifications based on market requirements derived from this market research. From this specification design, the entire chip is considered as one system, and the system design is designed to design the operation and hardware configuration of this chip. From the RTL (register transfer level) description for realizing the designed system, functional design and logic design (circuit design) for designing a detailed gate level circuit are performed, and layout design based on the circuit design is performed. Thereafter, a mask is manufactured, and a chip is manufactured using the mask.

  In layout design in which cell placement and inter-cell wiring are performed after circuit design, basic logic cells such as NAND and OR, and composite cells combining these basic logic cells are arranged in an array in a layout area, and predetermined by circuit design. The terminals of each cell are wired according to the circuit connection. In this layout design, since there is no information on the power supply voltage drop distribution before the layout design in which the cell arrangement and the wiring between cells are not performed, it is assumed that the maximum power supply voltage drop amount is uniformly distributed over the entire layout region. The layout is designed based on the assumed maximum power supply voltage drop. Information on the power supply voltage drop distribution is calculated based on the actual cell arrangement and inter-cell wiring after cell arrangement and inter-cell wiring.

A technique has been proposed in which a map that is a power supply voltage drop distribution is created before arranging logic blocks such as standard cells, and logic blocks are arranged based on the map (see, for example, Patent Document 1). In this proposal, there is no accurate power supply voltage drop distribution information before cell placement and inter-cell wiring.
JP 2000-99554 A

  However, in the power supply voltage drop distribution calculated based on the actual cell arrangement and inter-cell wiring, the power supply voltage drop amount of the cell placed near the power I / O (Input / Output) cell that supplies power is small. The power supply voltage drop amount of the cells arranged far away is large. Further, the power supply voltage drop amount of cells not densely arranged is small, and the power supply voltage drop amount of cells densely arranged is large. On the other hand, since it is assumed that the maximum power supply voltage drop amount is uniformly distributed over the entire layout area before the layout design, the following problems occur.

  For example, at the edge of the chip where the power I / O cell is close, although the power supply voltage drop amount is small, the power supply voltage is excessively increased based on the assumed maximum power supply voltage drop amount instead of the actual power supply voltage drop distribution. Cell placement and inter-cell wiring are performed by estimating the delay amount of the cell more than necessary as it descends. Therefore, at the edge of the chip, an excessively high speed cell is used to satisfy the timing constraint. Since the high speed cell consumes a large amount of power, the power consumption of the chip is larger than necessary.

  SUMMARY An advantage of some aspects of the invention is that it provides a layout design method for a semiconductor integrated circuit in which power consumption of a chip is small.

In the present invention, in order to solve the above problem, as illustrated in FIG. 1, in a layout design method for a semiconductor integrated circuit in which cell placement and inter-cell wiring are performed, the entire layout area is subjected to a computer before layout design. largest assuming the power supply voltage drop amount assuming step S1 and the power supply voltage drop amount is uniformly distributed, name, terminal shape, size, logical, library plural chromatic cell data composed of delay and power consumption Te a plurality of, that is the same cell name among the plurality of library library depends delay and power consumption, respectively, and a storage for storing terminal shape, the size and logic libraries are identical to the memory device Follow the steps and the library with the performance corresponding to the maximum power supply voltage drop in the library group. Placement and routing step S2 for performing cell placement and inter-cell wiring; and power supply voltage drop distribution calculating step S3 for calculating a power supply voltage drop distribution in the layout region based on cell placement and inter-cell wiring after cell placement and inter-cell wiring; In accordance with the power supply voltage drop distribution, the layout area dividing step S4 for dividing the layout area for each power supply voltage drop amount, and the cells arranged in each area divided by the layout area dividing step S4, There is provided a layout design method for a semiconductor integrated circuit, characterized in that a library replacement step S5 for performing replacement with a library cell having a performance corresponding to a power supply voltage drop amount is executed .

According to such a layout design method for a semiconductor integrated circuit, the power supply voltage drop amount assumption step S1 assumes that the maximum power supply voltage drop amount is uniformly distributed over the entire layout region before the layout design. The storage step, name, terminal shape, size, logical, a plurality of libraries of more chromatic cell data composed of delay and power consumption, the name the same cell between libraries of the plurality of libraries, the delay amount and varies the power consumption respectively, and terminal shape, libraries 10 size and logic are the same are stored in the storage device. In the placement and routing step S2, cell placement and inter-cell routing are performed on the layout region in accordance with a library with performance corresponding to the maximum power supply voltage drop in the library group 10. In the power supply voltage drop distribution calculation step S3, the power supply voltage drop distribution in the layout area is calculated based on the cell arrangement and the inter-cell wiring after the cell arrangement and the inter-cell wiring. In the layout area dividing step S4, the layout area is divided for each power supply voltage drop amount according to the power supply voltage drop distribution. In the library replacement step S5, the cells arranged in the respective regions divided in the layout region dividing step S4 are replaced with the library cells having the performance corresponding to the power supply voltage drop amount of each region in the library group 10, respectively.

  In the present invention, the library used in each area having the performance corresponding to the maximum power supply voltage drop amount is replaced with the library having the performance corresponding to the power supply voltage drop amount in each area in the library group. The library with the performance corresponding to the maximum power supply voltage drop amount is not used, and the library with the performance corresponding to the power supply voltage drop amount smaller than the maximum power supply voltage drop amount in each predetermined region is optimal. Is used. Therefore, since the power consumption of the library is smaller as the library cell has a performance corresponding to a small amount of power supply voltage drop, the power consumption of the chip is smaller.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking as an example a general chip layout design.
First, a layout design flowchart will be described. FIG. 1 is a flowchart of layout design.

  The library of the library group 10 is used in the layout design. This library has a plurality of cell data composed of names, terminal shapes, sizes, logics, delay amounts, and power consumption amounts. This cell data is data of a gate array cell or a standard cell. The library has a performance corresponding to a predetermined power supply voltage drop amount in the layout area. The library group 10 includes a plurality of such libraries. For example, when the power supply voltage drop amount is evaluated in 10 stages, the library group 10 includes 10 libraries. In the library group 10, cells having the same name between libraries have the same terminal shape, size, and logic. In the library group 10, the library cell having the performance corresponding to the large power supply voltage drop amount needs to satisfy the timing constraint after the delay amount of the cell is estimated later, so that the operation of the cell is a large current. It has become faster by flowing. That is, the power supply voltage drop amount and the cell delay amount have a correlation. Also, the higher the cell speed, the greater the power consumption.

  In the layout design, it is assumed that the maximum power supply voltage drop amount is uniformly distributed over the entire layout area before the layout design in the power supply voltage drop amount assumption step S1. In accordance with the library of performance corresponding to the assumed maximum power supply voltage drop, cell placement and inter-cell wiring are performed in the layout and wiring step S2 so as to satisfy predetermined timing constraints in the layout region. This library is prepared in the library group 10. After the cell arrangement and the inter-cell wiring, in a power supply voltage drop distribution calculating step S3, the power supply voltage drop distribution in the layout region is calculated based on the actual cell arrangement and the inter-cell wiring. According to the power supply voltage drop distribution, the layout area is divided for each power supply voltage drop amount in the layout area dividing step S4. In the library replacement step S5, the library used in each divided area is replaced with a library having a performance corresponding to the power supply voltage drop amount in each area while satisfying predetermined timing constraints. Here, the library used in each of these divided areas, that is, the library before replacement, is a library with performance corresponding to the assumed maximum power supply voltage drop amount, and is replaced with the optimal library for each area. Is done. A predetermined number of libraries suitable for each of these areas are prepared in the library group 10.

  Next, the library of the library group 10 will be described in detail. FIG. 2 is a diagram showing a library group. FIG. 3 is a diagram showing the delay amount of the cell with respect to the power supply voltage drop amount of each library.

  The library has a plurality of cell data including names, terminal shapes, sizes, logics, delay amounts, and power consumption amounts. For example, as illustrated in FIG. 2, each library has cell data of INVD1, INVD2, NANDD1, NANDD2, ORD1, and ORD2. This cell data is data of a gate array cell or a standard cell. There is only one cell in the library, and cells in one library are also present in all other libraries in the library group 10. The library has a performance corresponding to a predetermined power supply voltage drop amount in the layout area. For example, A library 11 has a performance corresponding to a power supply voltage drop 2%, B library 12 has a performance corresponding to a power supply voltage drop 4%, C library 13 has a performance corresponding to a power supply voltage drop 6%, and D The library 14 has a performance corresponding to the power supply voltage drop 8%. That is, the operation of the cell of the A library 11 is low speed, the operation of the cell of the B library 12 is medium speed, the operation of the cell of the C library 13 is high speed, and the operation of the cell of the D library 14 is ultra high speed.

  The library group 10 includes a plurality of such libraries. For example, when the power supply voltage drop amount is evaluated in four stages, the library group 10 includes the A library 11, the B library 12, the C library 13, and the D library 14. In the library group 10, cells having the same name between libraries have the same terminal shape, size, and logic. In the library group 10, the library cell having the performance corresponding to the large power supply voltage drop amount needs to satisfy the timing constraint after the delay amount of the cell is estimated later, so that the operation of the cell is a large current. It has become faster by flowing. That is, the power supply voltage drop amount and the cell delay amount have a correlation. Also, the higher the cell speed, the greater the power consumption.

As illustrated in FIG. 3, the delay amount of the cell with respect to the power supply voltage drop amount of the A library 11, the B library 12, the C library 13, and the D library 14 increases as the library having a high-speed cell increases. However, the amount of delay is unlikely to increase by passing a large current. Here, the delay amount of the cells of the A library 11 when the power supply voltage drop amount is 2% is d {A (2%)}, and the delay amount of the cells of the B library 12 when the power supply voltage drop amount is 4%. d {B (4%)}, the delay amount of the cell of the C library 13 when the power supply voltage drop amount is 6%, and the D library 14 when the power supply voltage drop amount is d {C (6%)} and 8%. If the delay amount of the cell is expressed as d {D (8%)},
d {A (2%)} ≈d {B (4%)} ≈d {C (6%)} ≈d {D (8%)}
It becomes. Note that it is not necessary to completely match the timing constraints such as the setup time and the hold time. Further, the power consumption of the cells of the A library 11 when the power supply voltage drop amount is 2% is P {A (2%)}. The power consumption of the cells of the B library 12 when the power supply voltage drop amount is 2% is P. {B (2%)} The power consumption of the cell of the C library 13 when the power supply voltage drop amount is 2% is P {C (2%)}. The power consumption of the D library 14 when the power supply voltage drop amount is 2% Expressing the power consumption of the cell as P {D (2%)},
P {A (2%)} <P {B (2%)} <P {C (2%)} <P {D (2%)}
It becomes. The same applies to other power supply voltage drop amounts.

Next, the layout area will be described. FIG. 4 is a diagram showing a layout area before placement and routing.
In the layout area before cell arrangement and inter-cell wiring, memories 31 and 32 are arranged in advance as macroblocks. In addition, power supply wirings 33 and 34 and ground wirings 35 and 36 are wired in advance in a region where cells can be arranged in the layout region. A power I / O cell, a ground I / O cell, and a signal I / O cell may be arranged in advance in the layout area. Further, an analog circuit block or the like may be arranged as a macro block.

Next, the assumption of the power supply voltage drop will be described.
In the power supply voltage drop amount assumption step S1, it is assumed that the maximum power supply voltage drop amount is uniformly distributed over the entire layout region before layout design. For example, it is assumed that a power supply voltage drop amount of 8% is uniformly distributed over the entire layout area. From this assumption, it is necessary to satisfy the timing constraint after the delay amount of the cell is estimated to be the latest, so that high-speed cells are likely to be used in the entire layout area.

Next, cell arrangement and inter-cell wiring will be described. FIG. 5 is a diagram showing a layout area after placement and routing. In FIG. 5, inter-cell wiring is not shown.
In the placement and routing step S2, cell placement and inter-cell routing are performed on the layout area so as to satisfy predetermined timing constraints in accordance with a library of performance corresponding to the assumed maximum power supply voltage drop. The library selected here is a library that can finally satisfy the timing constraint. For example, the ultra-high speed D library 14 is selected.

  Next, calculation of the power supply voltage drop distribution and division of the layout area for each power supply voltage drop amount will be described. FIG. 6 is a diagram showing a layout area after calculation of the power supply voltage drop distribution. In FIG. 6, cell arrangement and inter-cell wiring are not shown.

  In the power supply voltage drop distribution calculating step S3, the power supply voltage drop distribution in the layout region is calculated based on the cell arrangement and the inter-cell wiring. According to the power supply voltage drop distribution, the layout area is divided for each power supply voltage drop amount in the layout area dividing step S4. In the power supply voltage drop assumption step S1, it is assumed that the power supply voltage drop of 8% is uniformly distributed with respect to the A region 21, the B region 22, the C region 23, and the D region 24. Thus, the power supply voltage drop amount is calculated to be 2% for the A region 21, 4% for the B region 22, 6% for the C region 23, and 8% for the D region 24. That is, no deviation occurs in the D region 24, but a deviation of 6% occurs in the A region 21, 4% in the B region 22, and 2% difference in the C region 23.

  In the A region 21, the B region 22, and the C region 23, the actual power supply voltage drop amount is smaller than the assumed power supply voltage drop amount, and the actual cell delay amount is smaller than the assumed delay amount. Represents. That is, in the A region 21, the B region 22, and the C region 23, an excessively high-speed cell is used in order to satisfy a timing constraint that is more severe than necessary. The higher the power consumption, the higher the power consumption of the chip. These deviations become an excess margin of timing constraints.

  Next, library replacement will be described. FIG. 7 is a diagram showing a layout area after library replacement. FIG. 8 is a diagram showing a part of the A area before library replacement. FIG. 9 is a diagram showing a part of the A area after library replacement. In FIG. 7, cell arrangement and inter-cell wiring are not shown.

  In the library replacement step S5, the library used in each of the divided areas is replaced with a library having a performance corresponding to the amount of power supply voltage drop in each area while satisfying a predetermined timing constraint. Here, the D library 14 used in the A area 21 is replaced with the A library 11 optimal for the A area 21. The D library 14 used in the B area 22 is replaced with the B library 12 optimum for the B area 22. The D library 14 used in the C region 23 is replaced with the C library 13 that is optimal for the C region 23. That is, in the A region 21, the B region 22, and the C region 23, an excessively fast cell is replaced with a slow cell in accordance with the actual power supply voltage drop amount, and an excessive margin of timing constraints is deleted. Even if replacement is performed, since the terminal shape and size of each cell are the same, the cell arrangement and inter-cell wiring do not change.

  Before the library replacement in this library replacement step S5, for example, in the A region 21 with a power supply voltage drop of 2%, the D library 14 having a performance corresponding to the power supply voltage drop of 8% as illustrated in FIG. The cells 14a are arranged satisfying the timing constraint. Since the D library 14 having the performance corresponding to the power supply voltage drop amount of 8% is used for the A region 21 having the power supply voltage drop amount of 2%, the timing constraint is satisfied with an excess margin. After the replacement of the library, as illustrated in FIG. 9, the cell 11a of the A library 11 having the performance corresponding to the power supply voltage drop amount of 2% is arranged. Since the A library 11 having the performance corresponding to the power supply voltage drop amount of 2% is used for the A region 21 having the power supply voltage drop amount of 2%, the timing constraint is satisfied with the excess margin removed.

  In this way, the library used in each area with the performance corresponding to the maximum power supply voltage drop is replaced with the library with the performance corresponding to the power supply voltage drop in each area in the library group. Overall, the performance library corresponding to the maximum power supply voltage drop amount is not used, and the performance corresponding to the power supply voltage drop amount smaller than the maximum power supply voltage drop amount in each predetermined region is optimal for each region. A library is used. Therefore, since the power consumption of the library is smaller as the library cell has a performance corresponding to a small amount of power supply voltage drop, the power consumption of the chip is smaller. For example, the 1st to Lth cells exist in the A area 21, the 1st to Mth cells exist in the B area 22, and the 1st to Nth cells exist in the C area 23. 11 P (Ai), the power consumption of a predetermined cell of the B library 12 is P (Bi), the power consumption of a predetermined cell of the C library 13 is P (Ci), Suppose that the power consumption of a given cell is P (Di) and the reduced power consumption is Pd.

Can be expressed as
Further, since the excess margin of the timing constraint is simply deleted in the layout area that satisfies the timing constraint, the library can be replaced while the timing constraint is satisfied. Therefore, after the replacement of the library, it is not necessary to perform cell placement and inter-cell wiring again in order to satisfy the timing constraint, so that the layout design period can be shortened.

  In addition, since the power consumption of the chip can be reduced based on the power supply voltage drop distribution in the layout area calculated based on the actual cell placement and inter-cell wiring, the power supply voltage drop distribution before cell placement and inter-cell wiring is inaccurate. No longer exists.

  In the case of the hierarchical layout design, the layout design of the lower layer block is performed, the layout design of the upper layer block is performed, the cell arrangement and inter-cell wiring of the entire chip are performed, and the power supply voltage drop distribution of the entire chip is calculated. Calculate and replace the library according to the power supply voltage drop distribution.

The number of libraries in the library group 10 can be freely set, and the power consumption of the chip can be reduced more accurately as the number of libraries increases.
The number of cells in the library can be freely set, and the layout design can be more freely performed as the number of cells increases.

(Supplementary Note 1) In a layout design method of a semiconductor integrated circuit that performs cell placement and inter-cell wiring,
A power supply voltage drop amount assumption step that assumes that the maximum power supply voltage drop amount is uniformly distributed over the entire layout area before layout design;
A storage step of storing a plurality of cell data composed of a name, a terminal shape, a size, a logic, a delay amount, and a power consumption amount, and storing a library group in which only the delay amount and the power consumption amount are different from each other in a storage device;
A placement and routing step for performing cell placement and inter-cell routing for the layout region according to a library of performance corresponding to the maximum power supply voltage drop in the library group;
A power supply voltage drop distribution calculating step for calculating a power supply voltage drop distribution in the layout region based on the cell placement and the inter-cell wiring after the cell placement and the inter-cell wiring;
A layout area dividing step for dividing the layout area for each power supply voltage drop amount according to the power supply voltage drop distribution;
A library replacement step of replacing the library used in each region divided by the layout region dividing step with a library having a performance corresponding to the amount of power supply voltage drop in each region in the library group;
A layout design method for a semiconductor integrated circuit, comprising:

  (Supplementary Note 2) The placement and routing step performs the cell placement and the inter-cell routing so as to satisfy a predetermined timing constraint, and the library replacement step performs replacement while satisfying the predetermined timing constraint. 2. A layout design method for a semiconductor integrated circuit according to appendix 1, which is characterized by the following.

(Supplementary note 3) The layout design method for a semiconductor integrated circuit according to supplementary note 1, wherein the cell is a gate array cell.
(Supplementary note 4) The layout design method for a semiconductor integrated circuit according to supplementary note 1, wherein the cell is a standard cell.

  (Additional remark 5) In the library group, the cell of the library having the performance corresponding to a large power supply voltage drop amount has a higher operation speed and higher power consumption. Layout design method.

(Supplementary note 6) The layout design method for a semiconductor integrated circuit according to supplementary note 1, wherein the layout region is designed at a time.
(Supplementary note 7) The layout of the semiconductor integrated circuit according to supplementary note 1, wherein the layout area is designed by designing a layout of a lower-level block and designing a layout of a higher-level block. Design method.

(Supplementary Note 8) In a semiconductor integrated circuit layout design program for performing cell placement and inter-cell wiring,
On the computer,
A power supply voltage drop amount assumption step that assumes that the maximum power supply voltage drop amount is uniformly distributed over the entire layout area before layout design;
A storage step of storing a plurality of cell data composed of a name, a terminal shape, a size, a logic, a delay amount, and a power consumption amount, and storing a library group in which only the delay amount and the power consumption amount are different from each other in a storage device;
A placement and routing step for performing cell placement and inter-cell routing for the layout region according to a library of performance corresponding to the maximum power supply voltage drop in the library group;
A power supply voltage drop distribution calculating step for calculating a power supply voltage drop distribution in the layout region based on the cell placement and the inter-cell wiring after the cell placement and the inter-cell wiring;
A layout area dividing step for dividing the layout area for each power supply voltage drop amount according to the power supply voltage drop distribution;
A library replacement step of replacing the library used in each region divided by the layout region dividing step with a library having a performance corresponding to the amount of power supply voltage drop in each region in the library group;
A layout design program for a semiconductor integrated circuit, characterized in that the process is executed.

(Supplementary Note 9) In a library group including a plurality of libraries having a plurality of cell data,
A plurality of cell data having a plurality of cell data composed of name, terminal shape, size, logic, delay amount, and power consumption, and having a performance corresponding to a predetermined power supply voltage drop amount, and cells having the same name among the libraries The library group is characterized in that the terminal shape, the size, and the logic are the same, and the operation of the cell is faster and the power consumption is larger as the library cell has a performance corresponding to a large power supply voltage drop.

It is a flowchart of a layout design. It is a figure which shows a library group. It is a figure which shows the delay amount of the cell with respect to the power supply voltage drop amount of each library. It is a figure which shows the layout area | region before arrangement | positioning wiring. It is a figure which shows the layout area | region after arrangement | positioning wiring. It is a figure which shows the layout area | region after power supply voltage drop distribution calculation. It is a figure which shows the layout area | region after library replacement. It is a figure which shows a part of A area | region before library replacement. It is a figure which shows a part of A area | region after library replacement.

Explanation of symbols

10 library group S1 power supply voltage drop amount assumption step S2 placement and routing step S3 power supply voltage drop distribution calculation step S4 layout area division step S5 library replacement step

Claims (5)

In a method of designing a layout of a semiconductor integrated circuit that performs cell placement and inter-cell wiring,
On the computer,
A power supply voltage drop amount assumption step that assumes that the maximum power supply voltage drop amount is uniformly distributed over the entire layout area before layout design;
Name, terminal shape, size, logical, a plurality of libraries of more chromatic cell data composed of delay and power consumption, the name the same cell between libraries of the plurality of libraries, the delay and Unlike the power consumption, respectively, and a storage step of storing the terminal shape, the size and libraries the logic is the same in the storage device,
A placement and routing step for performing cell placement and inter-cell routing for the layout region according to a library of performance corresponding to the maximum power supply voltage drop in the library group;
A power supply voltage drop distribution calculating step for calculating a power supply voltage drop distribution in the layout region based on the cell placement and the inter-cell wiring after the cell placement and the inter-cell wiring;
A layout area dividing step for dividing the layout area for each power supply voltage drop amount according to the power supply voltage drop distribution;
A library replacement step of replacing the cells arranged in each region divided by the layout region dividing step with cells of a library having a performance corresponding to a power supply voltage drop amount of each region in the library group;
A layout design method for a semiconductor integrated circuit, comprising:   The placement and routing step performs the cell placement and inter-cell routing so as to satisfy a predetermined timing constraint, and the library replacement step performs replacement while satisfying the predetermined timing constraint. A layout design method for a semiconductor integrated circuit according to Item 1. 2. The layout design method for a semiconductor integrated circuit according to claim 1, wherein the cells of each library in the library group are gate array cells. 2. The layout design method for a semiconductor integrated circuit according to claim 1, wherein the cells of each library in the library group are standard cells. In the above libraries, the more cells in the library of performance ready for a large power supply voltage drop amount, operating the layout design method of a semiconductor integrated circuit according to claim 1, wherein the power consumption a high-speed large.

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