JP2004096103A - The design method and design equipment of semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of designing an integrated circuit device capable of considering the effect when the voltage drop changes and capable of performing a proper design even though a deviation occurs. <P>SOLUTION: In the method of designing the integrated circuit device where inter-terminal of transistors constituted on the silicon wafer are connected with metal wiring, information on the transistors are inputted, and the method has a first process where a schematic layout is prepared so as to minimize the wiring distances and wiring capacitance of the inter-transistor connections, a second process where an information on the voltage drop value is prepared based on the schematic layout of the transistors, and a third process where the transistors are arranged based on the information on the voltage drop value. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a method and an apparatus for designing a semiconductor integrated circuit device. In particular, the present invention relates to a method and an apparatus for designing a semiconductor integrated circuit device in which a transistor or a cell that is a transistor aggregate having a logical function is arranged in consideration of a voltage drop value.

In recent years, the miniaturization of semiconductor manufacturing processes has been rapidly progressing, and the scale of transistors included in the same chip size has also increased dramatically. At the same time, the power consumption of each semiconductor chip has been rapidly increasing, and the current situation is to reduce the increase in power consumption by taking measures such as lowering the supply voltage (operating voltage). is there.

(4) By reducing the supply voltage in order to suppress the increase in power consumption, the current value increases. The increase in the current value may adversely affect the circuit operation. In order to deal with such a problem caused by the voltage drop in the semiconductor chip, for example, Japanese Patent Application Laid-Open No. H11-44979 discloses a method for reducing the voltage drop. In Japanese Patent Laid-Open Publication No. H11-264, a method for accurately analyzing such a voltage drop value is disclosed. On the other hand, Japanese Patent Application Laid-Open No. 2000-163460 discloses a method for accurately analyzing a voltage drop value and reducing the voltage drop itself.

In the voltage drop analysis method and the reduction method described above, the power consumption and the voltage drop value of the transistors or cells that have been almost or completely arranged are analyzed. Then, by verifying the timing using the transistor delay according to the voltage drop value, it is necessary to suppress the occurrence of operation failure after manufacturing and to appropriately reinforce the power supply wiring to reduce the voltage drop rate. become.
Japanese Patent Application Laid-Open No. H11-45977 JP 2000-194732 A JP 2000-163460 A

However, generation of a certain voltage drop cannot be avoided, and the generated voltage drop is usually designed as a design margin of the entire circuit. That is, when it is estimated that a voltage drop of 10% occurs, a circuit design faster than the normal specification is performed by 10%, and even when a voltage drop occurs, the operation speed according to the specification is reduced. I can guarantee it.

Since such a design method is employed, power supply reinforcement similar to cells belonging to a critical path is performed for cells belonging to a path having relatively large timing based on timing verification on a circuit. Thus, there is a problem that an unnecessary chip area is increased.

Also, when performing logic synthesis, processing such as logic synthesis is usually performed on the premise of an ideal clock. Therefore, due to the effect of voltage drop, the path from the clock source to each flip-flop is an equal-length equal-capacity wiring. However, the delay variation occurs, and the clock delay variation (skew) margin included in the synthesis is largely determined by considering the voltage drop variation in addition to the functional wiring length and wiring capacitance control variation of the placement and routing tool. It is necessary to design a good margin.

Even when the timing margin is reduced and the timing optimization based on the actual clock delay information is performed after the wiring is completed, the voltage drop value is different from that before the timing optimization is performed due to a change in the circuit configuration. Therefore, there is a problem that the timing optimization process may not converge.

Further, in a test circuit (scan circuit) for detecting a failure portion in a circuit, a scan chain is normally generated on the assumption of an ideal clock, so that a voltage drop can be maximized during a scan operation. There is also a problem that a failure detection test cannot be performed due to clock skew due to the influence of the voltage drop.

An object of the present invention is to provide a method and an apparatus for designing a semiconductor integrated circuit device, which can take into account the effects of different voltage drop values and can perform an appropriate design even when variations occur. Aim.

A method for designing a semiconductor integrated circuit device according to the present invention is a method for designing a semiconductor integrated circuit device in which terminals of transistors formed on a silicon wafer are connected by metal wiring, wherein information on the transistors is input, and A first step of performing a general arrangement so as to minimize a wiring distance and a wiring capacitance of a connection between transistors; a second step of creating information on a voltage drop value based on the general arrangement of the transistors; and And a third step of arranging the transistors based on the information on the values.

A device for designing a semiconductor integrated circuit device according to the present invention is a device for designing a semiconductor integrated circuit device in which terminals of transistors formed on a silicon wafer are connected by metal wiring. A schematic arrangement means for performing an approximate arrangement so as to minimize a wiring distance and a wiring capacitance of a connection between transistors; a voltage drop value information creating means for creating information on a voltage drop value based on the schematic arrangement of the transistors; And a rearrangement means for arranging the transistors based on the information on the drop value.

According to the present invention, it is possible to provide a design method and a design apparatus for a semiconductor integrated circuit device, which can take into account the effects of different voltage drop values and can perform appropriate design even when there is variation. be able to.

The method of designing a semiconductor integrated circuit device according to the present embodiment includes a third step of arranging transistors based on information on a voltage drop value. With such a configuration, it is possible to perform cell placement in consideration of an increase in cell delay due to a voltage drop, and to perform a delay calculation in consideration of a voltage drop value after a cell placement as in the related art and perform a timing verification. Circuit optimization processing for timing correction can be performed at the processing stage, and the design period can be shortened.

In this embodiment, the second step is a step of performing a rough wiring for connecting the generally arranged transistors, and a wiring capacity is estimated based on the rough wiring, and a load capacity of each of the transistors is calculated. Calculating the power consumption, thereby determining the resistance value of the wired power / ground wiring, and, based on the calculated power consumption, applying a current source to the resistance value of the wired power / ground wiring. It is preferable to include a step of calculating a voltage drop value from a power supply source when the power supply is connected, and a step of obtaining a voltage drop distribution in the semiconductor integrated circuit device based on the calculated voltage drop value. This is because, by obtaining the voltage drop distribution in the semiconductor integrated circuit device, it is possible to more accurately and appropriately arrange the transistors.

{Preferably, the third step includes a step of arranging an appropriate transistor at a place where an arbitrary voltage drop value is assumed based on the voltage drop distribution.

In the third step, the entire path between flip-flops in the semiconductor integrated circuit device or the pair of flip-flops on the source side and the sink side is arranged in an area having a small voltage drop value difference based on the information on the voltage drop value. It is preferable to include a step of performing By setting each path to a constant voltage drop value, the delay calculation of the path can be calculated with a constant voltage drop value, and even when performing static timing analysis, the delay calculation considering the voltage drop value at high speed can be performed. Because you can.

Performing a general wiring for connecting the generally arranged transistors, calculating a path delay between flip-flops based on the general layout and the general wiring of the transistors, and calculating the calculated path delay and constraint delay time And determining a margin of a path delay in a path between the flip-flops, wherein the third step includes setting the transistor included in the path having a large path delay margin to a voltage drop value. It is preferable to include a step of preferentially arranging in a large area. Increase in cell delay due to voltage drop can be absorbed in the margin of path timing, which makes it possible to reinforce the power supply to compensate for the increase in critical path delay and reduce the ratio of timing margin, thereby reducing chip area and circuit. This is because the design period can be shortened by reducing the number of repetitions of the timing optimization process to satisfy the specification operation speed.

The method may further include a step of incorporating a test circuit for detecting a failure location of the transistor, and the third step may include a step of changing a connection order of the test circuit based on information on the voltage drop value. preferable. This is because the clock skew and the data arrival time of each flip-flop in consideration of the voltage drop can be calculated, so that the restriction on the hold time due to the influence of the voltage drop after the scan chain connection can be avoided beforehand. Therefore, even when the clock tree path to the scan flip-flop is different, it is possible to prevent the problem that the clock skew due to the voltage drop becomes large and the hold time error occurs, and the failure cannot be detected. Since a normally operable LSI which becomes a problem only by processing can be shipped as a non-defective product, the yield can be improved.

In the second step, among the supply signals to the flip-flop circuit, further includes a step of dividing a signal of multiple fan-out on a tree, in the third step, based on the information about the voltage drop value, Calculating the driving capability of the transistor belonging to the tree as a delay time, and causing the delay time from the signal source to the signal receiving end to match the delay time calculated as the driving capability of the transistor belonging to the tree. Calculating a resistance value and a capacitance value, and between the signal source and the transistor belonging to the tree, and the signal source and the signal receiving end so that the calculated resistance value and the calculated capacitance value are obtained. It is preferable to include a step of wiring between them.

By calculating a signal delay time difference in consideration of a voltage drop and performing wiring processing so that the delay time difference does not occur, the delay time difference generated when using the LSI can be reduced to zero, and unexpected operation abnormality may occur. This is because it can be avoided beforehand.

In the semiconductor integrated circuit device designing apparatus according to the present embodiment, there is provided a rearrangement means for arranging transistors based on information on a voltage drop value. With such a configuration, it is possible to perform cell placement in consideration of an increase in cell delay due to a voltage drop, and to perform a delay calculation in consideration of a voltage drop value after a cell placement as in the related art and perform a timing verification. Circuit optimization processing for timing correction can be performed at the processing stage, and the design period can be shortened.

In this embodiment, the voltage drop value information creating means estimates a wiring capacity based on the schematic wiring, and a general wiring means for performing general wiring for connecting the generally arranged transistors, and a load on each of the transistors. Power consumption calculation means for calculating power consumption by calculating a capacity; resistance value extraction means for determining a resistance value of a wired power supply / ground wiring; and a wired power supply based on the calculated power consumption. Voltage drop value calculation means for calculating a voltage drop value from a power supply source when a current source is connected to the resistance value of the ground wiring, and the semiconductor integrated circuit device based on the calculated voltage drop value And a voltage drop distribution generating means for obtaining a voltage drop distribution in the above.

It is preferable that the rearrangement unit arranges the appropriate transistor at a place where an arbitrary voltage drop value is assumed based on the voltage drop distribution.

The rearrangement means arranges an entire path between flip-flops or a pair of source-side and sink-side flip-flops in the semiconductor integrated circuit device in a region having a small voltage drop value difference based on information on the voltage drop value. Is preferred.

The voltage drop value information creating unit compares a path delay between flip-flops based on a schematic arrangement and a schematic wiring of the transistor with a path delay calculating unit, and compares the calculated path delay with a constraint delay time. Path delay margin calculating means for determining a path delay margin in a path between flip-flops, wherein the rearrangement means converts the transistors included in the path having a large path delay margin into a region having a large voltage drop value. It is preferable to arrange them preferentially.

The voltage drop value information creating means further includes a test circuit incorporation means for incorporating a test circuit for detecting a failure location of the transistor, and the rearrangement means includes a test circuit based on the information on the voltage drop value. It is preferable to change the connection order.

The voltage drop value information creating unit divides a multi-fanout signal among the supply signals to the flip-flop circuit into a tree, and the rearrangement unit belongs to the tree based on the information on the voltage drop value. Means for calculating the driving capability of the transistor as a delay time, and a resistance value and a delay value so that the delay time from the signal source to the signal receiving end matches the delay time calculated as the driving capability of the transistor belonging to the tree. Means for calculating a capacitance value, and between the signal source and the transistor belonging to the tree, and between the signal source and the signal receiving end so that the calculated resistance value and the calculated capacitance value are obtained. It is preferable to include means for wiring.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit design device 100 according to the first embodiment. The semiconductor integrated circuit designing apparatus 100 connects terminals of transistors formed on a silicon wafer with metal wiring. In the semiconductor integrated circuit design device 100, a schematic arrangement unit 2 is provided. The schematic arrangement unit 2 receives information on transistors as input and performs general arrangement so as to minimize the wiring distance and wiring capacitance of the connection between transistors. The semiconductor integrated circuit design device 100 includes a voltage drop value information generation unit 1. The voltage drop value information generation unit 1 creates information on a voltage drop value based on the schematic arrangement of the transistors by the schematic arrangement unit 2.

The voltage drop value information generation unit 1 has a schematic wiring unit 4. The general wiring unit 4 performs general wiring for connecting the transistors roughly arranged by the general arrangement unit 2. The voltage drop value information generator 1 includes a power consumption calculator 5. The power consumption calculation unit 5 estimates the wiring capacity based on the schematic wiring by the schematic wiring unit 4 and calculates the power consumption by calculating the load capacitance of each transistor. The voltage drop value information generator 1 has a resistance value extractor 6. The resistance value extraction unit 6 determines the resistance value of the wired power / ground wiring. The voltage drop value information generator 1 includes a voltage drop value calculator 7. The voltage drop value calculator 7 calculates a voltage drop value from the power supply source when the current source is connected to the resistance value of the wired power / ground wiring based on the calculated power consumption. The voltage drop value information generator 1 has a voltage drop distribution generator 8. The voltage drop distribution creating unit 8 obtains a voltage drop distribution in the semiconductor integrated circuit device based on the calculated voltage drop value.

The semiconductor integrated circuit design device 100 includes the rearrangement unit 3. The rearrangement section 3 arranges the transistors based on the information on the voltage drop value created by the voltage drop value information generation section 1.

The operation of the semiconductor integrated circuit designing apparatus 100 thus configured will be described. FIG. 2 is a flowchart of a process in the method for designing a semiconductor integrated circuit device according to the first embodiment of the present invention.

In FIG. 2, information on cells such as information 11 on cell shape, information on cell delay (information on cell operating power) 12, and information on cell connection 13 is first input, and the wiring distance of inter-cell connection, The general layout processing is performed so as to minimize the wiring capacitance (step S101). Then, a general wiring process for connecting the cells arranged approximately is performed (step S102). At this time, in addition to the signal wiring, power supply and ground wiring processing is also performed.

Next, the power consumption is calculated by estimating the wiring capacity based on the wiring length and the wiring capacity information stored as the physical parameter 14 based on the result of the schematic wiring processing, and calculating the load capacity of each cell. (Step S103). Then, the resistance value of the wired power supply / ground wiring is determined using information stored in the physical parameters 14 such as sheet resistance (step S104). The resistance value to be obtained is determined in a form corresponding to the connection information of the wiring shape.

Next, the amount of voltage drop from the power supply source is calculated based on the calculated power consumption value, assuming that the current source is connected to the resistance value of the wired power supply / ground wiring (step S105). Then, based on the calculated voltage drop value and the cell arrangement coordinate information, the voltage drop value is written to a location corresponding to each coordinate in the matrix database shown in FIG. (Step S106).

FIG. 3 is an exemplary diagram of matrix values showing a voltage drop distribution in the method of designing a semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 3, numerals represent voltage drop values, and the size of the matrix is determined so as to have a resolution sufficient to represent the voltage drop value in accordance with the wiring resistance value, the size of the chip, and the number of cells. Thereby, the voltage drop distribution by the matrix can be effectively used. FIG. 4 shows an image diagram of the change in the matrix value of the voltage drop distribution.

FIG. 4 is an image diagram of a voltage drop distribution on an LSI chip in the method of designing a semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 4, a thick solid line indicates the power supply wiring 31, and a contour shape is drawn in the LSI chip.

This represents an equipotential line 32 in which portions having a constant voltage drop value are connected by a line, similarly to a general contour line, and a region between the equipotential lines 32 to indicate a region within a constant voltage range. Are indicated by gray gradation display. This indicates that the voltage drop value increases as the gray density increases.

Next, based on the created voltage drop distribution, an appropriate cell is arranged at a place where an arbitrary voltage drop value is assumed (step S107). Then, a wiring process for connecting the terminals of the cell is performed (step S108).

As described above, according to the first embodiment, a rough placement process is performed before the final placement process, and a voltage drop value is predicted therefrom, thereby predicting a decrease in the operating performance of the cell (transistor). Can reduce the number of reworking steps to correct the floor plan later in response to the effects of voltage drops, and can develop LSI chips in a shorter design period. It becomes.

(Embodiment 2)
FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit design device 100A according to the second embodiment. In the first embodiment, the same components as those of the semiconductor integrated circuit design device 100 described above with reference to FIG. 1 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.

(4) The semiconductor integrated circuit design device 100A includes a voltage drop value information creating unit 1A. The voltage drop value information creation unit 1A has a path delay calculation unit 21. The path delay calculator 21 calculates a path delay between flip-flops based on the schematic arrangement and the general wiring of the transistors. The voltage drop value information creating unit 1A includes a path delay margin calculating unit 22. The path delay margin calculation unit 22 compares the path delay calculated by the path delay calculation unit 21 with the constraint delay time, and obtains a path delay margin in a path between each flip-flop.

(4) The semiconductor integrated circuit design device 100A includes a rearrangement unit 3A. The rearrangement unit 3A preferentially arranges the transistors included in the path having a large path delay margin calculated by the path delay margin calculation unit 22 in a region where the voltage drop value is large.

The operation of the semiconductor integrated circuit designing apparatus 100A thus configured will be described. FIG. 6 is a flowchart of a process in the method for designing a semiconductor integrated circuit device according to the second embodiment of the present invention. In the steps in FIG. 5, the steps for performing the same processing as in the first embodiment are denoted by the same step numbers as in FIG. 2, and detailed description will be omitted.

In FIG. 6, first, steps S101 to S106 are performed in the same manner as in the first embodiment, and a description thereof will be omitted. Next, after creating a voltage drop distribution chart (step S106), the information 13 on cell connection and the path delay constraint information 41 as a design condition are read, and are included in the information 13 on cell connection. However, paths that are irrelevant in circuit operation are excluded, and cell information included in the remaining paths is extracted (step S401), and a cell list within the path is generated (step S402).

Then, the cells included in each path in the intra-path cell list are arranged so as to be within a certain voltage drop value width from the voltage drop distribution diagram (step S403), and a wiring process for connecting the terminals of the cells is performed. (Step S108).

As described above, according to the second embodiment, it is possible to calculate the delay of a path with a constant voltage drop value by setting each path to a constant voltage drop value. Also, the delay calculation can be performed at high speed in consideration of the voltage drop value.

(Embodiment 3)
Hereinafter, a method for designing a semiconductor integrated circuit device according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a flowchart of a process in the method for designing a semiconductor integrated circuit device according to the third embodiment of the present invention. Steps in which the same processing as in the first embodiment is performed in each step in FIG. 7 are assigned the same step numbers as in FIG. 2, and detailed descriptions thereof will be omitted. The design method of the semiconductor integrated circuit device shown in FIG. 7 is executed by the semiconductor integrated circuit design device 100A described above with reference to FIG.

In FIG. 7, first, steps S101 and S102 are the same as those in the first embodiment, and thus description thereof is omitted. Then, after performing the general wiring processing (step S102), the wiring capacitance and the wiring resistance are extracted based on the general wiring information, and the path delay between each flip-flop is calculated (step S501).

Next, the timing constraint information on the path delay between the flip-flops is read and compared with the obtained path delay time to analyze the timing margin time for each path (step S502). Then, sorting is performed in ascending order of the timing margin time (step S503), and a path timing margin list is created (step S504). After that, from step S103 to step S106, the same processing as in the first embodiment is performed, and a voltage drop distribution diagram is created.

After creating the voltage drop distribution chart (step S106), the created voltage drop distribution chart is arranged in order from the area with the smallest voltage drop value and from the path at the top of the created path timing margin list. It goes (step S505). Here, when performing the arrangement processing, it is necessary to arrange the paths to be connected so as not to be largely separated in consideration of the arrangement of another path including the first and last flip-flops of the arranged path.

(4) Finally, the design is completed by performing the wiring process between the terminals of the arranged cells (step S108).

As described above, according to the third embodiment, by arranging paths in the order of small voltage drop from the path with the smallest path timing margin to the path with the strictest timing when operating as an LSI chip, the voltage drop is caused by the voltage drop. It is possible to design so as to be most resistant to the deterioration of the transistor operation performance, and it is possible to prevent the performance degradation of the LSI due to the voltage drop.

(Embodiment 4)
FIG. 8 is a block diagram showing a configuration of a semiconductor integrated circuit design device 100B according to the fourth embodiment. In the first embodiment, the same components as those of the semiconductor integrated circuit design device 100 described above with reference to FIG. 1 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.

(4) The semiconductor integrated circuit design device 100B includes a voltage drop value information creating unit 1B. The voltage drop value information creating section 1B has a test circuit incorporating section 23. The test circuit built-in unit 23 is provided to detect a failure location of a transistor. The semiconductor integrated circuit design device 100B includes a rearrangement unit 3B. The rearrangement unit 3B changes the connection order of the test circuits based on the information on the voltage drop value.

The operation of the semiconductor integrated circuit designing apparatus 100B thus configured will be described. FIGS. 9 and 10 are flowcharts of processing in the method for designing a semiconductor integrated circuit device according to the fourth embodiment of the present invention. 9 and FIG. 10, steps that perform the same processing as in the first embodiment are given the same step numbers as in FIG. 2, and detailed descriptions thereof are omitted.

In FIGS. 9 and 10, first, steps S101 to S106 are the same as those in the first embodiment, and thus description thereof is omitted. Then, after creating a voltage drop distribution diagram (step S106), the test signal connection information 61 in the failure detection test circuit is read. Then, based on the test signal connection information 61, the placement processing is performed according to the voltage drop distribution diagram so that the flip-flop transmitting the test signal always has a lower potential than the receiving cell. Step S601). Finally, a process of connecting and connecting the terminals of each cell is performed (step S108).

Normally, the test circuit directly connects the flip-flops or connects the flip-flops with a path shorter than that of a normal logic circuit, and the data signal of the flip-flop is larger than the delay time difference (clock skew) of the clock signal to the flip-flop cell. If the time obtained by adding the holding time constraint and the test signal delay time between the flip-flops is shorter, a hold error problem is caused, and the failure of the LSI chip cannot be diagnosed. However, according to the fourth embodiment, the voltage value of the cell transmitting the test signal is always lower than the voltage value of the cell receiving the signal. Becomes large, and a hold error can be avoided beforehand.

In FIG. 9, the placement processing is performed in consideration of the voltage drop distribution and the test signal connection information 61 before placement. However, as shown in FIG. The connection order of the test signals may be changed based on the signal connection information 61 so that the potential of the cell on the signal transmission side becomes lower than the potential of the cell on the signal reception side (step S701).

(Embodiment 5)
Hereinafter, a method for designing a semiconductor integrated circuit device according to a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a flowchart of a process in the method for designing a semiconductor integrated circuit device according to the fifth embodiment of the present invention. Steps in which the same processing as in the first embodiment is performed in each step in FIG. 11 are assigned the same step numbers as in FIG. 2 and detailed descriptions thereof are omitted.

In FIG. 11, first, the same information as in the first embodiment is read, and a rough arrangement process is performed (step S101). Next, in the cell connection information, such as a clock signal and a reset signal, a multi-fanout signal such that one cell drives many cells is formed on the tree by using buffer cells and even-numbered inverter cells. (Clock tree synthesis processing) (step S801), and the processing up to the placement of the inserted cells is performed (step S102).

Then, in steps S103 to S107, a voltage drop distribution chart is created in the same manner as in the first embodiment, and processing up to arranging cells is sequentially executed based on the voltage drop distribution chart. Next, delay calculation processing of the clock tree inserted in step 801 is performed in consideration of the reduction in the driving capability of the cell depending on the voltage drop value (step S802).

{Circle around (2)} Then, a wiring capacitance and a resistance value for adjusting the delay time from the calculated signal source of the clock tree to the signal receiving terminal such as a flip-flop are calculated (step S803). Next, wiring is performed in order from the wiring of the clock tree so as to have the calculated wiring capacitance and resistance (step S804).

As described above, according to the fifth embodiment, the wiring process is performed so as to reduce the skew of the clock tree in consideration of the decrease in the operation speed of the cell due to the voltage drop, and thereby the signal path in the path between flip-flops is reduced. , It is possible to suppress a decrease in the operation speed of the cell included in the circuit, and also to suppress a decrease in the circuit operation speed due to the clock skew.

As described above, according to the designing method of the semiconductor integrated circuit device according to the first to fifth embodiments, the general layout and the general wiring are performed before the final layout and the wiring processing are performed in the LSI layout design processing. The voltage drop value generated after the final cell placement and wiring processing is predicted based on the LSI, and the placement and wiring processing based on the prediction is performed, so that the performance of each transistor decreases due to the voltage drop during the actual operation of the LSI chip. Is processed on a simulation, and the yield can be improved.

The present invention can be applied to a method and an apparatus for designing a semiconductor integrated circuit device in which a transistor or a cell which is a transistor aggregate having a logical function is arranged in consideration of a voltage drop value.

FIG. 2 is a block diagram showing a configuration of a semiconductor integrated circuit design device 100 according to the first embodiment. 4 is a flowchart of a process in the method for designing a semiconductor integrated circuit device according to the first embodiment; FIG. 4 is an exemplary diagram of matrix values showing a voltage drop distribution in the method for designing a semiconductor integrated circuit device according to the first embodiment; FIG. 5 is a conceptual diagram of a voltage drop distribution on an LSI chip in the method for designing a semiconductor integrated circuit device according to the first embodiment; FIG. 9 is a block diagram showing a configuration of a semiconductor integrated circuit design device according to a second embodiment. 13 is a flowchart of a process in a method for designing a semiconductor integrated circuit device according to the second embodiment; 13 is a flowchart of a process in a method for designing a semiconductor integrated circuit device according to the third embodiment; FIG. 14 is a block diagram illustrating a configuration of a semiconductor integrated circuit design device according to a fourth embodiment. 14 is a flowchart of a process in a method for designing a semiconductor integrated circuit device according to a fourth embodiment; 14 is a flowchart of a process in a method for designing a semiconductor integrated circuit device according to a fourth embodiment; 15 is a flowchart of a process in a method for designing a semiconductor integrated circuit device according to a fifth embodiment;

Explanation of reference numerals

11 Cell shape information 12 Cell delay information (cell operating power information)
13 Cell Connection Information 14 Physical Parameters 31 Power Wiring 32 Equipotential Line 41 Path Delay Constraint Information 61 Test Signal Connection Information

Claims (14)

A method for designing a semiconductor integrated circuit device in which terminals of transistors formed on a silicon wafer are connected by metal wiring,
A first step of inputting information about the transistor and performing a general arrangement so as to minimize a wiring distance and a wiring capacitance of the connection between the transistors,
A second step of creating information about a voltage drop value based on the schematic arrangement of the transistor;
A third step of arranging the transistors based on the information on the voltage drop value. The second step,
Performing a general wiring for connecting the generally arranged transistors,
Estimating a wiring capacity based on the schematic wiring, and calculating a power consumption by calculating a load capacity of each of the transistors;
Determining the resistance value of the wired power / ground wiring;
A step of calculating a voltage drop value from a power supply source when a current source is connected to the resistance value of the wired power supply / ground wiring based on the calculated power consumption;
2. The method of designing a semiconductor integrated circuit device according to claim 1, further comprising: obtaining a voltage drop distribution in the semiconductor integrated circuit device based on the calculated voltage drop value. The third step,
3. The method of designing a semiconductor integrated circuit device according to claim 2, further comprising the step of arranging an appropriate transistor at a place where an arbitrary voltage drop value is assumed based on the voltage drop distribution. The third step,
2. A step of arranging the entire path between flip-flops in the semiconductor integrated circuit device or a pair of flip-flops on a source side and a sink side in an area having a small voltage drop value difference based on information on the voltage drop value. 3. The method for designing a semiconductor integrated circuit device according to item 1. Performing a general wiring for connecting between the generally arranged transistors;
Calculating a path delay between flip-flops based on the schematic layout and schematic wiring of the transistors;
Comparing the calculated path delay and the constraint delay time, and determining a margin of a path delay in a path between each flip-flop,
The third step,
2. The method of designing a semiconductor integrated circuit device according to claim 1, further comprising a step of preferentially arranging the transistors included in the path having a large margin of the path delay in a region having a large voltage drop value. Further comprising a step of incorporating a test circuit for detecting a fault location of the transistor,
The third step,
2. The method of designing a semiconductor integrated circuit device according to claim 1, further comprising a step of changing a connection order of the test circuits based on the information on the voltage drop value. In the second step, among the supply signals to the flip-flop circuit, further includes a step of dividing a signal of multiple fan-out on a tree,
In the third step,
Calculating a drive capability of the transistor belonging to the tree as a delay time based on the information about the voltage drop value;
Calculating a resistance value and a capacitance value such that a delay time from a signal source to a signal receiving end is equal to the delay time calculated as the driving capability of the transistor belonging to the tree;
2. A step of wiring between the signal source and the transistor belonging to the tree and between the signal source and the signal receiving end so that the calculated resistance value and the capacitance value are obtained. 3. The method for designing a semiconductor integrated circuit device according to item 1. A semiconductor integrated circuit device design apparatus for connecting terminals of transistors formed on a silicon wafer with metal wiring,
Schematic arrangement means for inputting information about the transistor, and performing schematic arrangement so as to minimize the wiring distance and wiring capacitance of the connection between the transistors,
Voltage drop value information creating means for creating information about a voltage drop value based on the schematic arrangement of the transistor,
And a rearrangement unit for arranging the transistors based on the information on the voltage drop value. The voltage drop value information creating means,
Schematic wiring means for performing general wiring for connecting the generally arranged transistors,
Power consumption calculation means for estimating a wiring capacity based on the schematic wiring and calculating power consumption by calculating a load capacity of each of the transistors;
Resistance value extracting means for determining the resistance value of the wired power / ground wiring;
Voltage drop value calculating means for calculating a voltage drop value from a power supply source when a current source is connected to the resistance value of the wired power supply / ground wiring based on the calculated power consumption;
9. The design apparatus for a semiconductor integrated circuit device according to claim 8, further comprising voltage drop distribution creating means for obtaining a voltage drop distribution in the semiconductor integrated circuit device based on the calculated voltage drop value. The relocation means,
The semiconductor integrated circuit device designing apparatus according to claim 9, wherein an appropriate transistor is arranged at a place where an arbitrary voltage drop value is assumed based on the voltage drop distribution. The relocation means,
10. The semiconductor integrated circuit device according to claim 9, wherein an entire path between flip-flops or a pair of source-side and sink-side flip-flops is arranged in a region having a small voltage drop value difference based on the information on the voltage drop value. Design equipment for semiconductor integrated circuit devices. The voltage drop value information creating means,
Path delay calculation means for calculating a path delay between flip-flops based on a schematic arrangement and a schematic wiring of the transistor;
Comparing the calculated path delay with the constraint delay time, and further comprising a path delay margin calculating means for obtaining a path delay margin in a path between each flip-flop;
The relocation means,
10. The semiconductor integrated circuit device designing apparatus according to claim 9, wherein the transistors included in the path having a large margin of the path delay are preferentially arranged in a region having a large voltage drop value. The voltage drop value information creating means,
Test circuit incorporating means for incorporating a test circuit for detecting a failure location of the transistor,
The relocation means,
10. The design apparatus for a semiconductor integrated circuit device according to claim 9, wherein the connection order of the test circuits is changed based on the information on the voltage drop value. The voltage drop value information creating unit divides a multi-fan-out signal among the supply signals to the flip-flop circuit into a tree,
The relocation means,
Means for calculating the drive capability of the transistor belonging to the tree as a delay time, based on the information about the voltage drop value;
Means for calculating a resistance value and a capacitance value such that a delay time from a signal source to a signal receiving end is equal to the delay time calculated as the driving capability of the transistor belonging to the tree;
10. A means for wiring between the signal source and the transistor belonging to the tree and between the signal source and the signal receiving end so that the calculated resistance value and the calculated capacitance value are obtained. 3. The method for designing a semiconductor integrated circuit device according to item 1.

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