JP4755123B2 - Operation mode control circuit for information processing apparatus and information processing apparatus - Google Patents

Description

  The present invention relates to a technique for preventing malfunction of an operation mode control circuit that controls an operation mode.

  In recent years, the use of microcomputers having a plurality of operation modes has increased. For example, it is used for home appliances and automobiles. In order to reduce power consumption, the operation mode is set to a low power consumption mode in addition to the normal operation mode. In a microcomputer having a plurality of operation modes, the normal operation mode is used at the time of normal use. However, erroneous transition to another mode causes a serious problem.

  Most recent vehicle equipment control is performed by microcomputer control. For this reason, in a vehicle-mounted microcomputer having a plurality of operation modes, it is necessary to ensure the safety of operation in the normal operation mode when used by a user. A microcomputer mounted on an automobile is placed in a high noise environment, and the possibility of transition to an undesired operation mode cannot be ignored. For this reason, a serious problem may occur due to erroneous transition. Further, when recovering from an erroneous transition, a reset is necessary when determining the mode, and a serious problem such as data loss is caused at the time of reset (forced reset). For this reason, in-vehicle microcomputers need to prevent transition to an erroneous mode in order to ensure reliability during use.

  For example, Patent Literature 1 describes an invention that solves the problem of transition to an unplanned operation mode due to changes in the write contents of the operation mode holding register due to noise or the like. When the contents written in the operation mode holding register are changed due to noise or the like and fall into an unplanned operation mode (low power consumption operation mode), there is no choice but to recover by resetting. A forced reset causes problems such as data loss. For this reason, Patent Document 1 discloses a technique for providing a microcomputer having a plurality of low power consumption operation modes that can prevent erroneous selection of operation modes.

  FIG. 1 of Patent Document 1 discloses a block diagram of a microcomputer device that solves the above-described problem, and explains that it operates as follows. One of the plurality of operation modes is set in the operation mode holding register B. Further, the low power consumption operation mode is written from the changeover switch 2 to the operation mode fixing register C. When the contents held in both registers B and C do not match, the register A write circuit writes the signal N indicating the normal operation mode to the register A regardless of the contents held in the operation mode holding registers A and B. The register A write circuit writes the held contents of the register B to the register A when the register B holds LP1 or LP2 and matches the holding circuit of the register C. When it is confirmed that the necessary conditions are satisfied by the program, the CPU (Central Processing Unit) outputs LP1 or LP2 to the register B.

  FIG. 15 is a block diagram showing a configuration example of a conventional operation mode control circuit. In the operation mode control circuit shown in FIG. 15, during normal use, it is important to use only the normal operation mode and not deviate from the normal operation mode. If the operation mode selection terminal or the reset signal used to determine the operation mode has a noise influence and the operation mode is erroneously changed, a reset is required to restore the operation mode. However, reset causes problems such as data loss. Therefore, a technique for providing a microcomputer having a plurality of operation modes capable of preventing erroneous transition of the operation modes is shown.

  In a microcomputer having a plurality of operation modes, there are a normal operation mode and various test modes for testing the function of each part, and these are used by switching. At this time, input terminals (plural) are used to select a plurality of operation modes. In each mode, at the time of power-on reset or reset, the data of the operation mode terminal is decoded and the internal function is switched for each selected mode.

  The operation mode control circuit 2 shown in FIG. 15 is configured to control a signal input from one operation mode terminal (operation mode designating terminal) 111. Therefore, the microcomputer includes the operation mode control circuit 2 shown in FIG. 15 for each operation mode terminal 111. The operation mode control circuit 2 operates as follows. The operation mode control circuit 2 latches the operation mode designation terminal signal 206 after the noise filter 202 by signals before and after the noise filter 203 of the reset signal 19. The operation mode control circuit 2 determines the logical product of the output signal 207 of the latch A23 and the output signal 208 of the latch B24 by the AND circuit 25 as the operation mode determination signal 130. With this configuration, erroneous transitions are reduced. Therefore, unless the output signal values of both the latch A 23 and the latch B 24 are “1”, the operation mode determination signal 130 is “0”. Further, in the microcomputer having the plurality of operation mode terminals 111, when all of the plurality of operation mode terminals are “0”, the microcomputer selects the normal operation mode.

  In the operation mode control circuit 2, pull-down resistors 21 and 27 and grounds (GND) 22 and 28 are inserted outside and inside the chip, respectively. The pull-down resistor 27 is for an operation mode signal external line, and the pull-down resistor 21 is for an operation mode signal internal line. Both resistors are arranged for the purpose of reducing erroneous input factors. The noise filter 202 is inserted into the operation mode designation terminal signal 204 and the noise filter 203 is inserted into the reset signal 19, both of which reduce the error input factor.

  16 and 17 show timing charts of the operation mode control circuit 2. FIG. FIG. 16 shows that when noise occurs in the operation mode designation terminal signal 206 after the noise filter 202 at the time of reset release, the mode is changed to an erroneous mode (the operation mode determination signal 130 is “1”). Also, FIG. 17 shows that when noise occurs in the operation mode designation terminal signal 206 after the noise filter 202 after the operation mode is determined by reset release, erroneous mode transition is prevented (the operation mode determination signal 130 is “0”). Show. However, when the values of the latch A23 and the latch B24 are inverted (noise is generated), it indicates that the mode is changed to the erroneous mode (the operation mode determination signal 130 is “1”).

  The microcomputer device disclosed in Patent Document 1 has a problem that the operation mode transitions when the operation mode output register A or the operation mode holding register B is affected by noise. Further, when there is an influence of noise on the operation mode signal line, there is also a problem that the operation mode changes. As described above, there is a problem that normal operation cannot be performed by shifting to an erroneous mode that is not intended by the user. For example, the operation mode holding register B changes from the signal N indicating the normal operation mode to the low power consumption operation mode LP1 or LP2 due to the influence of noise or the like, and may coincide with the operation mode fixed register C. In this case, LP1 or LP2 is written to the operation mode output register A, and the normal operation mode is changed to the low power consumption operation mode. Alternatively, the direct operation mode output register A may change from N to LP1 or LP2 due to the influence of noise or the like. In this case, the normal operation mode is shifted to the low power consumption operation mode.

  Further, the operation mode control circuit 2 shown in FIG. 15 has a problem that the operation mode transitions when there is an influence of noise on the latches A23 and B24. Further, when the output signals 207 and 208 of the latch are affected by noise, there is a problem that the operation mode is similarly changed. Furthermore, when reset is released, the operation mode is similarly shifted when there is an influence of noise on the operation mode designation terminal signal 206 after the noise filter. For example, the latch A23 and the latch B24 may be rewritten from “0” to “1” due to the influence of noise or the like. In this case, the operation mode determination signal 130 notified to the decoder becomes “1”, and the normal operation mode is changed to another mode. Alternatively, the latch A23 and the latch B24 may be rewritten due to noise or the like. In this case, a transition is made to the wrong mode regardless of the presence or absence of reset.

  FIG. 18 shows a state transition in the operation mode control circuit shown in FIG. FIG. 18 shows an operation state of the microcomputer determined by latching the value (“0” or “1”) of the operation mode terminal 111 based on the reset signal. The status block 3 shows the value of the operation mode terminal 111 in the area labeled “terminal”, the latch value in the area labeled “latch”, and the microcomputer operating status in the area indicated by the arrow. Here, in the configuration of FIG. 15, the value of the latch is the logical product of the latch A 23 and the latch B 24, that is, the output value of the AND circuit 25. When the microcomputer includes a plurality of operation mode terminals, the microcomputer selects the normal operation mode when the operation state of the microcomputer is “0” at all the operation mode terminals.

  The state block 31 shows a state in which “0” is entered in the operation mode terminal 111. Before reset release (during reset), the state of the operation mode terminal 111 is not related to the operation of the microcomputer. By releasing the reset 301, the latch becomes "0" and the operation state of the microcomputer also becomes "0". The state block 32 has the same latch value as the operation mode terminal 111 after the reset release 301 from the state of the state block 31, and can be said to be a stable state. In the state block 36, the operation mode terminal 111 is affected by the terminal noise 311 and the value of the operation mode terminal 111 is “1”. In the state of the state block 36, the operation state of the microcomputer does not transition to “1”. Further, the terminal block is stabilized 310, and the process returns to the state block 32.

  In the status block 34, the latch is affected by the latch noise 313, and the value of the latch is “1”. In the state of the state block 34, the operation state of the microcomputer erroneously changes to “1”. In the state block 33, there is a noise influence 303 on the mode terminal simultaneously with the reset release 302 from the state of the state block 31, and the value of the operation mode terminal 111 and the latch is “1”. Alternatively, there is an influence of the terminal noise 312 from the state of the state block 34 to the operation mode terminal 111, and the values of the operation mode terminal 111 and the latch are “1”. In the state of the state block 33, the operation state of the microcomputer erroneously changes to “1”.

  In the state block 35, the operation mode terminal 111 is stable from the state of the state block 33, and the value of the operation mode terminal 111 is “0”. Even if the operation mode terminal 111 is stabilized, the latch value is “1”, so that the operation state of the microcomputer is “1” which is an erroneous transition state.

Conventionally, a microcomputer has been externally monitored and reset by a WDT (Watchdog Timer) function, but a serious problem such as data loss has been caused at the time of reset. In addition, a time until WDT occurs and an initial routine until recovery are required.
JP 2001-67337 A

  However, if the user transitions to an incorrect operation mode due to external noise or the like while using the normal operation mode of an information processing device including an operation mode control circuit (for example, a device including a microcomputer equipped with an operation mode control circuit), the data Serious effects such as disappearance of In addition, the safety and stability of the device equipped with the operation mode control circuit cannot be ensured.

  As described above, there has been a problem that the operation mode control circuit for controlling the operation mode shifts to an incorrect operation mode due to the influence of external noise or the like.

  An aspect of the operation mode control circuit of the information processing apparatus according to the present invention is a first latch that latches an operation mode designation terminal signal based on a reset signal and retains a first retained value (for example, latch A23 in FIG. 3). ), A second latch (for example, latch B24 in FIG. 3) that latches the operation mode designating terminal signal based on the filtered reset signal, and holds the second holding value, the first holding value, A determination unit that outputs an operation mode determination signal based on the second hold value and the operation mode designation terminal signal (for example, the determination unit in FIG. 3).

  Further, the information processing apparatus (such as a microcomputer) according to the present invention includes an operation mode control circuit (for example, the operation mode control circuit in any one of FIGS. 3, 7, and 12).

  According to the present invention, it is possible to prevent the operation mode control circuit that controls the operation mode from shifting to an erroneous operation mode due to the influence of external noise or the like. As a result, the influence of external noise and the like can be reduced, and the safety and stability of the system can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

(Embodiment 1)
First, an example of a microcomputer on which the operation mode control circuit according to the present invention is mounted is shown. FIG. 1 is a block diagram showing a configuration example of a microcomputer according to the present invention. A microcomputer 1 shown in FIG. 1 includes an operation mode control unit 11, a CPU (Central Processing Unit) 12, a ROM (Read Only Memory) 13, a RAM (Random Access Memory) 14, an I / O (Input / Output) 15, and A macro 125 is provided, and an operation mode designation terminal signal is input from the operation mode terminals 111 to 113 and a reset signal 19 is input from the reset terminal 116. The operation mode control unit 11 includes a decoder 114 and three operation mode control circuits 127 to 129. The CPU 12 includes a register set 121, a control unit 122, a calculation unit 123, and a bus interface 124. The microcomputer 1 includes a CPU-ROM wiring 16, a CPU-RAM wiring 17, a CPU-I / O wiring 18, and a CPU-macro wiring 126.

  The microcomputer 1 controls operations of the CPU 12, the I / O 15, and the like by the operation mode control unit 11. In the operation mode control unit 11, each of the operation mode control circuits 127 to 129 determines the input signals (operation mode designation terminal signals) from the operation mode terminals 111 to 113 at the time of reset release and decodes the operation mode determination signals 130 to 132 by the decoder. To enter. Each of the operation mode determination signals 130 to 132 designates one of two operation modes, a first operation mode and a second operation mode. Thus, the operation mode control unit 11 determines the operation mode of the entire microcomputer 1 and outputs an operation mode signal 115 to each component. The microcomputer 1 operates based on the determined operation mode. In other words, in FIG. 1, three operation mode determination signals 130 to 132 are output based on operation mode designation terminal signals input from the three operation mode terminals 111 to 113, and one operation mode is determined by the decoder 114. In this example, the operation mode signal 115 is output.

  The operation modes include a normal operation mode and various test modes for testing the functions of the respective units, which are switched and used. Multiple input terminals are used to select multiple operation modes. When there are two operation modes, one operation mode terminal may be used. Further, the operation mode control circuit may be provided in accordance with the number of terminals. During normal use, use only the normal operation mode.

  Here, each operation mode will be described. FIG. 2 shows an example of the operation mode. In FIG. 2, “0” indicates that the voltage level of the operation mode terminal is Low, “1” indicates that the voltage level of the operation mode terminal is High, and “X” indicates a case where both values are selected. Yes. The normal operation mode is an operation mode in which a CPU built in the microcomputer executes an instruction based on an application program written in a ROM or a flash memory. The normal operation mode branches based on the user program (application) and starts instruction processing. As examples of modes other than the normal operation mode, a test mode for testing built-in functions, a programming mode that is a mode for rewriting to flash memory, etc., a debugging mode for debugging programs during application program development, and a chip for debugging There is a functioning emulator mode. For example, in the programming mode, communication is performed using a FLASH writer to rewrite FLASH. The test mode is a mode for testing the microcomputer, and a test instruction can be given from the outside to read the internal signal state.

  As shown in FIG. 2, when any terminal is “1”, the microcomputer 1 selects a mode other than the normal operation mode. During normal use, it is important to use only the normal operation mode and not deviate from the normal operation mode. If the normal operation mode is deviated, the program will not work during normal use, causing the user system to stop and an important problem leading to failure. If the operation mode pin that selects the operation mode or the reset signal used to determine the operation mode is affected by noise and the operation mode is erroneously changed, a reset is required to restore the operation mode. Invite problems.

  The mechanism of the operation mode control unit 11 that prevents erroneous transition of the operation mode when the operation mode control unit 11 is affected by external noise will be described below. FIG. 3 is a block diagram illustrating a configuration example of the operation mode control circuit according to the first embodiment of the present invention. The operation mode control circuit 4 shown in FIG. 3 shows a configuration example arranged in the operation mode control circuit 127 shown in FIG. Note that a circuit similar to the operation mode control circuit 127 can be arranged for the operation mode control circuits 128 and 129. The operation mode control circuit 4 includes a latch (first latch) A23, a latch B (second latch) 24, AND circuits 25 and 41, pull-down resistors 21 and 27, noise filters 202 and 203, and ground (GND). 22 and 28 are provided.

  The operation mode control circuit 4 shown in FIG. 3 outputs an AND circuit of the operation mode designation terminal signal 206 after the noise filter 202 and the output signal 401 of the AND circuit 25 to the operation mode control circuit 2 shown in FIG. 41 is a circuit to which 41 is added. Here, the AND circuit 25 and the AND circuit 41 are referred to as a determination unit 42. The determination unit outputs an operation mode determination signal 130 based on the operation mode designation terminal signal 206, the output signal 207 of the latch A23, and the output signal 208 of the latch B24.

  The operation mode terminal 111 is connected to the pull-down resistor 27 by an operation mode signal external line 201. The operation mode control circuit 4 inputs an operation mode designation terminal signal 204 from the operation mode terminal 111. In each embodiment of the present specification, a signal passing through a signal line (signal internal line, signal external line) is given a reference (for example, an operation mode designation terminal signal 206) for explanation.

  The reset signal 19 is a signal input from the reset terminal 116 shown in FIG. The reset signal 210 is a signal obtained by passing the reset signal 19 through the noise filter 203. The reset signals 19 and 210 are inverted by the inverting circuits 205 and 209, respectively, and input to the latch A23 and the latch B24.

The operation mode designation terminal signal 204 is input from the operation mode terminal 111, passes through the noise filter 202, and is input to the latch A23 and the latch B24 as the operation mode designation terminal signal 206 after passing through the noise filter. When the reset signal 19 is being reset, the latch A23 outputs the value (first hold value) indicated by the operation mode designation terminal signal 206 from the output signal 207, and when the reset signal 19 is releasing the reset, the reset release timing in holding the operation mode designation terminal signal 206 showed the value (first holding value), and outputs an output signal 207 of the latch A23 showing a first holding value. The latch B24 outputs the value (second hold value) indicated by the operation mode designation terminal signal 206 from the output signal 208 when the reset signal 210 is being reset, and when the reset signal 210 is releasing the reset, the reset release timing. Holds the value (second hold value) indicated by the operation mode designation terminal signal 206, and outputs the output signal 208 of the latch B24 indicating the second hold value.

  The AND circuit 25 outputs a logical product of the first holding value and the second holding value (the output signal 207 of the latch A 23 and the output signal 208 of the latch B 24) as the output signal 401 of the AND circuit 25. The AND circuit 41 outputs a logical product of the output signal 401 of the AND circuit 25 and the operation mode designation terminal signal 206 as the operation mode determination signal 130. That is, the determination unit 42 determines the operation mode based on the output signal 207 of the latch A23, the output signal 208 of the latch B24, and the operation mode designation terminal signal 206, and outputs the operation mode determination signal 130. The operation mode determination signal 130 is output to the decoder 114 in FIG.

  4 and 5 show timing charts of the operation mode control circuit 4 shown in FIG. FIG. 4 shows that when noise occurs in the operation mode designation terminal signal 206 (signal line of the operation mode designation terminal signal 206) at the time of reset release, transition to an erroneous mode (the operation mode determination signal 130 is “1”) during the noise generation. However, after that, when there is no noise in the operation mode designation terminal signal 206, the operation mode is restored (the operation mode determination signal 130 is “0”). However, when noise occurs in the operation mode designation terminal signal 206 after the operation mode is determined, there is a disadvantage that the mode is shifted to an erroneous mode while the noise is generated. FIG. 5 shows that after the operation mode is determined, when noise occurs in the latch A23 and the latch B24 and the values of the latch A23 and the latch B24 are inverted, the erroneous mode transition can be prevented, and in addition, the operation mode designation terminal signal If noise is generated at 206, it indicates that an erroneous mode transition occurs during the generation of noise.

  FIG. 6 shows a state transition in the operation mode control circuit 4 shown in FIG. In FIG. 18, when there is a noise influence on the latch, the operation state of the microcomputer is erroneously changed (state blocks 34 and 35 in FIG. 18). In the present embodiment, the operation mode designation terminal signal 206 and the AND circuit 41 of the output signal 401 of the AND circuit 25 are arranged in the operation mode control circuit 4. Thereby, even when there is a noise influence on the latch A23 and the latch B24, as shown in the state block 51, the operation state of the microcomputer 1 does not erroneously change. In the state block 34 of FIG. 18, the operation state of the microcomputer 1 is “1”, but in the state block 51 of FIG. 6, it becomes “0”. The same applies to the state of the state block 52 in FIG. The microcomputer 1 selects the normal operation mode when the operation state is “0” at all the operation mode terminals 111 to 113.

  As described above, in this embodiment, the AND circuit 41 is added, and the logical product of the operation mode designation terminal signal 206 after the noise filter and the output signal 401 of the AND circuit 25 is calculated. Thereby, it is possible to prevent erroneous transition of the operation mode when there is a noise influence on the latch or the output signal of the latch.

  In FIG. 3, the determination unit 42 is configured by two AND circuits 25 and 41. However, the determination unit 42 may be realized by one AND circuit. The output signals 207 and 208 and the operation mode and the terminal signal 206 may be input to one AND circuit, and a logical product may be output as the operation mode determination signal 130.

(Embodiment 2)
In the first embodiment, one mode for preventing the operation mode from erroneously changing when there is a noise influence on the latch or the output signal of the latch has been described. However, in the second embodiment, the operation mode terminal 111 affects the influence of the noise. An aspect of preventing the operation mode from erroneously changing when received will be described. FIG. 7 is a block diagram showing a configuration example of an operation mode control circuit according to the second embodiment of the present invention. The operation mode control circuit 6 shown in FIG. 7 is obtained by adding a configuration for relatching the latch value to the operation mode control circuit 4 shown in FIG. In addition to preventing erroneous transition of the operation mode, the operation mode control circuit 6 stabilizes the operation mode control circuit 127 by bringing the operation mode control unit 11 into a stable state.

  In FIG. 7, the latch A23 designates the operation mode when the operation mode designation terminal signal 206 is a value indicating the first operation mode and the output signal 207 (first hold value) of the latch A23 is not the first operation mode. The terminal signal 206 is latched again. Similarly, the latch B24 designates the operation mode when the operation mode designation terminal signal 206 is a value indicating the first operation mode and the output signal 208 (second hold value) of the latch B24 is not the first operation mode. The terminal signal 206 is latched again. By re-latching the latch value, even when external noise enters the latch, it can be corrected to a normal terminal value. Further, by making the mode terminal and the latch value the same, it becomes possible to achieve a stable state against noise.

  As shown in FIG. 7, by adding a circuit to the latch A23 or the latch B24, the latch A23 or the latch B24 can be re-latched. The AND circuit 61 uses a logical product of the value obtained by inverting the operation mode designation terminal signal 206 after the noise filter by the inverting circuit 607 and the first holding value (the output signal 207 of the latch A23) held by the latch A23 as an AND signal 601. Output. The AND circuit 63 outputs a logical product of the value obtained by inverting the AND signal 601 by the inverting circuit 603 and the reset signal 19 as an AND signal 605. The AND circuit 62 outputs, as an AND signal 602, a logical product of the value obtained by inverting the operation mode designation terminal signal 206 after the noise filter by the inverting circuit 608 and the second holding value held by the latch B24. The AND circuit 64 outputs a logical product of the value obtained by inverting the AND signal 602 by the inverting circuit 604 and the reset signal 210 after filtering as an AND signal 606.

  Specifically, when noise occurs in the latch A23, for example, when the operation mode designation terminal signal 206 is "0" and the output signal 207 of the latch A23 is "1", the AND signal 601 becomes "1" and the AND signal 605 The output signal 605 of the AND circuit 63, which is the value obtained by inverting the reset signal 19 and the AND signal 601 by the inverting circuit 603, is "0", and the output signal 207 of the latch A23 is a value "0" indicating the first operation mode. It becomes. Since a value “0” obtained by inverting the AND signal 605 by the inverting circuit 205 is input to the latch A 23, re-latching is performed (the operation mode designation terminal signal 206 is passed through and output from the output signal 207. ). The same applies to the latch B24.

8 to 10 show timing charts of the operation mode control circuit 6 shown in FIG.
In FIG. 8, when noise occurs in the operation mode designation terminal signal 206 at the time of reset release, the operation mode is temporarily switched to the erroneous mode. However, when the noise to the operation mode designation terminal signal 206 disappears thereafter, the operation mode is restored. As a result, the noise to the operation mode designation terminal signal 206 disappears, and at the same time, the latch A23 and the latch B24 are relatched, and the output signal 207 of the latch A23 and the output signal 208 of the latch B24 output from the latch A23 and the latch B24 This indicates that the value is the same as that of the operation mode terminal 111 (operation mode designation terminal signal 206). In addition, at this time, the operation mode control circuit 127 is in a stable state. It is shown that by re-latching the latch A23 and the latch B24, when noise occurs in the operation mode designation terminal signal 206 after the mode is determined, erroneous mode transition can be prevented.

  FIG. 9 shows that an erroneous mode transition can be prevented when the values of the latch A23 and the latch B24 are inverted after the mode is determined. In addition, when noise occurs in the operation mode designation terminal signal 206, it indicates that an erroneous mode transition can be prevented. Specifically, even when noise occurs in the latch, re-latching is performed based on the operation mode designation terminal signal 206, the AND circuit 61, the AND circuit 63, etc. (the latch B24 is the AND circuit 62, the AND circuit 64, etc.). As a result, the influence on the first holding value and the second holding value held by the latch immediately disappears. Even when noise occurs in the operation mode designation terminal signal 206, the values of the latch A23 and the latch B24 are values indicating the first operation mode due to re-latching, and the operation mode determination signal 130 is not affected.

  FIG. 10 is a timing chart at the time of re-latching in the operation mode control circuit 6 shown in FIG. As shown in FIG. 10, when noise occurs in the latch A 23, the output signal 601 of the AND circuit 61 becomes “1” and the output signal 605 of the AND circuit 63 becomes “0” by the AND circuits 61 and 63 and the like. . When the output signal 605 is “0”, the output signal 207 of the latch A 23 transfers the mode terminal signal 206 and becomes “0”. The operation mode circuit 127 can be brought into a stable state by re-latching by the AND circuits 61 and 63 and the like.

  FIG. 11 shows a state transition in the operation mode control circuit 6 shown in FIG. The difference from the first embodiment is that the microcomputer re-latches 71 and 72 from the state block 51 or the state block 52 to become the state block 32. For example, when the operation mode terminal 111 is affected by noise, the state block 51 becomes the state block 33 and shifts to an erroneous mode. However, by re-latching 71, the state block 32 is obtained, and the microcomputer 1 becomes stable.

  As described above, according to the present embodiment, it is possible to prevent an unstable state in which information of the latch (latch A23 and latch B24) and the operation mode terminal 111 are different. As a result, it is possible to prevent the latch from being affected by external noise, and then transitioning to an erroneous mode even if the external noise effect occurs at the operation mode terminal 111. Further, the operation mode control circuit 127 can be brought into a stable state.

(Embodiment 3)
In the third embodiment, in addition to the first embodiment, one mode for preventing an erroneous transition of the operation mode when there is an influence of noise on the operation mode designation terminal signal 206 after the noise filter at the time of reset release will be described. FIG. 12 is a block diagram illustrating a configuration example of an operation mode control circuit according to the third embodiment of the present invention. The operation mode control circuit 8 shown in FIG. 12 is obtained by adding an F / F circuit 81 and the like and an AND circuit 83 to the operation mode control circuit 4 shown in FIG.

  The F / F circuit 81 detects the timing at which the operation mode designation terminal signal 206 changes to the first operation mode (normal operation mode) when the reset signal indicates that reset is being released, and latches at the detected timing. The F / F circuit 81 latches by detecting the falling edge of the operation mode designation terminal signal 206 (latching is triggered by the falling edge). Further, a configuration (F / F circuit 81, inverting circuit 82) that outputs the operation mode designation terminal signal 206 to the AND circuit 83 is referred to as a detection unit 85.

  The AND circuit 83 determines the operation mode of the logical product of the signal 804 (the logical product of the output signal 401 of the AND circuit 25 and the operation mode designation terminal signal 206) output from the AND circuit 41 and the output signal 801 from the detection unit 85. The signal is output as the signal 130, and when the falling of the operation mode designation terminal signal is detected, the operation mode determination signal is changed to a value indicating the first operation mode (normal operation mode).

  With such a configuration, the operation mode control circuit 8 prevents erroneous transitions when the operation mode designation terminal signal 206 is affected by noise. Therefore, the operation mode control circuit 8 prevents an erroneous transition when the operation mode designation terminal signal 206 is affected by noise at the time of reset release.

  If the operation mode designation terminal signal 206 is affected by noise at the time of reset cancellation, a signal fall due to noise always occurs. In the F / F circuit 81, the inverted signal 801 of the output signal 802 of the F / F circuit 81 becomes “0” (normal operation mode) from the signal 802 latched by the falling of the operation mode designation terminal signal 206. As a result, the operation mode determination signal 130 is also set to “0” to prevent erroneous operation mode transition. That is, the detection unit 85 is configured such that the signal 801 indicates the first operation mode (normal operation mode) when the falling edge of the operation mode designation terminal signal is detected when the reset signal is being reset.

  When there is no falling due to noise at the operation mode designation terminal signal 206, the output signal 801 of the detection unit 85 is “1”, and the operation mode determination signal 130 is determined by the output signal 804 of the AND circuit 41. The circuit configuration can execute the operation mode transition.

  FIG. 13 shows a timing chart of the operation mode control circuit shown in FIG. In FIG. 13, when noise occurs in the operation mode designation terminal signal 206 at the time of reset release, the mode is temporarily shifted to an erroneous mode. However, when the noise to the operation mode designation terminal signal 206 is eliminated by the F / F circuit 81, the operation is performed. Indicates that the mode is restored. By adding the F / F circuit 81, if noise occurs in the operation mode designation terminal signal 206 after the mode is determined, the erroneous mode transition can be prevented.

  FIG. 14 shows a state transition in the operation mode control circuit shown in FIG. The difference from the first embodiment is that when there is a noise influence on the signal line after the noise filter 901, the operation state of the microcomputer in the state block 91 is “0” (indicated by reference numeral 92) by re-latching the F / F circuit 81. Part).

As described above, in the third embodiment, in addition to the influence of noise on the latch, it is possible to prevent an erroneous transition of the operation mode when the influence of the noise on the operation mode designation terminal signal 206 after the noise filter at the time of reset release. Compared to the first embodiment, the stability of the microcomputer against the influence of noise on the operation mode designation terminal signal 206 can be improved.
Note that an operation mode control circuit combining the second embodiment and the third embodiment can also be used.

As described above, according to a preferred embodiment of the present invention, when a reset is released and after the operation mode is determined, the microcomputer having a plurality of operation modes has an external noise influence on the operation mode control circuit 127. It is possible to prevent erroneous transition of the operation mode. In addition, the operation mode control unit after noise generation can be stabilized. Specifically, an AND logic of the output signals of the two latches A and B and the signal before the latch input is formed. Thereby, when there is an external noise influence on the latch and the signal line after the latch, it is possible to prevent erroneous transition of the operation mode and to stabilize the microcomputer.
Further, by latching and latching again in the two latches A and B, the operation mode control circuit 127 can be stabilized against the influence of noise on the latches. Further, when the operation mode designation terminal signal 206 is affected by noise, the noise to the operation mode designation terminal signal 206 is detected by detecting the timing at which the influence of noise disappears (fall of the operation mode designation terminal signal 206). It is possible to prevent erroneous transitions based on the influence of. Further, by combining the embodiments described above, it is possible to prevent the operation mode erroneous transition due to the external noise to be greater than that in the prior art and to stabilize the entire information processing apparatus.

  The operation mode control circuit described in each of the above embodiments can be applied to an information processing device such as a semiconductor circuit device, a processor without a built-in ROM, a flash built-in microcomputer, a microcomputer having a plurality of operation modes.

  In addition, this invention is not limited to embodiment shown above. Within the scope of the present invention, it is possible to change, add, or convert each element of the above-described embodiment to a content that can be easily considered by those skilled in the art.

It is a block diagram which shows the structural example of the microcomputer which concerns on this invention. It is a figure which shows an example of the operation mode of a microcomputer. It is a block diagram which shows the structural example of the operation mode control circuit which concerns on Embodiment 1 of this invention. 4 is a timing chart of the operation mode control circuit shown in FIG. 3. 4 is another timing chart of the operation mode control circuit shown in FIG. 3. It is a figure showing the state transition in the operation mode control circuit shown in FIG. It is a block diagram which shows the structural example of the operation mode control circuit which concerns on Embodiment 2 of this invention. It is a timing chart of the operation mode control circuit shown in FIG. It is another timing chart of the operation mode control circuit shown in FIG. 8 is a timing chart at the time of re-latching of the operation mode control circuit shown in FIG. It is a figure showing the state transition in the operation mode control circuit shown in FIG. It is a block diagram which shows the structural example of the operation mode control circuit which concerns on Embodiment 3 of this invention. 13 is a timing chart of the operation mode control circuit shown in FIG. It is a figure showing the state transition in the operation mode control circuit shown in FIG. It is a figure which shows the block diagram of the structural example of the conventional operation mode control circuit. 16 is a timing chart of the operation mode control circuit shown in FIG. 16 is another timing chart of the operation mode control circuit shown in FIG. FIG. 16 is a diagram illustrating state transition in the operation mode control circuit illustrated in FIG. 15.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Microcomputer 2, 4, 6, 8 Operation mode control circuit 3, 31-36, 51, 52, 71, 72, 91 Status block 11 Operation mode control part 12 CPU, 13 ROM, 14 RAM, 15 I / O
16 CPU-ROM wiring, 17 CPU-RAM wiring, 18 CPU-I / O wiring 19, 210 Reset signal 21, 27 Pull-down resistor 22, 28 Ground (GND)
23 Latch A
24 Latch B
25, 41, 61-64, 83, AND circuit 42 determination unit 71, 72 State transition 81 by re-latching F / F circuit (flip-flop circuit)
82, 205, 209, 603, 604, 607, 608, 803 Inversion circuit (inverter)
84 High clamp 85 Detection unit 111 to 113 Operation mode terminal 114 Decoder 115 Operation mode signal 116 Reset terminal 121 Register set 122 Control unit 123 Operation unit 124 Bus interface 125 Macro
126 CPU-macro wiring 127-129 operation mode control circuit 130-132 operation mode determination signal 201 operation mode designation terminal signal external line 202, 203 noise filter 204, 206, operation mode designation terminal signal 207 output signal 208 of latch A23 latch B24 Output signal 301, 302 State transition 303, 311, 312 due to reset release Terminal noise 304, 306 State transition due to terminal noise 305 State transition 307 due to latch noise, 310 State transition due to terminal stabilization 313 Latch noise 401 Output signal of AND circuit 25 601 Output signal 602 of AND circuit 61 Output signal 605 of AND circuit 62 Output signal 606 of AND circuit 63 Output signal 401 of AND circuit 64 Output signal 801 of AND circuit 25 Inverted signal 8 of signal 802 State transition by 2 F / F circuit of the output signal 901 the noise filter after the signal line noise 902 noise filter after the signal line noise of the output signal 804 the AND circuit 41

Claims (6)

A first latch for latching the operation mode designation terminal signal based on the reset signal and holding the first holding value;
Latching the operation mode designation terminal signal based on a reset signal filtered by a noise filter, and holding a second holding value;
A determination unit that outputs an operation mode determination signal based on the first hold value, the second hold value, and the operation mode designation terminal signal ;
The first latch latches the operation mode designation terminal signal again when the operation mode designation terminal signal is a value indicating the first operation mode and the first hold value is not the first operation mode;
The information processing for latching the operation mode specification terminal signal again when the operation mode specification terminal signal is a value indicating the first operation mode and the second holding value is not the first operation mode. Device operation mode control circuit.   The determination unit sets the operation mode determination signal to the first operation mode when the first holding value, the second holding value, and the value indicated by the operation mode designation terminal signal are not the same, and when the same, 2. The operation mode control circuit according to claim 1, wherein the operation mode is set to an operation mode. The first latch is a case where the operation mode designation terminal signal is a value indicating the first operation mode, and the first hold value is not the first operation mode, and the reset signal indicates reset release. The operation mode designation terminal signal is latched again,
The second latch is a case where the operation mode designation terminal signal is a value indicating the first operation mode and the second holding value is not the first operation mode, and the reset signal indicates reset release. 3. The operation mode control circuit of the information processing apparatus according to claim 1 , wherein the operation mode designation terminal signal is latched again. A detection unit for detecting a timing at which the operation mode designation terminal signal changes to a value indicating the first operation mode when the reset is released ;
The information according to any one of claims 1 to 3 , wherein the determination unit changes the operation mode determination signal to a value indicating a first operation mode when the detection unit detects the timing. An operation mode control circuit of the processing apparatus. The first operation mode is a normal operation mode, the second operation mode, the test mode, the programming mode, the emulator mode, and out of the debug mode of claims 1 to 4, characterized in that either An operation mode control circuit of the information processing apparatus according to any one of the above. An information processing apparatus comprising the operation mode control circuit according to any one of claims 1 to 5 .

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