JP4754872B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a shift register using a transistor, and more particularly to a shift register for controlling a display device.

In a display device using a self-luminous light emitting element represented by an organic light emitting diode (OLED (Organic Light Emitting Diode), an organic EL element, an electroluminescence (EL) element, etc.) or a liquid crystal display device, A circuit for driving a pixel is formed on the same substrate as the pixel.
In such a circuit, a shift register is often used because it is necessary to generate a signal that sequentially selects a plurality of wirings and a plurality of circuits (such as switches).

A clock signal is usually supplied to the shift register. The shift register operates in synchronization with the clock signal. However, since the clock signal is supplied to all the unit registers constituting the shift register, the load on the wiring for supplying the clock signal becomes large. As a result, power consumption increases.

  The unit register is a circuit for one stage or several stages of the shift register. A plurality of unit registers are connected in series to form a shift register.

Therefore, a technique has been proposed in which a clock signal is selectively supplied only to a unit register at a stage where data is at a significant level (for example, an H signal in the case of positive logic). (For example, refer to Patent Document 1).
Japanese Patent No. 3326691

  FIG. 19 is a circuit diagram of the unit register disclosed in Patent Document 1. An input signal and an output signal to the delay flip-flop circuit (DFF) are input to the NOR circuit 1903. When both the input signal and the output signal are L signals, both the transfer gate (also referred to as analog switch) 1901 and the transfer gate 1902 are turned off at the same time so that the clock signals CLK1 and CLK2 are not supplied to the DFF. When at least one of an input signal and an output signal to the DFF is an H signal, both the transfer gate 1901 and the transfer gate 1902 are simultaneously turned on so that the clock signals CLK1 and CLK2 are supplied to the DFF.

A detailed circuit diagram of the DFF is shown in FIG.

Next, another circuit shown in Patent Document 1 is shown in FIG. In FIG. 21, each of the transfer gate 2101 and the transfer gate 2102 is composed of only one polarity transistor. As a result, a NOR circuit is not required as shown in FIG. When either the input signal or the output signal to the DFF is an L signal, both the transfer gate 2101 and the transfer gate 2102 are turned off at the same time, and at least one of the input signal and the output signal to the DFF is an H signal. Both the transfer gate 2101 and the transfer gate 2102 are simultaneously turned off.

  However, in the case of Patent Document 1, both the transfer gates 1901 and 1902 and the transfer gates 2101 and 2102 are simultaneously turned on to control supply of both clock signals. For this reason, the load on the wiring for supplying the clock signal becomes large. As a result, power consumption increases.

In FIG. 19, since the NOR circuit 1903 is used, the circuit becomes complicated. On the other hand, in FIG. 21, the NOR circuit is not used. However, in the case of this circuit, as described in Patent Document 1, the voltage at the transfer gates 2101 and 2102 is lowered by the threshold voltage. For this reason, the amplitude of the clock signal supplied to the DFF becomes small. As a result, the transistor to be turned off is not turned off, which causes a malfunction. In addition, since current continues to flow in a transistor that is not turned off, power consumption also increases.

  In view of such problems, an object of the present invention is to provide a shift register that can supply only a necessary clock signal to a necessary unit register by using a simple configuration.

  The present invention achieves the above object by controlling the first clock signal and the second clock signal separately, rather than simultaneously controlling the supply of the first clock signal and the second clock signal to the flip-flop circuit. To do.

  That is, in a certain unit register, when only the first clock signal needs to be supplied, only the first clock signal is supplied. When only the second clock signal needs to be supplied, only the second clock signal is supplied. When both signals are required, both signals are supplied. When both signals are not required, both signals are not supplied.

  Such an operation is controlled using an input signal to the unit register and an output signal from the unit register.

The present invention is a semiconductor device having a shift register in which a plurality of unit registers are connected.
The unit register has a flip-flop circuit, a first switch, and a second switch,
The first wiring is electrically connected to the flip-flop circuit via the first switch.
The second wiring is electrically connected to the flip-flop circuit via the second switch.
The on / off of the first switch is controlled by an input signal to the flip-flop circuit.
The on / off state of the second switch is controlled by the output signal from the flip-flop circuit.

The present invention is a semiconductor device having a shift register in which a plurality of unit registers are connected.
The unit register has a flip-flop circuit, a first switch, and a second switch,
The first wiring is electrically connected to the flip-flop circuit via the first switch.
The second wiring is electrically connected to the flip-flop circuit via the second switch.
When the input signal to the flip-flop circuit is at a significant level, the first switch is turned on,
When the output signal from the flip-flop circuit is at a significant level, the second switch is turned on.

    In the present invention, the first switch or the second switch is composed of a complementary transfer gate.

  In the present invention, there are no limitations on the types of transistors that can be used, and the transistor is formed using a thin film transistor (TFT) using a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a semiconductor substrate, or an SOI substrate. A MOS transistor, a junction transistor, a bipolar transistor, a transistor using an organic semiconductor or a carbon nanotube, and other transistors can be used. There is no limitation on the kind of the substrate over which the transistor is provided, and the transistor can be provided on a single crystal substrate, an SOI substrate, a glass substrate, a plastic substrate, or the like.

  In the present invention, being connected is synonymous with being electrically connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, another element (for example, another element or a switch) that enables electrical connection may be disposed therebetween.

  Thus, in the present invention, the first clock signal CLK1 and the second clock signal CLK2 are controlled separately. Therefore, when one of the clock signals does not need to be supplied, the operation can be performed so as to stop the supply of the clock signal. As a result, the load on the wiring that supplies the first clock signal CLK1 and the second clock signal CLK2 is reduced. As a result of lightening the load on the clock signal line, (a) the rounding of the waveform of the clock signal is suppressed and the circuit operates normally. (B) The clock signal is applied to the substrate on which the transistor such as a shift register is formed. The power consumption of an IC that supplies the clock signal (hereinafter referred to as an external IC) is reduced. (C) The current supply capability of the external IC that supplies the clock signal can be reduced, so the external IC can be reduced in size. And cost reduction can be realized.

Further, since the structure is simple, the layout area of the circuit is reduced and the frame can be narrowed. As a result, more panels can be manufactured from one mother glass, and the so-called chamfering number increases. As a result, the cost per panel can be reduced and the price can be reduced.

  In addition, the voltage is lowered by the threshold voltage, the amplitude of the clock signal supplied to the flip-flop circuit 110 is reduced, and the transistor to be turned off is not turned off. Nothing happens.

Thus, by using the present invention, cost reduction and size reduction can be realized, and the circuit can operate more normally.

(Embodiment 1)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

  FIG. 1 shows a configuration example of one stage of the shift register. Here, the shift register for one stage or several stages is referred to as a unit register. The unit register includes switches 101 and 102, transistors 103 and 104, inverters 105 and 106, and a flip-flop circuit 110. One gate electrode of the switch 101 is connected to the gate electrode of the transistor 103 and the input side of the inverter 105, and the other is connected to the output side of the inverter 105. The first clock signal CLK1 is supplied to one of the source region and the drain region of the switch 101, and the source region or the drain region of the transistor 103 and the wiring CLK1_D are connected to the other. One gate electrode of the switch 102 is connected to the gate electrode of the transistor 104 and the output side of the inverter 106, and the other is connected to the input side of the inverter 106 and supplied with the input signal IN. The second clock signal CLK2 is supplied to one of the source region and the drain region of the switch 102, and the source region or the drain region of the transistor 104 and the wiring CLK2_D are connected to the other. A high potential power supply (Vdd) is connected to a side of the source region or drain region of the transistor 103 that is not connected to the source region or drain region of the switch 101. A low potential side power supply (Vss) is connected to a side of the source region or drain region of the transistor 104 that is not connected to the source region or drain region of the switch 102.

  The supply of two clock signals to the flip-flop circuit is controlled using the switches 101 and 102. The supply of the first clock signal CLK1 to the flip-flop circuit 110 is controlled by the switch 101. The switch 101 is controlled using an output signal from the flip-flop circuit 110. The second clock signal CLK <b> 2 is controlled to be supplied to the flip-flop circuit 110 by the switch 102. The switch 102 is controlled using an input signal to the flip-flop circuit 110.

  Thus, the first clock signal CLK1 and the second clock signal CLK2 are controlled separately. Therefore, when one of the clock signals does not need to be supplied, the operation can be performed so as to stop the supply of the clock signal. As a result, the load on the wiring that supplies the first clock signal CLK1 and the second clock signal CLK2 is reduced. As a result of lightening the load on the clock signal line, (a) the waveform rounding of the clock signal is suppressed and the circuit operates normally. (B) The clock signal is supplied to the substrate on which the shift register is formed. The power consumption of the external IC can be reduced, and (c) the current supply capability of the external IC for supplying the clock signal can be reduced, so that the external IC can be reduced in size and cost.

  Note that a substrate on which a transistor such as a shift register is formed and an external IC are arranged on the substrate and may be connected by COG (Chip On Glass), TAB (Tape Automated Bonding) or printing. In some cases, they are connected using a substrate. However, it is not limited to this. A circuit for supplying a clock signal may be formed on the same substrate as the shift register.

  Next, FIG. 2 shows an example of the internal circuit configuration of the flip-flop circuit 110. A clocked inverter 201, a loop portion inverter 203, and a clocked inverter 202 are included. As for the clock input section of the clocked inverter 201, the first clock signal CLK1 is connected to the P-channel transistor T1, and the second clock signal CLK2 is connected to the N-channel transistor T4. Regarding the clock input section of the clocked inverter 202, the first clock signal CLK1 is connected to the N-channel transistor T8, and the second clock signal CLK2 is connected to the P-channel transistor T5. Note that the flip-flop circuit is not limited to the configuration shown in FIG.

Such unit registers are connected in a plurality of stages to constitute the entire shift register. A general view is shown in FIG. The first clock signal CLK1 and the second clock signal CLK2 of each unit register are connected to the clock signal CLOCK and the clock bar signal CLOCKB. However, the clock signal CLOCK and the clock bar signal CLOCKB are alternately connected. Thereby, the signal can be shifted.

  Then, using the output signal of each unit register, it is possible to generate a signal that sequentially selects a plurality of arranged wirings, a plurality of arranged circuits (switches, etc.) and the like.

  Next, the operation will be described. The operation of the unit register corresponding to one stage, not the entire shift register, will be described. The waveforms of the first clock signal CLK1, the second clock signal CLK2, the input signal IN, and the output signal OUT are shown in FIG. As shown in FIG. 4, the description will be divided into five operation regions according to each operation state.

  First, the case of the operation 1 is shown in FIG. As shown in FIG. 4, the input signal IN and the output signal OUT are also L signals (corresponding to a low signal, a low voltage, binary 0, etc., and in the case of positive logic, an insignificant level). Therefore, both the switch 101 and the switch 102 are off, and the clock signal is not supplied into the circuit. Therefore, the load on the clock signal line is reduced. However, nothing is output from the clocked inverter 201 (floating state), and data must be held by the inverter 203 and the clocked inverter 202 in the loop portion. For this purpose, it is necessary to turn on the transistors T9 and T10 so that the wirings CLK1_D and CLK2_D do not float. As a result, the transistors T1 and T4 are turned off, and the transistors T5 and T8 are turned on. Note that in FIG. 5, it is assumed that the transistor marked with a cross is in an off state. On each terminal, H is an H signal, L is an L signal,? Can be either H or L.

  Next, the case of the operation 2 is shown in FIG. The input signal IN is an H signal (corresponding to a high signal, high voltage, binary 1 or the like, and a significant level in the case of positive logic). Then, the switch 102 is turned on, and the second clock signal CLK2 is supplied to the circuit. However, since the switch 101 remains off, the first clock signal CLK1 remains not supplied to the circuit. Therefore, the load of the signal line that supplies the first clock signal CLK1 remains light.

  The transistor T10 is in an off state, and the second clock signal CLK2 is supplied to the circuit. At this time, the second clock signal CLK2 is an L signal. Therefore, the transistor T4 remains off and the transistor T5 remains on. Therefore, nothing is output from the clocked inverter 201 (floating state), and the loop 203 and the clocked inverter 202 continue to hold data.

  Next, the case of operation 3 is shown in FIG. The first clock signal CLK1 becomes an L signal, and the second clock signal CLK2 becomes an H signal. Then, the transistor T4 is turned on and the transistor T5 is turned off. On the other hand, since the input signal IN is an H signal, the transistor T3 is turned on. As a result, the clocked inverter 201 outputs an L signal. Then, the L signal is input to the inverter 203 and the H signal is output. As a result, the switch 101 is turned on, the transistor T9 is turned off, and the first clock signal CLK1 is supplied to the circuit. Then, the transistor T1 is turned on and the transistor T8 is turned off.

  Next, the case of operation 4 is shown in FIG. The first clock signal CLK1 becomes an H signal, and the second clock signal CLK2 becomes an L signal. Then, since the switch 102 is turned off, the second clock signal CLK2 is not supplied to the circuit. Therefore, the load on the signal line that supplies the second clock signal CLK2 is reduced. Since the transistor T10 is turned on, the wiring CLK2_D becomes an L signal, the transistor T4 is turned off, and the transistor T5 is turned on. On the other hand, since the first clock signal CLK1 is supplied to the circuit, the transistor T1 is turned off and the transistor T8 is turned on. Therefore, nothing is output from the clocked inverter 201 (floating state), and data is continuously held by the inverter 203 and the clocked inverter 202 in the loop portion.

  Next, the case of operation 5 is shown in FIG. The first clock signal CLK1 becomes an L signal, and the second clock signal CLK2 becomes an H signal. At this time, since the switch 101 is in an on state, the first clock signal CLK1 is supplied to the circuit. Therefore, the transistor T1 is turned on and the transistor T8 is turned off. On the other hand, since the input signal IN is an L signal, the transistor T2 is turned on. As a result, the clocked inverter 201 outputs an H signal. Then, as shown in FIG. 9, the H signal is input to the inverter 203, and the L signal is output to the output signal OUT.

As a result, as shown in FIG. 10, the switch 101 is turned off, the transistor T9 is turned on, the wiring CLK1_D becomes an H signal, the transistor T1 is turned off, and the transistor T8 is turned on. Therefore, nothing is output from the clocked inverter 201 (floating state), and data is continuously held by the inverter 203 and the clocked inverter 202 in the loop portion. Since the switch 101 is turned off in this way, the first clock signal CLK1 is not supplied to the circuit. Therefore, the load on the signal line that supplies the first clock signal CLK1 is reduced.

  As described above, the unit register operates. Since the entire shift register is configured by connecting a plurality of unit registers, description of the operation of the entire shift register is omitted.

  Note that a circuit that performs the same operation can be realized in the same manner even if the connection configuration is changed.

  For example, the case where the connection configuration is changed is shown in FIGS. The unit register shown in FIG. 11 includes switches 1101 and 1103, inverters 1102 and 1104, transistors T9 and T10, and a flip-flop circuit 210. One gate electrode of the switch 1101 is connected to the output side of the transistor T9 and the inverter 1102, and the other gate electrode is connected to the input side of the inverter 1102, and the input signal CTR_D￣2 from the flip-flop circuit 210 is supplied. ing. One of the source region and the drain region of the switch 1101 is supplied with the first clock signal CLK1, and the other is connected to the source region or the drain region of the transistor T9 and the wiring CLK1_D￣2. Of the source region or the drain region of the transistor T9, the one not connected to the wiring CLK1_D 2 is connected to the high potential side power supply (Vdd). One gate electrode of the switch 1103 is connected to the output side of the transistor T10 and the inverter 1104, and the other gate electrode is supplied with the input signal IN and connected to the input side of the inverter 1104. One of the source region and the drain region of the switch 1103 is supplied with the second clock signal CLK2, and the other is connected to the source region or the drain region of the transistor T10 and the wiring CLK2_D￣2. Of the source region or the drain region of the transistor T10, the one not connected to the wiring CLK2_D 2 is connected to the low potential side power supply (Vss).

  FIG. 12 shows an internal configuration example of the flip-flop circuit 210. The clocked inverters 1201 and 1202 and a loop portion inverter 1203 are included. The clocked inverter 1201 receives the first and second clock signals from the wiring CLK1_D￣2 and the wiring CLK2_D￣2. The clocked inverter 1202 also receives the first and second clock signals from the wiring CLK1_D￣2 and the wiring CLK2_D￣2, respectively. The input side of the inverter 1203 in the loop portion is connected to the output side of the clocked inverter 1201 and 1202, and the output side of the inverter 1203 is connected to the input side of the clocked inverter 1202, and the output signal OUT_D￣2 is output. . Note that the flip-flop circuit is not limited to the configuration of FIG.

  As shown in FIG. 12, the switch 1101 in FIG. 11 is controlled using an input signal CTR_D 2 to the inverter 1203. In this case, the signal for controlling the switch 1101 is inverted as compared with FIG. Accordingly, the connection relation to the transistor T9 is changed accordingly, and the connection is made through the inverter 1102.

  In FIGS. 1 and 11 and the like, the transistors T9 and T10 are turned on and off using the input signal IN, the output signal OUT, and the like, but the present invention is not limited to this. It is only necessary that the wiring CLK1_D, the wiring CLK2_D, and the like can be prevented from being in a floating state.

FIG. 13 shows a configuration example different from FIGS. The unit register of FIG. 13 includes switches 1301 and 1302, inverters 1303 and 1304, transistors T11 and T12, and a flip-flop circuit 110. One gate electrode of the switch 1301 is connected to the output side of the inverter 1303, and the other is connected to the input side of the inverter 1303, and the output signal OUT_D from the flip-flop circuit 110 is supplied. The first clock signal CLK1 is supplied to one of the source region and the drain region of the switch 1301, and the source region or the drain region of the transistor T11 and the wiring CLK1_D are connected to the other. One gate electrode of the switch 1302 is connected to the output side of the inverter 1304, and the other is connected to the input side of the inverter 1304, and the input signal IN is supplied. The second clock signal CLK2 is supplied to one of the source region and the drain region of the switch 1302, and the source region or the drain region of the transistor T12 and the wiring CLK2_D are connected to the other. Of the source region or drain region of the transistor T11, the high-potential side power supply (Vdd) and the gate electrode of the transistor T12 are connected to the side not connected to the source region or drain region of the switch 1301. Of the source region or drain region of the transistor T12, the low-potential-side power supply (Vss) and the gate electrode of the transistor T11 are connected to the side not connected to the source region or drain region of the switch 1302.

  In order to prevent the wiring CLK1_D, the wiring CLK2_D, and the like from being in a floating state, transistors T11 and T12 that are always in an on state may be provided as illustrated in FIG. Resistors R1 and R2 may be disposed between the wiring CLK2_D and the high potential side power supply (Vdd) or the low potential side power supply (Vss).

  In FIG. 1 or FIG. 3, there are two clock signal lines, but the present invention is not limited to this. An inverted signal may be generated from one clock signal using an inverter. In FIG. 15, the first clock signal CLK1 is supplied to the unit register as it is. On the other hand, the second clock signal CLK2 uses a signal output from the inverter 1501 when the first clock signal CLK1 is input to the inverter 1501. Therefore, the second clock signal CLK2 is supplied from the first clock signal CLK1 to the unit register via the inverter 1501.

  By doing so, the number of clock signal lines can be reduced. By reducing the number of clock signal lines, the configuration of an external IC that supplies a signal to a substrate on which a transistor such as a shift register is formed is simplified. In addition, since the number of signals input from the external IC to the substrate on which the transistor is formed is reduced, the number of connections between the external IC and the substrate is reduced. When the number of connections is reduced, the possibility of failure of connection portions (such as poor contact) is reduced, and reliability is improved.

  In the present embodiment, it is configured to operate at the time of positive logic, but is not limited to this. In order to operate in the negative logic, the configuration may be changed as appropriate. A person skilled in the art can easily change the value.

  In FIG. 2 and the like, the case where a delay flip-flop circuit (DFF) is used as the flip-flop circuit is described, but the present invention is not limited to this. Various types of flip-flop circuits may be used. For example, a flip-flop circuit such as an RS type, JK type, or T type may be used.

  Note that the switches 101 and 102 in FIG. 1 and the like are described as CMOS transistors, but are not limited thereto. Any electrical or mechanical switch can be used. Anything that can control the current flow is acceptable. It may be a transistor, a diode, or a logic circuit combining them. Therefore, when a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desirable that the off-state current is small, it is desirable to use a transistor having a polarity with a small off-state current. As a transistor with low off-state current, there are a transistor provided with an LDD region and a transistor having a multi-gate structure. In addition, when the transistor operated as a switch operates at a source terminal potential close to a low potential power source (Vss, Vgnd, 0 V, etc.), the n-channel type is used. When operating in a state close to a side power supply (Vdd or the like), it is desirable to use a p-channel type. This is because the absolute value of the voltage between the gate and the source can be increased, so that it can easily operate as a switch. Note that a CMOS switch may be formed using both an n-channel type and a p-channel type.

(Embodiment 2)
Hereinafter, in this embodiment mode, structures and operations of a display device, a signal line driver circuit, a gate line driver circuit, and the like will be described. The circuit of the present invention can be applied to part of a signal line driver circuit, a gate line driver circuit, or the like.

  As shown in FIG. 16, the display device includes a pixel array 1601, a gate line driver circuit 1602, and a signal line driver circuit 1610. The gate line driver circuit 1602 sequentially outputs selection signals to the pixel array 1601. The gate line driver circuit 1602 includes a shift register 1621, a buffer circuit 1622, and the like.

  Here, the circuit described in Embodiment 1, for example, the circuits illustrated in FIGS. 1 to 3 and FIGS. 11 to 15 is applied to the shift register 1621; Becomes lighter and the rounding of the waveform of the clock signal is suppressed, so that the circuit can operate normally. In addition, power consumption can be reduced. Further, since the structure is simple, the layout area of the circuit is reduced and the frame can be narrowed. Further, the power consumption of the external IC that supplies the clock signal to the substrate on which the transistor such as the shift register is formed is reduced, and the current supply capability of the external IC that supplies the clock signal can be reduced. Can be reduced in size and cost.

In addition, the gate line driver circuit 1602 may be provided with a level shifter circuit, a pulse width control circuit, or the like. The shift register 1621 outputs pulses that are sequentially selected, and the circuits described in Embodiment Mode 1, for example, the circuits shown in FIGS. 1 to 3 and FIGS. I can do it. The signal line driver circuit 1610 sequentially outputs video signals to the pixel array 1601. The shift register 1603 outputs pulses that are sequentially selected, and the present invention can be applied thereto. The pixel array 1601 displays an image by controlling the state of light according to the video signal. A video signal input from the signal line driver circuit 1610 to the pixel array 1601 is often a current. That is, the display element arranged in each pixel and the element that controls the display element change states according to the video signal (current) input from the signal line driver circuit 1610. Examples of display elements arranged in pixels include EL elements (Electro Luminescence: EL); organic light emitting diodes (OLEDs), and FEDs (field emission displays). Examples include elements and liquid crystals.

  Note that a plurality of gate line driver circuits 1602 and signal line driver circuits 1610 may be provided.

  The signal line driver circuit 1610 is divided into a plurality of parts. Roughly, as an example, it is divided into a shift register 1603, a first latch circuit (LAT1) 1604, a second latch circuit (LAT2) 1605, and a digital / analog conversion circuit 1606. The digital / analog conversion circuit 1606 may have a function of converting voltage into current and a function of performing gamma correction. That is, the digital / analog conversion circuit 1606 may include a circuit for outputting a current (video signal) to the pixel, that is, a current source circuit.

  Depending on the configuration of the pixel, a digital voltage signal for a video signal and a control current for a current source circuit in the pixel may be input to the pixel. In that case, the digital / analog conversion circuit 1606 has a function of converting a voltage into a current instead of a digital / analog conversion function, and a circuit that outputs the current to the pixel as a control current, that is, a current. A source circuit.

  Further, the pixel has a display element such as an EL element. A circuit for outputting a current (video signal) to the display element, that is, a current source circuit is included.

  Therefore, the operation of the signal line driver circuit 1610 will be briefly described. The shift register 1603 receives a clock signal (S-CLK), a start pulse (SP), and a clock inversion signal (S-CLKb), and sequentially outputs sampling pulses according to the timing of these signals.

  Here, since the present invention is applied to the shift register 1603, the load on the wiring for supplying the clock signal is reduced, the waveform rounding of the clock signal is suppressed, and the circuit is likely to operate normally. In addition, power consumption can be reduced. Further, since the structure is simple, the layout area of the circuit is reduced and the frame can be narrowed. Further, the power consumption of the external IC that supplies the clock signal to the substrate on which the transistor such as the shift register is formed is reduced, and the current supply capability of the external IC that supplies the clock signal can be reduced. Can be reduced in size and cost.

  The sampling pulse output from the shift register 1603 is input to the first latch circuit (LAT1) 1604. A video signal is input to the first latch circuit (LAT1) 1604 from the video signal line 1608, and the video signal is held in each column in accordance with the timing at which the sampling pulse is input. In the case where the digital / analog conversion circuit 1606 is provided, the video signal is a digital value. Further, the video signal at this stage is often a voltage.

  However, in the case where the first latch circuit 1604 and the second latch circuit 1605 are circuits that can store analog values, the digital-analog conversion circuit 1606 can often be omitted. In that case, the video signal is often a current. In addition, in the case where data output to the pixel array 1601 is binary, that is, a digital value, the digital / analog conversion circuit 1606 can often be omitted.

  When the first latch circuit (LAT1) 1604 completes holding the video signal up to the last column, a latch pulse (Latch Pulse) is input from the latch control line 1609 during the horizontal blanking period, and the first latch circuit (LAT1) The video signals held in 1604 are transferred to the second latch circuit (LAT2) 1605 all at once. Thereafter, the video signal held in the second latch circuit (LAT2) 1605 is input to the digital / analog conversion circuit 1606 for one row at the same time. A signal output from the digital / analog conversion circuit 1606 is input to the pixel array 1601.

  While the video signal held in the second latch circuit (LAT2) 1605 is input to the digital-analog conversion circuit 1606 and is input to the pixel array 1601, the sampling pulse is output again in the shift register 1603. That is, two operations are performed simultaneously. Thereby, line-sequential driving becomes possible. Thereafter, this operation is repeated.

  Note that in the case where the current source circuit included in the digital-analog converter circuit 1606 is a circuit that performs a setting operation and an output operation, that is, when a current is input from another current source circuit, the characteristics of the transistor In the case of a circuit that can output a current that is not affected by variations, a circuit that allows current to flow is required for the current source circuit. In such a case, a reference current source circuit 1614 is arranged.

  Note that the signal line driver circuit and a part thereof (such as a current source circuit and an amplifier circuit) do not exist on the same substrate as the pixel array 1601 and may be configured using, for example, an external IC chip.

  Note that the structures of the signal line driver circuit, the gate line driver circuit, and the like are not limited to those in FIGS.

  For example, when the first latch circuit 1604 and the second latch circuit 1605 are circuits that can store analog values, as shown in FIG. 17, the reference current source circuit 1614 transfers the video to the first latch circuit (LAT1) 1604. A signal (analog current) may be input. Further, in FIG. 17, the second latch circuit 1605 may not exist. In such a case, more current source circuits are often arranged in the first latch circuit 1604. Alternatively, it may be constituted by a shift register and a sampling switch. In this case, dot sequential driving is performed.

  Note that as described above, the transistor in the present invention may be any type of transistor, and may be formed on any substrate. Therefore, the circuits as shown in FIGS. 16 and 17 may all be formed on a glass substrate, may be formed on a plastic substrate, may be formed on a single crystal substrate, It may be formed on an SOI substrate, or may be formed on any substrate. Alternatively, a part of the circuit in FIGS. 16 and 17 may be formed on a certain substrate, and another part of the circuit in FIGS. 16 and 17 may be formed on another substrate. That is, all the circuits in FIGS. 16 and 17 may not be formed on the same substrate. For example, in FIGS. 16 and 17, the pixel array 1601 and the gate line driver circuit 1602 are formed using a TFT over a glass substrate, and the signal line driver circuit 1610 (or part thereof) is formed over a single crystal substrate. The IC chip may be connected to the glass substrate by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed board.

  Although this embodiment mode describes the case where the present invention is applied to a display device, the present invention is not limited to this. The present invention can be applied to the case where a circuit that outputs signals that are sequentially selected is required. Therefore, the present invention can be applied to a storage device such as a memory. For example, the present invention can also be applied to nonvolatile memories such as mask ROM, DRAM, SRAM, and flash memory. Further, the present invention can be applied to an image sensor having a photoelectric conversion element. As a system, it can be applied to various types of image sensors such as a CMOS sensor and a CCD sensor.

  Note that the contents described in the present embodiment correspond to those using the contents described in the first embodiment. Therefore, the content described in Embodiment Mode 1 can be applied to this embodiment mode.

(Embodiment 3)
In this embodiment, a structure of a display panel including the shift register described in Embodiment 1 is described with reference to FIGS.

  22A is a top view showing the display panel, and FIG. 22B is a cross-sectional view of FIG. 22A taken along line A-A ′. A signal line driver circuit 2001, a pixel portion 2002, and a scan line driver circuit 2006 indicated by dotted lines are included. In addition, a sealing substrate 2004 and a sealing material 2005 are provided, and an inner side surrounded by the sealing material 2005 is a space 2007. The shift register of the present invention is provided in the signal line driver circuit 2001 and the scan line driver circuit 2006.

  Note that the wiring 2008 is a wiring for transmitting a signal input to the scan line driver circuit 2006 and the signal line driver circuit 2001, and a video signal, a clock signal, an FPC (flexible printed circuit) 2009 serving as an external input terminal, Receive a start signal, etc. An IC chip (semiconductor chip on which a memory circuit, a buffer circuit, and the like are formed) 2019 is mounted on a joint portion between the FPC 2009 and the display panel by COG (Chip On Glass) or the like. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC.

  Next, a cross-sectional structure will be described with reference to FIG. A pixel portion 2002 and its peripheral driver circuits (a scanning line driver circuit 2006 and a signal line driver circuit 2001) are formed over the substrate 2010. Here, the signal line driver circuit 2001 and the pixel portion 2002 are shown. Yes.

  Note that the signal line driver circuit 2001 may include a CMOS including a P-channel TFT 2020 and an N-channel TFT 2021. Note that in this embodiment mode, a display panel in which a peripheral driver circuit is integrally formed over a substrate is shown; however, this is not necessarily required, and all or part of the peripheral driver circuit is formed on an IC chip or the like and mounted with COG or the like. You may do it.

  The pixel portion 2002 includes a plurality of circuits that form a pixel including a switching TFT 2011 and a driving TFT 2012. Note that a source electrode or a drain electrode of the driving TFT 2012 is connected to the first electrode 2013. An insulator 2014 is formed so as to cover an end portion of the first electrode 2013. Here, a positive photosensitive acrylic resin film is used.

  In order to improve the coverage of a light-emitting layer including an electrode or an organic compound to be formed later, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the insulator 2014. For example, in the case where positive photosensitive acrylic is used as a material for the insulator 2014, it is preferable that only the upper end portion of the insulator 2014 has a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulator 2014, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used.

  On the first electrode 2013, a layer containing an organic compound (electroluminescent layer) 2016 and a second electrode 2017 are formed. Here, as a material used for the first electrode 2013 functioning as an anode, a material having a high work function is preferably used. For example, ITO (Indium Tin Oxide) film, Indium Zinc Oxide (IZO) film, Titanium nitride film, Chromium film, Tungsten film, Zn film, Pt film, etc., as well as titanium nitride and aluminum as main components And a three-layer structure of a titanium nitride film, a film containing aluminum as its main component, and a titanium nitride film can be used. Note that, when a stacked structure is used, resistance as a wiring is low and good ohmic contact can be obtained.

  The layer 2016 containing an organic compound is formed by an evaporation method using an evaporation mask or an inkjet method. For the layer 2016 containing an organic compound, an element periodic group 4 metal complex is used as a part thereof, and other materials that can be used in combination include high molecular weight materials even if they are low molecular weight materials. It may be. In addition, as a material used for the layer 2016 including an organic compound, an organic compound is usually used in a single layer or a stacked layer. In this embodiment, an inorganic compound is used for part of a film formed of the organic compound. The configuration is also included. Further, a known triplet material can be used.

Further, as a material used for the second electrode (cathode) 2017 formed on the layer 2016 containing an organic compound, a material having a low work function (Al, Ag, Li, Ca, or alloys thereof MgAg, MgIn, AlLi , CaF ₂ , or CaN) may be used. Note that in the case where light generated in the electroluminescent layer 2016 is transmitted through the second electrode 2017, a thin metal film and a transparent conductive film (ITO (indium oxide) are used as the second electrode (cathode) 2017. A stack with a tin oxide alloy), an indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like) is preferably used.

  Further, the sealing substrate 2004 is bonded to the substrate 2010 with a sealing material 2005, whereby the light-emitting element 2018 is provided in a space 2007 surrounded by the substrate 2010, the sealing substrate 2004, and the sealing material 2005. Note that the space 2007 includes a structure filled with a sealing material 2005 in addition to a case where the space 2007 is filled with an inert gas (nitrogen, argon, or the like).

  Note that an epoxy-based resin is preferably used for the sealing material 2005. Moreover, it is desirable that these materials are materials that do not transmit moisture and oxygen as much as possible. In addition to a glass substrate and a quartz substrate, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, acrylic, or the like can be used as a material for the sealing substrate 2004.

  As described above, a display panel having the shift register of the present invention can be obtained.

  Since the present invention is applied to the shift register included in the signal line driver circuit 2001 and the scan line driver circuit 2006 of the display panel illustrated in FIG. 22, waveform rounding of the clock signal is suppressed, and the circuit is likely to operate normally. . In addition, power consumption can be reduced. In addition, since the configuration is simple, the layout area of the circuit is reduced and the frame can be narrowed.

  Note that the structure of the display panel is not limited to the structure in which the signal line driver circuit 2001, the pixel portion 2002, and the scanning line driver circuit 2006 are integrally formed as shown in FIG. A corresponding signal line driver circuit 4201 shown in FIG. 23 may be formed over an IC chip and mounted on a display panel with COG or the like. Note that the substrate 4200, the pixel portion 4202, the scan line driver circuit 4203, the FPC 4205, the IC chip 4206, the sealing substrate 4208, and the sealant 4209 in FIG. 23 are the substrate 2010, the pixel portion 2002, and the scan line driver circuit in FIG. 2006, FPC 2009, IC chip 2019, sealing substrate 2004, and sealant 2005.

That is, only the signal line driver circuit that requires high-speed operation of the driver circuit is formed on the IC chip using CMOS or the like. By including the shift register of the present invention in the signal line driver circuit, the pixel portion can easily operate normally and low power consumption can be achieved. Further, by using a semiconductor chip such as a silicon wafer as the IC chip, higher speed operation and lower power consumption can be achieved.

(Embodiment 4)
As an electronic device using the present invention, a video camera, a digital camera, a goggle type display, a navigation system, a sound reproduction device (car audio, audio component, etc.), a personal computer, a game device, a portable information terminal (mobile computer, cellular phone, Portable game machines, electronic books, etc.), image playback devices equipped with recording media (specifically, devices equipped with a display that can play back recording media such as Digital Versatile Disk (DVD) and display the images), etc. Is mentioned. Specific examples of these electronic devices are shown in FIGS.

  FIG. 18A illustrates a light-emitting device, which includes a housing 13001, a support base 13002, a display portion 13003, a speaker portion 13004, a video input terminal 13005, and the like. The present invention can be used for a semiconductor device included in the display portion 13003. Further, according to the present invention, the light-emitting device shown in FIG. 18A is completed. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. The light emitting device includes all display devices for displaying information such as a computer, a TV broadcast receiver, and an advertisement display.

  By using the present invention, the light emitting device can easily operate normally, power consumption can be reduced, and the device can be reduced in size and cost.

  FIG. 18B shows a digital still camera, which includes a main body 13101, a display portion 13102, an image receiving portion 13103, operation keys 13104, an external connection port 13105, a shutter 13106, and the like. The present invention can be used for a semiconductor device included in the display portion 13102. Further, according to the present invention, the digital still camera shown in FIG. 18B is completed.

  By using the present invention, the display portion can easily operate normally, power consumption can be reduced, and the size and cost of the device can be reduced.

  FIG. 18C illustrates a laptop personal computer, which includes a main body 13201, a housing 13202, a display portion 13203, a keyboard 13204, an external connection port 13205, a pointing mouse 13206, and the like. The present invention can be used for a semiconductor device included in the display portion 13203. Further, according to the present invention, the light emitting device shown in FIG. 18C is completed.

  By using the present invention, the light emitting device can easily operate normally, power consumption can be reduced, and the device can be reduced in size and cost.

  FIG. 18D illustrates a mobile computer, which includes a main body 13301, a display portion 13302, a switch 13303, operation keys 13304, an infrared port 13305, and the like. The present invention can be used for a semiconductor device included in the display portion 13302. Further, according to the present invention, the mobile computer shown in FIG. 18D is completed.

  By using the present invention, the display portion can easily operate normally, power consumption can be reduced, and the size and cost of the device can be reduced.

  FIG. 18E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 13401, a housing 13402, a display portion A13403, a display portion B13404, and a recording medium (such as a DVD). A reading unit 13405, operation keys 13406, a speaker unit 13407, and the like are included. Although the display portion A 13403 mainly displays image information and the display portion B 13404 mainly displays character information, the present invention can be used for a semiconductor device included in the display portions A, B 13403, and 13404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like. Further, according to the present invention, the DVD reproducing apparatus shown in FIG.

  By using the present invention, the display portion can easily operate normally, power consumption can be reduced, and the size and cost of the device can be reduced.

  FIG. 18F illustrates a goggle type display (head mounted display), which includes a main body 13501, a display portion 13502, and an arm portion 13503. The present invention can be used for a semiconductor device included in the display portion 13502. Further, the goggle type display shown in FIG. 18F is completed by the present invention.

  By using the present invention, the display portion can easily operate normally, power consumption can be reduced, and the size and cost of the device can be reduced.

  FIG. 18G illustrates a video camera, which includes a main body 13601, a display portion 13602, a housing 13603, an external connection port 13604, a remote control reception portion 13605, an image receiving portion 13606, a battery 13607, an audio input portion 13608, operation keys 13609, and an eyepiece Part 13610 and the like. The present invention can be used for a semiconductor device included in the display portion 13602. The video camera shown in FIG. 18G is completed by the present invention.

  By using the present invention, the display portion can easily operate normally, power consumption can be reduced, and the size and cost of the device can be reduced.

  FIG. 18H illustrates a mobile phone, which includes a main body 13701, a housing 13702, a display portion 13703, an audio input portion 13704, an audio output portion 13705, operation keys 13706, an external connection port 13707, an antenna 13708, and the like. The present invention can be used for a semiconductor device included in the display portion 13703. Note that the display portion 13703 can suppress current consumption of the mobile phone by displaying white characters on a black background. Further, the mobile phone shown in FIG. 18H is completed by the present invention.

  By using the present invention, the display portion can easily operate normally, power consumption can be reduced, and the size and cost of the device can be reduced.

  If the emission luminance of the luminescent material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like to be used for a front type or rear type projector.

  In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the response speed of the light emitting material is very high, the light emitting device is preferable for displaying moving images.

  In addition, since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background. It is desirable to do.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic device of this embodiment may use the semiconductor device having any structure described in Embodiments 1 and 2.

6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 8A and 8B illustrate signal timing of a semiconductor device of the present invention. 8A and 8B illustrate operation of a semiconductor device of the present invention. 8A and 8B illustrate operation of a semiconductor device of the present invention. 8A and 8B illustrate operation of a semiconductor device of the present invention. 8A and 8B illustrate operation of a semiconductor device of the present invention. 8A and 8B illustrate operation of a semiconductor device of the present invention. 8A and 8B illustrate operation of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. FIG. 10 illustrates a structure of a display device to which the present invention is applied. FIG. 10 illustrates a structure of a display device to which the present invention is applied. 1 is a diagram of an electronic device to which the present invention is applied. 6A and 6B illustrate a structure of a conventional semiconductor device. 6A and 6B illustrate a structure of a conventional semiconductor device. 6A and 6B illustrate a structure of a conventional semiconductor device. 8A and 8B illustrate a structure of a display panel to which the present invention is applied. 8A and 8B illustrate a structure of a display panel to which the present invention is applied.

Explanation of symbols

101 switch 102 switch 103 transistor 104 transistor 105 inverter 106 inverter 110 flip-flop circuit 201 clocked inverter 202 clocked inverter 203 inverter 210 flip-flop circuit

Claims (12)

A shift register having a flip-flop circuit, a first switch, a second switch, a first wiring, and a circuit having a second wiring electrically connected in multiple stages;
The first wiring is electrically connected to the first terminal of the flip-flop circuit through the first switch,
The second wiring is electrically connected to the second terminal of the flip-flop circuit through the second switch,
A signal output from the output terminal of the flip-flop circuit is input to the control terminal of the first switch ,
Wherein the control terminal of the second switch, and wherein a signal inputted to the input terminal of the flip-flop circuit is inputted. Shift in which a circuit having a flip-flop circuit, a first switch, a second switch, a first wiring, a second wiring, a first transistor, and a second transistor is electrically connected in multiple stages Has a register,
The first wiring is electrically connected to a first terminal of the flip-flop circuit through the first switch,
The second wiring is electrically connected to a second terminal of the flip-flop circuit through the second switch,
One of a source and a drain of the first transistor is electrically connected to a third wiring;
The other of the source and the drain of the first transistor is electrically connected to the first terminal;
One of a source and a drain of the second transistor is electrically connected to a fourth wiring;
The other of the source and the drain of the second transistor is electrically connected to the second terminal;
A signal output from the output terminal of the flip-flop circuit is input to the control terminal of the first switch and the gate of the first transistor,
  A semiconductor device, wherein a signal input to an input terminal of the flip-flop circuit is input to a control terminal of the second switch and a gate of the second transistor. In claim 2,
When the first transistor is on, the first switch is off; when the first transistor is off, the first switch is on;
The semiconductor device, wherein the second switch is turned off when the second transistor is on, and the second switch is turned on when the second transistor is off. Shift in which a circuit having a flip-flop circuit, a first switch, a second switch, a first wiring, a second wiring, a first transistor, and a second transistor is electrically connected in multiple stages Has a register,
The first wiring is electrically connected to a first terminal of the flip-flop circuit through the first switch,
The second wiring is electrically connected to a second terminal of the flip-flop circuit through the second switch,
One of a source and a drain of the first transistor is electrically connected to a third wiring;
The other of the source and the drain of the first transistor is electrically connected to the first terminal;
One of a source and a drain of the second transistor is electrically connected to a fourth wiring;
The other of the source and the drain of the second transistor is electrically connected to the second terminal;
A gate of the first transistor is electrically connected to the fourth wiring;
A gate of the second transistor is electrically connected to the third wiring;
A signal output from the output terminal of the flip-flop circuit is input to the control terminal of the first switch,
  The semiconductor device according to claim 1, wherein a signal input to an input terminal of the flip-flop circuit is input to the control terminal of the second switch. Shift in which a circuit having a flip-flop circuit, a first switch, a second switch, a first wiring, a second wiring, a first resistor, and a second resistor is electrically connected in a plurality of stages Has a register,
The first wiring is electrically connected to a first terminal of the flip-flop circuit through the first switch,
The second wiring is electrically connected to a second terminal of the flip-flop circuit through the second switch,
One terminal of the first resistor is electrically connected to a third wiring;
The other terminal of the first resistor is electrically connected to the first terminal;
One terminal of the second resistor is electrically connected to a fourth wiring;
The other terminal of the second resistor is electrically connected to the second terminal;
A signal output from the output terminal of the flip-flop circuit is input to the control terminal of the first switch,
  The semiconductor device according to claim 1, wherein a signal input to an input terminal of the flip-flop circuit is input to the control terminal of the second switch. In any one of Claims 1 thru | or 5,
  At least one of the first switch and the second switch is a transistor. In any one of Claims 1 thru | or 6 ,
At least one of the first switch and the second switch is composed of a complementary transfer gate. In any one of Claims 1 thru | or 7,
The semiconductor device, wherein the first wiring is electrically connected to the second wiring through an inverter. 9. The semiconductor device according to claim 1, wherein on / off of the first switch and the second switch is individually controlled.   The first clock signal is input to the first wiring according to any one of claims 1 to 9,
  A semiconductor device, wherein a second clock signal that is an inverted signal of the first clock signal is input to the second wiring. It said semiconductor device according to any one of claims 1 to 10, the display device being characterized in that a display unit. An electronic apparatus characterized by comprising said display device; and a manipulation key or speakers to claim 11.

Images