JP4753709B2 - Data multiplexing storage device and processing device - Google Patents

Description

  The present invention relates to a data storage device, and more particularly, to a multiplexed storage device, a processing device, and the like that can suppress the storage capacity by multiplexing and storing data as compared with the case of individually storing data.

  An FPGA (Field Programmable Gate Array) is an LSI (Large Scale Integrated circuit) in which circuit data can be written and a circuit configuration can be designed relatively freely. The FPGA includes a basic cell composed of a look-up table (LUT) for storing a truth table and an output flip-flop, a programmable wiring resource connecting the basic cells, a memory for storing setting data and intermediate data, and the like. including. In the FPGA, a desired logical operation can be realized by writing data stored in the LUT and wiring data. However, when an LSI is designed with an FPGA, the mounting area is very large and the cost is high compared to the design with an ASIC (Application Specific Integrated Circuit). Therefore, a method has been proposed in which the circuit configuration is reused by dynamically reconfiguring the FPGA (see, for example, Patent Document 1).

  For example, in satellite broadcasting, the image quality may be adjusted by switching the broadcasting mode depending on the season. For this reason, in a conventional receiver, a plurality of circuits are built in hardware for each broadcast mode in advance, and the circuit is switched by a selector according to the broadcast mode for reception. Therefore, the other broadcast mode circuits of the receiver are idle during that time.

When switching between multiple dedicated circuits, such as mode switching, and when the switching interval is relatively long, instead of creating multiple dedicated circuits, the LSI can be reconfigured at the time of switching. This makes it simple to increase versatility and reduce mounting costs. In order to meet such needs, there is an increasing interest in dynamically reconfigurable LSIs. In particular, LSIs governed by mobile terminals such as mobile phones and PDAs (Personal Data Assistants) must be downsized, and if LSIs can be dynamically reconfigured and the functions can be switched appropriately according to the application, The mounting area can be kept small.
Japanese Patent Laid-Open No. 10-256383 (full text, FIGS. 1 to 4)

  As described above, the FPGA has a high degree of freedom in design of the circuit configuration and is versatile. On the other hand, in order to enable connection between basic cells, a control circuit for controlling ON / OFF of a large number of switches and switches is provided. It is necessary to include, and the mounting area becomes large. On the other hand, due to demands for downsizing and high-density mounting of devices, downsizing of FPGAs is also demanded, and the size of memory and the like is also limited. For this reason, it is desired that a limited amount of memory can be used more effectively as the required functions become more sophisticated.

  In particular, in the case of a dynamically reconfigurable FPGA, for example, the FPGA is configured in a first processing circuit, the processing result is stored in a memory, and then the FPGA is configured in a second processing circuit. It is also possible to perform processing such as additional processing of the processing result. In such a case, depending on the application, a large amount of intermediate data and final data are generated, and it is necessary to effectively use a limited amount of memory.

  The problem of effective use of memory is a problem that exists in common in various processing circuits, not limited to FPGAs, in recent processing circuits that require higher density and higher function.

The present invention has been made in view of the above situation, and an object thereof is to provide a storage device that can effectively or efficiently use a limited storage capacity and a processing circuit using the storage device.
Another object of the present invention is to contribute to reducing the circuit scale of an integrated circuit.

In order to achieve the above object, a data multiplexing storage device according to the first aspect of the present invention provides:
A memory for storing data at a predetermined data size at each address position;
Storage means for multiplexing a plurality of data and storing them at each address of the memory;
Data reproduction means for reproducing the original data by reading and separating the data stored in each address position of the memory;
It is characterized by providing.

  According to a predetermined standard, data is switched between being stored and not multiplexed at each address of the memory, and the data stored at each address of the memory is divided or not divided You may arrange | position the switching control means which switches and controls these.

  Whether the switching control means multiplexes based on at least one of relevance of data to be multiplexed, memory access time, memory access processing amount, memory usage, processing speed, for example. Means for determining whether or not.

  For example, the storage means multiplexes a pair of complex data and stores it in one address position of the memory, and the data reproduction means divides the data read from one address position of the memory, thereby The pair of data is reproduced.

  For example, the storage means multiplexes a plurality of data to be accessed in order in a predetermined number of consecutive data units and stores them in the memory, and the data reproduction means stores the data multiplexed from each address position. Are sequentially read and divided to reproduce a plurality of data to be accessed in the order.

  For example, the storage means multiplexes a pair of correlated data and stores them in the memory at each address position, and the data reproduction means sequentially reads and divides the multiplexed data from each address position. Thus, a pair of correlated data is reproduced.

  For example, the storage means does not perform data multiplexing when there is no data to be accessed at the same time and the amount of data multiplexing / demultiplexing processing is greater than a predetermined value.

  The data multiplexing storage device having the above configuration is suitable for use in a processing device. In this case, the data processed by the processing means is processed and supplied to the storage means and multiplexed and stored in the memory, or the data reproduced by the data reproduction means is processed by the processing means.

  It is also possible to supply the data processed by the reconfigurable circuit to the storage means and store the data multiplexed in the memory, or to process the data reproduced by the data reproduction means by the reconfigurable circuit. is there. In this case, for example, the reconfigurable circuit supplies the data processed by the first circuit configuration to the storage means, multiplexes and stores the data in the memory, and changes the circuit configuration to the second circuit configuration by the setting means. After the switching, the data read from the memory via the data reproducing means may be processed. With such a configuration, the size of the entire circuit can be reduced by suppressing the size of the memory as compared with the case where data is stored in the memory without being multiplexed. If the overall size is not changed, the size of the reconfigurable circuit can be increased.

  According to the present invention, since a plurality of data is multiplexed and stored in the memory, a large amount of data can be stored as compared with the case where the data is not multiplexed.

Hereinafter, a processing device 10 including a multiplexed storage device according to an embodiment of the present invention will be described.
The processing apparatus 10 includes an integrated circuit device 26 as shown in FIG. The integrated circuit device 26 has a function that makes it possible to reconfigure the circuit configuration. The integrated circuit device 26 is configured by one chip, and includes a reconfigurable circuit 12, a setting unit 14, a control unit 18, a memory 20, an output circuit 22, a memory control circuit 24, a bus 42, and a register group 44. , 46.

  The reconfigurable circuit 12 can change the function by changing the setting.

  The setting unit 14 includes a first setting unit 14a, a second setting unit 14b, a third setting unit 14c, a fourth setting unit 14d, and a selector 16, and configures an intended circuit in the reconfigurable circuit 12. The setting data 40 is supplied.

The register group 46 primarily stores the intermediate output data of the reconfigurable circuit 12.
The bus 42 functions as a feedback path, and connects the intermediate output of the reconfigurable circuit 12 to the input of the reconfigurable circuit 12.
The register group 44 temporarily stores the intermediate output data fed back via the bus and supplies it to the input of the reconfigurable circuit 12.

  The memory 20 is a memory circuit having a storage capacity of 1 word (2 bytes (16 bits)) at each address position (1 address), and includes a DRAM (Dinamic Randam Access Memory) or the like. The memory 20 multiplexes the intermediate data output from the reconfigurable circuit 12 to save the storage capacity and store it.

  The output circuit 22 includes a sequential circuit such as a data flip-flop (D-FF) and receives the output of the reconfigurable circuit 12.

  The memory control circuit 24 multiplexes the intermediate data output from the reconfigurable circuit 12 and stores the multiplexed data in the memory 20. The memory control circuit 24 reproduces the original two data by separating the data read from the memory 20. Output above. The memory data multiplexing process and the original data restoring process performed by the memory control circuit 24 will be described later with reference to FIG.

  The reconfigurable circuit 12 is configured as a logic circuit such as a combinational circuit or a sequential circuit.

  The reconfigurable circuit 12 includes a logic circuit whose function can be changed. Specifically, the reconfigurable circuit 12 has a configuration in which a plurality of logic circuits capable of selectively executing a plurality of arithmetic functions are arranged in a plurality of stages, and an output of a preceding logic circuit string and an input of a succeeding logic circuit string The connection part which can set the connection relation with is included. The plurality of logic circuits are arranged in a matrix. The function of each logic circuit and the connection relationship between the logic circuits are set based on setting data 40 supplied by the setting unit 14. The setting data 40 is generated by the following procedure.

  A program 36 to be realized by the integrated circuit device 26 is held in the storage unit 34. The program 36 describes a signal processing circuit or a signal processing algorithm in a high-level language such as C language. A compiling unit 30 for compiling the program 36 stored in the storage unit 34, converting it into a data flow graph 38 and storing it in the storage unit 34 is arranged in the processing apparatus 10. The data flow graph 38 expresses the flow of calculation of input variables and constants in a graph structure.

  Further, the setting data generation unit 32 provided in the storage unit 34 generates setting data 40 from the data flow graph 38. The setting data 40 is data for mapping the data flow graph 38 to the reconfigurable circuit 12 and determines the function of the logic circuit in the reconfigurable circuit 12 and the connection relationship between the logic circuits. In the present embodiment, the setting data generation unit 32 generates setting data 40 for a plurality of circuits obtained by dividing one generation target circuit 60.

  FIG. 2 is a diagram for explaining the setting data 40 of a plurality of circuits obtained by dividing one arbitrary generation target circuit 60. A circuit generated by dividing one generation target circuit 60 is referred to as a “divided circuit”. In the example of FIG. 2, one generation target circuit 60 is divided into four divided circuits, that is, a divided circuit A, a divided circuit B, a divided circuit C, and a divided circuit D. The generation target circuit 60 is divided according to the calculation flow in the data flow graph 38. In the data flow graph 38, when the calculation flow is expressed in a direction from the top to the bottom, the data flow graph 38 is cut from the top at a predetermined interval, and the cut portion is set as a dividing circuit. The interval to be cut according to the flow is determined to be equal to or less than the number of logic circuit stages in the reconfigurable circuit 12.

  The output data (intermediate data) of each division circuit is multiplexed and efficiently stored in the memory 20, and after the circuit configuration of the reconfigurable circuit 12 is switched, it is read out, separated, and supplied to the input. .

  The arbitrary generation target circuit 60 may be divided in the horizontal direction of the data flow graph 38. The width to be divided in the horizontal direction is determined to be equal to or less than the number of logic circuits in the reconfigurable circuit 12 per stage.

  In particular, when the generation target circuit 60 is larger than the reconfigurable circuit 12, the setting data generation unit 32 preferably divides the generation target circuit 60 so that the setting data generation unit 32 has a size that can be mapped to the reconfigurable circuit 12. . The setting data generation unit 32 determines the division method of the generation target circuit 60 based on the arrangement structure of the logic circuits in the reconfigurable circuit 12 and the data flow graph 38. The arrangement structure of the reconfigurable circuit 12 may be transmitted from the control unit 18 to the setting data generation unit 32 or may be recorded in the storage unit 34 in advance. In addition, the control unit 18 may instruct the setting data generation unit 32 on how to divide the generation target circuit 60.

  By executing the above procedure, the storage unit 34 stores a plurality of setting data 40 for configuring the reconfigurable circuit 12 as the intended generation target circuit 60. The plurality of setting data 40 constitute setting data A for configuring the dividing circuit A, setting data B for configuring the dividing circuit B, setting data C for configuring the dividing circuit C, and dividing circuit D. This is setting data D.

  FIG. 3 is a configuration diagram of the reconfigurable circuit 12. The reconfigurable circuit 12 includes a plurality of columns of logic circuits 50 arranged in a plurality of stages, and the connection unit 52 provided in each stage outputs the output of the column of the logic circuit 50 in the preceding stage and the logic circuit 50 in the subsequent stage. The input of the column of can be connected arbitrarily by setting. Each logic circuit 50 includes, for example, an ALU (arithmetic logic unit) that can selectively execute a plurality of types of multi-bit operations such as logical sum, logical product, and bit shift by setting.

  As shown in FIG. 3, the reconfigurable circuit 12 is configured as an array of ALUs 50 in which Y ALUs 50 in the horizontal direction and X ALUs 50 in the vertical direction are arranged. Input variables and constants are input to the first-stage ALU11, ALU12,..., ALU1Y, and a set predetermined calculation is performed. The output of the calculation result is input to the second-stage ALU 21, ALU 22,..., ALU 2Y according to the connection set in the first-stage connection unit 52. In the first-stage connection unit 52, an arbitrary connection relationship between the output of the column of the first-stage ALU 50 and the input of the column of the second-stage ALU 50, or a connection selected from a predetermined combination The connection is configured so that the relationship can be realized, and the intended connection is enabled by setting. Hereinafter, the connection section 52 of the (X-1) th stage has the same configuration, and the column of the ALU 50 of the Xth stage, which is the final stage, outputs the final result of the calculation.

  Returning to FIG. 1, when configuring the reconfigurable circuit 12, the control unit 18 selects a plurality of setting data 40 for configuring one generation target circuit 60. Here, the control unit 18 sets the setting data 40 for configuring the generation target circuit 60 shown in FIG. 2, that is, the setting data A of the dividing circuit A, the setting data B of the dividing circuit B, the setting data C of the dividing circuit C, and Assume that the setting data D of the dividing circuit D is selected. The control unit 18 supplies the selected setting data 40 to the setting unit 14. The setting unit 14 includes a cache memory and other types of memory, and holds the supplied setting data 40.

  The setting unit 14 sets the selected setting data 40 in the reconfigurable circuit 12 and reconfigures the circuit of the reconfigurable circuit 12. As a result, the reconfigurable circuit 12 can execute a desired calculation.

Next, the configuration and operation of the memory 20, the memory control circuit 24, the bus 42, and the register groups 44 and 46 shown in FIG. 1 will be described with reference to FIG.
Of the data output from the reconfigurable circuit 12, final output data is output to the outside of the integrated circuit device 26 via the output circuit 22. On the other hand, intermediate output data (intermediate data) is output through a register group 46 including a plurality of output registers 46a to 46c. The intermediate data is supplied to the multiplexing circuit 241 constituting the memory control circuit 24 under the control of the control unit 18. The multiplexing circuit 241 multiplexes two pieces of data and stores them in the memory 20 to effectively use the memory space.

Here, the multiplexing process executed by the multiplexing circuit 241 will be described.
In this embodiment, as shown in FIG. 5A, each address position (access unit) of the memory 20 has a capacity of 1 word (2 bytes), and the intermediate data output from the reconfigurable circuit 12 As shown in FIG. 5B, although it has a 1-word configuration, at least the upper 1 byte (8 bits) is all “0” invalid data, and only the lower 1 byte is valid (effective) data. Shall.

  Even in such a case, normally, one data is stored at one address.

  However, in the present embodiment, the multiplexing circuit 241 makes effective use of the memory 20 by multiplexing two pieces of data and storing them in one address of the memory 20.

First, it is assumed that the data to be multiplexed by the multiplexing circuit 241 is 2-byte data D1 and D2 shown in FIG. The multiplexing circuit 241 shifts one data, for example, the data D2 by 8 bits in the upper (MSB) direction. At this time, bit data “0” is supplied to each lower bit. Subsequently, the logical sum of the other data D1 and the shifted one data D2 is taken, and both data are multiplexed to generate multiplexed data including D1 in the lower 1 byte and D2 in the upper 1 byte.
The multiplexing circuit 241 stores the multiplexed data generated in this way at an appropriate address position in the memory 20.

  When reading the data stored in this way, the separation circuit 242 constituting the memory control circuit 24 reads the 2-byte data to be read according to the control of the control unit 18 as shown in FIG. The data D1 stored in the lower 1 byte of the read 1 word data is restored by reading and taking the logical product with the data 0Fh (0000000011111111).

  Further, by shifting the read 2-byte data by 8 bits in the lower direction, the data D2 stored in the upper 1 byte of the read 1-word data is restored. At this time, 0 is supplied to the upper bits.

  The separation circuit 242 supplies the read two reproduced data to, for example, the input register group 46 via the bus 42 and supplies the input register group 46 with the input.

  Next, the operation of the processing apparatus 10 having the above-described configuration will be described by taking as an example the case where the generation target circuit 60 is a QPKS (quadrature phase shift keying) modulation signal demodulation (orthogonal detection) circuit illustrated in FIG.

First, the demodulation circuit shown in FIG. 6 will be described.
The tuning circuit 104 tunes to a target frequency and receives a signal via the antenna 102. The received signal is subjected to processing such as amplification, then converted to a digital signal by an A / D (analog / digital) conversion circuit 106 and temporarily stored in the buffer circuit 108.

The data stored in the buffer circuit 108 is supplied to the mixers 110 and 114.
The mixer 110 mixes the supplied reception signal and the cosine signal (cosωt) to generate an in-phase component signal I, which is filtered by a low-pass filter (LPF) 112 to generate an in-phase component FI.

  The mixer 114 mixes the supplied reception signal and the sine signal (sin ωt) to generate a quadrature component signal Q, which is filtered by a low-pass filter (LPF) 116 to generate a quadrature component FQ.

In order to realize such a configuration, the reconfigurable circuit 12 is first configured as mixers (multipliers) 110 and 114 according to the setting of the first setting unit 14a, and the in-phase component I and the quadrature component for one frame. Q is calculated. The obtained in-phase component I and quadrature component Q for one frame are multiplexed by the multiplexing circuit 241 and stored in the memory 20. Subsequently, the reconfigurable circuit 12 is reconfigured as low-pass filters 112 and 116. The in-phase component I and the quadrature component Q for one frame stored in the memory 20 are sequentially read and separated by the separation circuit 242 and input to the input of the reconfigurable circuit 12. The reconfigurable circuit 12 filters the in-phase component I and the quadrature component Q to obtain the in-phase component FI and the quadrature component FQ, and outputs them to the outside via the output circuit 22.
This process is repeated for each frame.

  While the reconfigurable circuit 12 operates as the mixers 110 and 114, at each address position in the memory 20, as shown in FIG. 7, corresponding data of the in-phase component data I and the quadrature component data Q are present. Multiplexed and stored.

  That is, the in-phase component I (x) and the quadrature component Q (x) are output from the reconfigurable circuit 12, and are multiplexed by the multiplexing circuit 241 to generate multiplexed data I (x) Q (x). This is stored in one address location. Thereafter, I (x + 1) and Q (x + 1), I (x + 2) and Q (x + 2),. . Are sequentially output, and the multiplexed data 241 outputs multiplexed data I (x + 1) Q (x + 1), I (x + 2) Q (x + 2),. . Are generated and stored while sequentially updating the addresses.

  On the other hand, while the reconfigurable circuit 12 operates as a low-pass filter, multiplexed data I (x) Q (x), I of the in-phase component data I and the quadrature component data Q from each address position in the memory 20. (X + 1) Q (x + 1), I (x + 2) Q (x + 2),. . Is read out. Then, the separation circuit 242 separates the in-phase component and the quadrature component, and the original data I (x) and Q (x), I (x + 1) and Q (x + 1), I (x + 2) and Q (x + 2) ,. . Are sequentially reproduced and output onto the bus 42. The reproduced data I and Q are supplied to the reconfigurable circuit 12 via the bus 42 and the input register 44 (44a to 44c), and a filtering process is performed.

  According to such a configuration, two data I (x) and Q (x) can be stored in each address position of the memory 20. Therefore, twice as much data can be stored in the memory 20 as compared with the case where the in-phase component data I and the quadrature component data Q are stored in each address position. Therefore, if the storage capacity of the memory 20 is the same, twice the amount of data can be accumulated as compared with the case where I and Q are stored at different addresses. In other words, if the same amount of data is stored, the storage capacity of the memory 20 can be halved.

As described above, the generation target circuit 60 can be divided in the horizontal direction.
For example, as shown in FIG. 8, the reconfigurable circuit 12 is first configured as a circuit for in-phase component processing (mixer 110, low-pass filter 112), and the received data after A / D conversion is processed to perform in-phase processing. The component data FI is obtained and stored in the memory 20, and then the reconfigurable circuit 12 is reconfigured as a quadrature component processing circuit (mixer 114, low-pass filter 116) to process the same data. The orthogonal component data FQ may be obtained.

  In this case, while the reconfigurable circuit 12 is processing the in-phase component, the memory control circuit 24 has the in-phase component data FI (x), FI (x + 1), FI (x + 2), FI (x + 3). ). . . Are sequentially supplied. As shown in FIG. 9A, the multiplexing circuit 241 includes two continuous data FI (x) and FI (x + 1), FI (x + 2) and FI (x + 3). . . Are multiplexed and sequentially stored in each address position of the memory 20.

  While the reconfigurable circuit 12 is processing the quadrature component, the memory control circuit 24 stores the quadrature component data FQ (x), FQ (x + 1), FQ (x + 2), FQ (x + 3). . . Are sequentially supplied. As shown in FIG. 9B, the multiplexing circuit 241 includes two continuous data FQ (x) and FQ (x + 1), FQ (x + 2) and FQ (x + 3). . . Are multiplexed and sequentially stored in each address position of the memory 20.

  The separation circuit 242 reads each data stored in this way under the control of the control circuit 18, appropriately separates it, outputs it to the outside, or re-supplies it to the reconfigurable circuit 12.

As shown in FIGS. 5 to 7, when it is necessary to simultaneously access complex data I and Q, the time required for multiplexing and demultiplexing can be suppressed by multiplexing these to reduce the memory capacity. It becomes possible to suppress.
On the other hand, as shown in FIG. 8 and FIG. 9, when it is necessary to access continuous data at the same time, the time required for multiplexing / separation can be suppressed by multiplexing these to reduce the memory capacity. It becomes possible.

  Also, for example, in the circuit of FIG. 5, there is a time difference between the in-phase component I and the quadrature component Q. For example, the in-phase component I (x) and the quadrature component Q (x + a), I (x + 1) and Q (x + a + 1) ), I (x + 2) and Q (x + a + 2),. . . When there is a correlation in the positional relationship between data that simultaneously access and, as shown in FIG. 10 (a), it is desirable to multiplex data that have a positional correlation. For example, such a situation occurs when in-phase component data or quadrature component data is supplied via a delay element such as a register.

  Similarly, in the case where data at different positions are accessed in the data sequence of the in-phase component FI and the data sequence of the quadrature component FQ, as shown in FIGS. 10B and 10C, they are accessed simultaneously. It is desirable to multiplex data to be processed.

  Whether or not to multiplex data is determined in accordance with, for example, the criteria shown in FIG.

  First, whether or not there is a margin for multiplexing between the storage capacity of each address position of the memory 20 and the bit width of the data (I, Q) to be multiplexed is, for example, the amount of memory used Based on the determination (step S11). For example, when each address position in the memory 20 is one word and the valid data of two data is larger than 1 byte, the data cannot be multiplexed. Conversely, if the valid data of one data is 7 bits and the other data is 9 bits, multiplexing is possible.

  Next, it is determined whether or not data with the same relative address is accessed simultaneously (step S12). That is, it is determined whether or not data having the same relative address (position) in each data array is accessed simultaneously, such as complex data (I, Q). If it is determined that the same relative address is accessed simultaneously (step S12; Yes), it is determined whether there is a time / processing margin for the demultiplexing process (step S13).

  If it is determined that there is a time / processing allowance (step S13; Yes), the first data that multiplexes data having the same relative position in each data array as in I (x) and Q (x). The multiplexing method is adopted (step S14). This multiplexing method is particularly effective when simultaneously accessing data having the same relative address in a plurality of data arrays, such as complex data (I, Q).

  On the other hand, if it is determined as No in step S12 or S13, it is determined whether there is a correlation between the relative addresses accessed simultaneously (step S15). For example, as shown in FIG. 10 (a), when two data arrays I (x) and Q (x + a) are accessed simultaneously, or as shown in FIGS. 10 (b) and 10 (c), one data When FI (x) and FI (y) are accessed simultaneously in array I (x), or when FQ (x) and FQ (x + b) are accessed simultaneously, it is determined that there is a correlation.

  If there is a correlation between the relative addresses accessed at the same time (step S15; Yes), it is determined whether or not there is a time / processing margin for the demultiplexing process (step S16). If there is a time and processing allowance (step S16; Yes), I (x) and Q (x + a), I (x) and I (y), Q (x) and Q (x + b) are correlated. Multiplexing method 2 for multiplexing data at a certain position is selected (step S17). This method is effective when there is a correlation between the relative addresses accessed simultaneously, such as Sin and Cos data, or when there is a delay in one of the complex data as described above.

  On the other hand, if NO is determined in step S15 or S16, it is determined whether there is a time / processing margin for the demultiplexing process (step S18). If there is time and processing allowance (step S18; Yes), data at consecutive positions in the same data array such as I (x) and I (x + 1), Q (y) and Q (y + 1) Is selected (step S19). In this multiplexing method, access to two pieces of array data is not simultaneous, and access time and access processing amount (multiplexing / separation processing) are available, or continuous data of the same array data is accessed simultaneously. This is particularly effective in some cases.

  If it is also determined No in step S19, that is, if it is determined that there is no room for multiplexing based on the memory access time, the memory access processing amount, the memory usage, the processing speed, etc., It is determined that data is not multiplexed (step S20).

  Note that the amount of time required for the multiplexing / demultiplexing processing is determined in advance, for example, the memory access processing time, the memory access processing amount, the processing speed, the time required for the multiplexing processing, and the time required for the separation processing. When the access (write / read) to the memory 20 is shorter than the processing speed of the reconfigurable circuit 12, it is determined that there is a margin, and when it is long, it is determined that there is no margin.

  In addition, the compiling unit 30 may perform the determination process illustrated in FIG. 11 to generate the data flow graph 38 according to the determination result.

  In this case, for example, in the storage unit 34, the size of the address position of the memory 20, the processing time of the multiplexing circuit 241 and the separation unit 242, the access time to the normal memory 20, the processing amount of memory access, the reconfigurable circuit 12 The data such as the operation clock frequency (processing speed) and the sampling frequency of the input signal are registered in advance. The program 36 stores a determination program for executing the above-described determination processing. The compiling unit 30 simulates the operation of the reconfigurable circuit 12 during the compiling process, determines which of the above conditions is met, specifies the presence / absence of multiplexing, the multiplexing method, and outputs the determination result. Generate a corresponding data flow diagram. The setting data generation unit 32 generates setting data 40 corresponding to the generated data flow. The control unit 18 supplies the generated setting data 40 to the setting unit 14.

  According to such a configuration, the presence / absence of multiplexing / setting of the multiplexing method itself can be automated.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and applications are possible.
For example, in the above-described embodiment, an example in which the present invention is applied to the demodulation circuit of the receiving circuit has been shown. However, an application to which the present invention is applied is arbitrary, and a plurality of data arrays accessed simultaneously as described above, This is widely applicable when accessing a plurality of data in the data array simultaneously.

  In the above-described embodiment, an example in which the memory capacity is suppressed by applying the present invention to an FPGA having a large hardware configuration and a large occupied area has been shown. That is, the processing result (intermediate data) of the reconfigurable circuit 12 is multiplexed and stored in the memory 20, and the circuit configuration of the reconfigurable circuit 12 is switched to reproduce and process the original data. As a result, the size of the memory 20 can be reduced, and the area occupied by the memory 20 in the integrated circuit chip 26 can be reduced. In such a configuration, when the processing content of the reconfigurable circuit 12 is advanced and complicated, the occupied area of the reconfigurable circuit 12 is increased, or when the integrated circuit chip 26 is required to have a higher density. Is particularly effective. Similarly, when a large amount of data is processed or generated by the reconfigurable circuit 12, it is effective in reducing the size of the memory 20.

  However, the present invention is not limited to this, and the type of integrated circuit to which the present invention is applied is arbitrary. For example, the present invention may be applied to a DSP (Digital Signal Processor), a CPU (Central Processing Unit), and the like to reduce the capacity of the internal memory.

  Furthermore, in the above embodiment, an example of multiplexing data stored in the memory in the integrated circuit element has been shown. However, access from the integrated circuit (processing device) 70 via the external bus 72 as shown in FIG. When storing / reading data to / from an external (external) memory 76, it is necessary to multiplex / separate the data by arranging the memory control circuit 74 so that a plurality of data can be accessed at once. It is possible to speed up access.

  In the above embodiment, the example in which each memory storage location is configured with one word and the number of effective bits of each data is 8 bits, but the size of the memory storage location and the number of effective bits of each data is mainly shown. Is optional. For example, each storage position (address position) of the memory has a 2-word configuration, the number of effective bits of each data is 16 bits, the number of effective bits of one data is 10 bits, and the number of effective bits of the other data is 22 It may be a bit.

  Further, the data to be multiplexed is not limited to two, and three or more data may be multiplexed.

  As described above, according to the present embodiment, when the bit width of the data to be held is smaller than the bit width of the memory and there is room to multiplex a plurality of data, the relevance of data access, the memory access time, In consideration of the data access processing amount, etc., the data is multiplexed by a method most suitable for the required conditions such as the usage amount and processing speed of the memory. As a result, the required memory usage can be reduced or the processing speed can be increased.

It is a block diagram which shows the structure of the FPGA circuit (processing apparatus) which concerns on embodiment of this invention. It is a block diagram which shows the structure of the setting part shown in FIG. FIG. 2 is a diagram illustrating a configuration example of a reconfigurable circuit illustrated in FIG. 1. FIG. 2 is a block diagram for explaining the configuration and operation of a reconfigurable circuit, a memory control circuit, and a memory shown in FIG. 1. It is a figure for demonstrating a multiplexing process and a separation process, (a) shows the structure of 1 address (1 storage position) of a memory, (b) shows the structure of data, (c) shows the structure of multiplexing. The method is shown, and (d) shows the separation method. It is a figure which shows an example of the demodulation circuit implement | achieved by the processing circuit of FIG. FIG. 7 is a diagram illustrating an example of data obtained by multiplexing complex data stored in each storage position of the memory when the circuit of FIG. 6 is configured. It is a figure which shows the other example of the demodulation circuit implement | achieved by the processing circuit of FIG. FIG. 9 is a diagram illustrating an example of data obtained by multiplexing the continuously accessed data stored in each storage position of the memory when the circuit of FIG. 8 is configured. FIG. 7 is a diagram illustrating an example of data obtained by multiplexing data having addresses correlated at the same time, which are stored at each storage location of the memory when the circuit of FIG. 6 is configured, and FIG. (B) and (c) show examples of accessing data of the same data array when accessing the data of the array at the same time. It is a flowchart for discriminating whether or not to multiplex data and what kind of multiplexing is to be performed. It is a block diagram which shows the structural example at the time of applying this invention when accessing external memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Processing circuit 12 Reconfigurable circuit 14 Setting part 18 Control part 20 Memory 24 Memory control circuit 42 Bus 26 Integrated circuit device

Claims (5)

A memory for storing data at a predetermined data size at each address position;
Storage means for multiplexing a plurality of data and storing them at each address of the memory;
Data reproduction means for reproducing the original data by reading and separating the data stored in each address position of the memory;
Determining means for determining data to be stored at each address of the memory according to a predetermined standard,
The determining means includes
When the plurality of data accessed simultaneously is the first type in which the relative positions in the respective data arrays are equal , the plurality of data is multiplexed and stored in one address position of the memory,
When a plurality of data accessed at the same time is the second type in which the relative positions in the respective data arrays are correlated , the plurality of data are multiplexed and stored in one address position of the memory. Let
A data multiplexed storage device.
The determining means includes
When the plurality of data is neither the first type nor the second type, the plurality of data to be accessed in order is multiplexed in a predetermined number of consecutive data units and stored in the memory.
The data multiplexed storage device according to claim 1.
The determining means includes
When the amount of data multiplexing and separation processing is greater than a predetermined value, data multiplexing is not performed.
The data multiplexing storage device according to claim 1 or 2, characterized in that
A data multiplexed storage device according to any one of claims 1 to 3 ,
And a processing unit that processes the data and supplies the data to the storage unit, or processes the data reproduced by the data reproduction unit.
A data multiplexed storage device according to any one of claims 1 to 3 ,
A reconfigurable circuit that processes data and supplies it to the storage means, or processes data reproduced by the data reproduction means;
And a setting unit that switches and sets the circuit configuration of the reconfigurable circuit.

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