JP4749049B2 - Constant current circuit and electronic equipment - Google Patents

Description

  The present invention relates to a constant current circuit that adjusts a supply current by switching a power supply and an electronic apparatus including the constant current circuit, and more particularly to a constant current circuit that suppresses an adjustment error due to a delay in gate voltage applied to a switching element and the same. It relates to electronic equipment.

  Conventionally, a power supply device that switches a power supply circuit to adjust a supply current and a supply voltage is known. In such a power supply device, a supply current and a supply are changed by changing a ratio of on-time (hereinafter referred to as a duty ratio) within one cycle by a pulse width modulation (PWM) method. It is common to adjust the voltage.

  For example, Patent Document 1 discloses a DC / DC switching converter that can adjust a supply voltage by a PWM method and set a maximum duty ratio close to 100%.

  Patent Document 2 discloses a constant current circuit that drives a current to a current driven element such as an LED (Lighting Emitting Diode).

  FIG. 9 is a schematic configuration diagram of a conventional PWM constant current circuit 200. The constant current circuit 200 is a modification of the constant current circuit disclosed in Patent Document 2 so that the output current value is negatively fed back.

  Referring to FIG. 9, load LED, constant current circuit 200, and resistor R are connected in series between power supply node 2 and the reference potential. The constant current circuit 200 adjusts the current supplied from the power supply node 2 to the load LED by switching the circuit.

  The constant current circuit 200 includes voltage dividing resistors R1 and R2, an operational amplifier OP (Operational Amplifier) 1, a PWM signal generator 80, a transistor TR, and a switch SW6.

The voltage dividing resistors R1 and R2 are connected in series between the power supply node 2 and the reference potential, and the power supply voltage _VCC is converted into a current set value V _I according to the ratio between the voltage dividing resistors R1 and R2, and is calculated. Output to amplifier OP1.

The operational amplifier OP1 amplifies the difference between the current set value V _I received from the voltage dividing resistors R1 and R2 and the voltage (= R × I _OUT ) generated in the resistor R to generate a differential voltage V _A , and the switch SW6 Output to.

  The PWM signal generation unit 80 generates a PWM signal having a predetermined cycle and having a pulse width corresponding to the duty ratio received from the outside, and outputs the PWM signal to the switch SW6.

The transistor TR is interposed between the power supply node 2 and the reference potential, and supplies an output current _IOUT corresponding to the gate voltage to the load LED.

The switch SW6 receives the PWM signal from the PWM signal generation unit 80, applies the differential voltage _VA to the gate of the transistor TR during the on period of the PWM signal, and applies the ground potential to the gate of the transistor TR during the off period. . Therefore, the transistor TR supplies the output current I _OUT corresponding to the differential voltage _VA during the on period of the PWM signal, and interrupts the current during the off period.

Further, during the ON period, the voltage generated in the resistor R is negatively fed back, and the output current I _OUT supplied to the load LED is stabilized at I _OUT = V _I / R. Therefore, when viewed constantly, the constant current circuit 200 supplies the load LED with a current value obtained by multiplying the output current I _OUT during the ON period by the duty ratio.
JP 2003-219638 A JP 7-321623 A

However, in the constant current circuit shown in FIG. 9, since the output current I _OUT is zero during the off period, the rise time of the output current I _OUT immediately after the start of the on period becomes a problem.

FIG. 10 is a diagram showing the time waveform of each part in the conventional constant current circuit 200.
FIG. 10A shows a time waveform of the PWM signal.

FIG. 10B is a time waveform of the switch SW6.
FIG. 10C shows a time waveform of the output current I _OUT .

Referring to FIG. 10A and FIG. 10B, switch SW6 switches on and off alternately according to the PWM signal output from PWM signal generation unit 80. FIG. 10A shows a case where the duty ratio is about 50%. On the other hand, referring to FIG. 10C, the output current I _OUT cannot completely follow the PWM signal.

FIG. 11 is a time waveform of each part in the enlarged section shown in FIG.
FIG. 11A shows a time waveform of the PWM signal.

FIG. 11B is a time waveform of the output current I _OUT .
FIG. 11C is a time waveform of the differential voltage _VA .

Referring to FIGS. 11A and 11B, there is a dead time Td1 and a delay time Td2 from immediately after the start of the ON period of the PWM signal until the output current I _OUT becomes a predetermined value. During the dead time Td1, the output current I _OUT does not increase at all, and during the delay time Td2, the output current I _OUT gradually increases with a predetermined time constant. The dead time Td1 is mainly caused by the response speed of the switch SW6 and the charge / discharge time of the gate capacitance of the transistor TR. During this period, the transistor TR is not yet in a conductive state. The delay time Td2 is mainly caused by the response speed of the operational amplifier OP1.

Referring to FIG. 11C, when the dead time Td1 elapses and the transistor TR becomes conductive, current supply from the constant current circuit 200 to the load LED is started. On the other hand, since the output current I _OUT is zero during the OFF period of the PWM signal, the voltage that is negatively fed back to the operational amplifier OP is also zero. For this reason, the operational amplifier OP cannot increase the differential voltage V _A as an output instantaneously even during the ON period, and increases the differential voltage V _A according to its own response speed.

Thus, for on the timing of the PWM signal, when the rising of the output current I _OUT is delayed, it is impossible to provide a desired current value to the load LED. In particular, when the duty ratio is small, the on period of the PWM signal may end before the output current _IOUT rises, and the error appears more prominently.

By the way, the dead time Td1 is several microseconds, whereas the delay time Td2 may be ten and several microseconds. Therefore, to accelerate the rise of the output current I _OUT, it is necessary to increase the response speed of the operational amplifier OP1 which is the main cause of the delay time Td2.

  However, when a high-speed operational amplifier is used, there is a problem that the manufacturing cost increases.

  Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to provide a constant current circuit capable of adjusting a current with high accuracy while suppressing cost, and an electronic apparatus including the constant current circuit. That is.

  According to the present invention, the current adjustment unit that adjusts the current supplied to the load according to the current adjustment command is compared with the first set value and the value corresponding to the current value supplied to the load, and the current value is the first value. A comparison unit that outputs a first current adjustment command so as to match the set value and a switching command for adjusting a time ratio at which current is supplied from the current adjustment unit based on the second set value The first current adjustment command is interrupted based on the switching command from the control unit, the switch unit to be given to the current adjustment unit, and the holding command is received, the first current adjustment command is held at that time And a holding unit that outputs the held first current adjustment command as the second current adjustment command. Then, the control unit gives a holding command to the holding unit when the current value supplied to the load substantially coincides with the first set value, and then replaces the switch unit with the first current adjustment command. A switching command for intermittently supplying the second current adjustment command output from the holding unit to the current adjustment unit is output.

  Preferably, the switching command is a pulse signal that is alternately turned on and off, and the control unit receives an output start command for starting the supply of current from the outside, and starts outputting the switching command. In addition, in the first ON period after the output of the switching command is started, the holding command is given to the holding unit.

  Preferably, when the first set value is updated, the control unit outputs a switching command for intermittently supplying the first current adjustment command to the current adjustment unit to the switch unit, and then the load A holding command is given to the holding unit at a point in time when the current value supplied to is substantially coincident with the updated first set value.

Preferably, the holding unit converts the first current adjustment command into a digital value and stores the digital value.
Preferably, the holding unit holds the first current adjustment command by storing a charge amount corresponding to the first current adjustment command.

Preferably, the holding unit outputs the second current adjustment command via the output buffer.
Preferably, the comparison unit further functions as an output buffer for a second current adjustment command output from the holding unit.

  According to the invention, the power source, the load connected to the power source, the power source and the load are connected in series, and adjusts the current supplied to the load in accordance with the current adjustment command, and the first set value. And a value corresponding to the current value supplied to the load, and outputs a first current adjustment command so that the current value matches the first set value, and based on the second set value And a control unit that outputs a switching command for adjusting a time ratio at which the current is supplied from the current adjustment unit, and the first current adjustment command is interrupted based on the switching command from the control unit, An electronic device comprising: a switch unit to be applied; and a holding unit that receives the holding command and holds the first current adjustment command at that time and outputs the held first current adjustment command as the second current adjustment command is there. Then, the control unit gives a holding command to the holding unit when the current value supplied to the load substantially coincides with the first set value, and then replaces the switch unit with the first current adjustment command. A switching command for intermittently supplying the second current adjustment command output from the holding unit to the current adjustment unit is output.

  According to this invention, the current adjustment command for supplying the current value equal to the first set value to the load is held, and the held current adjustment command is given to the current adjustment unit without going through the comparison unit. . Therefore, it is possible to avoid the influence of the time delay that occurs in the first current adjustment command output from the comparison unit due to the interruption of the current supplied to the load. Therefore, since the current according to the first set value can be supplied regardless of the intermittent state of the load current, a constant current circuit capable of adjusting the current with high accuracy and an electronic apparatus including the constant current circuit can be realized.

  Embodiments of the present invention will be described in detail with reference to the drawings. Note that the same or corresponding parts in the drawings are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a schematic configuration diagram of a constant current circuit 101 according to the first embodiment.

  Referring to FIG. 1, load LED, constant current circuit 101 and resistor R are connected in series between power supply node 2 and a reference potential. The constant current circuit 101 adjusts the current supplied from the power supply node 2 to the load LED by opening and closing the circuit. The constant current circuit 101 includes a current setting unit 10, an operational amplifier OP1, a control unit 20, a transistor TR, a switch SW1, and a holding unit 30.

The current setting unit 10 receives a current set value (digital value) from the outside, and outputs the current set value V _I to the operational amplifier OP1. The current setting unit 10 includes a register 12 and a digital / analog converter (D / A) 14. The current set value is determined so that the current set value V _I matches the product (V _I = R × I _OUT ) of the resistor R and the output current I _OUT during the ON period.

The register 12 stores a current setting value received from the outside.
The digital / analog converter 14 reads the current setting value stored in the register 12, generates a voltage corresponding to the value, and outputs the voltage to the operational amplifier OP1.

The operational amplifier OP1 amplifies the difference between the current setting value V _I received from the current setting unit 10 and the voltage (= R × I _OUT ) generated in the resistor R to generate a differential voltage V _A and outputs it to the switch SW1. It is a comparison part. That is, the operational amplifier OP1 negatively feeds back the voltage generated in the resistor R, and changes the differential voltage V _A that is the current command value so that the output current I _OUT matches the current value corresponding to the current setting value V _I. Let

When the holding unit 30 receives a holding command from the control unit 20, the holding unit 30 stores the differential voltage V _A output from the operational amplifier OP1 at that time. Then, the holding unit 30 outputs the stored differential voltage V _A as the holding voltage V _B to the switch SW1. That is, the holding unit 30 holds the current setting value V _I at the time of receiving the holding instruction, and outputs the holding voltage V _B is a current command value. Further, the holding unit 30 includes an analog / digital converter (A / D) 32, a register 34, a digital / analog converter (A / D) 36, and an operational amplifier OP2.

The analog / digital converter 32 receives the differential voltage _VA output from the operational amplifier OP1, converts it to a digital value, and outputs it to the register 34.

The register 34 stores the digital value of the differential voltage _VA output from the analog / digital converter 32 when receiving a holding command from the control unit 20.

The digital / analog converter 36 reads the digital value of the differential voltage _VA stored in the register 34, converts it into an analog value, and outputs it to the operational amplifier OP2.

The operational amplifier OP2 amplifies and outputs the result of negative feedback of its own output with respect to the differential voltage _VA received from the digital / analog converter 36. In other words, the operational amplifier OP2 is a unity gain buffer and functions as an output buffer of the holding unit 30. Therefore, holding unit 30 outputs a holding voltage V _B having the same voltage as differential voltage V _A received from digital / analog converter 36 and having a large output capacity to switch SW1.

Switch SW1 connects any one of the three ports A, B, and C to the gate of transistor TR in response to a switching command received from control unit 20, and provides a current command. That is, the switch SW1 is one of the differential voltage V _A (port A) output from the operational amplifier OP1, the holding voltage V _B (port B) output from the holding unit 30, and the reference potential (port C). One is applied to the gate of transistor TR.

The transistor TR is an adjustment unit that is interposed between the power supply node 2 and the reference potential, and adjusts the output current I _OUT supplied to the load LED according to the voltage applied to the gate. The transistor TR is composed of, for example, an NMOS transistor.

The control unit 20 includes a PWM signal generation unit 24 and, upon receiving an output start command, generates a PWM signal in a predetermined cycle and according to the duty ratio received from the outside. Then, based on the generated PWM signal, the control unit 20 applies the differential voltage V _A or the holding voltage V _B to the gate of the transistor TR during the on period, and supplies the reference potential to the transistor TR during the off period. A switching command for giving to the gate of the switch is output to the switch SW1. Further, the control unit 20 periodically reads the current setting value from the register 12 and determines whether or not the value has been updated.

Furthermore, the control unit 20 provides the differential voltage V _A to the gate of the transistor TR only in the first on period immediately after receiving the output start command and in the first on period immediately after the current set value is updated, in other oN period, a holding voltage V _B to output the switching command so as to provide to the gate of the transistor TR. Then, after the differential voltage V _A is applied to the gate of the transistor TR, the control unit 20 waits for a predetermined time after which the operational amplifier OP1 can make the output current I _OUT substantially match the current set value. A holding command is given to 30.

  The load LED is, for example, an LED used for a liquid crystal backlight or the like, and changes its emission luminance according to the supply time of the supplied current.

Resistor R is inserted between the constant current circuit 101 and the reference potential, for generating a voltage for detecting the output current I _OUT. Therefore, the value of the resistor R is appropriately designed according to the output current I _OUT , the operational amplifier OP1, the current set value V _{I, and the} like.

Hereinafter, an operation of constant current circuit 101 according to the first embodiment will be described in detail.
FIG. 2 is a diagram illustrating a time waveform of each part of the constant current circuit 101 immediately after the output start command is given.

FIG. 2A shows a time waveform of the PWM signal generated by the PWM signal generator 24.
FIG. 2B is a time waveform of the switch SW1.

FIG. 2C shows a time waveform of the differential voltage _VA .
Figure 2 (d) is a time waveform of the holding voltage _{V B.}

Figure 2 (e) is a time waveform of the gate voltage _{V G} applied to the transistor TR.
FIG. 2F shows a time waveform of the output current _IOUT .

  Referring to FIG. 2A, when receiving an output start command, control unit 20 starts generating a PWM signal. Referring to FIG. 2B, the control unit 20 causes the switch SW1 to select the port A or B during the PWM signal on period, and causes the switch SW1 to select the port C during the PWM signal off period. . In particular, the control unit 20 causes the switch SW1 to select the port A in the first on period immediately after receiving the output start command, and causes the switch SW1 to select the port B in the subsequent on period.

Referring to FIG. 2C, the operational amplifier OP1 changes the differential voltage V _A according to the difference between the current set value V _I and the voltage generated in the resistor R with a predetermined response speed.

Referring to FIG. 2D, the control unit 20 holds the holding command when a predetermined time has elapsed from the start of the ON period and the differential voltage V _A output from the operational amplifier OP1 reaches a predetermined value. To the unit 30. The holding unit 30 stores the differential voltage V _A at the time of receiving the holding command in the register 34, and outputs the holding voltage V _B that is the same as the stored differential voltage V _A to the switch SW1. That is, the control unit 20 causes the holding unit 30 to hold the gate voltage V _G for supplying the output current I _OUT corresponding to the current set value V _I.

Referring to FIG. 2 (e), the gate voltage V _G applied to the gate of the transistor TR becomes the differential voltage V _A output from the operational amplifier OP1 in the first ON period immediately after receiving the output start command. In the subsequent ON period, the holding voltage V _B output from the holding unit 30 is obtained. Since the holding voltage V _B is held at a constant value regardless of whether the PWM signal is on or off, the holding voltage V _B is applied to the gate of the transistor TR immediately after the start of the on period and without a rise time.

Referring to FIG. 2F, the output current I _OUT is supplied from the transistor TR corresponding to the gate voltage V _G of the transistor TR. Therefore, in the first on-period immediately after receiving the output start command, the output current I _OUT is delayed with respect to the PWM signal, but in the subsequent on-period, the output rises sharply in synchronization with the PWM signal. A current I _OUT is supplied.

Even if the same current set value is given to the constant current circuit 101, the differential voltage V output from the operational amplifier OP1 due to manufacturing variations, electrical characteristics, temperature characteristics, and the like of the transistor TR. _A is not determined. Therefore, the control unit 20 receives the output start instruction, only at its first on period, the differential voltage V _A output from the operational amplifier OP1 supplied to the transistor TR, an output current corresponding to current set value V _I The holding unit 30 holds the gate voltage V _G for supplying I _OUT .

Incidentally, the adjustment of the output current is mainly performed by changing the duty ratio given to the control unit 20, but the current set value V _I may be changed. When the current set value V _I is changed, it is necessary to store the gate voltage V _G for supplying the output current I _OUT corresponding to the current set value V _I in the holding unit 30 again.

Therefore, the control unit 20 monitors whether or not the current set value V _I has been changed, and when it is changed, gives a holding command to the holding unit 30 again.

FIG. 3 is a diagram illustrating a time waveform of each part of the constant current circuit 101 when the current set value V _I is changed.

FIG. 3A is a time waveform of the PWM signal generated by the PWM signal generator 24.
FIG. 3B is a time waveform of the current set value V _I.

FIG. 3C is a time waveform of the switch SW1.
FIG. 3D is a time waveform of the differential voltage _VA .

Figure 3 (e) is a time waveform of the holding voltage _{V B.}
Figure 3 (f) is a time waveform of the gate voltage _{V G} applied to the transistor TR.

FIG. _{3G is} a time waveform of the output current I _OUT .
Referring to FIGS. 3 (a) and (b), when a new current set value to the current setting portion 10 is provided, the current setting unit 10 outputs a new current set value V _I.

Referring to FIG. 3 (c), the control unit 20, in the first ON period immediately following the current set value V _I is changed, the port A is selected in the switch SW1, the subsequent on-period, the switch Let SW1 select port B.

Referring to FIG. 3 (d), operational amplifier OP1, for any current setting value V _I, with a predetermined time constant, corresponding to the difference between the voltage generated and the current set value V _I in the resistor R The differential voltage _VA is changed.

Referring to FIG. 3 (e), the control unit 20 determines that the predetermined voltage elapses from the start of the first ON period after the change of the current set value V _{I and} the differential voltage V _A output from the operational amplifier OP1. When the value reaches a predetermined value, a holding command is output to the holding unit 30. That is, the control unit 20 causes the holding unit 30 to hold the gate voltage V _G for supplying the output current I _OUT corresponding to the new current setting value V _I as in the case where the output start command is received.

Referring to FIG. 3F, the gate voltage V _G applied to the gate of the transistor TR is the differential voltage V _A output from the operational amplifier OP1 in the first ON period after the change of the current setting value V _I. In the subsequent ON period, the holding voltage V _B output from the holding unit 30 is obtained.

Referring to FIG. _3G , the output current I _OUT is supplied from the transistor TR corresponding to the gate voltage V _G of the transistor TR. Therefore, in the first on period after the change of the current set value V _I , the output current I _OUT is delayed with respect to the PWM signal, but in the subsequent on period, the rectangular output synchronized with the PWM signal is generated. A current I _OUT is supplied.

FIG. 4 is a process flowchart in the control unit 20 of the constant current circuit 101.
Referring to FIG. 4, control unit 20 determines whether an output start command has been received (step S100). If an output start command has not been received (NO in step S100), control unit 20 waits until an output start command is received (step S100).

  When an output start command is received (YES in step S100), control unit 20 starts generating a PWM signal (step S102). Then, the control unit 20 gives a switch command for selecting the port A to the switch SW1 during the first ON period (step S104). Furthermore, the control unit 20 determines whether or not a predetermined time has elapsed since the start of the first on-period (step S106). If the predetermined time has not elapsed (NO in step S106), control unit 20 waits until the predetermined time elapses (step S106).

  If the predetermined time has elapsed (YES in step S106), control unit 20 provides a holding command to holding unit 30 (step S108). Then, when the ON period ends, the control unit 20 gives a switch command for selecting the port C to the switch SW1 (step S110). Furthermore, when the off period ends, the control unit 20 gives a switch command for selecting the port B to the switch SW1 (step S112).

  Thereafter, the control unit 20 determines whether or not the current set value has been updated (step S114). If the current set value has been updated (YES in step S114), control unit 20 provides a switch command for selecting port A to switch SW1 during the next ON period (step S104). And the control part 20 performs above-mentioned step S106, S108, S110, S112 again.

  If the current set value has not been updated (NO in step S114), control unit 20 determines whether or not the output start command is continued (step S116).

  If the output start command is continued (YES in step S116), control unit 20 repeats steps S110, S112, and S114 described above.

  If the output start command is not continued (NO in step S116), control unit 20 ends the process.

Note that the timing at which the control unit 20 gives the holding command to the holding unit 30 is determined according to the response speed of the operational amplifier OP1, but when the ON period is shorter than the response speed of the operational amplifier OP1, In some cases, the output current I _OUT cannot rise to the current set value within the ON period.

  Therefore, the control unit 20 ignores the duty ratio and calculates the first on-period immediately after receiving the output start command and the first on-period immediately after the current setting unit 10 receives a new current set value. You may extend according to the response speed of amplifier OP1.

  In the first embodiment described above, the case where the constant current circuit 101 supplies current to the LED has been described. However, the load is not limited to the LED, and if the constant current load needs to adjust the supply current, It goes without saying that the same applies.

  According to the first embodiment of the present invention, the differential voltage for flowing the output current corresponding to the current set value is held in the holding unit, and the control unit sends the holding voltage output from the holding unit to the gate of the transistor. A switching command is output so as to give. Therefore, a constant gate voltage can be applied to the gate of the transistor without being affected by the time delay in the differential voltage from the operational amplifier. Therefore, since an output current corresponding to the current set value can be supplied regardless of the duty ratio and the period of the PWM signal, a constant current circuit capable of current adjustment with high accuracy can be realized.

  Further, according to the first embodiment of the present invention, the control unit operates the operational amplifier only in the first on-period immediately after receiving the output start command and the first on-period immediately after the current set value is updated. Is applied to the gate of the transistor to generate a differential voltage for flowing an output current corresponding to the current set value. Therefore, the gate voltage corresponding to the current setting value can be accurately applied to the gate of the transistor, and the influence of the response delay of the operational amplifier can be minimized. Therefore, a constant current circuit capable of current adjustment with high accuracy can be realized.

  Further, according to the present invention, the holding unit converts the differential voltage output from the operational amplifier into a digital value and stores it in the register, so that the value does not change due to the passage of time or disturbance. Therefore, stable current supply can be realized when the frequency of updating the current set value is low and current supply for a long time is required.

[Embodiment 2]
In the first embodiment, the configuration in which the differential voltage applied to the gate of the transistor by the holding unit is converted into a digital value and held has been described.

  On the other hand, in the second embodiment, a configuration in which the holding unit holds the differential voltage as a charge amount corresponding to the voltage value will be described.

FIG. 5 is a schematic configuration diagram of constant current circuit 102 according to the second embodiment.
Referring to FIG. 5, constant current circuit 102 is obtained by replacing holding unit 30 and control unit 20 with holding unit 40 and control unit 22 in constant current circuit 101 according to the first embodiment, respectively.

The holding unit 40 receives the differential voltage _VA output from the operational amplifier OP1, and stores an amount of charge corresponding to the voltage. Then, the holding unit 40 outputs a voltage corresponding to the charge amount as the holding voltage V _B. That is, the holding unit 40 functions as a sample / hold circuit. Furthermore, the holding unit 40 includes switches SW2 and SW3, a capacitor 46, and an operational amplifier OP2.

  The switch SW2 is disposed between the output side of the operational amplifier OP1 and the capacitor 46, and is closed when a switching command for selecting the port B or C is received from the control unit 22. The switch SW3 is disposed between the capacitor 46 and the input side of the operational amplifier OP2, and is closed when a switching command for selecting the port A is received from the control unit 22. Therefore, the switches SW2 and SW3 are not “closed” at the same time, and only one of them is “closed” at any time.

The capacitor 46 is inserted between the switches SW2 and SW3 and the reference potential, and is connected to the output side of the operational amplifier OP1 and the switch SW3 is “closed” during the period when the switch SW2 is “closed”. Is connected to the input side of the operational amplifier OP2. The capacitor 46 accumulates charges according to the differential voltage V _A during the period when the switch SW2 is “closed”, and is based on the accumulated charges during the period when the switch SW3 is “closed”. The differential voltage _VA is output to the operational amplifier OP2.

Similar to the first embodiment, the operational amplifier OP2 is a unity gain buffer and functions as an output buffer. Then, the operational amplifier OP2 is a differential voltage V _A and the same voltage received from capacitor 46, and outputs the holding voltage V _B having a large output capacity to the switch SW1.

The control unit 22 includes a PWM signal generation unit 24. Upon receiving an output start command, the control unit 22 generates a PWM signal in a predetermined cycle and according to the duty ratio received from the outside. Then, based on the PWM signal, the control unit 22 supplies the differential voltage V _A or the holding voltage V _B to the gate of the transistor TR during the on period, and applies the reference potential to the gate of the transistor TR during the off period. Is output to the switch SW1. In addition, the control unit 22 periodically reads the current setting value from the register 12 and determines whether or not the value has been updated.

Further, the control unit 22 provides the differential voltage V _A to the gate of the transistor TR only in the first on period immediately after receiving the output start command and in the first on period immediately after the current set value is updated, in other oN period, a holding voltage V _B to output the switching command so as to provide to the gate of the transistor TR. In addition, the control unit 22 applies the differential voltage _VA to the gate of the transistor TR, and at the same time, sets the switch SW2 to “close” and causes the capacitor 46 to store electric charge. Then, the control unit 22, in other periods, the switch SW3 as "closed", thereby outputting a voltage corresponding to the charge stored in the capacitor 46 as a holding voltage V _B.

Hereinafter, the operation of constant current circuit 102 according to the second embodiment will be described in detail.
FIG. 6 is a diagram illustrating a time waveform of each part of the constant current circuit 102 immediately after the output start command is given.

FIG. 6A is a time waveform of the PWM signal generated by the PWM signal generator 24.
FIG. 6B is a time waveform of the switch SW1.

FIG. 6C shows a time waveform of the switch SW2.
FIG. 6D is a time waveform of the switch SW3.

FIG. 6E is a time waveform of the differential voltage _VA .
FIG. 6F shows a time waveform of the capacitor voltage _Vch .

Shown in FIG. 6 (g) is the time waveform of the holding voltage _{V B.}
FIG 6 (h) is the time waveform of the gate voltage _{V G} applied to the transistor TR.

  Referring to FIGS. 6A and 6B, similarly to the first embodiment, when receiving an output start command, control unit 22 starts generating a PWM signal. The control unit 22 causes the switch SW1 to select the port A or B during the PWM signal on period, and causes the switch SW1 to select the port C during the PWM signal off period. In particular, the control unit 22 causes the switch SW1 to select the port A in the first on period immediately after receiving the output start command, and causes the switch SW1 to select the port B in the subsequent on period.

  Referring to FIG. 6C, the switch SW2 is “open” while the switch SW1 is selecting the port B or C, and is “closed” when the switch SW1 is selecting the port A. .

  Referring to FIG. 6D, the switch SW3 is “open” while the switch SW1 is selecting the port A, and is “closed” when the switch SW1 is selecting the port B or C. .

Referring to FIG. 6E, the operational amplifier OP1 changes the differential voltage V _A according to the difference between the current set value V _I and the voltage generated in the resistor R with a predetermined time constant.

Referring to FIG. 6F, when the switch SW2 is “closed”, accumulation of electric charge in the capacitor 46 is started. Thereafter, when a predetermined time elapses, electric charge corresponding to the differential voltage V _A is accumulated in the capacitor 46, and the capacitor voltage V _ch of the capacitor 46 rises to the differential voltage V _A.

Referring to FIG. 6G, after the electric charge corresponding to the differential voltage _VA is accumulated in the capacitor 46, when the switch SW2 is “open” and the switch SW3 is “closed”, the operational amplifier OP2 Outputs the capacitor voltage V _ch as the holding voltage V _B. Thereafter, operational amplifier OP2, until the switch SW3 is "open", continues to output the holding voltage _{V B.}

Referring to FIG. 6 (h), the gate voltage V _G applied to the gate of the transistor TR is in the first ON period immediately after receiving the output start instruction, the differential voltage V _A becomes output from the operational amplifier OP1 In the subsequent ON period, the holding voltage V _B output from the holding unit 40 is obtained. Since the holding voltage V _B is held at a constant value regardless of whether the PWM signal is on or off, the holding voltage V _B is applied to the gate of the transistor TR immediately after the start of the on period and without a rise time.

Incidentally, the charge accumulated in the capacitor 46 decreases with time due to the occurrence of leakage due to the resistance component and the fact that the amplification factor of the operational amplifier OP2 is finite. If the reduction rate is moderate, but not caused little problem, if susceptible to or when noise charges decreases rapidly becomes unable to provide sufficient gate voltage V _G to the transistor TR. In view of this, when the rate of charge reduction of the capacitor 46 is large or when it is susceptible to noise, the power storage operation may be performed periodically.

  FIG. 7 is a diagram showing a time waveform of each part of the constant current circuit 102 when the power storage operation is periodically performed.

FIG. 7A shows a time waveform of the PWM signal generated by the PWM signal generator 24.
FIG. 7B is a time waveform of the switch SW1.

FIG. 7C shows a time waveform of the switch SW2.
FIG. 7D is a time waveform of the switch SW3.

FIG. 7E shows a time waveform of the differential voltage _VA .
FIG. 7F shows a time waveform of the capacitor voltage _Vch .

Shown in FIG. 7 (g) is the time waveform of the holding voltage _{V B.}
Figure 7 (h) is the time waveform of the gate voltage _{V G} applied to the transistor TR.

  Referring to FIGS. 7A, 7B, 7C, and 7D, control unit 22 gives a switching command to switches SW1, SW2, and SW3 so as to periodically perform a power storage operation.

Referring to FIGS. 7E and 7F, when the switch SW2 is “closed”, accumulation of electric charge in the capacitor 46 is started, and the capacitor voltage _Vch increases. Then, next to the switch SW2 is "open", the switch SW3 is "closed", the capacitor voltage _{V ch} is applied to the gate of the transistor TR as a holding voltage _{V B.} On the other hand, as the charge accumulated in the capacitor 46 decreases, the capacitor voltage _Vch decreases at a predetermined speed. Therefore, the control unit 22, so that the voltage decrease amount [Delta] V _ch capacitor voltage V _ch is within a predetermined range, the switch SW2 "closed", and switches the switch SW3 to "open", the regular power storage operation Do. Immediately after the storage operation, the capacitor voltage V _ch rises to the differential voltage V _A.

Referring to FIG. 7G, the holding voltage V _B decreases at a predetermined speed according to the capacitor voltage V _ch , but is periodically raised to the differential voltage V _A by performing a power storage operation. A necessary voltage can be applied to the gate of TR.

Referring to FIG. 7H, differential voltage V _A is applied to the gate of transistor TR in the on period in which the storage operation is performed, and holding voltage V _B is applied to the gate of transistor TR in the other on period. Given to.

Capacitor 46 performs a power storage operation only in the first ON period. Therefore, when the ON period is short or when the time constant (capacitance) of capacitor 46 is large, the capacitor 46 stores the required holding voltage V _B. May not be possible.

  Therefore, the control unit 22 ignores the duty ratio and extends the first on-period immediately after receiving the output start command and the first on-period immediately after the current setting unit 10 receives a new current set value. May be.

  According to the second embodiment of the present invention, the holding unit stores a charge amount according to the differential voltage output from the operational amplifier, and outputs a holding voltage based on the stored charge amount. Therefore, since the holding unit can be realized only by a capacitor for storing electric charge and a switch for controlling the electric storage operation, the holding unit has a more simplified configuration and can suppress the cost.

  According to the second embodiment of the present invention, since the holding unit outputs a holding voltage corresponding to the stored charge amount via the output buffer, the reduction in the charge amount due to the output of the holding voltage is suppressed. it can. In addition, since the holding portion can supply a sufficient current to the gate of the transistor, high-speed switching can be performed even for a transistor having a large gate capacitance.

[Embodiment 3]
In the first and second embodiments, the configuration in which the holding voltage is output via the output buffer included in the holding unit has been described.

  On the other hand, in the third embodiment, a configuration in which an operational amplifier for negatively feeding back an output current value is also used as an output buffer will be described.

FIG. 8 is a schematic configuration diagram of constant current circuit 103 according to the third embodiment.
Referring to FIG. 8, constant current circuit 103 is the same as constant current circuit 102 according to the second embodiment, except that switch SW4 is added and holding unit 40 and switch SW1 are replaced with holding unit 50 and switch SW5, respectively. It is.

Switch SW4 is arranged on the input side of operational amplifier OP1, and switches a signal applied to operational amplifier OP1 in accordance with a switching command received from control unit 20. When receiving a switching command for selecting the port A from the control unit 22, the switch SW5 gives the current set value V _I to the “+” side of the operational amplifier OP1 and the voltage generated in the resistor R on the “−” side. give. That is, switch SW5 forms a negative feedback circuit for supplying output current I _OUT corresponding to current set value V _I as in the first and second embodiments.

On the other hand, when receiving the switching command for selecting the port B or C from the control unit 22, switch SW4, the operational amplifier OP1 "+" side to give the capacitor voltage V _ch, "-" side of the operational amplifier OP1 Give the output voltage. That is, the switch SW4 forms a unity gain buffer including the operational amplifier OP1 and functions as an output buffer of the holding unit 50.

  Holding unit 50 is obtained by removing operational amplifier OP2 that is an output buffer from holding unit 40 in constant current circuit 102 according to the second embodiment. Since other parts are the same as those of holding unit 40, detailed description will not be repeated.

Switch SW5 is arranged on the input side of the gate of transistor TR, and switches the voltage applied to the gate of transistor TR in accordance with a switching command received from control unit 20. When receiving a switching command for selecting port A or B from the control unit 22, the switch SW5 causes the differential voltage V _A (at the switching command to the port A) or the holding voltage V output from the operational amplifier OP1. _B (when switching to port B is commanded) is applied to the gate of transistor TR. On the other hand, upon receiving a switching command for selecting port C from control unit 22, switch SW5 applies a reference potential to the gate of transistor TR.

Hereinafter, the operation of constant current circuit 103 according to the third embodiment will be described in detail.
In the ON period of the PWM signal, when the switching command is given for selecting the port A from the control unit 22, the operational amplifier OP1 receives a voltage generated in the current set value V _I and the resistor R. Then, the operational amplifier OP1 provides a differential voltage V, which is a current command value, so that the voltage generated in the resistor R is negatively fed back so that the output current I _OUT matches the current value corresponding to the current set value V _I. Change _A. At the same time, the differential voltage _VA output from the operational amplifier OP1 is applied to the gate of the transistor TR. The holding unit 50 receives the differential voltage _VA output from the operational amplifier OP1, and stores an amount of charge corresponding to the voltage.

Next, when the ON period of the PWM signal ends and a switching command for selecting port C is given from the control unit 22, the holding unit 50 ends the charge storage by the differential voltage V _A and the capacitor 46. The capacitor voltage _Vch corresponding to the amount of charge stored in is output. At the same time, the operational amplifier OP1 receives the capacitor voltage _Vch and its own output voltage. The operational amplifier OP1, to increase the output capacitance of the capacitor voltage _{V ch,} outputs a holding voltage _{V B.}

A reference potential is applied to the gate of the transistor TR.
Further, when the OFF period of the PWM signal ends and a switching command for selecting port B is given from the control unit 22, the states of the holding unit 50 and the operational amplifier OP1 do not change, and the gate of the transistor TR The holding voltage V _B output from the amplifier OP1 is applied.

Hereinafter, the same operation is repeated according to the switching command output from the control unit 22.
As described above, in the period in which the holding voltage V _B is applied to the gate of the transistor TR output from the holding unit, in principle, there is no need to negative feedback voltage generated in the resistor R. Therefore, the negative feedback operation can be stopped and the operational amplifier OP1 can function as an output buffer.

  According to the third embodiment of the present invention, in addition to the effect of the second embodiment, in order to cause the operational amplifier for adjusting the output current to function as the output buffer of the holding unit, the constant current circuit is configured by one operational amplifier. Can be configured. Therefore, the configuration of the constant current circuit is further simplified, and the manufacturing cost can be suppressed.

  In addition to the above-described embodiment, for example, a constant current circuit in which a plurality of transistors respectively supply current to a load may be configured to have a common holding unit that supplies a holding voltage to each transistor. In addition, the register included in the holding unit is a non-volatile register, and the power supplied from the outside is lost after the first on-period or after the first on-period after the current set value is changed. However, the differential voltage may be omitted. Furthermore, the operation of the current setting unit and the operational amplifier may be stopped after the first on period after the output is started or after the first on period after the current set value is changed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic configuration diagram of a semiconductor device according to a first embodiment. It is a figure which shows the time waveform of each part of the constant current circuit immediately after an output start command is given. It is a figure which shows the time waveform of each part of a constant current circuit when a current setting value is changed. It is a process flowchart in the control part of a constant current circuit. FIG. 6 is a schematic configuration diagram of a constant current circuit according to a second embodiment. It is a figure which shows the time waveform of each part of the constant current circuit immediately after an output start command is given. It is a figure which shows the time waveform of each part of a constant current circuit in the case of performing an electrical storage operation | movement regularly. FIG. 6 is a schematic configuration diagram of a constant current circuit according to a third embodiment. It is a schematic block diagram of the conventional constant current circuit of a PWM system. It is a figure which shows the time waveform of each part in the conventional constant current circuit. It is a time waveform of each part in the expansion section shown in Drawing 10 (c).

Explanation of symbols

2 power supply node, 10 current setting unit, 12, 34 register, 14, 36 digital / analog converter (D / A), 20, 22 control unit, 24, 80 PWM signal generation unit, 30, 40, 50 holding unit, 32 digital / analog converter (D / A), 46 capacitor, 101, 102, 103, 200 constant current circuit, _IOUT output current, LED load, OP1, OP2 operational amplifier, R resistor, R1, R2 voltage dividing resistor, SW1, SW2, SW3, SW4, SW5, SW6 switch, Td1 dead time, Td2 delay time, TR transistor, _{V A} differential voltage, _{V B} holding _{voltage, V CC} supply _{voltage, V ch} capacitor voltage, _{V G} gate voltage, V _I current setting value, [Delta] V _ch voltage decrement.

Claims (8)

A switching element for adjusting the current supplied to the load according to the current adjustment command;
A comparison unit that compares a first set value with a value corresponding to a current value supplied to the load and outputs a first current adjustment command so that the current value matches the first set value; ,
A control unit based on the second set value, the current from the switching element to output a PWM switching signal for adjusting the time ratio to be supplied,
When receiving a hold command, a holding unit for outputting holding the first current adjustment command at that time, the first current adjustment command holding a second current adjustment command,
The first current adjustment command, the second current adjustment command, a reference voltage, and the switching signal are input, and during the ON period of the switching signal from the control unit, the first current adjustment command or outputting the second current adjustment command, the off period by outputting the reference voltage, and a switch section that gives to said switching element a PWM signal as said current adjustment command,
The control unit gives the holding command to the holding unit at a time point when a current value supplied to the load substantially coincides with the first set value, and then the switch unit sets an ON period of the switching signal. characterized in that providing the second current adjusting command output from the holding portion to the front Symbol switching element in place of said first current adjustment command, the constant current circuit. Before Symbol control unit,
Receiving an output start command for starting the supply of current from the outside, and starts output of the switching signal, and,
Wherein in the first on period after starting the output of the switching signal, providing the hold command to the holding portion, a constant current circuit according to claim 1. When the first set value before Symbol is updated, the switch unit, the output to Previous Stories switching element said first current adjustment command to the on-period of the switching signal, then the control unit, the 3. The constant current circuit according to claim 1, wherein the holding command is given to the holding unit when a current value supplied to the load substantially coincides with the updated first set value. 4.   The constant current circuit according to claim 1, wherein the holding unit converts the first current adjustment command into a digital value and stores the digital value.   The constant current circuit according to any one of claims 1 to 3, wherein the holding unit holds the first current adjustment command by storing a charge amount according to the first current adjustment command.   The constant current circuit according to claim 1, wherein the holding unit outputs the second current adjustment command via an output buffer.   The constant current circuit according to claim 1, wherein the comparison unit further functions as an output buffer for the second current adjustment command output from the holding unit. Power supply,
A load connected to the power source;
A switching element that is connected in series with the power source and the load and adjusts a current supplied to the load according to a current adjustment command;
A comparison unit that compares a first set value with a value corresponding to a current value supplied to the load and outputs a first current adjustment command so that the current value matches the first set value; ,
A control unit based on the second set value, the current from the switching element to output a PWM switching signal for adjusting the time ratio to be supplied,
When receiving a hold command, a holding unit for outputting holding the first current adjustment command at that time, the first current adjustment command holding a second current adjustment command,
The first current adjustment command, the second current adjustment command, a reference voltage, and the switching signal are input, and during the ON period of the switching signal from the control unit, the first current adjustment command or outputting the second current adjustment command, the off period by outputting the reference voltage, and a switch section that gives to said switching element a PWM signal as said current adjustment command,
The control unit gives the holding command to the holding unit at a time point when a current value supplied to the load substantially coincides with the first set value, and then the switch unit sets an ON period of the switching signal. characterized in that providing the second current adjusting command output from the holding portion to the front Symbol switching element in place of said first current adjustment command, the electronic apparatus.

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