JP4742731B2 - Manufacturing method of stacked semiconductor device - Google Patents

Manufacturing method of stacked semiconductor device Download PDF

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JP4742731B2
JP4742731B2 JP2005226179A JP2005226179A JP4742731B2 JP 4742731 B2 JP4742731 B2 JP 4742731B2 JP 2005226179 A JP2005226179 A JP 2005226179A JP 2005226179 A JP2005226179 A JP 2005226179A JP 4742731 B2 JP4742731 B2 JP 4742731B2
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semiconductor chip
circuit board
semiconductor
liquid resin
semiconductor chips
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JP2007042904A (en
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悟 脇山
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Description

本発明は、積層型半導体装置の製造方法および積層型半導体装置に関し、特に、回路基板上に複数の半導体チップがフリップチップ接続により積層搭載された積層型半導体装置の製造方法およびこれにより得られる積層型半導体装置に関するものである。   The present invention relates to a method for manufacturing a stacked semiconductor device and a stacked semiconductor device, and more particularly, to a method for manufacturing a stacked semiconductor device in which a plurality of semiconductor chips are stacked and mounted on a circuit board by flip chip connection, and a stacked layer obtained thereby. The present invention relates to a type semiconductor device.

電気製品の小型化、低消費電力化といった要求に応えるため、半導体チップの高集積化技術とともに、これらの半導体チップを高密度に配置する実装技術も展開されてきている。このような実装技術のうち、多層配線が形成された回路基板（インターポーザ）上に、半導体チップがフリップチップ接続によりフェイスダウン実装された半導体装置は、半導体装置の小型化だけではなく、高速化の点からも有利である。   In order to meet the demands for miniaturization of electric products and low power consumption, along with high integration technology for semiconductor chips, mounting technology for arranging these semiconductor chips at high density has been developed. Among such mounting techniques, a semiconductor device in which a semiconductor chip is mounted face-down by flip chip connection on a circuit board (interposer) on which a multilayer wiring is formed is not only reduced in size but also increased in speed. This is also advantageous from the point of view.

そして、さらなる実装密度を図るために、回路基板上にフェイスダウン実装された半導体チップ上に、樹脂層を介してもう１つの半導体チップを搭載し、上部の半導体チップと回路基板とをワイヤーボンディングにより接続した積層型半導体装置が報告されている（例えば、下記特許文献１参照）。   In order to further increase the mounting density, another semiconductor chip is mounted on the semiconductor chip face-down mounted on the circuit board via a resin layer, and the upper semiconductor chip and the circuit board are bonded by wire bonding. A connected stacked semiconductor device has been reported (for example, see Patent Document 1 below).

また、図３に示すように、フリップチップ接続により、半導体チップ１１ａ、１１ｂを回路基板２１上に順次積層搭載した積層型半導体装置も検討されている。このような積層型半導体装置は、各半導体チップ１１が半導体素子を備えた回路基板となっており、特許文献１に記載された積層型半導体装置と比較して、上部の半導体チップ１１ａと回路基板２１とをワイヤーボンディングにより接続しないため、小型化が可能であり、より多くの半導体チップ１１を積層可能である、という利点がある。   In addition, as shown in FIG. 3, a stacked semiconductor device in which semiconductor chips 11a and 11b are sequentially stacked and mounted on a circuit board 21 by flip-chip connection has been studied. In such a stacked semiconductor device, each semiconductor chip 11 is a circuit board provided with a semiconductor element. Compared with the stacked semiconductor device described in Patent Document 1, an upper semiconductor chip 11a and a circuit board are provided. 21 is not connected by wire bonding, so that the size can be reduced and more semiconductor chips 11 can be stacked.

この積層型半導体装置は、回路基板２１と半導体チップ１１ａとの間隙および半導体チップ１１ａと半導体チップ１１ｂとの間隙に樹脂（液状樹脂３１）が充填されることで、各半導体チップ１１に設けられたバンプ１２による応力が緩和され、バンプ１２の接続信頼性が確保されている。   This stacked semiconductor device is provided in each semiconductor chip 11 by filling the gap between the circuit board 21 and the semiconductor chip 11a and the gap between the semiconductor chip 11a and the semiconductor chip 11b with resin (liquid resin 31). The stress due to the bumps 12 is relieved, and the connection reliability of the bumps 12 is ensured.

上記積層型半導体装置を製造する場合には、回路基板２１上に配置される半導体チップ１１ａを回路基板２１よりも一回り小さく形成し、さらに、半導体チップ１１ａ上に配置される半導体チップ１１ｂを半導体チップ１１ａよりも一回り小さく形成する。   When manufacturing the stacked semiconductor device, the semiconductor chip 11a disposed on the circuit board 21 is formed to be slightly smaller than the circuit board 21, and the semiconductor chip 11b disposed on the semiconductor chip 11a is formed as a semiconductor. It is formed slightly smaller than the chip 11a.

そして、回路基板２１と半導体チップ１１ａとの間隙付近の回路基板２１上の周縁の一部に液状樹脂３１を充填器４１から滴下すると、毛細管現象により回路基板２１と半導体チップ１１ａとの間隙に液状樹脂３１が供給され、回路基板２１と半導体チップ１１ａとの間隙が液状樹脂３１で充填される。同様に、半導体チップ１１ａと半導体チップ１１ｂとの間隙付近の半導体チップ１１ａ上の周縁の一部に液状樹脂３１を滴下することで、半導体チップ１１ａと半導体チップ１１ｂとの間隙が液状樹脂３１で充填される。   Then, when the liquid resin 31 is dropped from the filler 41 on a part of the peripheral edge on the circuit board 21 in the vicinity of the gap between the circuit board 21 and the semiconductor chip 11a, the liquid is placed in the gap between the circuit board 21 and the semiconductor chip 11a due to a capillary phenomenon. Resin 31 is supplied, and the gap between the circuit board 21 and the semiconductor chip 11 a is filled with the liquid resin 31. Similarly, the liquid resin 31 is dropped on a part of the periphery on the semiconductor chip 11a near the gap between the semiconductor chip 11a and the semiconductor chip 11b, so that the gap between the semiconductor chip 11a and the semiconductor chip 11b is filled with the liquid resin 31. Is done.

特開２００５−２６５６４号公報JP 2005-26564 A

しかし、上述したような積層型半導体装置の製造方法では、回路基板２１と半導体チップ１１ａとの間隙および半導体チップ１１ａと半導体チップ１１ｂとの間隙に、それぞれ液状樹脂３１を充填する工程を行うため時間を要し、多くの半導体チップ１１を積層する程、さらなる時間を要するという問題がある。また、液状樹脂３１を充填する際に下層側となる半導体チップ１１ａまたは回路基板２１の周縁に液状樹脂３１を滴下するため、半導体チップ１１ａおよび回路基板２１の周縁に液状樹脂３１を滴下するスペースが必要となり、積層型半導体装置のさらなる小型化を妨げる、という問題があった。   However, in the manufacturing method of the stacked semiconductor device as described above, the time for performing the process of filling the gap between the circuit board 21 and the semiconductor chip 11a and the gap between the semiconductor chip 11a and the semiconductor chip 11b with the liquid resin 31 respectively. And the more semiconductor chips 11 are stacked, the more time is required. Further, when the liquid resin 31 is filled, the liquid resin 31 is dropped on the periphery of the semiconductor chip 11a or the circuit board 21 which is the lower layer side, so that there is a space for dropping the liquid resin 31 on the periphery of the semiconductor chip 11a and the circuit board 21. There is a problem that it is necessary and hinders further miniaturization of the stacked semiconductor device.

また、図４（ａ）に示すように、積層される各半導体チップ１１の形状と大きさが同一である場合には、各半導体チップ１１間の間隙に液状樹脂３１を充填するために、液状樹脂３１を滴下するスペースがない。このため、各半導体チップ１１間の間隙に充填器４１を横から挿入して液状樹脂３１を供給する必要がある等、液状樹脂３１の供給が困難であり、液状樹脂３１の未充填領域が生じてしまう、という問題も生じている。液状樹脂３１の未充填領域が発生すると、バンプ１２に発生する応力が緩和されず、接続信頼性が悪くなる。また、この積層型半導体装置をマザーボードへ実装する際のリフロープロセスでバンプ１２が再溶融するため、未充填領域にハンダが流れ込みショートする危険性がある。このような問題は、図４（ｂ）に示すように、積層型半導体装置の一部（領域Ｂ）において、半導体チップ１１がその直下部に配置される半導体チップ１１よりも大きい場合でも同様に生じている。   As shown in FIG. 4A, when the shape and size of each semiconductor chip 11 to be stacked are the same, the liquid resin 31 is filled to fill the gap between the semiconductor chips 11. There is no space for dropping the resin 31. For this reason, it is difficult to supply the liquid resin 31 such that it is necessary to supply the liquid resin 31 by inserting the filling device 41 into the gap between the semiconductor chips 11 from the side, and an unfilled region of the liquid resin 31 is generated. There is also a problem that When the unfilled region of the liquid resin 31 is generated, the stress generated in the bumps 12 is not relieved and the connection reliability is deteriorated. Further, since the bumps 12 are remelted in a reflow process when the stacked semiconductor device is mounted on the mother board, there is a risk that the solder flows into the unfilled region and short-circuits. As shown in FIG. 4B, such a problem similarly occurs even when the semiconductor chip 11 is larger than the semiconductor chip 11 disposed immediately below the part of the stacked semiconductor device (region B). Has occurred.

かかる問題点を改善するために、本発明は、液状樹脂により各半導体チップ間の間隙および半導体チップと基板との間隙を確実に充填するとともに液状樹脂の充填工程を短くすることができる積層型半導体装置の製造方法および積層型半導体装置を提供することを目的とする。   In order to remedy such problems, the present invention provides a laminated semiconductor that can reliably fill the gap between each semiconductor chip and the gap between the semiconductor chip and the substrate with a liquid resin and shorten the filling process of the liquid resin. An object of the present invention is to provide a device manufacturing method and a stacked semiconductor device.

上述したような課題を解決するために、本発明における積層型半導体装置の製造方法は、一主面側にバンプが設けられた３層以上の回路基板をフリップチップ接続により積層搭載してなる積層型半導体装置の製造方法であって、次のような工程を順次行うことを特徴としている。まず、第１工程では、回路基板のうち、少なくとも両端側の回路基板に挟持される回路基板に貫通孔を形成する。次に、第２工程では、各回路基板をフリップチップ接続により積層搭載することで、貫通孔によって各回路基板間の間隙を連通させる。次いで、第３工程では、一端の回路基板側から回路基板間の間隙に液状樹脂を供給し、貫通孔によって他端の回路基板側まで回路基板間の間隙に液状樹脂を行き渡らせることで、各回路基板間の間隙を液状樹脂で充填する。   In order to solve the above-described problems, a method for manufacturing a stacked semiconductor device according to the present invention is a stacked structure in which three or more circuit boards each provided with a bump on one main surface side are stacked and mounted by flip chip connection. Type semiconductor device manufacturing method, characterized by sequentially performing the following steps. First, in a 1st process, a through-hole is formed in the circuit board clamped at least by the circuit board of the both ends side among circuit boards. Next, in the second step, the circuit boards are stacked and mounted by flip-chip connection, so that the gaps between the circuit boards are communicated by the through holes. Next, in the third step, the liquid resin is supplied from the circuit board side at one end to the gap between the circuit boards, and the liquid resin is distributed in the gap between the circuit boards to the circuit board side at the other end through the through holes. The gap between the circuit boards is filled with a liquid resin.

このような積層型半導体装置の製造方法によれば、回路基板のうち、少なくとも両端側の回路基板に挟持される回路基板に貫通孔を形成した後、各回路基板をフリップチップ接続により積層搭載することから、貫通孔を介して各回路基板間の間隙が連通した状態となる。この状態で、一端の回路基板側から回路基板間の間隙に液状樹脂を供給することで、毛細管現象が生じ、貫通孔によって他端の回路基板側まで回路基板間の間隙に液状樹脂を行き渡らせることが可能となる。これにより、回路基板の大きさや形状に関わらず、一回の供給で液状樹脂を各回路基板間の間隙に確実に充填することが可能となる。   According to such a method for manufacturing a stacked semiconductor device, through holes are formed in a circuit board that is sandwiched between at least both of the circuit boards, and then each circuit board is stacked and mounted by flip-chip connection. For this reason, the gaps between the circuit boards communicate with each other through the through holes. In this state, by supplying the liquid resin from the circuit board side of one end to the gap between the circuit boards, a capillary phenomenon occurs, and the liquid resin is spread to the gap between the circuit boards to the circuit board side of the other end by the through hole. It becomes possible. Thereby, regardless of the size and shape of the circuit board, the liquid resin can be reliably filled into the gaps between the circuit boards with a single supply.

また、本発明の積層型半導体装置は、一主面側にバンプが設けられた３層以上の回路基板をフリップチップ接続により積層搭載してなる積層型半導体装置であって、少なくとも両端側の回路基板に挟持される回路基板には、貫通孔が設けられており、各回路基板間の間隙には樹脂が充填されていることを特徴としている。   The stacked semiconductor device of the present invention is a stacked semiconductor device in which three or more circuit boards having bumps provided on one main surface side are stacked and mounted by flip-chip connection, and at least circuits on both ends. The circuit board sandwiched between the boards is provided with a through hole, and a gap between the circuit boards is filled with resin.

このような積層型半導体装置は、上述した製造方法によって製造されるものであり、液状樹脂を各回路基板の間隙に確実に充填することができるため、接続信頼性に優れている。
Such a stacked semiconductor device is manufactured by the above-described manufacturing method, and since the liquid resin can be reliably filled in the gaps between the circuit boards, the connection reliability is excellent.

以上説明したように、本発明の積層型半導体装置の製造方法および積層型半導体装置によれば、回路基板の大きさや形状に関わらず、一回の供給で液状樹脂を各回路基板間の間隙に確実に充填することができるため、液状樹脂の充填工程を短くすることができ、生産性に優れている。また、液状樹脂を各回路基板間の間隙に確実に充填することができるため、接続信頼性に優れた積層型半導体装置を得ることができる。   As described above, according to the method for manufacturing a stacked semiconductor device and the stacked semiconductor device of the present invention, the liquid resin is put into the gaps between the circuit boards with a single supply regardless of the size and shape of the circuit boards. Since filling can be ensured, the filling process of the liquid resin can be shortened, and the productivity is excellent. In addition, since the liquid resin can be reliably filled in the gaps between the circuit boards, a stacked semiconductor device having excellent connection reliability can be obtained.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。ここでは、回路基板上に４つの半導体チップをフリップチップ接続により積層してなる積層型半導体装置の製造方法および積層型半導体装置の例について説明する。なお、本実施形態では、積層型半導体装置の構成を製造工程順に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Here, a manufacturing method of a stacked semiconductor device in which four semiconductor chips are stacked on a circuit board by flip chip connection and an example of the stacked semiconductor device will be described. In the present embodiment, the configuration of the stacked semiconductor device will be described in the order of manufacturing steps.

図１（ａ）に示すように、半導体チップ１１には、一主面側に複数のバンプ１２が配列形成されている。ここでは、バンプ１２は２次元的に均等に配列されていることとする。ここで、後工程で、回路基板（図示省略）上に順次積層搭載される４つの半導体チップ１１は、半導体素子が搭載された回路基板であって、例えば矩形状であり、同じ大きさであることとする。なお、本実施形態では、４つの半導体チップを積層搭載させた積層型半導体装置を例にとり説明するが、本発明はこれに限定されず、回路基板２１と半導体チップ１１からなる回路基板とを合わせて３層以上積層搭載した積層型半導体装置であれば、適用可能である。   As shown in FIG. 1A, the semiconductor chip 11 has a plurality of bumps 12 arranged on one main surface side. Here, it is assumed that the bumps 12 are equally arranged two-dimensionally. Here, in the subsequent process, the four semiconductor chips 11 sequentially stacked and mounted on a circuit board (not shown) are circuit boards on which semiconductor elements are mounted, and are, for example, rectangular and have the same size. I will do it. In the present embodiment, a stacked semiconductor device in which four semiconductor chips are stacked and mounted will be described as an example. However, the present invention is not limited to this, and the circuit board 21 and the circuit board including the semiconductor chip 11 are combined. Any stacked semiconductor device in which three or more layers are stacked and mounted is applicable.

ここで、本発明の特徴的な構成として、半導体チップ１１の例えばバンプ１２の形成領域よりも外側の周縁部に、後工程で液状樹脂を通過させる貫通孔１３を形成する。この貫通孔１３の孔径は０．６ｍｍ以上２ｍｍ以下であることとする。ここでは、矩形状の半導体チップ１１の４つの角部のうち一箇所に貫通孔１３を形成する。この貫通孔１３は、例えば複数の半導体チップ１１が設けられたダイシング前のウェハー上に、貫通孔１３部分が開口されたレジストパターンを形成した後、ドライエッチングにより形成されることとする。ただし、貫通孔１３の形成方法は、ドライエッチングに限定されるものではなく、ウェットエッチングでもよく、メカドリルを用いて形成してもよい。   Here, as a characteristic configuration of the present invention, a through-hole 13 through which the liquid resin passes is formed in a peripheral step on the outer periphery of the semiconductor chip 11, for example, outside the formation region of the bump 12. The hole diameter of the through hole 13 is 0.6 mm or more and 2 mm or less. Here, the through hole 13 is formed at one of the four corners of the rectangular semiconductor chip 11. For example, the through hole 13 is formed by dry etching after forming a resist pattern in which the through hole 13 is opened on a wafer before dicing provided with a plurality of semiconductor chips 11. However, the method for forming the through-hole 13 is not limited to dry etching, but may be wet etching or may be formed using a mechanical drill.

この際、各半導体チップ１１の貫通孔１３を、この半導体チップ１１の直上部または直下部に配置される半導体チップ１１の貫通孔１３に対して、最も離れた位置に形成することが好ましい。ここでは、回路基板上に搭載される最下部の半導体チップ１１ａと下から３番目に配置される半導体チップ１１ｃには、各半導体チップ１１を積層搭載した状態で、平面視的に同一の角部に、貫通孔１３ａ、１３ｃをそれぞれ形成する。一方、図１（ｂ）に示すように、下から２番目に配置される半導体チップ１１ｂと最上部に配置される半導体チップ１１ｄには、各半導体チップ１１を積層搭載した状態で、貫通孔１３ａ、１３ｃが配置された半導体チップ１１ａ、１１ｃ（前記図１（ａ）参照）の角部と平面視的に対角となる角部に貫通孔１３ｂ、１３ｄを形成する。   At this time, the through hole 13 of each semiconductor chip 11 is preferably formed at a position farthest from the through hole 13 of the semiconductor chip 11 disposed immediately above or directly below the semiconductor chip 11. Here, the lowermost semiconductor chip 11a mounted on the circuit board and the semiconductor chip 11c arranged third from the bottom have the same corner portion in plan view in a state where the semiconductor chips 11 are stacked and mounted. The through-holes 13a and 13c are formed respectively. On the other hand, as shown in FIG. 1B, the through hole 13a is formed in a state in which the semiconductor chips 11 are stacked and mounted on the semiconductor chip 11b arranged second from the bottom and the semiconductor chip 11d arranged on the top. Through holes 13b and 13d are formed at corners that are diagonally opposite to the corners of the semiconductor chips 11a and 11c (see FIG. 1A) where the semiconductor chips 11c and 13c are disposed.

上述したように、各半導体チップ１１に貫通孔１３をそれぞれ形成した後、図２（ａ）に示すように、多層配線が設けられた回路基板（インターポーザ）２１上に、半導体チップ１１ａ〜１１ｄを順次積層搭載する。ここで、図２は、図１のＡ−Ａ’断面図である。   As described above, after the through holes 13 are formed in the respective semiconductor chips 11, as shown in FIG. 2A, the semiconductor chips 11 a to 11 d are formed on the circuit board (interposer) 21 provided with the multilayer wiring. Stacked sequentially. Here, FIG. 2 is a cross-sectional view taken along the line A-A ′ of FIG. 1.

この場合には、上記回路基板２１は、例えば各半導体チップ１１よりも一回り大きい矩形状であり、半導体チップ１１が搭載される面の反対側には、外部電極となる複数のバンプ２２が設けられていることとする。なお、ここでは、回路基板２１が半導体チップ１１よりも一回り大きく形成された例について説明するが、回路基板２１は半導体チップ１１と形状と大きさが同一であってもよい。   In this case, the circuit board 21 has, for example, a rectangular shape that is slightly larger than each semiconductor chip 11, and a plurality of bumps 22 serving as external electrodes are provided on the opposite side of the surface on which the semiconductor chip 11 is mounted. It is assumed that Here, an example in which the circuit board 21 is formed to be slightly larger than the semiconductor chip 11 will be described, but the circuit board 21 may have the same shape and size as the semiconductor chip 11.

まず、各半導体チップ１１のバンプ１２形成面側の周縁に、例えば熱可塑性樹脂からなる封止材１４を、この熱可塑性樹脂のガラス転移温度（Ｔｇ）以上に加熱した状態で塗布する。ここで、この熱可塑性樹脂に、後工程で半導体チップ１１間の間隙に供給される液状樹脂を注入する際の温度や硬化する温度よりも高いＴｇを有するものを用いることで、液状樹脂の供給〜硬化プロセスの間で再溶融しないため、好ましい。また、回路基板２１上に配置される半導体チップ１１ａの周縁には、封止材１４を一部形成せずに、後工程で、各半導体チップ１１間の間隙に液状樹脂を充填する際の出口となる開口部１４ａとする。この開口部１４ａは、各半導体チップ１１を積層搭載した状態で、半導体チップ１１ａに設けられた貫通孔１３ａに対して、平面視的に対角となる位置に設けられることが好ましい。また、半導体チップ１１aと回路基板２１の間には、熱可塑性樹脂からなる封止材１４を塗布しなくてもよい。   First, the sealing material 14 made of, for example, a thermoplastic resin is applied to the periphery of each semiconductor chip 11 on the bump 12 formation surface side while being heated to a glass transition temperature (Tg) or higher of the thermoplastic resin. Here, by using the thermoplastic resin having a Tg higher than the temperature at which the liquid resin to be supplied to the gap between the semiconductor chips 11 is injected in a later step or the curing temperature, the liquid resin is supplied. -Preferred because it does not remelt during the curing process. In addition, an outlet when filling the gap between the semiconductor chips 11 in a later step without forming a part of the sealing material 14 around the periphery of the semiconductor chip 11a disposed on the circuit board 21. It becomes the opening part 14a which becomes. The opening 14a is preferably provided at a diagonal position in plan view with respect to the through hole 13a provided in the semiconductor chip 11a in a state where the semiconductor chips 11 are stacked and mounted. Further, the sealing material 14 made of a thermoplastic resin may not be applied between the semiconductor chip 11a and the circuit board 21.

なお、ここでは、封止材１４として熱可塑性樹脂を用い、塗布することとしたが、各半導体チップ１１間の間隙または半導体チップ１１ａと回路基板２１との間隙程度の厚みを有するフィルム状の熱可塑性樹脂を、回路基板２１上に各半導体チップ１１を積層搭載する際に、回路基板２１と半導体チップ１１との間の周縁および各半導体チップ１１間の周縁に挟み込む状態で配置してもよい。また、ここでは、封止材１４に熱可塑性樹脂を用いた例について説明したが、封止材１４としては、紫外線硬化性樹脂等の光硬化性樹脂を用いてもよく、熱硬化性樹脂を用いてもよい。   Here, a thermoplastic resin is used and applied as the sealing material 14, but a film-like heat having a thickness approximately equal to the gap between the semiconductor chips 11 or the gap between the semiconductor chip 11 a and the circuit board 21. When the semiconductor chips 11 are stacked and mounted on the circuit board 21, the plastic resin may be disposed so as to be sandwiched between the peripheral edge between the circuit board 21 and the semiconductor chip 11 and the peripheral edge between the semiconductor chips 11. Here, an example in which a thermoplastic resin is used for the sealing material 14 has been described. However, as the sealing material 14, a photocurable resin such as an ultraviolet curable resin may be used, and a thermosetting resin may be used. It may be used.

次いで、回路基板２１上に、周縁に封止材１４が塗布された上記半導体チップ１１ａを搭載する。この際、半導体チップ１１ａに設けられたバンプ１２による回路基板２１へのフリップチップ接続と、封止材１４による周縁部の接合とは同一工程で行われる。同様に、半導体チップ１１ｂ〜１１ｄを半導体チップ１１ａ上に順次積層する。   Next, the semiconductor chip 11 a with the sealing material 14 applied to the periphery is mounted on the circuit board 21. At this time, the flip chip connection to the circuit board 21 by the bumps 12 provided on the semiconductor chip 11a and the joining of the peripheral edge by the sealing material 14 are performed in the same process. Similarly, the semiconductor chips 11b to 11d are sequentially stacked on the semiconductor chip 11a.

具体的には、回路基板２１と最上部の半導体チップ１１ｄとで挟持される半導体チップ１１ａ〜１１ｃには、各半導体チップ１１を膜厚方向に貫通する状態の配線１５とこの配線１５から最配線されたメッキ層１６とが設けられており、下部側の半導体チップ１１のメッキ層１６上に上部側の半導体チップ１１のバンプ１２が電気的に接続される。また、上述したように、各半導体チップ１１の周縁にＴｇ以上で加熱した状態の熱可塑性樹脂からなる封止材１４を塗布した状態で、回路基板２１上に半導体チップ１１ａ〜１１ｄを積層搭載した後、常温に放置することで、封止材１４は硬化状態となり、回路基板２１と各半導体チップ１１とが、その周縁で封止材１４により密着し隙間がなくなる。   Specifically, the semiconductor chips 11a to 11c sandwiched between the circuit board 21 and the uppermost semiconductor chip 11d include the wiring 15 in a state of penetrating each semiconductor chip 11 in the film thickness direction, and the wiring 15 from the wiring 15. The bump 12 of the upper semiconductor chip 11 is electrically connected to the plating layer 16 of the lower semiconductor chip 11. As described above, the semiconductor chips 11a to 11d are stacked and mounted on the circuit board 21 in a state where the sealing material 14 made of a thermoplastic resin heated to Tg or more is applied to the periphery of each semiconductor chip 11. Thereafter, the sealing material 14 is cured by being left at room temperature, and the circuit board 21 and each semiconductor chip 11 are in close contact with the sealing material 14 at the periphery thereof, and there is no gap.

これにより、各半導体チップ１１間の間隙および半導体チップ１１ａと回路基板２１との間隙は、半導体チップ１１ａ〜１１ｄに設けられた貫通孔１３ａ〜１３ｄにより連通された状態となる。ここで、各半導体チップ１１間の間隙および回路基板２１と半導体チップ１１との間隙は、これらの間隙に毛細管現象により液状樹脂３１を充填できる程度の間隔であることが好ましい。   As a result, the gap between the semiconductor chips 11 and the gap between the semiconductor chip 11a and the circuit board 21 are communicated with each other through the through holes 13a to 13d provided in the semiconductor chips 11a to 11d. Here, the gap between the semiconductor chips 11 and the gap between the circuit board 21 and the semiconductor chip 11 are preferably such that these gaps can be filled with the liquid resin 31 by capillary action.

特に、ここでは、回路基板２１と半導体チップ１１との間および各半導体チップ１１の間の周縁が封止材１４により封止されていることから、最上部の半導体チップ１１ｄの貫通孔１３ｄから、回路基板２１と半導体チップ１１ａの間の周縁を覆う封止材１４に設けられた開口部１４ａまでが一連の通路として連通される。この通路の一端となる貫通孔１３ｄから他端となる開口部１４ａまでの各貫通孔１３は上層側から順に対角になるように配置されている。   In particular, here, since the periphery between the circuit board 21 and the semiconductor chip 11 and between each semiconductor chip 11 is sealed with the sealing material 14, from the through hole 13d of the uppermost semiconductor chip 11d, The openings 14a provided in the sealing material 14 covering the periphery between the circuit board 21 and the semiconductor chip 11a communicate with each other as a series of passages. Each through hole 13 from the through hole 13d serving as one end of the passage to the opening 14a serving as the other end is disposed so as to be diagonally arranged in order from the upper layer side.

続いて、図２（ｂ）に示すように、最上部の半導体チップ１１ｄの貫通孔１３ｄに充填器４１のニードルを挿入し、液状樹脂（アンダーフィル樹脂）３１を注入する。ここで用いる液状樹脂３１は、例えば１分子中に２個以上のエポキシ基を有する多価エポキシ樹脂と、１分子中に２個以上の活性水素を有する硬化剤からなる樹脂中に酸化シリコン（ＳｉＯ2）からなるフィラーが含有されたものであり、その粘度は１Ｐａ・ｓ〜２０Ｐａ・ｓであることとする。 Subsequently, as shown in FIG. 2B, the needle of the filler 41 is inserted into the through hole 13d of the uppermost semiconductor chip 11d, and a liquid resin (underfill resin) 31 is injected. The liquid resin 31 used here is, for example, silicon oxide (SiO 2) in a resin composed of a polyvalent epoxy resin having two or more epoxy groups in one molecule and a curing agent having two or more active hydrogens in one molecule. 2 ) is contained, and its viscosity is 1 Pa · s to 20 Pa · s.

貫通孔１３ｄから半導体チップ１１ｄと半導体チップ１１ｃの間隙に供給された液状樹脂３１は、半導体チップ１１ｄと半導体チップ１１ｃの間に立設されるバンプ１２に生じた毛細管現象により、広がっていく。この際、バンプ１２が２次元的に均等に配列されている場合には、貫通孔１３ｃに向かって液状樹脂３１は等方的に広がる。ここで、上述したように、半導体チップ１１ｄの貫通孔１３ｄに対して半導体チップ１１ｃの貫通孔１３ｃは、平面視的に対角に設けられているため、貫通孔１３ｃに液状樹脂３１が到達するまでに、半導体チップ１１ｄと半導体チップ１１ｃとの間隙は、液状樹脂３１により確実に充填される。そして、毛細管現象または重力により貫通孔１３ｃを通過した液状樹脂３１は、半導体チップ１１ｃと半導体チップ１１ｂとの間隙に流入する。   The liquid resin 31 supplied from the through hole 13d to the gap between the semiconductor chip 11d and the semiconductor chip 11c spreads due to capillary action generated on the bumps 12 standing between the semiconductor chip 11d and the semiconductor chip 11c. At this time, when the bumps 12 are two-dimensionally arranged uniformly, the liquid resin 31 spreads isotropically toward the through hole 13c. Here, as described above, since the through hole 13c of the semiconductor chip 11c is diagonally provided in plan view with respect to the through hole 13d of the semiconductor chip 11d, the liquid resin 31 reaches the through hole 13c. By the time, the gap between the semiconductor chip 11d and the semiconductor chip 11c is reliably filled with the liquid resin 31. Then, the liquid resin 31 that has passed through the through hole 13c due to capillary action or gravity flows into the gap between the semiconductor chip 11c and the semiconductor chip 11b.

続いて、図２（ｃ）に示すように半導体チップ１１ｃと半導体チップ１１ｂとの間隙を液状樹脂３１により充填した後、貫通孔１３ｂを通過した液状樹脂３１により半導体チップ１１ｂと半導体チップ１１ａとの間隙が充填され、貫通孔１３ａを通過した液状樹脂３１により半導体チップ１１ａと回路基板２１との間隙が順に充填される。そして、半導体チップ１１ａと回路基板２１との間の周縁に設けられた封止材１４の開口部１４ａに液状樹脂３１が到達した時点で、貫通孔１３ｄからの液状樹脂３１の注入を止める。   Subsequently, as shown in FIG. 2C, the gap between the semiconductor chip 11c and the semiconductor chip 11b is filled with the liquid resin 31, and then the liquid resin 31 that has passed through the through hole 13b is used to connect the semiconductor chip 11b and the semiconductor chip 11a. The gap is filled, and the gap between the semiconductor chip 11a and the circuit board 21 is filled in order with the liquid resin 31 that has passed through the through hole 13a. Then, when the liquid resin 31 reaches the opening 14a of the sealing material 14 provided at the periphery between the semiconductor chip 11a and the circuit board 21, the injection of the liquid resin 31 from the through hole 13d is stopped.

その後、熱処理により液状樹脂３１を硬化させることで、回路基板２１上に半導体チップ１１ａ〜１１ｄがフリップチップ接続により積層搭載された積層型半導体装置を完成させる。   Thereafter, the liquid resin 31 is cured by heat treatment to complete a stacked semiconductor device in which the semiconductor chips 11a to 11d are stacked and mounted on the circuit board 21 by flip chip connection.

このような積層型半導体装置の製造方法およびこれによって得られる積層型半導体装置によれば、最上部の半導体チップ１１ｄに設けられた貫通孔１３ｄにより、液状樹脂３１を１回供給することで、各半導体チップ１１間の間隙および半導体チップ１１ａと回路基板２１との間隙が確実に充填される。したがって、液状樹脂３１の充填工程を短くすることができ、生産性に優れている。   According to the manufacturing method of such a stacked semiconductor device and the stacked semiconductor device obtained thereby, the liquid resin 31 is supplied once through the through-hole 13d provided in the uppermost semiconductor chip 11d. The gap between the semiconductor chips 11 and the gap between the semiconductor chip 11a and the circuit board 21 are reliably filled. Therefore, the filling process of the liquid resin 31 can be shortened, and the productivity is excellent.

さらに、最上部の半導体チップ１１ｄの貫通孔１３ｄから液状樹脂３１を注入するため、各半導体チップ１１の周縁に液状樹脂３１を滴下するスペースを設けなくてもよい。したがって、各半導体チップ１１の形状と大きさを同一にすることができ、積層型半導体装置のさらなる小型化が可能である。   Further, since the liquid resin 31 is injected from the through hole 13d of the uppermost semiconductor chip 11d, it is not necessary to provide a space for dropping the liquid resin 31 on the periphery of each semiconductor chip 11. Therefore, the shape and size of each semiconductor chip 11 can be made the same, and the stacked semiconductor device can be further miniaturized.

なお、上述した実施形態では、一例として各半導体チップ１１の角部に１つの貫通孔１３をそれぞれ形成することとしたが、貫通孔１３を形成する位置および貫通孔１３の個数については、１回の液状樹脂３１の供給により、各半導体チップ１１間の間隙および半導体チップ１１ａと回路基板２１との間隙が確実に充填されれば、特に限定されるものではない。ただし、貫通孔１３の形成位置については、素子特性等への影響を考えると各半導体チップ１１の周縁に設けられていた方が、実用性が高いため好ましく、特に貫通孔１３が１つの場合には、上記実施形態のように、各半導体チップ１１の角部に各半導体チップ１１の直上部または直下部に配置される半導体チップとは対角になるように配置されることが、液状樹脂３１の充填効率がよいため、好ましい。   In the embodiment described above, one through hole 13 is formed at each corner of each semiconductor chip 11 as an example. However, the positions where the through holes 13 are formed and the number of the through holes 13 are set once. The liquid resin 31 is not particularly limited as long as the gap between the semiconductor chips 11 and the gap between the semiconductor chip 11a and the circuit board 21 are reliably filled. However, regarding the formation position of the through-hole 13, it is preferable that it is provided at the periphery of each semiconductor chip 11 in view of the influence on the element characteristics and the like because it is highly practical. Especially when the number of the through-holes 13 is one. As in the above-described embodiment, the liquid resin 31 is arranged at the corner of each semiconductor chip 11 so as to be diagonal to the semiconductor chip disposed immediately above or directly below each semiconductor chip 11. Is preferable because of its good packing efficiency.

また、各半導体チップ１１に貫通孔１３を複数形成してもよい。この場合には、各半導体チップ１１の各貫通孔１３が、この半導体チップ１１の直上部または直下部に配置される半導体チップ１１の各貫通孔１３に対して、重ならないように、なるべく離れた位置に配置された方が、各半導体チップ１１間の間隙および半導体チップ１１ａと回路基板２１との間隙を効率よく充填することができ、好ましい。   A plurality of through holes 13 may be formed in each semiconductor chip 11. In this case, each through hole 13 of each semiconductor chip 11 is separated as much as possible so as not to overlap with each through hole 13 of the semiconductor chip 11 arranged immediately above or directly below the semiconductor chip 11. It is preferable to arrange them at the positions because the gaps between the semiconductor chips 11 and the gaps between the semiconductor chip 11a and the circuit board 21 can be efficiently filled.

また、回路基板２１と半導体チップ１１ａとの間隙に液状樹脂３１を供給する場合には、積層型半導体装置を上下反転させた状態で、液状樹脂３１を供給してもよい。ただし、この場合には、半導体チップ１１ａを回路基板２１よりも一回り大きく形成する等、液状樹脂３１を滴下するスペースが必要がある。さらに、回路基板２１に貫通孔を形成し、この貫通孔から液状樹脂３１を供給してもよい。   When supplying the liquid resin 31 to the gap between the circuit board 21 and the semiconductor chip 11a, the liquid resin 31 may be supplied in a state where the stacked semiconductor device is turned upside down. However, in this case, a space for dropping the liquid resin 31 is required, such as forming the semiconductor chip 11a slightly larger than the circuit board 21. Furthermore, a through hole may be formed in the circuit board 21 and the liquid resin 31 may be supplied from the through hole.

また、上記実施形態では、各半導体チップ１１間および半導体チップ１１ａと回路基板２１との間の周縁を封止材１４で接合した例について説明したが、封止材１４は特に形成しなくてもよい。この場合には、各半導体チップ１１に設けられる貫通孔１３の位置および個数を制御して、各半導体チップ１１の周縁から液状樹脂３１が流出しないようにする。   Moreover, although the said embodiment demonstrated the example which joined the periphery between each semiconductor chip 11 and between the semiconductor chip 11a and the circuit board 21 with the sealing material 14, it does not need to form the sealing material 14 in particular. Good. In this case, the position and the number of through holes 13 provided in each semiconductor chip 11 are controlled so that the liquid resin 31 does not flow out from the peripheral edge of each semiconductor chip 11.

本発明の実施の形態における積層型半導体装置を構成する半導体チップの平面図（ａ）、（ｂ）である。It is a top view (a) of a semiconductor chip which constitutes a lamination type semiconductor device in an embodiment of the invention, (b). 本発明の積層型半導体装置の製造方法に係る実施の形態を説明するための製造工程断面図である。It is manufacturing process sectional drawing for demonstrating embodiment which concerns on the manufacturing method of the laminated semiconductor device of this invention. 従来の積層型半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the conventional laminated semiconductor device. 従来の積層型半導体装置の製造方法に係る課題を説明するための断面図である。It is sectional drawing for demonstrating the subject which concerns on the manufacturing method of the conventional laminated semiconductor device.

符号の説明Explanation of symbols

１１（１１ａ，１１ｂ，１１ｃ，１１ｄ）…半導体チップ、１２…バンプ、１３（１３ａ，１３ｂ，１３ｃ，１３ｄ）…貫通孔、１４…封止材、２１…回路基板、２２…バンプ、３１…液状樹脂   11 (11a, 11b, 11c, 11d) ... semiconductor chip, 12 ... bump, 13 (13a, 13b, 13c, 13d) ... through hole, 14 ... sealing material, 21 ... circuit substrate, 22 ... bump, 31 ... liquid resin

Claims (2)

バンプが一主面側に設けられている複数の半導体チップを、フリップチップ接続によって回路基板上に積層して搭載する搭載工程と、
前記搭載工程で前記回路基板上に搭載された前記複数の半導体チップの間の間隙、および、前記複数の半導体チップのうち前記回路基板の直上に設けられた最下部の半導体チップと前記回路基板の間の間隙に、液状樹脂を注入して充填する液状樹脂充填工程と
を有し、
前記搭載工程の実施前に、
前記複数の半導体チップのそれぞれに貫通孔を形成する貫通孔形成工程と、
前記複数の半導体チップの一主面の周縁部に封止材を形成する封止材形成工程と
を実施し、
前記搭載工程では、前記複数の半導体チップの間の間隙、および、前記最下部の半導体チップと前記回路基板との間の間隙が、前記複数の半導体チップのそれぞれに設けられた前記貫通孔で連通された状態になるように、前記複数の半導体チップのそれぞれを、前記回路基板上に順次搭載し、前記封止材で互いを接合し、
前記液状樹脂充填工程では、前記搭載工程で前記回路基板上に搭載された前記複数の半導体チップのうち前記回路基板から最も離れた最上層の半導体チップに設けられた貫通孔から、前記液状樹脂を注入する、
積層型半導体装置の製造方法。 A mounting step of stacking and mounting a plurality of semiconductor chips with bumps provided on one main surface side on a circuit board by flip chip connection;
Gaps between the plurality of semiconductor chips mounted on the circuit board in the mounting step, and a lowermost semiconductor chip provided immediately above the circuit board among the plurality of semiconductor chips and the circuit board A liquid resin filling step for injecting and filling the liquid resin in the gap between
Before carrying out the mounting process,
A through hole forming step of forming a through hole in each of the plurality of semiconductor chips;
Performing a sealing material forming step of forming a sealing material on a peripheral portion of one main surface of the plurality of semiconductor chips,
In the mounting step, a gap between the plurality of semiconductor chips and a gap between the lowermost semiconductor chip and the circuit board are communicated with each other through the through holes provided in each of the plurality of semiconductor chips. Each of the plurality of semiconductor chips is sequentially mounted on the circuit board so as to be in a state of being bonded, and bonded to each other with the sealing material,
In the liquid resin filling step, the liquid resin is removed from a through hole provided in an uppermost semiconductor chip farthest from the circuit board among the plurality of semiconductor chips mounted on the circuit board in the mounting step. inject,
A method of manufacturing a stacked semiconductor device. 前記貫通孔形成工程では、前記複数の半導体チップの一主面の周縁部において前記バンプが設けられる部分よりも外側の部分に、前記貫通孔を形成し、
前記封止材形成工程では、前記複数の半導体チップの一主面の周縁部において、前記貫通孔が形成される部分よりも外側の部分に、前記封止材を形成する、
請求項１に記載の積層型半導体装置の製造方法。 In the through-hole forming step, the through-hole is formed in a portion outside a portion where the bump is provided in a peripheral portion of one main surface of the plurality of semiconductor chips,
In the sealing material forming step, the sealing material is formed in a peripheral portion of one main surface of the plurality of semiconductor chips in a portion outside a portion where the through hole is formed.
A method for manufacturing a stacked semiconductor device according to claim 1.
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