JP4729872B2 - Method for manufacturing field effect transistor - Google Patents

Description

The present invention relates to a manufacturing method capable of manufacturing a field effect transistor (various FET or HEMT etc.) by a Group III nitride compound semiconductor crystal growth.

As a structure of a field effect transistor manufactured by crystal growth of a group III nitride compound semiconductor and a manufacturing method thereof, for example, a technique described in Patent Document 1 below is widely known.
In these conventional techniques, hydrogen (H ₂ ) gas is often used as a carrier gas for carrying a material gas when a semiconductor layer is crystal-grown.

The reason is as follows.
(Reason 1) When hydrogen gas is used, it is relatively easier to form a semiconductor layer for crystal growth with good crystallinity than other carrier gases. This is advantageous in terms of variations in sheet resistance of the elements, element characteristics, yield, and the like.
(Reason 2) When hydrogen gas is used, the flatness of the interface between the semiconductor layers such as the buffer layer and the barrier layer, or the sharpness of the composition fluctuation in the vicinity of the interface is improved compared to other carrier gases. Easy. For this reason, it is relatively easy to ensure high and favorable mobility of carriers moving through the channel. This is advantageous in terms of downsizing and high performance of the element.
JP2003-45899

However, when hydrogen (H ₂ ) gas is used as the carrier gas, the surface of the semiconductor layer to be finally stacked is difficult to be formed flat or smooth, and as a result, the following problems occur.
(Problem 1) If the unevenness of the surface of the semiconductor layer is too large relative to the size of the electrode to be connected, it becomes difficult to accurately form the electrode on the surface. . For this reason, miniaturization of the electrode is hindered, and it is difficult to reduce the size of the element.
(Problem 2) Alternatively, even if an electrode can be formed at a desired position, electrode characteristics such as connection strength and ohmic properties cannot always be sufficiently stabilized. For this reason, it is difficult to ensure the yield of the element, and it is therefore difficult to establish an industrial mass production system of a desired field effect transistor.

It is considered that the cause of the surface roughness as described above is due to the etching action produced by hydrogen (H ₂ ) gas. Therefore, in order to improve this point, for example, when the barrier layer is crystal-grown using nitrogen (N ₂ ) gas as a carrier gas, the above-described problem of surface roughness can be improved. However, according to this method, it is inevitably difficult to simultaneously obtain desired electrical characteristics related to mobility, sheet resistance, and the like, which have been obtained based on the above-described reasons 1 and 2.

  The present invention was made in order to solve the above-mentioned problems, and the purpose thereof was excellent in the sheet resistance of the element, the reliability of the formation of the fine electrode, the mobility of carriers in the channel, etc. It is to realize a field effect transistor suitable for high performance and miniaturization.

First, an example of a field effect transistor manufactured by the present manufacturing method will be described.
A field effect transistor has a buffer layer made of a group III nitride compound semiconductor and a barrier layer, and a channel is formed on the interface side of the buffer layer with respect to the barrier layer. , A multilayer structure having at least the following two layers (1) and (2) .
(1) A steep interface providing layer that constitutes the lowermost semiconductor layer of the barrier layers and has a sharp change in composition at the interface with the buffer layer.
(2) An electrode connection surface providing layer that constitutes the uppermost semiconductor layer of the barrier layers and has a flat upper surface.
Further, each of the semiconductor layers constituting the barrier layer may be formed from non-doped Al _x Ga _1-x N (0 <x ≦ 1) .

However, the barrier layer is generally sometimes referred to as a carrier supply layer. In addition, the above buffer layer is generally sometimes referred to as a base layer. In the field of semiconductor crystal growth, the buffer layer referred to in the above first means is used to solve or alleviate the problem of the difference in lattice constant between the desired semiconductor layer to be crystal-grown and the crystal growth substrate. Although it does not mean a thin semiconductor layer (eg, an AlN layer having a film thickness of about 250 nm) formed between the layers, in the actual configuration, such a semiconductor layer is also referred to as the first means. It may be included in the concept of the buffer layer (underlayer).
For example, when a crystal growth substrate made of a GaN bulk crystal is used, the above problem of difference in lattice constant does not exist from the beginning, but in such a case, a buffer layer (underlayer) is necessary. However, in this case, the crystal growth substrate made of the GaN bulk crystal, may serve as buffer layer (underlying layer).

A drain electrode, a source electrode, and a gate electrode are formed on the uppermost semiconductor layer of the barrier layer. However, the gate electrode may be formed indirectly through an insulating film or the like. The configuration related to these various electrodes may be arbitrary. For example, a well-known appropriate configuration may be arbitrarily selected and adopted in consideration of ohmic properties, rectifying action, and the like. Further, the electric field effect transistor data, such as by the thickness of the barrier layer, even in the transistor of the normally-on, even in the normally-off transistor can be configured to any of the type of field-effect transistors. These various configurations may be arbitrary.

Below, it is described with the various requirements for optimizing the structure or procedure for manufacturing the electric field effect transistor.
In order to form a channel with a high carrier mobility or to optimize the ohmic characteristics of the barrier layer in the vicinity of each ohmic electrode, the carrier energy level in the direction perpendicular to the barrier layer (ie Needless to say, optimization of (band gap) is required, but at least the following parameters (1) to (3) are very important in order to perform the optimization.

(1) Thickness of semiconductor layer In particular, by optimizing each thickness of each semiconductor layer constituting the barrier layer, the barrier layer can be appropriately depleted, or the probability of carrier tunneling in the tunnel effect described above Can be optimized. Alternatively, by optimizing the thicknesses of the respective semiconductor layers constituting the barrier layer, it is possible to further ensure the controllability of the channel generation / extinction due to the gate voltage. That is, by optimizing the thickness of each semiconductor layer, the flow of electron supply and the controllability of the electron storage layer (channel) can be improved.

(2) Al composition ratio If the Al composition ratio of each semiconductor layer is optimized, the band gap energy or the electron affinity of each semiconductor layer can be optimized, thereby forming a good channel structure. be able to.
For example, the electron affinity of the barrier layer must be smaller than the electron affinity of the buffer layer. That is, basically, the band gap energy of the barrier layer must be larger than the band gap energy of the buffer layer. Therefore, when both the barrier layer and the buffer layer are formed of Al _x Ga _1-x N (0 <x ≦ 1), the Al composition ratio x of the barrier layer is greater than the Al composition ratio x of the buffer layer. Must also be large. Moreover, it is desirable that the difference between the band gap energies of both layers is basically large. Of course, the Al composition ratio of the barrier layer can also be an optimization parameter for the ohmic characteristics of the barrier layer.
In particular, in the case of a semiconductor layer directly bonded to an ohmic electrode (source electrode, drain electrode), good ohmic properties can be ensured by optimizing the Al composition ratio.

(3) Presence / absence of impurities The carrier density, insulation, ohmic characteristics, etc. of each semiconductor layer can be optimized by the presence / absence or concentration of the dopant (impurities). In order to realize high mobility, it is better not to add impurities in order to prevent carrier scattering in at least a semiconductor layer that forms a channel and its vicinity. Further, it is better not to add impurities even if the semiconductor layer is required to have a high resistivity. In these meanings, in particular, the semiconductor layer constituting at least the uppermost layer of the buffer layer is preferably a non-doped layer.
However, the barrier layer is not necessarily a non-doped layer, and may be formed, for example, in an n-type. Even by this configuration, it is possible to manufacture a high-performance field-effect transistor.

The first present invention, and a buffer layer and a barrier layer made of group III nitride compound semiconductor, a method of manufacturing a field effect transistor channel interface side with respect to the barrier layer of the buffer layer is formed, the barrier In the crystal growth process for crystal growth of the layer, the gas partial pressure ratio R occupied by hydrogen (H ₂ ) gas in the carrier gas carrying the material gas of the barrier layer is set to “r ₁ ≧ R ≧ r ₂ (1 ≧ r ₁ > _{1 / 4,1 / 2> r 2} ≧ 0, r 1> r 2) "within a range of, continuously or stepwise with respect to time t, the field effect transistor and decreases monotonously It is a manufacturing method.
However, more preferably, in the crystal growth step for crystal growth of the barrier layer, the gas partial pressure ratio R is set to “r ₁ ≧ R ≧ r ₂ (1 ≧ r ₁ > 1/2, 1/4> r _2). Within a range of “≧ 0)”, the time t is decreased monotonously continuously or stepwise.
In the second aspect of the invention , the gas partial pressure ratio R is decreased m times (m ≧ 1) stepwise in the crystal growth step, thereby making the barrier layer non-doped Al _x Ga _1-x N (0 <x A method of manufacturing a field effect transistor, characterized in that the field effect transistor is formed from a total of m + 1 semiconductor layers .
Further, according to the third invention, the barrier layer has a two-layer structure, and the barrier layer first layer to be stacked first is crystal-grown using hydrogen (H ₂ ) gas as a main carrier gas, and then the barrier layer second layer to be stacked A method of manufacturing a field effect transistor, characterized in that a layer is crystal-grown using an inert gas composed of a rare gas or nitrogen (N ₂ ) gas as a main carrier gas .
It is very important to optimize each parameter examined above .
The conditions described below have been devised based on the above viewpoints. Therefore, it is more desirable to employ any one of the following means in carrying out the present invention more specifically.

Also, any of the semiconductor layers constituting the barriers layers may be formed of non-doped _{Al x Ga 1-x N (} 0.15 ≦ x ≦ 0.3).

Also, the aluminum composition ratio x of each semiconductor layer forming the barrier-layer, may be set so as to decrease monotonically in accordance with the stacking sequence.
However, the above-mentioned “decrease monotonically” means that it generally shows the following decreasing trend. That is, with the function z = f (N) for an independent variable the number N, "N ₁ <N ₂ ⇒f for any number N _1, N ₂ on the domain of N (N ₁₎ ≧ When “f (N ₂ )” holds, this function f is called a monotonically decreasing function in a broad sense, and the dependent variable z is said to monotonously decrease with respect to the number N. Therefore, it includes bringing all aluminum composition ratio x of each semiconductor layer forming the barrier-layer or partially identical.

Similarly, when the number N is replaced with a continuous variable such as time t, the same expression as above is used in the following. That is, for example, when “t ₁ <t ₂ ⇒z ₁ = f (t ₁ ) ≧ z ₂ = f (t ₂ )” holds for arbitrary times t ₁ and t ₂ in a predetermined domain. Similarly, the dependent variable z is said to decrease monotonically with respect to the independent variable t.

In the following, a first layer barrier layer stacked on the lower side, of a total of two layers semiconductor layer between the barrier layer barrier layer a second layer which is laminated on the upper side of the first layer, to form the barrier layer May be.
That is, here refers barrier layer first layer per suddenly Shun interface providing layer, said barrier layer a second layer impinging on the electrodes connecting surface providing layer.

Also, the film thickness d ₂ of the barrier layer a first layer thickness d ₁ and the barrier layer a second layer of both _{"10nm ≦ d 1 ≦ 30nm, 10nm} ≦ d 2 ≦ 30nm and,, 30 nm ≦ d ₁ It is desirable to set so that “+ d ₂ ≦ 60 nm” is satisfied .

Also, it is desirable to form the uppermost layer of the buffer layer of undoped GaN. However, the buffer layer may of course have a single layer structure. In that case, the uppermost layer of the buffer layer corresponds to the buffer layer itself.

The above- described means of the present invention can solve the above problem effectively or rationally.

The effects obtained by the above-described means of the present invention are as follows.
Further, according to the first invention, in the above crystal growth process, since the gas partial pressure ratio R is decreased stepwise or continuously monotonously, is possible to manufacture the electric field effect transistor allows or facilitates In addition, it is also possible or easy to manufacture a field effect transistor having a single layer structure of a barrier layer having device performance equivalent to those of the above. For example, when manufacturing a field effect transistor having a single-layer structure of the barrier layer, the gas partial pressure ratio R may be monotonously decreased, for example, substantially uniformly.
The reason why this first invention works well as described above is that, as mentioned above, the higher the gas partial pressure ratio R, the easier the above-mentioned steep interface providing layer is formed, This is because as the gas partial pressure ratio R is lower, the electrode connection surface providing layer is more easily formed. However, the advantage of the steep interface is that the mobility of electrons moving in the channel is improved as mentioned above. The advantage of the flat or smooth surface is that, as mentioned above, the electrodes can be miniaturized or easier than before. According to the second invention, it said gas partial pressure ratio R is than reduced stepwise and monotonic over m times, it is possible to produce a superior field-effect transistor.
According to the third invention, it becomes possible or easier to manufacture the electric field effect transistor. In addition, the higher the gas partial pressure ratio R, the easier the formation of the steep interface providing layer, and the lower the gas partial pressure ratio R, the better the electrode connecting surface providing layer. Therefore, according to the third aspect of the invention , extremely good device characteristics can be realized.
According to the field effect transistor as an example manufactured by the manufacturing method of the present invention, the crystallinity of the barrier layer can be satisfactorily ensured by the steep interface providing layer, and the vicinity of the interface between the barrier layer and the buffer layer The compositional change of the semiconductor crystal becomes sharp.
Further, the flatness and smoothness of the surface of the barrier layer are ensured by the electrode connection surface providing layer.

  Ensuring the steepness of the interface between the barrier layer and the buffer layer is considered to have an effect of suppressing reduction in carrier mobility due to scattering of carriers moving in the channel.

Therefore, the electric field effect transistor, the mobility and the carrier moving in the channel formed in the vicinity of the interface of the above, or the various electrical properties such as sheet resistance of the device can be secured satisfactorily simultaneously, the surface of the barrier layer The flatness and smoothness of the gate electrode are ensured well, thereby improving the adhesion of the gate electrode, so that it is possible or easy to improve the controllability of the field effect by the gate voltage at the same time.

Furthermore, it is easy to ensure a large band gap energy of the barrier layer. Therefore, a sufficiently large difference between the band gap energy of the barrier layer and the band gap energy of the buffer layer can be ensured without using a semiconductor crystal containing indium (In) for the buffer layer. Therefore, rough interface between the barrier layer and the buffer layer is less likely to occur. Immediate Chi, it is possible to secure flat or smooth interface between the barriers layers and the buffer layer, it is possible to satisfactorily ensure more reliably carrier mobility.
Moreover, it is advantageous from the viewpoint of the pressure resistance of the semiconductor element to make the barrier layer a non-doped layer.

In addition, when a semiconductor crystal containing indium (In) is crystal-grown, the situation in which interface roughness is likely to occur between other semiconductor layers stacked thereafter is easy from the following documents, for example. Can understand.
(1) Published patent publication: JP-A-11-068159
(2) Published patent publication: JP-A-9-139543
(3) Published patent publication: JP-A-8-88432

Also, it becomes possible or easier to optimizing the potential curve of the peripheral switch Yaneru. In particular, the setting of the lower limit for the aluminum composition ratio is a constraint for reliably forming a channel, while the setting of the upper limit is a constraint for forming a good ohmic electrode .

Further, it is possible to secure a large difference in band gap energy and the buffer layer of the barrier-layer, it becomes possible or easier to optimizing the potential curve around the channel. In particular, for a semiconductor layer to which an ohmic electrode is directly bonded, it is easy to ensure good ohmic properties by optimizing the electron affinity .

Also, the barrier layer of the field effect transistor can be realized in a two-layer structure. That is, the steep interface providing layer can be formed by the barrier layer first layer, and the electrode connection surface providing layer can be constituted by the barrier layer second layer. That is, it is possible to realize the barriers layers which have a respective and abrupt interface providing layer and the electrode connection plane providing layer which includes an individual advantages of above minimum stackup.
That is, this arrangement is a means for realizing the most easily electric field effect transistor, thus, according to this configuration, efficient field effect transistor highly advantageous present invention to the miniaturization and higher performance Can be produced.

Also, since the total thickness of the barrier layer is optimized, it is possible to optimize the ohmic characteristic of the barrier layer. However, if the electrode connection surface providing layer (the second barrier layer) is formed too thin, a flat or smooth surface becomes difficult to be formed. Because it becomes easy, attention is required.
Immediately Chi, with the thickness of the thickness of the barrier layer first layer and the barrier layer a second layer, in view of these effects, shows the empirical and comprehensively optimized proper range.

Further, in order to realize high mobility, it is preferable that at least a semiconductor layer in which a channel is formed does not contain impurities in order to prevent carrier scattering. Further, it is better not to add impurities even if the semiconductor layer is required to have a high resistivity. In these sense, in particular, a semiconductor layer constituting at least the uppermost layer of the buffer layer, it is desirable that non-doped layer.

Also, in the case of forming the uppermost bar Ffa layer of GaN, if formed from a semiconductor containing no indium uppermost buffer layer _{(Al x Ga 1-x N} (0 ≦ x ≦ 1)), The band gap energy of the uppermost layer can be minimized. Indium (In) is not used here in order to satisfactorily prevent the roughening of the interface between the buffer layer and the barrier layer as mentioned above. In these cases, GaN has the smallest band gap. It can be said that it is a semiconductor that gives energy.
Therefore, it is possible to satisfactorily form the Nozomu Tokoro channel.

As an inert gas used for crystal growth of the barrier layer, a rare gas (He, Ne, Ar, Kr, Xe, Rn), nitrogen (N ₂ ) gas, or a mixed gas thereof can be used. Moreover, when using these mixed gases as an inert gas, the mixing ratio may be arbitrary. In addition, when hydrogen (H ₂ ) gas, nitrogen (N ₂ ) gas, or rare gas is used as the main carrier gas (that is, the main component of the carrier gas), it is desirable in the semiconductor crystal to be crystal-grown. As long as there is no fear of remaining (mixed) atoms or molecules, even if a small amount or a slight amount of other gases are mixed in the carrier gas, the action of the present invention is not particularly disturbed.

In addition, as a material for the crystal growth substrate constituting the field effect transistor of the present invention, silicon carbide (SiC) is most suitable in terms of heat resistance and heat dissipation, but sapphire, An embodiment using silicon (Si) or the like can be sufficiently considered. In addition, using a GaN substrate is not advantageous in terms of cost and heat dissipation, but adoption of the GaN substrate does not particularly impede application of the present invention.
Further, any known form can be adopted as a form of forming the ohmic electrode or the Schottky electrode. For example, the gate electrode may be formed on the uppermost layer of the barrier layer via a thin insulating film as mentioned above.

Hereinafter, the present invention will be described based on specific examples.
However, the embodiments of the present invention are not limited to the following examples.

  FIG. 1 is a cross-sectional view of the field effect transistor 100 of the first embodiment. This field effect transistor 100 is a semiconductor element formed by sequentially stacking group III nitride compound semiconductors by crystal growth, and the crystal growth substrate 101 is made of sapphire having a thickness of about 300 μm. On the crystal growth substrate 101, an AlN layer 102 made of AlN having a thickness of about 40 nm is formed. This AlN layer 102 is for eliminating or alleviating the mismatch in lattice constant between the crystal growth substrate 101 and the semiconductor layer 103 to be stacked later.

  A semiconductor layer 103 made of non-doped GaN having a thickness of about 2 μm is formed on the AlN layer 102. Hereinafter, the total two layers of the semiconductor layer 103 and the AlN layer 102 may be collectively referred to simply as a buffer layer. Of course, this buffer layer (layer 102 and layer 103) is a semiconductor layer corresponding to the buffer layer described in claim 1 or the like.

Further, a semiconductor layer 104 made of non-doped Al _0.2 Ga _0.8 N having a thickness of about 40 nm is stacked on the semiconductor layer 103. The film thickness (about 40 nm) of the semiconductor layer 104 is such that a channel generated near the interface between the barrier layer and the buffer layer when the gate is turned on, that is, the interface between the layer 1041 and the layer 103, and the following individual ohmic electrodes: The tunnel effect of carriers (electrons) between (105, 107) is set so as to surely and satisfactorily appear.

That is, the semiconductor layer 104 is composed of a total of two semiconductor layers, a steep interface providing layer 1041 having a thickness of about 30 nm based on the present invention and an electrode connection surface providing layer 1042 having a thickness of about 10 nm based on the present invention. . Both of these are formed of non-doped Al _0.2 Ga _0.8 N as described above, but H ₂ was used as a carrier gas when the steep interface providing layer 1041 was grown. In addition, N ₂ was used as a carrier gas when the electrode connection surface providing layer 1042 was crystal-grown.

  Reference numerals 105, 106, and 107 denote a source electrode (ohmic electrode), a gate electrode (Schottky electrode), and a drain electrode (ohmic electrode), respectively. Each ohmic electrode (source electrode 105 and drain electrode 107) is formed by laminating a thin metal layer made of titanium (Ti) with a thickness of about 100 mm and depositing aluminum (Al) thereon with a thickness of about 3000 mm. A metal layer is further laminated by vapor deposition. These ohmic electrodes are well adhered and alloyed by heat treatment at about 700 ° C. to 900 ° C. by flash annealing for less than 1 second. On the other hand, the gate electrode 106 is a Schottky electrode formed by depositing a metal layer made of nickel (Ni) of about 100 Å by vapor deposition, and further depositing a metal layer made of gold (Au) on it about 3000 Å. .

Hereinafter, the manufacturing method of the above-described field effect transistor 100 will be described focusing on the characteristic portions (semiconductor layers 1041 and 1042) of the present invention.
Each of the semiconductor layers (semiconductor layers 102, 103, 104) of the field effect transistor 100 is grown by vapor phase growth using a metal organic compound vapor phase growth method (MOVPE). The gases used here are carrier gas (H ₂ or N ₂ ), ammonia gas (NH ₃ ), trimethyl gallium (Ga (CH ₃ ) ₃ ), trimethyl aluminum (Al (CH ₃ ) ₃ ), etc. It is.
However, as a method for crystal growth of these semiconductor layers, in addition to the above-mentioned organometallic compound vapor phase epitaxy (MOVPE), molecular beam vapor phase epitaxy (MBE), halide vapor phase epitaxy (HVPE), etc. Is effective.

FIG. 2 shows a carrier gas supply mode when the barrier layer 104 (that is, the steep interface providing layer 1041 and the electrode connection surface providing layer 1042) is formed in the first embodiment. The vertical axis of this graph indicates the partial pressure ratio R of hydrogen (H ₂ ) gas in the carrier gas. The horizontal axis represents the crystal growth time. Time t = 0 represents the crystal growth start time of the steep interface providing layer 1041, and time t = t ₁ represents the crystal growth end time of the electrode connection surface providing layer 1042. .
More specifically, the barrier layer 104 was laminated according to the following crystal growth conditions.

(Crystal growth conditions for barrier layer 104)
(1) Steep interface providing layer 1041
(A) Carrier gas: H ₂ (R≈1)
(B) Crystal growth temperature: 1000 [° C.]
(C) Crystal growth pressure: 1013 [hPa] (total pressure in crystal growth furnace)

(2) Electrode connection surface providing layer 1042
(A) Carrier gas: N ₂ (R≈0)
(B) Crystal growth temperature: 1000 [° C.]
(C) Crystal growth pressure: 1013 [hPa] (total pressure in crystal growth furnace)

FIG. 3 shows that when the thickness (: d ₁ + d ₂ ) of the entire barrier layer 104 is fixed to 400 mm, the film thickness d ₂ [Å] of the electrode connection surface providing layer 1042 is used as a parameter. 5 types of surface images (surface morphology) (d ₂ = 0 to 400 mm) are output using an atomic force microscope.
FIG. 4-A shows the relationship between the film thickness d _{2 of the} electrode connection surface providing layer 1042 and the roughness of each surface. The vertical axis represents the average amplitude (Root Mean Square) of the uneven waveform in one direction on the surface of the electrode connection surface providing layer 1042, with the value when d ₂ = 0Å as a reference (: normalized surface roughness = 1), That is, it is standardized with reference to the case where the entire barrier layer 104 is formed by only the steep interface providing layer 1041 having a thickness of about 400 mm.

Further, the graph of FIG. 4-B shows the relationship between the normalized value of the sheet resistance of the field effect transistor 100 before the formation of the gate electrode 106 and the film thickness d ₂ as in the case of FIG. The value when ₂ = 0 ₂ is shown as a reference (standardized sheet resistance = 1).
From these measurements, when the barrier layer 104 total thickness to 400 Å, a proper range of the thickness d ₂ of the electrode connection plane providing layer 1042 is in the range of about 100A～300A, more preferably about 150Å It can be said that it is in a range of about ~ 200 mm.

  As described above, as a result of forming the barrier layer 104, in the field effect transistor 100 of the first embodiment, various electrical characteristics such as sheet resistance can be secured satisfactorily, and at the same time, electrodes are formed based on good surface flatness. It was possible to miniaturize more effectively.

  FIG. 5 is a cross-sectional view of the field effect transistor 200 of the second embodiment. The field effect transistor 200 is a semiconductor element formed by sequentially stacking group III nitride compound semiconductors by crystal growth, and the crystal growth substrate 201 is formed of silicon carbide (SiC) having a thickness of about 400 μm. ing. An AlN layer 202 made of AlN having a thickness of about 0.2 μm is formed on the crystal growth substrate 201. This AlN layer 202 is for eliminating or alleviating the mismatch of lattice constants between the crystal growth substrate 201 and the semiconductor layer 203 to be laminated later.

  A semiconductor layer 203 made of non-doped GaN having a thickness of about 2 μm is formed on the AlN layer 202. Hereinafter, the total two layers of the semiconductor layer 203 and the AlN layer 202 may be collectively referred to simply as a buffer layer. Of course, this buffer layer (the layer 202 and the layer 203) is a semiconductor layer corresponding to the buffer layer described in claim 1 or the like.

Further, a semiconductor layer 204 made of non-doped Al _0.25 Ga _0.75 N having a thickness of about 40 nm is stacked on the semiconductor layer 203. The film thickness (about 40 nm) of the semiconductor layer 204 is such that when the gate is turned on, a channel generated near the interface between the barrier layer and the buffer layer, that is, the interface between the layer 2041 and the layer 203, and the following individual ohmic electrodes: The tunnel effect of carriers (electrons) between (205, 207) is set so as to surely and satisfactorily appear.

That is, the semiconductor layer 204 is composed of a total of two semiconductor layers, a steep interface providing layer 2041 having a thickness of about 10 nm based on the present invention and an electrode connection surface providing layer 2042 having a thickness of about 30 nm based on the present invention. . Both of these are formed of non-doped Al _0.25 Ga _0.75 N as described above, but H ₂ was used as a carrier gas when the steep interface providing layer 2041 was crystal-grown. In addition, N ₂ was used as a carrier gas when the electrode connection surface providing layer 2042 was crystal-grown.

  Reference numerals 205, 206, and 207 denote a source electrode (ohmic electrode), a gate electrode (Schottky electrode), and a drain electrode (ohmic electrode), respectively. Each ohmic electrode (source electrode 205 and drain electrode 207) is formed by laminating a thin metal layer made of titanium (Ti) with a thickness of about 100 mm and depositing thereon with a thickness of about 3000 mm made of aluminum (Al). A metal layer is further laminated by vapor deposition. These ohmic electrodes are well adhered and alloyed by heat treatment at about 700 ° C. to 900 ° C. by flash annealing for less than 1 second. On the other hand, the gate electrode 206 is a Schottky electrode formed by depositing a metal layer made of nickel (Ni) of about 100% by vapor deposition and further depositing a metal layer made of gold (Au) on the metal layer by about 3000%. .

Hereinafter, the manufacturing method of the above-described field effect transistor 200 will be described focusing on the characteristic portions (semiconductor layers 2041 and 2042) of the present invention.
Each of the semiconductor layers (semiconductor layers 202, 203, and 204) of the above-described field effect transistor 200 is grown by vapor phase growth using a metal organic compound vapor phase growth method (MOVPE). The gases used here are carrier gas (H ₂ or N ₂ ), ammonia gas (NH ₃ ), trimethyl gallium (Ga (CH ₃ ) ₃ ), trimethyl aluminum (Al (CH ₃ ) ₃ ), etc. It is.
However, as a method for crystal growth of these semiconductor layers, in addition to the above-mentioned organometallic compound vapor phase epitaxy (MOVPE), molecular beam vapor phase epitaxy (MBE), halide vapor phase epitaxy (HVPE), etc. Is effective.

The carrier gas supply mode at the time of forming the barrier layer 204 (that is, the steep interface providing layer 2041 and the electrode connection surface providing layer 2042) in the second embodiment is shown in FIG. 2 as in the first embodiment. The vertical axis of this graph indicates the partial pressure ratio R of hydrogen (H ₂ ) gas in the carrier gas, as in Example 1 described above. The horizontal axis represents the crystal growth time. Time t = 0 represents the crystal growth start time of the steep interface providing layer 2041, and time t = t ₁ represents the crystal growth end time of the electrode connection surface providing layer 2042. .
More specifically, the barrier layer 204 was laminated according to the following crystal growth conditions.

(Crystal growth conditions for the barrier layer 204)
(1) Steep interface providing layer 2041
(A) Carrier gas: H ₂ (R≈1)
(B) Crystal growth temperature: 1000 [° C.]
(C) Crystal growth pressure: 1013 [hPa] (total pressure in crystal growth furnace)

(2) Electrode connection surface providing layer 2042
(A) Carrier gas: N ₂ (R≈0)
(B) Crystal growth temperature: 1000 [° C.]
(C) Crystal growth pressure: 1013 [hPa] (total pressure in crystal growth furnace)

FIG. 6 shows that when the thickness (: d ₁ + d ₂ ) of the entire barrier layer 204 is fixed to 40 nm, the film thickness d ₂ [Å] of the electrode connection surface providing layer 2042 is used as a parameter. Two types of images of the surface (d ₂ = 0 nm, 30 nm) are output using an atomic force microscope.
FIG. 7A shows the relationship between the film thickness d _{2 of the} electrode connection surface providing layer 2042 and the roughness of each surface. The vertical axis represents the average amplitude (Root Mean Square) of the uneven waveform in one direction of the surface of the electrode connection surface providing layer 2042, with the value when d ₂ = 0Å being the reference (: normalized surface roughness = 1), That is, it is standardized with reference to the case where the entire barrier layer 204 is formed by only the steep interface providing layer 2041 having a film thickness of about 40 nm.

7B shows the relationship between the normalized value of the sheet resistance of the field effect transistor 200 before the formation of the gate electrode 206 and the film thickness d ₂ as in the case of FIG. 7A. The value when ₂ = 0 nm is shown as a reference (standardized sheet resistance = 1).
Also from these measurement results, the barrier layer 204 is composed of two layers of a steep interface providing layer 2041 and an electrode connection surface providing layer 2042 in order to achieve both high and reasonable desired electrical characteristics and electrode miniaturization. It turns out that it is good to have a configuration.

  As described above, as a result of the formation of the barrier layer 204, in the field effect transistor 200 of the second embodiment, various electrical characteristics such as sheet resistance can be secured satisfactorily, and at the same time, electrodes can be formed based on good surface flatness. It was possible to miniaturize more effectively.

[Other variations]
The embodiment of the present invention is not limited to the above-described embodiment, and other modifications as exemplified below may be made. Even with such modifications and applications, the effects of the present invention can be obtained based on the functions of the present invention.

(Modification 1)
For example, in the first embodiment, as can be seen from FIG. 2, the partial pressure ratio R of the hydrogen gas occupying the carrier gas is reduced from about 1 to about 0 at a stroke. As illustrated in FIG. 4, the partial pressure ratio R of the hydrogen gas in the carrier gas may be continuously reduced substantially uniformly. In this case, the barrier layer 104 in question cannot be clearly divided into two layers (that is, the steep interface providing layer 1041 and the electrode connection surface providing layer 1042) as described above. A field effect transistor having substantially the same performance as the field effect transistor 100 can be manufactured.

(Modification 2)
Further, the partial pressure ratio R of the hydrogen gas occupying in the carrier gas may be reduced step by step in multiple steps. Further, it may be carried out in combination with a mode in which the current is gradually decreased or rapidly decreased in a stepwise manner. The embodiment illustrated in FIG. 9 exemplifies such a combination form.
In any of these embodiments, the actions and effects of the present invention can be obtained based on the means of the present invention.

The present invention relates to a method for preventing surface roughness of a semiconductor, and is intended to satisfactorily ensure the possibility or ease of miniaturization of electrodes of a semiconductor element. At the same time, the present invention relates to the mobility of carriers moving in a channel generated in a substantially planar shape in the vicinity of the interface between semiconductor layers stacked by crystal growth, in order to ensure good mobility. .
Therefore, the present invention is very useful for the design and manufacture of field effect transistors (such as various FETs and HEMTs) that can be manufactured by crystal growth of group III nitride compound semiconductors. It is very effective in improving performance and performance.

Sectional drawing of the field effect transistor 100 of Example 1 The graph which shows the carrier gas supply form in Example 1 Micrograph of each surface at each film thickness d ₂ of layer 1042 Graph showing the relationship between the roughness of the film thickness d ₂ and the surface of the layer 1042 Graph showing the relationship between the thickness d ₂ and the sheet resistance of the layer 1042 Sectional drawing of the field effect transistor 200 of Example 2. FIG. Micrograph of each surface at each film thickness d ₂ of layer 2042 Graph showing the relationship between the film thickness d _{2 of the} layer 2042 and the surface roughness Graph showing the relationship between the thickness d ₂ and the sheet resistance of the layer 2042 The graph which shows the carrier gas supply form in the modification 1 The graph which shows the carrier gas supply form in the modification 2

100: Field effect transistor (Example 1)
101: Crystal growth substrate (sapphire)
102: AlN layer (buffer layer)
103: Semiconductor layer (buffer layer) made of GaN
104: Semiconductor layer (barrier layer) made of AlGaN
1041: Steep interface providing layer 1042: Electrode connection surface providing layer 105: Source electrode (ohmic electrode)
106: Gate electrode (Schottky electrode)
107: drain electrode (ohmic electrode)

200: Field effect transistor (Example 2)
201: Crystal growth substrate (SiC)
202: AlN layer (buffer layer)
203: Semiconductor layer (buffer layer) made of GaN
204: Semiconductor layer (barrier layer) made of AlGaN
2041: Steep interface providing layer 2042: Electrode connection surface providing layer 205: Source electrode (ohmic electrode)
206: Gate electrode (Schottky electrode)
207: Drain electrode (ohmic electrode)

Claims (8)

A method of manufacturing a field effect transistor, comprising a buffer layer made of a group III nitride compound semiconductor and a barrier layer, wherein a channel is formed on an interface side of the buffer layer with respect to the barrier layer,
In the crystal growth step for crystal growth of the barrier layer, the gas partial pressure ratio R occupied by hydrogen (H ₂ ) gas in the carrier gas carrying the material gas of the barrier layer is set to “r ₁ ≧ R ≧ r ₂ (1 ≧ r ₁ > 1/4, 1/2> r ₂ ≧ 0, r ₁ > r ₂ ) ”, and continuously or stepwise with respect to time t. Effect transistor manufacturing method. In the crystal growth step, the gas partial pressure ratio R is decreased m times (m ≧ 1) stepwise so that the barrier layer is made of non-doped Al _x Ga _1-x N (0 <x ≦ 1). 2. The method of manufacturing a field effect transistor according to claim 1 , wherein the field effect transistor is formed of m + 1 semiconductor layers. The barrier layer has a two-layer structure,
The barrier layer first layer to be laminated first is crystal-grown using hydrogen (H ₂ ) gas as the main carrier gas,
3. The field effect transistor according to claim 2 , wherein the second barrier layer to be laminated is crystal-grown using an inert gas composed of a rare gas or nitrogen (N ₂ ) gas as a main carrier gas. Method. The film thickness d _{1 of the first} barrier layer and the film thickness d ₂ of the second barrier layer are 10 nm ≦ d ₁ ≦ 30 nm, 10 nm ≦ d ₂ ≦ 30 nm, and 30 nm ≦ d ₁ + d ₂ ≦ 60 nm. 4. The method of manufacturing a field effect transistor according to claim 3 , wherein the first layer and the second layer are formed so as to satisfy each other . Method of manufacturing a field effect transistor according to any one of claims 1 to 4, characterized in that the uppermost layer of the buffer layer was formed by non-doped GaN. Each semiconductor layer constituting the barrier layer is made of non-doped Al. _x Ga _1-x 6. The method of manufacturing a field effect transistor according to claim 1, wherein the field effect transistor is formed of N (0 <x ≦ 1). Each semiconductor layer constituting the barrier layer, any one of claims 1 to 5, characterized in that formed in the undoped _{Al x Ga 1-x N (} 0.15 ≦ x ≦ 0.3) 1 The manufacturing method of the field effect transistor as described in a term . Manufacturing a field effect transistor according to the aluminum composition ratio x of each semiconductor layer constituting the barrier layer, to any one of claims 1 to 7, characterized in that monotonically decreases in accordance with stacking sequence Method.

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