JP4722582B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device.

  In the solid-state imaging device described in Patent Document 1 below, in order to reduce vertical stripe noise (fixed pattern noise) due to offset variation in each readout circuit, offset noise generated in each column (each readout circuit) is reduced for each column. A plurality of CDS circuits are prepared, the average value of the offset is obtained, and the CDS circuit closest to the average value (the least variation) is selected in each column.

The solid-state imaging device described in Patent Document 2 below is a multi-port type solid-state imaging device that divides all pixels in a light receiving region into multiple parts and reads out each light receiving block by using different readout circuits, in order to correct variations in each block. Correction is performed using a histogram.
JP 2004-80467 A JP 2004-88190 A

  However, since the conventional solid-state imaging device performs correction using only the dark level signal, sufficient correction of the final output cannot be easily performed.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a solid-state imaging device capable of easily correcting the final output.

In order to solve the above-described problem, a solid-state imaging device according to the present invention reads from an imaging region in a solid-state imaging device including an imaging region having a plurality of pixel columns and an optical black region adjacent to the imaging region. A processing circuit for generating a digital video signal from the received signal, a dark level signal read from the optical black area, and a virtual light level signal passing through the same path as the path to the processing circuit for the dark level signal And a control circuit that controls the offset or gain of the processing circuit in accordance with the received dark bell signal and virtual bright level signal, and the pixels constituting the pixel column and the dummy pixels in the optical black region are A photodiode to which a bias voltage is applied via a reset switch, and a cathode of the photodiode is connected to an input terminal. And an addressing switch that reads out the output of the photodiode or the bias voltage output from the amplifier, and the bias switch is turned on when the reset switch is turned on in the optical black region. Is the voltage or current output from the addressing switch as the virtual bright level signal, and the bias voltage at this time is the output voltage of the photodiode when it is assumed that the reference level light is incident on the photodiode. It is characterized by.

  According to the present invention, the control circuit receives a virtual bright level signal in addition to the dark level signal from the optical black region, but these differences and the like are correlated with the standard gain in the path. In other words, the difference between the virtual light level signal and the dark level signal is proportional to the gain of the pixel output with respect to the incident light quantity, so if the relationship between this gain and the final output gain from the processing circuit is deviated, the deviation amount The gain of the processing circuit may be adjusted according to the above. Therefore, the final output from the processing circuit can be easily corrected.

  Here, the virtual bright level signal is set equal to the voltage input to the processing circuit when it is assumed that the reference level light is incident on the photodiode included in the pixel.

  The dummy pixel in the optical black region has a photodiode to which a bias voltage is applied via a reset switch, and an addressing switch for reading the photodiode output or the bias voltage output, and the reset switch is turned on. Thus, the bias voltage is the voltage or current output from the addressing switch as a virtual bright level signal, and the bias voltage at this time is the output voltage of the photodiode assuming that the reference level light is incident on the photodiode. It is characterized by being.

  When the reset switch is turned on, if the photodiode and the bias voltage source are not connected, the bias voltage is input to the amplifying transistor provided as necessary, and a virtual bright level signal is generated according to the input voltage. appear. That is, the bias voltage at this time may be set as the output voltage of the photodiode estimated to be generated when the reference level light is incident on the photodiode. As to whether to use an amplifying transistor, in order to reduce the influence of the variation of the transistor, it is possible to use only a bias voltage and a transistor for switching it without using the transistor.

  The control circuit preferably controls the gain of the processing circuit according to the ratio of the reference value to the difference between the virtual light level signal and the dark level signal. The control circuit preferably controls the offset of the processing circuit in accordance with the magnitude of the dark level signal.

  According to the solid-state imaging device of the present invention, the final output can be sufficiently corrected easily.

  Hereinafter, the solid-state imaging device according to the embodiment will be described. Note that the same reference numerals are used for the same elements, and redundant description is omitted.

  FIG. 1 is a circuit diagram of a solid-state imaging device according to an embodiment.

  This solid-state imaging device includes an imaging element and a control circuit. This imaging element has an imaging region in which imaging blocks B1, B2, and B3 in which N pixel rows (N1, N2, and N3) are adjacently arranged are arranged in K pieces (K = 3 in this example). is doing. The order from the left of each imaging block is kth. FIG. 2 shows a detailed configuration of each pixel P (x, y) constituting each pixel column. A pixel row adjacent to the imaging region forms an optical black region OB, and includes a light shielding film (not shown) on the pixel. The configuration of the optical black region OB is the same as the configuration of the pixel P (x, y) in the other imaging region except that the optical black region OB includes a light shielding film.

As shown in FIG. 2, the pixel P (x, y) is connected between the photodiode PD (x, y), the cathode of the photodiode PD (x, y) and the reset potential Vr1 (Vr _DARK , Vr _BRIGHT ). Reset switch Q _reset (x, y), an amplifier AMP (x, y) in which the cathode of the photodiode PD (x, y) is connected to an input terminal, an amplifier AMP (x, y), and a video line L _n And an addressing switch Q _address (x, y) connected to each other.

The pixel P (x, y) includes a transfer switch Q _trans (x, y) interposed in series between the cathode of the photodiode PD (x, y) and the reset switch Q _reset (x, y). . The upstream end of the transfer switch Q _trans (x, y) is input to the gate of the amplifying transistor Q _amp (x, y) constituting the AMP (x, y) via the hold switch Q _hold (x, y). Has been. An addressing switch (transistor) Q _address (x, y) is interposed between the amplifying transistor Q _amp (x, y) and the video line L _n .

When a high-level shift signal (vertical) V _shift (y) (or V _address (y)) is input to the addressing switch Q _address (x, y), the pixel signal amplified by the amplifier AMP (x, y) is input. , it is a state to transfer to the video line L _n. Photodiodes PD (x, y) voltage corresponding to the charges accumulated in accordance with the amount of light incident on is amplified by the amplifier AMP (x, y), it is output as a voltage V to the video line L _n. Thereafter, a high level reset signal (vertical) V _reset (y) is input to the reset switch (transistor) Q _reset , and when this is turned on, the electric charge accumulated in the photodiode PD (x, y) is reset.

More specifically, the transfer signal V _trans (x, y) is input to the gate of the transfer switch Q _trans (x, y), and the reset signal V _trans (x, y) is input to the gate of the reset switch Q _reset (x, y). _reset (x, y) is input. In addition, the hold signal V _hold (y) is input to the gate of the hold switch Q _hold (x, y), and the address signal V _address (y) is input to the gate of the addressing switch Q _address (x, y). The The address signal V _address (y) can also be expressed as a first shift signal (vertical) V _shift (y).

When all signals of V _reset (y), V _trans (y), V _hold (y), and V _address (y) are at a low level, V _reset (y) is set to a high level and V _hold (y) is set to a high level. Thus, the charge of the gate of the amplifying transistor Q _amp (x, y) is reset. V _hold (y) is set to a low level, V _reset (y) is set to a low level, V _trans (y) is set to a high level, and V _hold (y) is set to a high level, whereby photodiode PD (x, y ) Is transferred to the gate of the amplifying transistor Q _amp (x, y).

After that, V _hold (y) is set to low level and V _trans (y) is set to low level, and then V _trans (y) and V _reset (y) are set to high level to accumulate in the photodiode PD (x, y). After resetting the generated charge, V _trans (y) and V _reset (y) are set to low level to start the next accumulation.

The above operation is performed in the imaging region, but in the optical black region OB, the bias voltages Vr _DARK and Vr _BRIGHT are switched and used as the reset potential Vr1.

In the optical black region OB, since the photodiode PD (x, y) is shielded from light, a bias voltage Vr _DARK equal to the reset potential Vr in the imaging region is applied to the photodiode PD (x, y), and the photodiode PD (x, y) ) _Is input to the amplifying transistor Q _amp . At this time, the dark level signal V _DARK read from the addressing switch Q _address (x, y) is held by the hold circuit, and then is input to the processing circuit. input.

On the other hand, the virtual bright level signal is set as follows. That is, when reference level light is incident on the photodiode PD (x, y), an output potential assumed to be output from the photodiode PD (x, y) is a bias voltage Vr _BRIGHT, and this bias voltage Vr _BRIGHT is This is input to the amplifying transistor Q _amp at the time of resetting. At this time, the virtual bright level signal V _BRIGHT output from the addressing switch Q _address (x, y) is held by the hold circuit and then input to the processing circuit.

The virtual bright level signal V _BRIGHT is set equal to the voltage input to the processing circuit when it is assumed that the reference level light is incident on the photodiode included in the pixel in the imaging region.

As described above, the dummy pixel p (x, y) in the optical black region OB includes the photodiode PD (x, y) to which the bias voltage is applied via the reset switch Q _reset (x, y) and the photodiode PD ( The output of x, y) or the amplifying transistor Q _amp (x, y) to which the bias voltage Vr _BRIGHT is input and the addressing switch Q _address (reading the output amplified by the amplifying transistor Q _amp (x, y)) x, y). By turning on the reset switch Q _reset (x, y), the bias voltage Vr1 (Vr _BRIGHT ) is input to the amplifying transistor Q _amp (x, y), and the voltage V _BRIGHT or current output is virtually clarified. The level signal V _BRIGHT is used, and the bias voltage Vr _BRIGHT at this time is an output voltage of the photodiode PD (x, y) when it is assumed that the reference level light is incident on the photodiode PD (x, y).

The addressing switch Q _address (x, y) reads out the photodiode output or bias voltage output, and the reset switch Q _reset (x, y) is turned on, so that the bias voltage Vr _BRIGHT is changed to the addressing switch Q _address. The voltage or current output from (x, y) is used as a virtual bright level signal V _BRIGHT . The amplifying transistor Q _amp (x, y) is provided as necessary. However, as to whether the amplifying transistor Q _amp (x, y) is used, in order to reduce the influence of transistor variations, the transistor is As an alternative, it may be configured only with a bias voltage and a transistor for switching the bias voltage.

When the reset switch Q _reset (x, y) is turned on, if the photodiode PD (x, y) and the bias voltage source (Vr) are not connected, the bias voltage Vr _BRIGHT is applied to the amplifying transistor Q _amp (x, y). The virtual bright level signal V _BRIGHT is output from the addressing switch Q _address (x, y) according to the input voltage. That is, the bias voltage Vr _BRIGHT at this time is a voltage estimated to be generated at the photodiode PD (x, y) when the reference level light is incident on the photodiode PD (x, y).

Instead of changing the bias voltage Vr1 in the optical black region OB, the virtual bright level signal V _BRIGHT may be generated by changing the bias voltage Vr2 of the amplifying transistor Q _amp (x, y). The bias voltage Vr2 at this time is the voltage generated by the photodiode PD (x, y) when the reference level light is assumed to be incident on the photodiode PD (x, y). The amplifying transistor Q _amp (x, y) ) _Is a voltage applied to the addressing switch Q _address .

Further, by omitting the previous circuit of the amplifying transistor Q _amp (x, y) and applying Vr1 (Vr _DARK , Vr _BRIGHT ) directly to the input side of the Vadress switch, the dark level signal V _DARK and the virtual light A level signal V _BRIGHT can also be generated. That is, not only provides for generating virtual light level signal _{V BRIGHT,} as the bias voltage Vr of the dark level signal _{V DARK} equivalent voltage may generate a dark level signal _{V DARK.} These bias voltage Vr generation circuits are preferably formed of a common circuit.

  Referring to FIG. 1, there are nine pixels P (x, y) in the imaging region along the row direction (x) and nine along the column direction (y), which are defined by the address (x, y). Are arranged in two dimensions. In this example, a partial readout region R is set at the center of the imaging region, and a signal of a pixel P (x, y) inside the partial readout region R is read out.

  The partial read area R is designated by the image data calculation unit 10. The image data calculation unit 10 designates the partial readout region R according to the input digital video signal. That is, for example, the address of a pixel P (x, y) having a luminance equal to or higher than a predetermined value in an image of one frame in a digital video signal is stored. When an object such as a missile is an object to be imaged, the image sensor is made of silicon, and its infrared image spreads continuously around the center of gravity of the object image with the maximum luminance starting point, and the luminance is less than a predetermined value at the periphery. Become.

  That is, a rectangular area that includes a point with the maximum luminance and includes a point with a luminance within a predetermined value ± Δ is selected as the partial readout region R. When the object is moving, the difference between the position of the center of gravity of the object image in the previous frame (x1, y1) and the position of the center of gravity of the object image in the current frame (x2, y2) The vector (x2-x1, y2-y1) is calculated, and the position obtained by adding this vector to the centroid position (x1, y2) of the object image in the current frame is the centroid position (x3, y3) of the next object image. ) And a rectangular area having this as the center of gravity position is set as a new partial readout area R.

  A digital video signal is input to the image data calculation unit 10, and this digital video signal is obtained by processing signals for each pixel column (three columns) from each imaging block B1 (B2, B3) as processing circuits PU1, PU2. , PU3 can be obtained by inputting. Each processing circuit PU1, PU2, PU3 is formed by connecting amplifiers AMP1, AMP2, AMP3, AD conversion circuits ADC1, ADC2, ADC3, and output circuits OC1, OC2, OC3. The analog pixel signal output from each pixel column is converted into a digital video signal by the processing circuits PU1, PU2, and PU3.

  Partial image selection position information (x = x4 to x6, y = y4 to y6) that defines the partial readout region R is input to the timing generation circuit 11. In addition, the solid-state imaging device includes a row selection circuit 12 that selects a pixel row corresponding to the partial readout region R and a column selection circuit 13 that selects a pixel column corresponding to the partial readout region R. The timing generation circuit 11 generates a row selection circuit control signal and a column selection circuit control signal based on the input partial image selection position information.

  In short, the row selection circuit control signal causes the row selection circuit 12 to select a pixel so that the signal of the pixel row of y = y4 to y6 is read, and the column selection circuit control signal is the pixel column of x = x4 to x6. The column selection circuit 13 is made to select a pixel so that the above signal is read out. In other words, the timing generation circuit 11 generates a control signal that causes the row selection circuit 12 and the column selection circuit 13 to select based on the output of the image data calculation unit 10.

Although not shown in FIG. 1, the solid-state imaging device is a control circuit that performs offset adjustment and gain adjustment of the processing circuits PU1, PU2, and PU3 based on the dark level signal V _DARK and the virtual bright level signal V _BRIGHT. It has. This control circuit controls the gains of the processing circuits PU1, PU2, PU3 in accordance with the ratio of the reference value D to the difference between the virtual bright level signal V _BRIGHT and the dark level signal V _DARK . Further, the control circuit controls the offset of the processing circuits PU1, PU2, PU3 according to the magnitude of the dark level signal V _DARK . The details will be described below.

  FIG. 3 shows pixels p (x) and p (x + 1) of the optical black region OB in the x and x + 1 columns, hold circuits H (x) and H (x + 1), and processing circuits PU (x) and PU (x + 1). ), Control circuits FBC (x), FBC (x + 1), and pixels p (x, y) and p (x + 1, y) in the x-th column and the x + 1-th column in the imaging region. . Note that the x column and the x + 1 column represent, for example, the N1 column and the N2 column in FIG. 1, and the processing circuits PU (x) and PU (x + 1) corresponding thereto represent the PU1 and PU2, respectively. .

The pixel outputs V _x output from the pixels p (x, y) and p (x + 1, y) in the imaging area are V (x, y) and V (x, x + 1), respectively, and are output from the optical black area OB. The pixel outputs are V _DARK (x), V _BRIGHT (x), V _DARK (x + 1), and V _BRIGHT (x + 1).

In the period before the offset and gain adjustment of the processing circuit PU (x), V _DARK (x) and V _BRIGHT (x) are input to the control circuit FBC (x). Here, V _DARK (x) and V _BRIGHT (x) are input to the control circuit FBC (x) before being input to the processing circuit PU (x).

The processing circuit PU (x) performs a process of V _x ′ = a _x × (V _x + b _x ) on the input signal V _X. Note that V _x ′ = a _x × V _x + a _x b _x , and a _x and b _x are coefficients.

The control circuit FBC (x) sets the coefficients a _x and b _x based on the input signals V _DARK (x) and V _BRIGHT (x) as follows.
Gain: a _x = D / (V _BRIGHT (x) −V _DARK (x))
Offset: a _x b _x = −V _DARK (x)

Note that D is an ideal value of the difference between the light level signal and the dark level signal. That is, the gain of the actual pixel output V _{x in} the processing circuit PU (x) is corrected by the ratio of the difference between the ideal value and the actual difference (V _BRIGHT (x) −V _DARK (x)).

When a plurality of pixels are included in one column of the optical black region OB, the average value AVG is used by dividing the integrated output value by the number of pixels δ in the column. As the virtual bright level signal V _BRIGHT (x) in each equation, the average value AVG = Σ (each virtual bright level signal V _BRIGHT (x) in one pixel column) / (integration in one pixel column) The number of pixels δ) used in the above is used. Further, as the dark level signal V _DARK (x), the average value AVG of the dark level signal AVG = Σ (dark level signal V _DARK (x) in one pixel column) ÷ (number of pixels δ used for integration in one pixel column). Use.

The processing circuit PU (x + 1) is also adjusted in offset and gain in the same manner as the processing of the processing circuit PU (x). That is, the control circuit FBC (x + 1) sets the coefficients a _{x + 1} and b _{x + 1} of the processing circuit PU (x + 1) based on the input signals V _DARK (x + 1) and V _BRIGHT (x + 1) as follows.
Gain: a _{x + 1} = D / (V _BRIGHT (x + 1) −V _DARK (x + 1))
Offset: a _{x + 1} b _{x + 1} = −V _DARK (x + 1)

FIG. 4 shows pixels p (x) and p (x + 1) in the optical black region OB in the x and x + 1 columns, hold circuits H (x) and H (x + 1), and processing circuits PU (x) and PU (x + 1). ), Control circuits FBC (x), FBC (x + 1), and pixels p (x, y), p (x + 1, y) in x columns and y rows of the imaging region. Note that the control circuits FBC (x) and FBC (x + 1) are provided in the subsequent stages of the processing circuits PU (x) and PU (x + 1), respectively, and input signals V ′ _BRIGHT (x) and V ′ _DARK (x), respectively. The coefficients a _x , b _x , a _{x + 1} , and b _{x + 1} are determined based on the input signals V _BRIGHT (x + 1) and V _DARK (x + 1).

Furthermore, in the adjustment method described above, independent gain / offset adjustment is performed for each column, but fine adjustment can be performed using difference information from adjacent pixels. A specific method will be described. That is, V ′ _BRIGHT (x) and V ′ _DARK (x) satisfy the following relational expression.
V ′ _BRIGHT (x) = a _x × V _BRIGHT (x) + a _x b _x
V _BRIGHT (x) = (V ′ _BRIGHT (x) −a _x b _x ) / a _x
V ′ _DARK (x) = a _x × V _DARK (x) + a _x b _x
V _DARK (x) = (V ′ _DARK (x) −a _x b _x ) / a _x
V ′ _BRIGHT (x + 1) = a _{x + 1} × V _BRIGHT (x + 1) + a _{x + 1} b _{x + 1}
V _BRIGHT (x + 1) = (V ′ _BRIGHT (x + 1) −a _{x + 1} b _{x + 1} ) / a _{x + 1}
V ′ _DARK (x + 1) = a _{x + 1} × V _DARK (x + 1) + a _{x + 1} b _{x + 1}
V _DARK (x + 1) = (V ′ _DARK (x + 1) −a _{x + 1} b _{x + 1} ) / a _{x + 1}

Therefore, the gains a _x and a _{x + 1 and the} offsets a _x b _x and a _{x + 1} b _{x + 1} are set as follows. Note that new is used for new values, and old is used for old values.
<Initial value setting>
Gain: a _x = 1
Offset: a _x b _x = 0
Gain: a _{x + 1} = 1
Offset: a _{x + 1} b _{x + 1} = 0
<Fine adjustment of values by feedback>
Gain: a _x (new) = a _x (old) + α x DIFF1
DIFF1 = D ′ − (V ′ _BRIGHT (x) −V ′ _DARK (x))
Gain: a _{x + 1} (new) = a _{x + 1} (old) + α × DIFF1
DIFF1 = D ′ − (V ′ _BRIGHT (x + 1) −V ′ _DARK (x + 1))
Offset: a _x b _x (new) = a _x b _x (old) + β x DIFF2
DIFF2 = −V ′ _DARK (x)
Offset: a _{x + 1} b _{x + 1} (new) = a _{x + 1} b _{x + 1} (old) + β × DIFF2
DIFF2 = −V ′ _DARK (x + 1)

Here, α and β are correction weights at the time of feedback, and generally values of about 0.1 to 0.5 are used. D ′ is a difference between the desired output values of the light level signal V _BRIGHT and the dark level signal V _DARK , and the value of (V ′ _BRIGHT (x + 1) −V ′ _DARK (x + 1)) is obtained by the above feedback. , the coefficient so as to approach the D _{'a x,} is _{a x + 1,} is determined.

  FIG. 5 shows the pixels p (x) and p (x + 1) of the optical black region OB in the x and x + 1 columns, the hold circuits H (x) and H (x + 1), and the processing circuits PU (x) and PU (x + 1). ), A control circuit FBC, and pixels p (x, y) and p (x + 1, y) in x columns and y rows of the imaging region.

In this example, one control circuit FBC is provided in the subsequent stage of the processing circuits PU (x) and PU (x + 1), respectively, and also takes into account variations in luminance between adjacent pixel columns as follows. , Gain a _x , a _{x + 1,} offset a _x b _x , a _{x + 1} b _{x + 1} are set.

Here, in order to reduce the noise caused by the offset variation of the adjacent pixel, the offset a _x b _x is finely adjusted so as to minimize the difference between the value of the left adjacent pixel and the value of the pixel. Sequentially for all pixel rows, fine adjustment of the entire screen is performed.
First, the following adjacent pixel error Δ (x + 1) is calculated. The subscript DARK indicates the value at the dark level.

Δ ′ _DARK (x + 1) = Σ (V ′ _DARK (x + 1, y + 1) −V ′ _DARK (x, y))

y is a pixel in all rows (y = 1... m), and adjacent pixels to be integrated may be in the same row “y” at the dark level. Based on the offset variation obtained in this way, the offsets a _{x + 1} b _{x + 1} of the x + 1 column are corrected as follows.

a _{x + 1} b _{x + 1 (new)} = a _{x + 1} b _{x + 1 (old)} + Δ′dark (x + 1) / m
Here, m indicates the number of pixels in one row. The above calculation is performed for each column in order from the left side of the pixel to correct the entire image.

As described above, the control circuit FBC (x) processes the gain adjustment signal C _GAIN (x) and the offset adjustment signal C _OFFSET (x) so that the gain a _x and the offset a _x b _x are set. Output to circuit PU (x). Since the number of processing circuits PU1, PU2, and PU3 in FIG. 1 is three, it is assumed that x = 1 to 3 here.

  FIG. 6 shows a detailed configuration of the processing circuit PU (x).

The processing circuit PU (x) has an amplifier Amp (x), an AD conversion circuit ADC (x), and an output circuit OC (x) connected in series, and V _x ′ = a _{x with} respect to the input signal V _X. A process of × (V _x + b _x ) is performed. The gain a _x and the offset a _x b _x may be adjusted by adjusting the output of any one of the amplifier Amp (x), the AD conversion circuit ADC (x), and the output circuit OC (x).

  FIG. 7 is a circuit diagram illustrating an example of adjusting the amplifier Amp (x).

The gain of the amplifier Amp (x) is determined by the ratio (R2 / R1) between the resistance value of the resistor R1 on the input side of the operational amplifier OP and the feedback resistor R2 between the input and output. Therefore, the gain adjustment signal _{C GAIN} (x), by adjusting the resistance value of the resistor R2, the gain may be _{a x.}

  The offset can be controlled by adjusting one variable resistor R3 among the voltage dividing resistors R3 and R4 that determine the reference potential Vref of the non-inverting amplifier terminal. That is, the voltage dividing resistors R3 and R4 are connected between the power supply potential Vdd and the reference potential Vss, and the reference potential Vref serving as an offset potential is determined by the resistance ratio between the resistors R3 and R4.

The offset adjustment signal C _OFFSET (x) has a magnitude of a _x b _x Vref (= (Vdd−Vss) × (R4 / (R3 + R4)) so that the offset a _x b _{x for} the dark level signal is subtracted from the input. )) Is determined so as to satisfy the resistance value of the variable resistor R3.

  FIG. 8 is a circuit diagram illustrating an example of adjusting the AD conversion circuit ADC (x).

  In this example, a pipeline type AD conversion circuit is shown. For simplicity, it is assumed that the AD conversion circuit has a 4-bit output. Four AD conversion stages STAGE1 (x), STAGE2 (x), STAGE3 (x), and STAGE4 (x) are connected in order, and the output of each AD conversion stage is input to the shift register SR (x). Each AD conversion stage includes an AD conversion comparator Comp, a DA conversion circuit Dac to which the output of the comparator Comp is input, a subtraction circuit Sub for subtracting the input signal from the output of the DA conversion circuit Dac, and the output of the subtraction circuit Sub. A multiplication circuit Mul for multiplying by a constant (× 2) is provided.

  For example, when an analog input voltage of 1.31V is input to the AD converter circuit ADC (x), in the first AD conversion stage STAGE1 (x), if the reference voltage Vref of the comparator Comp is 0.8V, 1 Since .31V is 0.8V or higher, high level “1” is output from the comparator Comp, 0.8V is output from the DA conversion circuit Dac, and the subtraction circuit Sub outputs the output 0.8V of the DA conversion circuit Dac. Decrease from input voltage 1.31V. That is, 0.51V is output from the subtraction circuit Sub, and the multiplication circuit Mul doubles this to output 1.02V.

  In the second AD conversion stage STAGE2 (x), assuming that the reference voltage Vref of the comparator Comp is 0.8V, 1.02V is 0.8V or higher, so that the comparator Comp outputs a high level “1”. The DA conversion circuit Dac outputs 0.8V, and the subtraction circuit Sub subtracts the output 0.8V of the DA conversion circuit Dac from the input voltage 1.02V. That is, 0.22V is output from the subtraction circuit Sub, and the multiplication circuit Mul doubles this to output 0.44V.

  In the third AD conversion stage STAGE3 (x), assuming that the reference voltage Vref of the comparator Comp is 0.8V, 0.44V is smaller than 0.8V, so that the low level “0” is output from the comparator Comp. Then, 0V is output from the DA conversion circuit Dac, and the subtraction circuit Sub subtracts the output 0V of the DA conversion circuit Dac from the input voltage 0.44V. That is, 0.44V is output from the subtraction circuit Sub, and the multiplication circuit Mul doubles this to output 0.88V.

  In the fourth AD conversion stage STAGE4 (x), assuming that the reference voltage Vref of the comparator Comp is 0.8V, 0.88V is 0.8V or higher, so that the comparator Comp outputs a high level “1”. The DA conversion circuit Dac outputs 0.8V, and the subtraction circuit Sub subtracts the output 0.8V of the DA conversion circuit Dac from the input voltage 0.88V. That is, 0.08V is output from the subtraction circuit Sub, and the multiplication circuit Mul doubles this to output 0.16V.

That is, “1”, “1”, “0”, and “1” are sequentially input to the shift register SR (x) through the pipeline of these AD conversion stages. Note that “1101” is 13 in decimal, and in order from the least significant bit, 0.1 V × 2 ⁰ = 0.1 V, 0.1 V × 2 ¹ = 0.2 V, 0.1 V × 2 ² = 0.4V, 0.1V × 2 ³ = 0.8V, “1101” represents an analog signal of 1.3V.

The gain of the AD conversion circuit is inversely proportional to the reference voltage Vref of the comparator Comp. Therefore, gain adjustment can be performed by controlling one variable resistor R5 of the series resistors R5 and R6 for determining Vref by the gain adjustment signal C _GAIN (x). That is, the gain adjustment signal C _GAIN (x) has a resistance value of the variable resistor R5 so as to satisfy the gain a _x ∝ (1 / Vref) = 1 / ((Vdd−Vss) × (R6 / (R5 + R6))). To decide.

From the output of the shift register SR (x), the amount of the offset a _x b _x is reduced by using the digital adder circuit Add. If the offset a _x b _x is negative, it may be added. That is, the offset adjustment signal C _OFFSET (x) input to the digital adder circuit Add indicates the offset a _x b _x .

  FIG. 9 is a circuit diagram illustrating an example of adjusting the digital output circuit OC (x).

The output circuit OC (x) includes a digital addition circuit Add that adds a constant b _x to an input and a digital multiplication circuit Mul that multiplies the output of the addition circuit Add by a _x , and V _x ′ = a _x × ( V _x + b _x ) is output. That is, the gain adjustment signal C _GAIN (x) designates a _x as a multiple of the digital multiplication circuit Mul, and the offset adjustment signal C _OFFSET (x) designates b _x as the addition value of the digital addition circuit Add. Is. Note that b _x is obtained by dividing the offset a _x b _x by the gain a _x .

  FIG. 10 is a graph showing the relationship between the incident light amount I and the pixel output V to the pixel p (x, y) in the imaging region.

The pixel output V includes a dark level signal V _DARK and increases linearly from the incident light amount I = 0 to the bright level signal V _BRIGHT when the reference light level with the incident light amount I = I ₀ is incident. Ideally, the ratio between the reference level light intensity I ₀ and (bright level signal V _BRIGHT -dark level signal V _DARK ) is constant.

  FIG. 11 is a graph showing the relationship between the pixel output V and the final output V ′ from the processing circuit.

  The final output V ′ is obtained by removing the offset component from the pixel output V and correcting the gain to the reference value. Adjustment of offset and gain is as described above.

  Next, readout of pixel output will be described.

  FIG. 12 is a timing chart of the solid-state imaging device shown in FIG.

  In this example, an example of reading a signal of the partial reading region R shown in FIG. 1 is shown.

From time t _{0 to} t ₂ , the first to third shift signals (vertical) V _shift (1 to 3), the first to third reset signals (vertical) V _reset (1-3), the fourth shift signal ( (Vertical) V _shift (4), fourth reset signal (vertical) V _reset (4), fifth shift signal (vertical) V _shift (5), fifth reset signal (vertical) V _reset (5), sixth shift Signal (vertical) V _shift (6), sixth reset signal (vertical) V _reset (6), seventh to ninth shift signals (vertical) V _shift (7 to 9), seventh to ninth reset signals (vertical) ) V _reset (7-9), first shift signal (horizontal) H _shift (1), second shift signal (horizontal) H _shift (2), third shift signal (horizontal) H _shift (3) are all Low level. Each number in the signal indicates an address of coordinates x or y. In the description, FIG. 2 is referred to as appropriate.

At time t _{2 to} t ₃ , since the high-level fourth shift signal (vertical) V _shift (4) is input from the row selection circuit 12, the shift switch Q of the fourth pixel row from the bottom in FIG. _address (x, 4) are turned oN, the charges accumulated in the photodiodes PD (x, 4) in accordance with the incident light is amplified by the amplifier aMP (x, 4), is output as a voltage to the video line _{L n} The hold circuits H (1) to H (9) hold. Each hold circuit is connected in parallel with a current source. Subsequently, since the high-level fourth reset signal V _reset (4) is input from time t _{3 to} t ₄ , the reset switch Q _reset (x, 4) is turned on, and the photodiode PD (x, 4) is turned on. The accumulated charge is reset.

At times t _{4 to} t ₅ , the high-level second shift signal (horizontal) H _shift (2) is _sent from the column selection circuit 13 to the fourth column switch Q (4) and the fifth pixel column. Switch Q (5) and the switch Q (6) in the sixth column of the pixel column are simultaneously input, so that the pixel P (4) accumulated in the hold circuits H (4), H (5), H (6) , 4), P (5, 4), and P (6, 4) are input to the processing circuits PU1, PU2, and PU3, respectively.

At time t _{6 to} t ₇ , the high-level fifth shift signal (vertical) V _shift (5) is input from the row selection circuit 12, so that the shift switch Q of the fifth pixel row from the bottom in FIG. _address (x, 5) is turned oN, the charge accumulated in the photodiodes PD (x, 5) in response to the incidence of light is amplified by the amplifier aMP (x, 5), is output as a voltage to the video line _{L n} The hold circuits H (1) to H (9) hold.

Subsequently, since the high-level fifth reset signal V _reset (5) is input from time t _{7 to} time t ₈ , the reset switch Q _reset (x, 5) is turned on, and the photodiode PD (x, 5) is turned on. The accumulated charge is reset. At times t _{8 to} t ₉ , the high-level second shift signal (horizontal) H _shift (2) is _sent from the column selection circuit 13 to the fourth column switch Q (4) and the fifth pixel column. Switch Q (5) and the switch Q (6) in the sixth column of the pixel column are simultaneously input, so that the pixel P (4) accumulated in the hold circuits H (4), H (5), H (6) , 5), P (5, 5), and P (6, 5) are input to the processing circuits PU1, PU2, and PU3, respectively.

At time t _{10 to} t ₁₁ , the high-level sixth shift signal (vertical) V _shift (6) is input from the row selection circuit 12, so that the shift switch Q of the sixth pixel row from the bottom in FIG. _address (x, 6) is turned oN, the charge accumulated in the photodiodes PD (x, 6) in response to the incidence of light is amplified by the amplifier aMP (x, 6), is output as a voltage to the video line _{L n} The hold circuits H (1) to H (9) hold.

Subsequently, since the high-level sixth reset signal V _reset (6) is input at times t _{11 to} t ₁₂ , the reset switch Q _reset (x, 6) is turned on, and the photodiode PD (x, 6) is turned on. The accumulated charge is reset. At time _t 12 _{~t 13,} the column select circuit 13, high-level second shift signal _{(horizontal) H Shift} (2) is, the fourth column of the switch Q (4) of the pixel column, the fifth column of the pixel row Switch Q (5) and the switch Q (6) in the sixth column of the pixel column are simultaneously input, so that the pixel P (4) accumulated in the hold circuits H (4), H (5), H (6) , 6), P (5, 6), and P (6, 6) are input to the processing circuits PU1, PU2, and PU3, respectively.

  As described above, the solid-state imaging device is connected to N pixel columns via the switches Q (4), Q (5), and Q (6) that are turned on by selection of the column selection circuit 13, respectively. N processing circuits PU1, PU2, and PU3 are provided. The n-th processing circuit PU1 (PU2, PU3) is all connected to the n-th pixel column N1 (N2, N3) in each imaging block B1, B2, B3 via the switches Q (1) to Q (9). It is possible to connect. The N processing circuits PU1, PU2, and PU3 generate digital video signals from signals for each pixel column selected by the row selection circuit 12 and the column selection circuit 13.

  According to the above-described solid-state imaging device, the n-th processing circuit (for example, PU1) includes the n-th pixel column (N1) in each of the imaging blocks B1, B2, and B3 as switches Q (1) and Q Since all the connections are possible via (4) and Q (7), even when the partial readout region R is small, signals from the adjacent pixel column N2 are processed separately by different processing circuits PU2. . In addition, since the image data calculation unit 10 limits the area to be read out to the partial read area R, it is possible to perform higher-speed imaging.

  The solid-state imaging device includes a plurality of hold circuits H (1) to H (9) connected to the individual pixel columns N1, N2, and N3, and the switches Q (1) to Q ( 9) The charges accumulated in the individual hold circuits H (1) to H (9) for each pixel column are synchronized with the control signal input from the timing generation circuit 11 to the column selection circuit 13, and It is connected to the processing circuits PU1, PU2, PU3 corresponding to the pixel columns N1, N2, N3, and the signals for each pixel row are temporarily stored in the hold circuits (1) to H (9). By connecting with the control signals Q (1) to Q (9), the charges accumulated in each pixel row can be transferred to the processing circuits PU1, PU2, PU3 for each pixel column N1, N2, N3. .

  The pixels in the optical black area OB are read in the same procedure as the pixels in the imaging area, but the readout timing is read out before the readout timing of the imaging area. Note that the pixel output of the optical black area OB can be stored in the control circuit FBC, and the same pixel output of the imaging area can be corrected at the next readout timing.

  Note that the number of pixel columns is not limited to the above.

  In FIG. 13, one imaging block is composed of 8 pixel columns, and includes 64 imaging blocks Bk (k = 1 to 64) (K = 64), the vertical pixel column has 512 pixels, 2 shows a solid-state imaging device having 512 pixels in a horizontal pixel row. Note that the nth processing circuit PUn is connected to each nth pixel column in each of the imaging blocks B1, B2,..., B64 (n = 1 to 8). Hold circuit groups H (1) to H (N × K) are interposed between the switch groups Q (1) to Q (N × K) controlled by the column selection circuit 13 and the imaging region. . The switch groups Q (1) to Q (N × K) and the hold circuit groups H (1) to H (N × K) are the above switch groups Q (1) to Q (9) and the hold circuit group H (1 ) To H (9).

  The operation of partial reading with this solid-state imaging device will be described below. Here, partial readout of the central 492 × 492 pixels excluding only the peripheral 10 rows and 10 columns out of the entire 512 × 512 pixels from the previous image based on the output of the image data calculation unit is performed. The timing generation circuit supplies a control signal necessary for the selection to the row selection circuit 12 and the column selection circuit 13.

  FIG. 14 is a detailed circuit diagram of the pixel P (x, y) in the imaging region.

  In the following description, a switch refers to a field effect transistor.

The pixel P (1,1) includes a transfer switch Q _trans (1) and a reset switch Q _reset (1) interposed in series between the cathode of the photodiode PD (1) and the reset potential Vr1. The upstream end of the transfer switch Q _trans (1) is input to the gate of the amplification transistor Q _amp (1) via the hold switch Q _hold (1). An addressing switch Q _address (1) is interposed between the amplifying transistor Q _amp (1) and the video line L ₁ .

The transfer signal V _trans (1) is input to the gate of the transfer switch Q _trans (1), and the reset signal V _reset (1) is input to the gate of the reset switch Q _reset (1). The hold signal V _hold (1) is input to the gate of the hold switch Q _hold (1). The address signal V _address (1) is input to the gate of the addressing switch Q _address (1). The address signal V _address (1) can also be expressed as a first shift signal (vertical) V _shift (1).

  The configuration of the pixel P (1,2) is the same as that of the pixel P (1,1) except that the number of each element is “2”.

  FIG. 15 is a circuit diagram of the row selection circuit 12 for generating each signal. FIG. 16 is a timing chart of each signal. This figure is for achieving partial readout of the central 492 rows excluding 10 rows in the vertical direction.

Shift registers S1, S2,... Are provided for each row, and each shift register includes a set input terminal ST, a reset input terminal rst, a clock input terminal CLK, and an output terminal Q. The reset input terminal is connected to the ground potential. The set input terminal ST of the shift register S1 is the start signal V _st is input, the output shiftout1 from the output terminal Q of the shift register S1 is, as that is input to the set input terminal of the shift register S2 ST, each shift register The set input terminal sequentially receives the output from the output terminal Q of the previous shift register.

V _reset , V _trans , V _hold , and V _address generated from the timing generation circuit 11 are predetermined timings at the time of reading the first pixel P (1, 1), respectively, and V _reset (1), V _trans (1), As V _hold (1) and V _address (1), the switches QA1, QB1, QC1, and QD1 are turned on and input to the above-described switches. This predetermined timing is determined by the s-mode signal generated by the timing generation circuit 11 and the start signal _Vst , and when the reading of the pixels in the first row is completed, the reading of the pixels in the second row is sequentially performed. Transition. In FIG. 16, the number indicated by (V _shift ) indicates the pixel row being read, and the number indicated by (H _shift ) indicates the pixel column being read.

The s-mode signal is input to the NOR circuit (NOR1) together with the output when the start signal _Vst is input to the shift register S1. In the case of reading in the second row, these signals are input to the NOR circuit (NOR2). This figure shows an example of the operation in the global shutter mode in which the charges accumulated in the photodiodes PD (x, y) are simultaneously held in all the 512 × 512 pixels. By setting the s-mode signal to the high level, V _Reset , V _trans , and V _hold signals can be supplied all at once. As a result, the charge accumulated in the photodiode PD (x, y) can be transferred and accumulated in the gate of the amplification transistor Q _amp (x, y) over the entire pixel at the same timing.

The actual operation is as follows. The s-mode signal is set to a high level so that signals of V _reset , V _trans , and V _hold are input over all rows. When all signals of V _reset , V _trans , V _hold , and V _address are at a low level, the charge of the gate of the amplification transistor is reset by setting V _reset to a high level and V _hold to a high level. After V _{hold is set} to low level and V _{reset is set} to low level, V _{trans is set} to high level and V _{hold is set} to high level, whereby the charge accumulated in the photodiode PD (x, y) is transferred to the gate of the amplification transistor. Transferred.

_Then, after the _{V trans} low level in the _{V hold} in a low _level, and the _{V trans} and _{V reset} to the high level, the photodiodes PD (x, y) after resetting the electric charges accumulated _{in, V trans} and V _{Reset is set} to low level to start the next accumulation.

  Here, by returning the s-mode signal to the low level, the charge accumulated in the photodiode PD (x, y) over all the pixels is transferred and held in the gate of the amplification transistor of each pixel. In the photodiode, the next accumulation is started, and the operation in the global shutter mode in which the accumulation starts and ends in all the pixels is realized at the same time. Thereafter, only the pixel for which the charge held at the gate of the amplification transistor is to be read is selected and read.

The vertical clock signal V _clk generated by the timing generation circuit 11 is input to the clock input terminals CLK of the shift registers S1, S2 _,. Start signal V _st is input to the set input terminal of the shift register S1, so that the output shiftout1 from the output terminal Q of the shift register S1 is input to the set input terminal of the shift register S2, the set input terminal of each shift register When the output from the output terminal Q of the previous shift register is sequentially input, the reading of the charges accumulated in the pixels of each row is started, but V _address is set to the low level, and the vertical clock signal V _clk is By making the period longer, the first 10 lines skip signals.

After that, the voltage obtained by amplifying the stored charge from the pixel in the eleventh row with V _{address set} to high level is once transferred to the hold circuit, and then V _reset and V _hold are also set to high level to set the gate of the amplification transistor After resetting the charge, V _{hold is set} to low level, V _reset is returned to low level, the reset voltage is also sent to the hold circuit, the voltage obtained by amplifying the accumulated charge, and the gate of the amplification transistor Two kinds of voltages output from the amplifying transistor when the electric charge is reset are input to the hold circuit.

The hold circuit calculates and holds the difference between the two kinds of voltages in a CDS circuit for subtracting and reducing noise. The charge of 512 pixels is accumulated in the hold circuit by shortening the cycle of the vertical clock signal V _clk , and then the pixel column read start signal H _st generated by the timing generation circuit 11 is input to the column selection circuit 13. Thus, among the charges accumulated in the hold circuit for 512 pixels in synchronization with the horizontal clock signal H _clk generated by the timing generation circuit 11, eight processing circuits are provided for the pixel corresponding to the selected partial readout region R. Are input to the image data calculation unit.

  This operation will be described later with reference to FIGS. Note that in the subsequent 10 rows from the 503th pixel row, the period of the vertical clock signal is shortened and signal reading is similarly skipped.

That is, by shortening the period of the vertical clock signal, the readout time of unnecessary pixel rows is shortened. In the readout period of unnecessary pixel rows, the address signal V _address is not input, that is, the video signal is Not output.

FIG. 17 is a circuit diagram of the switch groups Q (1) to Q (N × K) for reading out the charges accumulated in the hold circuit groups H (1) to H (N × K). Video lines _{L 1, L 2, L 3} ··· L N × K every switch Q (1), Q (2 ), Q (3) ··· Q (N × K) is connected. The H _shift signal is input to the switch group of one imaging block, and the charge accumulated in the hold circuit is read when the H _shift signal is at a high level.

FIG. 18 is a circuit diagram of the column selection circuit 13 for generating each signal. FIG. 19 is a timing chart of each signal. This figure is for achieving partial reading of only the central 492 columns excluding 10 columns on the left and right in the horizontal direction. This figure shows only the timing at which the horizontal start signal _Hst goes high after the s-mode signal in FIG.

  Shift registers S10, S20, S30,... Are provided corresponding to the imaging blocks. Each shift register includes a set input terminal ST, a reset input terminal rst, a clock input terminal CLK, and a Q output terminal. A horizontal clock signal Hclk is input to the clock input terminal CLK.

  The timing generation circuit generates a horizontal readout start signal Hst corresponding to the pixel of the desired readout start number in the 64 imaging blocks and inputs it to the 6-bit decoder (0ch to 63ch) D. The decoder D includes binary input terminals dih0, dih1, dih2, dih3, dih4, and dih5. A NAND circuit and a NOT circuit are interposed between the decoder output terminals 1, 2, 3... And each set input terminal ST.

The decoder D generates a signal in which the H _shift signal input to a desired imaging block becomes a high level in response to H _st and binary input generated by the timing generation circuit 11. And a start signal _{H st,} by the imaging block specifying signal dih0, dih1, dih2, dih3, dih4, dih5 inputs, signals of the pixel column of the given imaging block is read. The H _shift (1) signal generated in response to the decoder output terminal 0 turns on the switches Q (1) to Q (8) when it is at the high level, and the H _shift (2) generated in response to the decoder output terminal 1 ) When the signal is at a high level, the switches Q (9) to Q (16) are turned ON.

The all reset signal H _shift-reset generated by the timing generation circuit 11 can be input to the reset terminal rst of each of the shift registers S10, S20, and S30. If the H _shift-reset is at a high level, the hold signal is held. The readout of the charges accumulated in the circuit is finished, and partial readout is performed at high speed. In this way, by applying both the methods of FIG. 16 and FIG. 19, partial signal readout of the center 492 × 492 pixels can be achieved by removing the 512 × 512 pixel signal by 10 rows and 10 columns in the periphery.

  In the above-described example, the partial read region R is determined by the image data calculation unit based on the previous image, and the timing generation circuit generates a necessary control signal. This is shown in Japanese Patent Application No. 2003-189181. It may be determined based on information obtained from a profile detection function of an imaging apparatus (referred to as a profile imager), or may be determined based on an image stored in a hold circuit or a frame memory.

  Further, it is not necessary to limit the partial read region R based on the accumulated image, and a signal for selecting only a part of all the pixels to be read is given from the outside instead of the image data calculation unit. May be. By doing this, the number of pixels to be read and the number of pixels can be changed depending on the signal input from the outside, and the number of pixels can be small. Can be realized.

As described above, the solid-state imaging device described above is a processing circuit PU (x) that generates a digital video signal from a signal read from the imaging region in a solid-state imaging device including an imaging region and an optical black region OB. ), The dark level signal V _DARK (x) read out from the optical black area OB, and the virtual light passing through the same path as the path of the dark level signal V _DARK (x) to the processing circuit PU (x). The level signal V _BRIGHT (x) is received, and in accordance with the received dark bell signal V _DARK (x) and the virtual bright level signal V _BRIGHT (x), the offset a _x b _{x of} the processing circuit PU (x), or, and a control circuit FBC for controlling the gain _{a x (x).}

The control circuit FBC (x) also receives a virtual bright level signal V _BRIGHT (x) in addition to the dark level signal V _DARK (x) from the optical black area OB. There is a correlation with general gain. That is, the difference between the virtual bright level signal V _BRIGHT (x) and the dark level signal V _DARK (x) is proportional to the gain of the pixel output V _x with respect to the incident light quantity I, and therefore this gain and the processing circuit PU (x) If the relationship of the final output gain from the output is shifted, the gain of the processing circuit PU (x) may be adjusted according to the shift amount. Therefore, it is possible to easily correct the final output V _x ′ from the processing circuit PU (x).

  The present invention can be used for a solid-state imaging device.

1 is a circuit diagram of a solid-state imaging device according to an embodiment. It is a circuit diagram which shows the detailed structure of each pixel P (x, y) which comprises each pixel column. It is a block diagram which shows the connection relation containing a processing circuit and a control circuit. It is a block diagram which shows the connection relation containing a processing circuit and a control circuit. It is a block diagram which shows the connection relation containing a processing circuit and a control circuit. The detailed structure of processing circuit PU (x) is shown. It is a circuit diagram which shows the example in the case of adjusting amplifier Amp (x). It is a circuit diagram which shows the example in the case of adjusting AD conversion circuit ADC (x). It is a circuit diagram which shows the example in the case of adjusting output circuit OC (x). It is a graph which shows the relationship between the incident light quantity I and pixel output V to the pixel p (x, y) of an imaging region. It is a graph which shows the relationship between the pixel output V and the final output V 'from a processing circuit. 2 is a timing chart of the solid-state imaging device illustrated in FIG. 1. 1 is a circuit diagram of a solid-state imaging device according to an embodiment. FIG. 4 is a detailed circuit diagram of a pixel P (x, y). It is a circuit diagram of the row selection circuit 12 for generating each signal. It is a timing chart of each signal. FIG. 4 is a circuit diagram of switch groups Q (1) to Q (N × K) for reading out charges accumulated in hold circuit groups H (1) to H (N × K). It is a circuit diagram of the column selection circuit 13 for generating each signal. It is a timing chart of each signal.

Explanation of symbols

  ADC1, ADC2, ADC3 ... converter, 10 ... image data calculation unit, 11 ... timing generation circuit, 12 ... row selection circuit ..., 13 ... column selection circuit, AMP ... amplifier, B1, B2, B3 ... imaging block, H ... hold circuit, PD ... photodiode, PU1, PU2, PU3 ... processing circuit, optical black area OB.

Claims (3)

In a solid-state imaging device including an imaging region having a plurality of pixel columns and an optical black region adjacent to the imaging region ,
A processing circuit for generating a digital video signal from a signal read from the imaging region;
The dark level signal read from the optical black area and a virtual bright level signal passing through the same path as the path to the processing circuit of the dark level signal are received, and the received dark bell signal and virtual bright signal are received. A control circuit for controlling the offset or gain of the processing circuit according to a level signal;
Equipped with a,
The pixels constituting the pixel column and the dummy pixels in the optical black area are respectively
A photodiode to which a bias voltage is applied via a reset switch;
An amplifier in which the cathode of the photodiode is connected to an input terminal;
An addressing switch for reading out the output of the photodiode or the bias voltage output from the amplifier ;
Have
When the reset switch is turned on in the optical black region, the bias voltage is a voltage or current output from the addressing switch as the virtual bright level signal, and the bias voltage at this time is based on the photodiode. A solid-state imaging device characterized in that it is an output voltage of the photodiode when it is assumed that level light is incident. The control circuit controls the gain of the processing circuit according to a ratio of a reference value to a difference between the virtual light level signal and the dark level signal ;
The solid-state imaging device according to claim 1, wherein the control circuit controls an offset of the processing circuit in accordance with a magnitude of the dark level signal.   The processing circuit comprises: a _x , B _x Is the input signal V _X V _x ‘= A _x V _X + A _x b _x Output
  A dark level signal V output from a dummy pixel in the optical black area _DARK (X) virtual light level signal V _BRIGHT (X) Using the ideal value D of the difference between the light level signal and the dark level signal, the coefficient a _x , B _x Is the following relation:
  Gain a _x = D / (V _BRIGHT (X) -V _DARK (X))
  Offset a _x b _x = -V _DARK (X)
And the coefficient a of the processing circuit for the pixels adjacent to _{x + 1} , B _{x + 1} Is the following relation:
  Gain a _{x + 1} = D / (V _BRIGHT (X + 1) -V _DARK (X + 1))
  Offset a _{x + 1} b _{x + 1} = -V _DARK (X + 1)
The filling,
  The offset coefficient a is set so as to minimize the difference between the output values of adjacent pixels. _{x + 1} b _{x + 1} The solid-state imaging device according to claim 1, wherein the solid-state imaging device is adjusted.

Images