JP4721552B2 - Semiconductor integrated circuit and driving method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and a driving method thereof, and more particularly to a semiconductor integrated circuit including a malfunction detector and a driving method thereof.
[0002]
[Prior art]
In recent years, many portable devices powered by batteries have become widespread, and semiconductor integrated circuits used in these devices are strongly required to further reduce power consumption in order to extend the battery driving time. ing. In addition, demands for higher performance of semiconductor integrated circuits that lead to improvements in functions of portable devices are increasing year by year.
[0003]
The processing performance of the semiconductor integrated circuit depends on the operating frequency of the clock signal in a circuit that is designed to store data in the latch circuit in synchronization with the clock signal. That is, in order to improve the processing performance of the semiconductor integrated circuit, the operating frequency of the clock signal may be increased.
[0004]
On the other hand, in order for the circuit to operate correctly, the one with the longest delay time when data is transmitted between the latch circuits needs to be smaller than the clock cycle which is the reciprocal of the operating frequency. However, the setup time and hold time of the latch circuit are not considered here.
[0005]
However, the data transmission speed in the semiconductor integrated circuit varies depending on various factors. The main factors are changes in the temperature and power supply voltage of the semiconductor chip, and variations in manufacturing. In normal design, circuit design is performed assuming the worst case of variations in these characteristics.
[0006]
In recent years, a temperature detection function has been mounted on the chip, and the clock cycle and power supply voltage are changed according to these changes, and the equivalent of a circuit that generates the maximum delay time between the latch circuit and the latch circuit. A configuration has been proposed in which a circuit is made separately, the operation speed of the circuit is detected, and the power supply voltage is changed to a clock cycle suitable for the clock cycle.
[0007]
FIG. 9 is a block circuit diagram of a semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. 11-234113. In the figure, when signals 109c and 109d are input to the combinational circuit 106a, a signal 108a is output, and this signal 108a is input to the flip-flop 105a. An internal clock 107 is also input to the flip-flop 105a, and a signal 110a is output from the flip-flop 105a. Next, when the signal 110a and the signal 109a are input to the combinational circuit 106b, the signal 108b is output. When the signal 108b and the internal clock 107 are input to the flip-flop 105b, the signal 110b is output. When the signal 110b and the signal 109b are input to the combinational circuit 106c, the signal 108c is output. When the signal 108c and the internal clock 107 are input to the flip-flop 105c, the signal 110c is output. Next, when the signal 110c and the output clock 112 are input to the output device 111, a signal 113 is output.
[0008]
When the clock 102 is input to the delay measuring device 101, the clock correction signal 104 is output. When the clock correction signal 104 and the clock 102 are input to the clock correction device 103, the internal clock 107 and the output clock 112 are output. Are output.
[0009]
According to the present invention, the delay measuring device 101 determines the circuit delay of the combination circuits 106a, 106b and 106c designed in advance, and this circuit is operated with the internal clock 107 suitable for the operation speed of the circuit based on this. Can do. As a result, malfunction of the circuit can be prevented and the operation speed can be increased and the number of circuits can be reduced. As a result, the manufacturing cost of the semiconductor device can be reduced. These conventional methods can be used when the actual operating circuit environment can be inferred from a circuit provided outside.
[0010]
[Problems to be solved by the invention]
However, there are cases where the operation speed of a circuit changes depending on the history of the circuit and cannot be estimated from the outside. As an example, there is a case where a circuit is designed using a MOSFET using an SOI (Silicon on Insulator) substrate that has been developed in recent years. The SOI MOSFET is characterized in that the MOSFET is formed on a thick insulating film, and the bottom surface of the source and drain is in contact with the insulating film, so that the junction capacitance is smaller than that of a normal bulk MOSFET. In addition, since MOSFETs are completely isolated from each other, there is an advantage that latch-up does not occur and higher integration can be achieved. SOI MOSFETs include an FD (Fully-Depleted) type in which a region under a channel is completely depleted and a PD (Partially-Depleted) type in which a region called a body that is not depleted exists. The potential of the body region under the channel floating in the channel changes during circuit operation, and the threshold voltage changes. Therefore, the operation characteristics change depending on the operation history of the circuit so far.
[0011]
In the conventional synchronous design, it is necessary to give the change width of the characteristic fluctuation due to the operation history as a timing margin, and there is a problem that the operation speed becomes slow.
[0012]
As a conventional technique that can cope with this, there is a technique (Japanese Patent Laid-Open No. 08-288822) that detects the stationary operation of the combinational logic circuit unit and generates the next clock. However, in order to completely detect a stationary state, it is necessary to attach a stationary detection circuit to all internal nodes of the combinational logic circuit unit, which is difficult to realize because the circuit scale increases extremely.
[0013]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that can improve the operation speed even when there is a variation in delay time that cannot be predicted from an external circuit, and that consumes less power, and a driving method thereof.
[0014]
[Means for Solving the Problems]
The semiconductor integrated circuit according to the present invention includes a clock generation circuit that generates a clock signal, a combinational logic circuit, a latch circuit that latches and outputs the output of the combinational logic circuit in accordance with the clock signal, and a clock to the latch circuit. An input signal to the latch circuit and an output signal from the latch circuit are detected when a check period, which is a fixed period, has elapsed after the signal is added. If the logical values of both signals do not match, a malfunction signal is output. A semiconductor integrated circuit having a malfunction detection circuit for outputting, wherein when the malfunction signal is output, the latch circuit latches the input signal again and outputs an output signal, and the clock signal generation circuit When no malfunction signal is output, a clock signal is generated at a constant clock cycle. When the malfunction signal is output, the clock signal is generated. A click signal is generated by delaying more than the check period.
[0015]
Thereby, even when the delay time of the circuit becomes longer than the clock cycle, it is possible to prevent malfunction of the circuit. In addition, since the clock period can be set shorter than the latest time (maximum path delay time) among the time that the signal travels through the combinational logic circuit, the circuit can be operated at high speed.
[0016]
Further, the clock signal generation circuit outputs a check signal delayed by a check period from the clock signal every clock cycle, so that each flip-flop can surely compare the input and output at the same timing, It is possible to reliably prevent malfunction of the circuit.
[0017]
In addition, when the clock signal rises or falls, the output signal from the combinational logic circuit is latched in the latch circuit, and a malfunction occurs when the clock signal transitions in a direction opposite to the latch operation of the latch circuit. The detection circuit compares the input signal to the latch circuit and the output signal from the latch circuit, and if the logical values of the two signals do not match, outputting a malfunction signal eliminates the need to generate a check signal. As a result, the circuit configuration can be simplified, and the manufacturing cost can be reduced.
[0018]
In addition, the semiconductor integrated circuit of the present invention operates to supply the combinational logic circuit, the latch circuit, and the malfunction detection circuit if the frequency per time that the malfunction signal is detected is higher than a certain malfunction upper limit frequency. A power supply voltage control circuit having a function of raising the voltage and lowering the operating voltage supplied to the combinational logic circuit, the latch circuit, and the malfunction detecting circuit if the frequency per malfunction signal is lower than a certain malfunction lower limit frequency Is further provided.
[0019]
Thereby, since an optimal power supply voltage can be set, power consumption can be reduced effectively. Since the power consumption of the circuit is proportional to the square of the power supply voltage, it is effective for reducing the power consumption of equipment using a semiconductor integrated circuit.
[0020]
Further, the semiconductor integrated circuit of the present invention increases the clock cycle if the frequency per time at which the malfunction signal is detected is higher than a certain malfunction upper limit frequency, and the frequency per time at which the malfunction signal is detected. Is further provided with a clock cycle control circuit having a function of shortening the clock cycle if the frequency is smaller than a certain malfunction lower limit frequency.
[0021]
As a result, the circuit can be operated at an optimum clock cycle, and malfunction of the circuit can be prevented. In addition, since the circuit can be operated with an optimal clock cycle, the operation speed of the circuit can be improved.
[0022]
A method for driving a semiconductor integrated circuit according to the present invention is a method for driving a semiconductor integrated circuit configured to send a signal between a first combinational circuit and a second combinational circuit via a latch circuit, and generates a clock signal. Step (a) of outputting a clock signal having a fixed clock cycle from the circuit and comparing the signal input to the latch circuit with the signal output from the latch circuit, and if both signals are different, malfunction occurs. A step (b) of outputting a signal, a step (c) of receiving the malfunction signal, causing the latch circuit to latch the signal from the first combination circuit again, and outputting the signal to the second combination circuit; A step (d) of outputting the clock signal after delaying it for a check period or more when the malfunction signal is output.
[0023]
This method can prevent malfunction of the circuit even when the delay time of the circuit becomes longer than the clock period. In addition, since the clock period can be set shorter than the latest time (maximum path delay time) among the time that the signal travels through the combinational logic circuit, the circuit can be operated at high speed.
[0024]
After the step (a), before the step (b), the method further includes a step (e) in which a check signal is output from the clock signal generation circuit with a check period delayed from the clock signal. Therefore, it is possible to reliably compare the input and output at the same timing, and to reliably prevent malfunction of the circuit.
[0025]
Further, before the step (b), the output signal from the combinational logic circuit is latched in the latch circuit when the clock signal rises or falls, and the direction opposite to that when the latch circuit performs a latch operation. Further including the step (e) in which the clock signal transitions to this eliminates the need to generate a check signal, so that the circuit configuration can be simplified and the manufacturing cost can be reduced.
[0026]
Further, if the frequency per time the malfunction signal is detected is higher than a certain malfunction upper limit frequency, the operation voltage supplied to the combinational logic circuit, the latch circuit, and the malfunction detection circuit is increased, and the certain malfunction lower limit frequency is increased. The method further includes a step (f) of lowering the operating voltage supplied to the combinational logic circuit, the latch circuit, and the malfunction detection circuit if the frequency of the malfunction signal per time is lower.
[0027]
By this method, an optimum power supply voltage can be set, so that the power consumption of the circuit can be effectively reduced. Since the power consumption of the circuit is proportional to the square of the power supply voltage, it is very effective for power saving of equipment using a semiconductor integrated circuit.
[0028]
In the semiconductor integrated circuit driving method of the present invention, if the frequency per time when the malfunction signal is detected is higher than a certain malfunction upper limit frequency, the clock cycle is lengthened and the time when the malfunction signal is detected. If the hit frequency is less than a certain malfunction lower limit frequency, the method further includes a step (g) of shortening the clock cycle.
[0029]
According to this method, the circuit can be operated at an optimal clock cycle, so that the operation speed can be increased and malfunction of the circuit can be prevented.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
[0031]
FIG. 1 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the present embodiment. Referring to the figure, 14a and 14b are flip-flops which are latch circuits, 15a and 15b are malfunction detection circuits, 16a and 16b are combinational logic circuits, Ser1 and Ser2 are malfunction signals, 18 is a check signal line, and 19 is a clock signal. Line, check signal is Sch, clock signal is Sck, 20 is a clock signal generation circuit, S1 is an input signal, S2 is an output signal from the combinational circuit 16b, Sin1 is an input signal to the flip-flop 14a, and Sin2 is to the flip-flop 14b , Sou1 is an output signal from the flip-flop 14a, and Sou2 is an output signal from the flip-flop 14b.
[0032]
In the semiconductor integrated circuit according to the present embodiment, the flip-flop 14a and the flip-flop 14b are arranged between the combinational logic circuit 16a and the combinational logic circuit 16b, the malfunction detection circuit 15a is in the flip-flop 14a, and the malfunction is in the flip-flop 14b. Each detection circuit 15b is connected. The first circuit A composed of the flip-flop 14a and the malfunction detection circuit 15a and the second circuit B composed of the flip-flop 14b and the malfunction detection circuit 15b have the same configuration. In the semiconductor integrated circuit of the embodiment, a plurality of circuits similar to this are arranged in parallel, and are connected to the combinational logic circuits 16a and 16b and the clock generation circuit 20, respectively.
[0033]
The semiconductor integrated circuit according to the present embodiment includes a malfunction detection circuit 15a in addition to a normal synchronous circuit configuration (flip-flop 14a, combinational logic circuit 16a, combinational logic circuit 16b, clock signal generation circuit 20 and the like), and a clock. The signal generation circuit 20 also has a mechanism for generating the check signal Sch. The malfunction detection circuit 15a compares the input signal Sin1 and the output signal Sou1 to the flip-flop 14a with the transition time of the check signal Sch (here, the rising transition time), and generates the malfunction signal Ser1 when they are different from each other. To do.
[0034]
Next, the operation (driving method) of the semiconductor integrated circuit of this embodiment will be described with reference to the drawings. Hereinafter, the first circuit A including the flip-flop 14a and the malfunction detection circuit 15a will be described as an example.
[0035]
2A and 2B are timing charts showing the operation of the semiconductor integrated circuit of the present embodiment. As shown in the figure, the check signal Sch is generated with a delay of the check period tc from the clock signal Sck.
[0036]
Here, the flip-flop 14a has a function of re-storing the data of the input signal Sin1 to the flip-flop 14a and outputting the output signal Sou1 from the flip-flop 14a when the malfunction signal Ser1 is generated.
[0037]
Further, the mechanism for generating the clock signal Sck and the check signal Sch delays both pulses of the clock signal Sck and the check signal Sch to be generated next by the check period tc or more than usual when the malfunction signal Ser1 is generated. Generate. Here, it is delayed by one clock cycle.
[0038]
Further, the delay time of the minimum delay path of the combinational logic circuit 16a is longer than the above-described tc (with respect to “tc + clock skew + hold time of the flip-flop 14a” in consideration of the clock skew and the hold time). It shall be designed.
[0039]
As shown in FIG. 2A, when the maximum path delay time is shorter than the clock period, a clock signal is generated for each predetermined clock period as in the case of a normal synchronization circuit.
[0040]
On the other hand, as shown in FIG. 2B, when the maximum path delay time becomes longer than the clock cycle, the malfunction signal Ser1 first changes from low (low voltage) to high (high voltage), and then the flip-flop. After the input signal Sin1 to the flip-flop 14a is stored in the flip-flop 14a, the output signal Sou1 from the flip-flop 14a is output. Following this, the next clock signal 18 and check signal 19 pulses are delayed by one clock cycle.
[0041]
As described above, in the semiconductor integrated circuit according to the present embodiment, the normal clock cycle can be set shorter than the absolute maximum path delay time, so the clock cycle is set longer than the absolute maximum path delay time. It can operate at higher speed than the conventional semiconductor integrated circuit. Further, in the semiconductor integrated circuit of this embodiment, even when a path delay longer than the clock cycle occurs and a timing shift occurs, a malfunction of the entire circuit can be avoided. However, if the maximum path delay time is longer than the clock cycle + the check period tc, it is difficult to avoid malfunction.
[0042]
As described above, according to the semiconductor integrated circuit of the present embodiment, the operation speed can be improved as compared with the conventional semiconductor integrated circuit, and malfunction of the semiconductor integrated circuit can be suppressed. In particular, the above-described effect is remarkable in a circuit in which an operation speed varies depending on an operation history, which is configured by a semiconductor device using SOI or the like as a substrate.
[0043]
In the present embodiment, the first circuit A including the flip-flop 14a and the malfunction detection circuit 15a has been described as an example. However, other flip-flops such as the second circuit B connected in parallel with these circuits are described. The malfunction detection circuit operates in the same manner as the flip-flop 14a and malfunction detection circuit 15a.
[0044]
The malfunction detection circuit shown in this embodiment is preferably connected only to a flip-flop circuit in which an input signal may arrive later than the clock cycle. That is, even if a signal transmitted through the combinational circuit connected to the input arrives at the latest due to operational fluctuations, the malfunction detection device is not connected to the flip-flop that arrives within the clock cycle from the beginning. As a result, the number of circuits can be reduced as compared with the case where malfunction detection circuits are connected to all flip-flop circuits, and the manufacturing cost can be reduced.
[0045]
(Second Embodiment)
FIG. 3 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the second embodiment of the present invention. As shown in the figure, the semiconductor integrated circuit of this embodiment is configured by integrating a latch circuit and a malfunction detection circuit in the semiconductor integrated circuit of the first embodiment.
[0046]
Referring to the figure, 14 is a flip-flop which is a latch circuit, 15 is a malfunction detection circuit, Ser is a malfunction signal, 18 is a check signal line, 19 is a clock signal line, check signal is Sch, clock signal is Sck, 20 Is a clock signal generation circuit, Sin is an input signal to the flip-flop, Sou is an output signal from the flip-flop, 25 is a CK master latch, 26 is a CH master latch, 27 is a slave latch, Clk is an external clock signal, and Che is an external signal A check signal, ON is a clock generation signal, and 30 is a multiplexer.
[0047]
The flip-flop 14 in which the malfunction detection circuit in the present embodiment is integrated includes two master latches (CK master latch 25 and CH master latch 26), one slave latch 27, a malfunction detection circuit 15, and a multiplexer 30. It consists of. The malfunction detection circuit 15 compares the output signal from the CK master latch 25 and the output signal from the CH master latch 26, and has a function of setting the malfunction signal Ser to high if they are different from each other. It has a function of selecting one of the output signal from the master latch 25 and the output signal from the CH master latch 26.
[0048]
The CK master latch 25 and the CH master latch 26 transmit a signal applied to the data input terminal to the output terminal when the enable signal is low, and hold the output data when the enable signal is high. The slave latch 27 transmits a signal applied to the data input terminal to the output terminal when the enable signal is high, and holds output data when the enable signal is low. When the clock signal Sck changes from low to high, the output signal from the CK master latch 25 is held, this output signal is transmitted to the input terminal of the slave latch 27, and the output signal Sou from the flip-flop is output. When the check signal Sch changes from low to high, the output signal from the CH master latch 26 is held.
[0049]
Here, when the output signal from the CK master latch 25 and the output signal from the CH master latch 26 are the same, the malfunction detection circuit Ser becomes low by the malfunction detection circuit 15, and the output signal of the CK master latch 25 is input to the slave latch 27. It is transmitted to the terminal. When the output signal from the CK master latch 25 and the output signal from the CH master latch 26 are different from each other, the malfunction detection signal Ser is changed to high by the malfunction detection circuit 15, and the output signal from the CH master latch 26 is output from the slave latch 27. When input to the input terminal, the output signal from the flip-flop 14 is output.
[0050]
In the clock signal generation circuit 20, when the malfunction signal Ser is high, the clock generation signal ON becomes low when the external check signal Che falls, and even if the external clock signal Clk changes, Both the clock signal Sck and the check signal Sch, which are output signals, remain low. When the check signal Sch becomes low, the malfunction signal Ser changes to low. Therefore, when the external check signal Che next changes from high to low, the clock generation signal ON in the clock signal generation circuit 20 becomes high, and the next clock signal and check signal pulse are output. As described above, the timing operation as shown in FIG. 2 can be performed.
[0051]
By adopting the above configuration, in the semiconductor integrated circuit of this embodiment, the number of elements and the number of wirings constituting the semiconductor integrated circuit can be reduced as compared with the first embodiment. That is, a semiconductor integrated circuit can be manufactured at low cost.
[0052]
In addition, by including a latch circuit having a malfunction detection function in the standard cell library, a semiconductor integrated circuit having a malfunction detection function can be easily designed using a conventional logic synthesis and placement and routing design method. Become.
[0053]
The malfunction detection circuit shown in this embodiment is preferably connected only to a flip-flop circuit in which an input signal may arrive later than the clock cycle. That is, even if a signal transmitted through the combinational circuit connected to the input arrives at the latest due to operational fluctuations, the malfunction detection device is not connected to the flip-flop that arrives within the clock cycle from the beginning. As a result, the number of circuits can be reduced as compared with the case where malfunction detection circuits are connected to all flip-flop circuits, and the manufacturing cost can be reduced.
[0054]
(Third embodiment)
FIG. 4 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the third embodiment of the present invention.
[0055]
Referring to the figure, 14a and 14b are flip-flops which are latch circuits, 15a and 15b are malfunction detection circuits, 16a and 16b are combinational logic circuits, Ser1 and Ser2 are malfunction signals, 19 is a clock signal line, and 20 is a clock. S1 is an input signal, S2 is an output signal, Sin1 is an input signal input to the flip-flop 14a, Sin2 is an input signal input to the flip-flop 14b, Sou1 is an output signal from the flip-flop 14a, and Sou2 is This is an output signal from the flip-flop 14b.
[0056]
The semiconductor integrated circuit of this embodiment further includes a malfunction detection circuit 15 in addition to the flip-flop 14a, flip-flop 14b, combinational logic circuit 16a, combinational logic circuit 16b, and clock signal generation circuit 20 that constitute a normal synchronous circuit. Is. The first circuit A composed of the flip-flop 14a and the malfunction detection circuit 15a and the second circuit B composed of the flip-flop 14b and the malfunction detection circuit 15b have the same configuration. In the semiconductor integrated circuit of the embodiment, a plurality of circuits similar to this are arranged in parallel, and are connected to the combinational logic circuits 16a and 16b and the clock generation circuit 20, respectively.
[0057]
Hereinafter, the first circuit A including the flip-flop 14a and the malfunction detection circuit 15a will be described as an example. Data is stored in the flip-flop 14a when the clock signal Sck rises and transitions. The malfunction detection circuit 15a compares the input signal Sin1 to the flip-flop 14a and the output signal Sou1 from the flip-flop 14a when the clock signal Sck falls and generates a malfunction signal Ser1 when they are different from each other. . The clock signal generation circuit 20 has a mechanism for generating the clock signal Sck. The difference from the first embodiment is that the clock signal generation circuit 20 does not generate a check signal, and substitutes the check signal at the falling edge of the clock signal Sck.
[0058]
5A and 5B are timing charts for explaining the operation of the semiconductor integrated circuit according to the present embodiment.
[0059]
As shown in the figure, the clock signal Sck is generated so as to perform a falling transition after a check period tc after performing a rising transition. The flip-flop 14a has a function of re-storing the data of the input signal Sin1 to the flip-flop 14a and outputting the output signal Sou1 when the malfunction signal Ser1 is generated. In addition, when the malfunction signal Ser1 is generated, the mechanism that generates the clock signal Sck generates a pulse of the clock signal Sck that is generated next by delaying the pulse by a check period tc or more than usual. In this embodiment, it is delayed by one clock cycle.
[0060]
Further, the delay time of the minimum delay path of the combinational logic circuit 16a is longer than the above-described tc (with respect to “tc + clock skew + hold time of the flip-flop 14a” in consideration of the clock skew and the hold time). It shall be designed.
[0061]
In the semiconductor integrated circuit according to the present embodiment, when the maximum path delay time is shorter than the clock cycle, the clock signal Sck is generated every clock cycle determined in the same manner as in a normal synchronization circuit.
[0062]
When the maximum path delay time becomes longer than the clock cycle, first, the malfunction signal Ser1 changes from low to high, the input signal Sin1 to the flip-flop 14a is stored again in the flip-flop 14a, and the output signal Sou1 is output. . The next pulse of the clock signal Sck is generated with a delay of one clock cycle.
[0063]
In this way, by setting the normal clock cycle to be shorter than the absolute maximum path delay time, the circuit can be operated at a higher speed, and even when a timing shift occurs, a malfunction of the circuit is avoided. be able to. However, if the maximum path delay time is longer than the clock cycle + the check period tc, it is difficult to avoid malfunction.
[0064]
Further, according to the configuration of the semiconductor integrated circuit of the present embodiment, since it is not necessary to generate a check signal, the number of wirings can be reduced as compared with the semiconductor integrated circuit of the first embodiment. That is, the manufacturing cost can be reduced as compared with the semiconductor integrated circuit of the first embodiment.
[0065]
In the present embodiment, the first circuit A including the flip-flop 14a and the malfunction detection circuit 15a has been described as an example. However, other circuits such as the second circuit B connected in parallel with these circuits are described. The flip-flop and malfunction detection circuit operate in the same manner as the flip-flop 14a and malfunction detection circuit 15a.
[0066]
The malfunction detection circuit shown in this embodiment is preferably connected only to a flip-flop circuit in which an input signal may arrive later than the clock cycle. That is, even if a signal transmitted through the combinational circuit connected to the input arrives at the latest due to operational fluctuations, the malfunction detection device is not connected to the flip-flop that arrives within the clock cycle from the beginning. As a result, the number of circuits can be reduced as compared with the case where malfunction detection circuits are connected to all flip-flop circuits, and the manufacturing cost can be reduced.
[0067]
(Fourth embodiment)
FIG. 6 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the fourth embodiment of the present invention. As shown in the figure, the semiconductor integrated circuit of this embodiment is configured by integrating the latch circuit and the malfunction detection circuit of the semiconductor integrated circuit of the third embodiment.
[0068]
Referring to the figure, 14 is a flip-flop which is a latch circuit, 15 is a malfunction detection circuit, Ser is a malfunction signal, 19 is a clock signal line, 20 is a clock signal generation circuit, Sin is an input to the flip-flop, and Sou is Flip-flop output, Clk is an external clock signal, 30 is a multiplexer, 31 is a master latch, 32 is a CK slave latch, 33 is a CH slave latch, 34 is a toggle flip-flop, and ON is a clock generation signal.
[0069]
In the semiconductor integrated circuit of the present embodiment, the flip-flop 14 provided with the malfunction detection circuit 15 includes one master latch 31, two slave latches (CK slave latch 32, CH slave latch 33), a multiplexer 30, And a malfunction detection circuit 15. The malfunction detection circuit 15 compares the output signal from the CK slave latch 32 and the output signal from the CH slave latch 33 and has a function of setting the malfunction signal Ser to high if they are different from each other. It has a function of selecting one of the output signal from the slave latch 32 and the output signal from the CH slave latch 33.
[0070]
The master latch 31 transmits a signal input to the data input terminal to the output terminal when the enable signal is low, and holds output data when the enable signal is high. The CK slave latch 32 and the CH slave latch 33 transmit a signal applied to the data input terminal to the output terminal when the enable signal is high, and hold the output signal when the enable signal is low. When the clock signal Sck changes from low to high, the output signal from the master latch 31 is held, which is transmitted to the input terminal of the CK slave latch 32, and the output signal Sou is output from the output terminal of the flip-flop.
[0071]
When the clock signal Sck changes from high to low, the output signal from the CH slave latch 33 is held. At this time, if the output signal from the CK slave latch 32 and the output signal from the CH slave latch 33 are the same, the malfunction detection circuit Ser becomes low by the malfunction detection circuit 15, and the output signal from the CK slave latch 32 becomes the flip-flop 14. Is output as an output signal Sou.
[0072]
On the other hand, when the output signal from the CK slave latch 32 and the output signal from the CH slave latch 33 are different, the malfunction detection circuit Ser changes to high by the malfunction detection circuit 15 and the output signal from the CH slave latch 33 is flip-flops. 14 is output as an output signal Sou.
[0073]
The clock generation signal ON output from the toggle flip-flop 34 in the clock signal generation circuit 20 is initialized to high. The toggle flip-flop 34 holds the output signal when the malfunction signal Ser is low, and inverts the output signal when the external clock signal Clk rises when the malfunction signal Ser is high. That is, when the malfunction signal Ser changes to high and the external clock signal Clk rises next time, the clock generation signal ON changes from high to low. As a result, even if the external clock signal Clk changes, the clock signal Sck that is the output of the clock generation circuit 20 remains low.
[0074]
Then, when the external clock signal Clk rises, the malfunction signal Ser remains high, so that the output signal (clock generation signal ON) from the toggle flip-flop 34 changes from low to high again. Then, the clock signal Sck rising from low to high is input to the flip-flop 14. At this time, the malfunction signal Ser changes to low. As described above, the timing operation as shown in FIG. 5 can be performed.
[0075]
In the semiconductor integrated circuit of the present embodiment, the number of elements and the number of wirings constituting the semiconductor integrated circuit can be reduced as compared with the semiconductor integrated circuit of the third embodiment. That is, the manufacturing cost can be reduced compared to the semiconductor integrated circuit of the third embodiment.
[0076]
In addition, by including a latch circuit having a malfunction detection function in the standard cell library, a semiconductor integrated circuit having a malfunction detection function can be easily designed using a conventional logic synthesis and placement and routing design method. Become.
[0077]
(Fifth embodiment)
FIG. 7 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the fourth embodiment of the present invention. As shown in the figure, the semiconductor integrated circuit of this embodiment is obtained by further adding a power supply voltage control circuit and a power supply circuit to the semiconductor integrated circuit of the first embodiment.
[0078]
Referring to the figure, 14a and 14b are flip-flops which are latch circuits, 15a and 15b are malfunction detection circuits, 16a and 16b are combinational logic circuits, Ser1 and Ser2 are malfunction signals, 18 is a check signal line, and 19 is a clock. The signal line, 20 is a clock signal generation circuit, S1 is an input signal, S2 is an output signal, Sin1 is an input signal to the flip-flop 14a, Sin2 is an input signal to the flip-flop 14b, Sou1 is an output signal from the flip-flop 14a, Sou2 is an output signal from the flip-flop 14b, 35 is a power supply circuit, 36 is a power supply line, and 37 is a power supply voltage control circuit. The first circuit A composed of the flip-flop 14a and the malfunction detection circuit 15a and the second circuit B composed of the flip-flop 14b and the malfunction detection circuit 15b have the same configuration. In the semiconductor integrated circuit of the embodiment, a plurality of circuits similar to this are arranged in parallel, and are connected to the combinational logic circuits 16a and 16b and the clock signal generation circuit 20, respectively. Hereinafter, the first circuit A including the flip-flop 14a and the malfunction detection circuit 15a will be described as an example.
[0079]
In the semiconductor integrated circuit of this embodiment, both the clock signal Sck and the malfunction signal Ser1 are input to the power supply voltage control circuit 37, and the number of pulses of the clock signal Sck and the malfunction signal Ser1 are measured. When the number of pulses per time of the clock signal Sck reaches a certain number of times, the power supply voltage control circuit 37 may exceed a certain number of times (the upper limit of malfunction) of the number of pulses per malfunction signal Ser1. For example, a control signal for increasing the power supply voltage is transmitted to the power supply circuit 35, and if it is less than a certain number of times (lower malfunction limit), a signal for increasing the power supply voltage is transmitted to the power supply circuit 35. The power supply voltage used here means an operating voltage that actually flows through the circuit.
[0080]
As a result, the circuit can be operated with an optimum power supply voltage. In the conventional semiconductor integrated circuit, it is necessary to set the power supply voltage higher in consideration of the fluctuation of the maximum path delay time. However, in the semiconductor integrated circuit of this embodiment, the optimum power supply voltage can be set. Therefore, power consumption can be effectively reduced.
Since the power consumption of the circuit is proportional to the square of the power supply voltage, the semiconductor integrated circuit of the present invention is very effective for power saving of equipment using the circuit.
[0081]
The malfunction detection circuit shown in this embodiment is preferably connected only to a flip-flop circuit in which an input signal may arrive later than the clock cycle. That is, even if a signal transmitted through the combinational circuit connected to the input arrives at the latest due to operational fluctuations, the malfunction detection device is not connected to the flip-flop that arrives within the clock cycle from the beginning. As a result, the number of circuits can be reduced as compared with the case where malfunction detection circuits are connected to all flip-flop circuits, and the manufacturing cost can be reduced.
[0082]
In the semiconductor integrated circuit of this embodiment, the clock signal generation circuit has a function of generating a check signal. However, the clock signal generation circuit does not generate a check signal and the clock signal falls when the clock signal falls. A structure in which an input signal to the flip-flop and an output signal from the flip-flop are compared may be employed.
[0083]
(Sixth embodiment)
FIG. 8 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the fifth embodiment of the present invention. As shown in the figure, the semiconductor integrated circuit of this embodiment is obtained by adding a clock cycle control circuit to the semiconductor integrated circuit of the first embodiment.
[0084]
Referring to the figure, 14a and 14b are flip-flops which are latch circuits, 15a and 15b are malfunction detection circuits, 16a and 16b are combinational logic circuits, Ser1 and Ser2 are malfunction signals, 18 is a check signal line, and 19 is a clock. The signal line, 20 is a clock signal generation circuit, S1 is an input signal, S2 is an output signal, Sin1 is an input signal to the flip-flop 14a, Sin2 is an input signal to the flip-flop 14b, Sou1 is an output signal from the flip-flop 14a, Sou2 is an output signal from the flip-flop 14b, and 38 is a clock cycle control circuit. Here, in the semiconductor integrated circuit of the present embodiment, the same circuit composed of the flip-flop and the malfunction detection circuit is arranged in parallel. Therefore, the flip-flop 14a and the malfunction detection circuit 15a will be described below as an example. To do.
[0085]
In the semiconductor integrated circuit of the present embodiment, both the clock signal Sck and the malfunction signal Ser1 are input to the clock cycle control circuit 38, and the number of pulses of the clock signal Sck and the malfunction signal Ser1 are measured. When the number of pulses per time of the clock signal Sck reaches a certain number of times, the clock cycle control circuit 38 clocks if the number of pulses per time of the malfunction signal Ser1 exceeds a certain number (malfunction upper limit). A control signal for increasing the cycle is transmitted to the clock signal generation circuit 20, and if it is smaller than a certain number of times (malfunction lower limit), a signal for shortening the clock cycle is transmitted to the clock signal generation circuit 20.
[0086]
As a result, the circuit can be operated with an optimum clock cycle. That is, the semiconductor integrated circuit of this embodiment can improve the operation speed in accordance with the operating environment.
[0087]
The malfunction detection circuit shown in this embodiment is preferably connected only to a flip-flop circuit in which an input signal may arrive later than the clock cycle. That is, even if a signal transmitted through the combinational circuit connected to the input arrives at the latest due to operational fluctuations, the malfunction detection device is not connected to the flip-flop that arrives within the clock cycle from the beginning. As a result, the number of circuits can be reduced as compared with the case where malfunction detection circuits are connected to all flip-flop circuits, and the manufacturing cost can be reduced.
[0088]
In the semiconductor integrated circuit of this embodiment, the clock signal generation circuit has a function of generating a check signal. However, the clock signal generation circuit does not generate a check signal and the clock signal falls when the clock signal falls. A structure in which an input signal to the flip-flop and an output signal from the flip-flop are compared may be employed.
[0089]
Further, the semiconductor integrated circuit of the present embodiment may have a structure further including the above-described power supply circuit and power supply voltage control circuit.
[0090]
As a structure of the clock cycle control circuit used in this embodiment, a structure using a ring oscillator can be considered. At this time, the clock cycle can be varied by controlling the voltage applied to the ring oscillator, for example, by a signal from the clock cycle control circuit.
[0091]
【The invention's effect】
According to the semiconductor integrated circuit and the operation method thereof of the present invention, by including the malfunction detection circuit, the operation speed of the circuit can be improved even when there is a variation in delay time that cannot be predicted from an external circuit, and the semiconductor The power consumption of the integrated circuit can be reduced.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a first embodiment of the present invention.
FIGS. 2A and 2B are timing charts showing the operation of the semiconductor integrated circuit according to the first embodiment of the present invention. FIGS.
FIG. 3 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 4 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a third embodiment of the present invention.
FIGS. 5A and 5B are timing diagrams illustrating the operation of a semiconductor integrated circuit according to a third embodiment of the present invention.
FIG. 6 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a fourth embodiment of the present invention.
FIG. 7 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a fourth embodiment of the present invention.
FIG. 8 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a fifth embodiment of the present invention.
FIG. 9 is a block circuit diagram schematically showing a conventional semiconductor integrated circuit.
[Explanation of symbols]
14, 14a, 14b flip-flop
15, 15a, 15b Malfunction detection circuit
16a, b combinational logic circuit
18 Check signal line
19 Clock signal line
20 Clock signal generation circuit
25 CK master latch
26 CH master latch
27 Slave latch
30 multiplexer
31 Master latch
32 CK slave latch
33 CH slave latch
34 Toggle flip-flop
35 Power supply circuit
36 Power line
37 Power supply voltage control circuit
38 Clock cycle control circuit
ON clock generation signal
S1 input signal
S2 output signal
Ser, Ser1, Ser2 Malfunction signal
Sin, Sin1, Sin2 Input signal to flip-flop
Sou, Sou1, Sou2 Output signal from flip-flop
Clk external clock signal
Che external check signal
Sch check signal
Sck clock signal

Claims (14)

A clock generation circuit for generating a clock signal;
Combinational logic,
A latch circuit that latches and outputs the output of the combinational logic circuit according to the clock signal;
Detecting an output signal from the input signal and the latch circuit to said latch circuit when the check period is constant period after the clock signal is applied to the latch circuit has elapsed, the logic value of the two signals coincide A semiconductor integrated circuit having a malfunction detection circuit that outputs a malfunction signal if not,
When the malfunction signal is output, the latch circuit latches the input signal again and outputs an output signal,
The clock signal generating circuit, the semiconductor integrated circuit when the malfunction signal is not outputted to generate the clock signal at a predetermined clock cycle, when said malfunction signal is output to generate delaying the clock signal or the check period . The semiconductor integrated circuit according to claim 1,
The clock signal generating circuit, a semiconductor integrated circuit characterized by further outputs a check signal delayed by checking period than the clock signal for each clock cycle. The semiconductor integrated circuit according to claim 1 or 2,
The output signal from the combinational logic circuit is latched in the latch circuit when the clock signal rises or falls,
When the clock signal transitions in the opposite direction to when the latch circuit performs the latch operation, the malfunction detection circuit compares the input signal to the latch circuit with the output signal from the latch circuit, and the logic of both signals A semiconductor integrated circuit characterized by outputting a malfunction signal if the values do not match. The semiconductor integrated circuit according to any one of claims 1 to 3,
If the frequency per time that the malfunction signal is detected is higher than a certain malfunction upper limit frequency, the operating voltage supplied to the combinational logic circuit, the latch circuit, and the malfunction detection circuit is increased, and the malfunction lower limit frequency is exceeded. And a power supply voltage control circuit having a function of reducing an operating voltage supplied to the combinational logic circuit, the latch circuit, and the malfunction detecting circuit if the frequency of the malfunctioning signal per time is low. Integrated circuit. In the semiconductor integrated circuit according to any one of claims 1 to 4,
If the frequency per time that the malfunction signal is detected is higher than a certain malfunction upper limit frequency, the clock cycle is lengthened, and if the frequency per time that the malfunction signal is detected is smaller than a certain malfunction lower limit frequency. A semiconductor integrated circuit, further comprising a clock cycle control circuit having a function of shortening the clock cycle. The semiconductor integrated circuit according to claim 1,
A semiconductor integrated circuit, wherein the clock signal is generated with a delay of one clock period when the malfunction signal is output. A clock generation circuit for generating a clock signal;
Combinational logic,
A latch circuit that latches and outputs the output of the combinational logic circuit according to the clock signal;
The input signal to the latch circuit and the output signal from the latch circuit are detected when a check period, which is a certain period, has elapsed since the clock signal is applied to the latch circuit, and the logical values of both signals match. A semiconductor integrated circuit having a malfunction detection circuit that outputs a malfunction signal if not,
The latch circuit, when the malfunction signal is output, latches the input signal again and outputs an output signal. The semiconductor integrated circuit according to claim 1 or 7,
The latch circuit further includes a CH latch circuit that latches and outputs the output of the combinational logic circuit with a check signal delayed by the check period with respect to the clock signal,
The semiconductor integrated circuit according to claim 1, wherein when the malfunction signal is output, the latch circuit latches the output signal of the CH latch circuit and outputs an output signal. A semiconductor integrated circuit according to any one of claims 1 to 8,
A semiconductor integrated circuit comprising a standard cell library including a latch circuit including the malfunction detection circuit. A method of driving a semiconductor integrated circuit configured to send a signal between a first combinational circuit and a second combinational circuit via a latch circuit,
Outputting a clock signal having a constant clock period from the clock signal generation circuit (a);
Comparing the signal input to the latch circuit with the signal output from the latch circuit, and outputting a malfunction signal if both signals are different;
Receiving the malfunction signal, causing the latch circuit to latch the signal from the first combination circuit again and outputting the signal to the second combination circuit;
And (d) a step of outputting the clock signal after delaying it for a check period or more when the malfunction signal is output. The method for driving a semiconductor integrated circuit according to claim 10 ,
The semiconductor integrated circuit further comprising a step (e) of outputting a check signal from the clock signal generation circuit after the step (a) and before the step (b) with a delay of a check period from the clock signal. Circuit driving method. The method for driving a semiconductor integrated circuit according to claim 10 or 11 ,
Before step (b), when the clock signal rises or falls, an output signal from the combinational logic circuit is latched in the latch circuit, and the latch circuit performs the latch operation in the opposite direction. A method for driving a semiconductor integrated circuit, further comprising the step (e) of transition of a clock signal. The method of driving a semiconductor integrated circuit according to any one of claims 10 to 12 ,
If the frequency per time that the malfunction signal is detected is higher than a certain malfunction upper limit frequency, the operating voltage supplied to the combinational logic circuit, the latch circuit, and the malfunction detection circuit is increased, and the malfunction signal is lower than the certain malfunction lower limit frequency. A method of driving a semiconductor integrated circuit, further comprising a step (f) of lowering an operating voltage supplied to the combinational logic circuit, the latch circuit, and the malfunction detection circuit if the frequency of the malfunction signal per time is low. . The method of driving a semiconductor integrated circuit according to any one of claims 10 to 13 ,
If the frequency per time that the malfunction signal is detected is higher than a certain malfunction upper limit frequency, the clock cycle is lengthened, and if the frequency per time that the malfunction signal is detected is smaller than a certain malfunction lower limit frequency. A method for driving a semiconductor integrated circuit, further comprising the step (g) of shortening the clock cycle.

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